LTC2202UK [Linear]
16-Bit, 25Msps/10Msps ADCs; 16位， 25Msps时/ 10MSPS模数转换器
| 型号： | LTC2202UK |
| 厂家： | 
Linear |
| 描述： | 16-Bit, 25Msps/10Msps ADCs |
| 文件： | 总32页 (文件大小：1646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2203/LTC2202
16-Bit, 25Msps/10Msps ADCs
U
FEATURES
DESCRIPTIO
The LTC®2203/LTC2202 are 25Msps/10Msps, sampling
16-bitA/Dconvertersdesignedfordigitizinghighfrequen-
cy, wide dynamic range signals with input frequencies up
to 380MHz. The input range of the ADC can be optimized
with the PGA front end.
■
Sample Rate: 25Msps/10Msps
■
81.6dB SNR and 100dB SFDR (2.5V Range)
■
SFDR 90dB at 70MHz (1.667V Input Range)
P-P
■
■
■
■
■
■
■
■
■
PGA Front End (2.5V or 1.667V Input Range)
P-P
P-P
380MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
The LTC2203/LTC2202 are perfect for demanding ap-
plications, with AC performance that includes 81.6dB
SNR and 100dB spurious free dynamic range (SFDR).
Maximum DC specs include ±±LSB ꢀNL, ±1LSB DNL (no
missing codes).
Power Dissipation: 220mW/1±0mW
Clock Duty Cycle Stabilizer
Out-of-Range ꢀndicator
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
Pin Compatible Family
25Msps: LTC2203 (16-Bit)
10Msps: LTC2202 (16-Bit)
±8-Pin (7mm × 7mm) QFN Package
Asingle-endedCLKinputcontrolsconverteroperation.An
optionalclockdutycyclestabilizerallowshighperformance
at full speed with a wide range of clock duty cycles.
■
U
APPLICATIO S
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including ±8±3302 and 69±9965B1
■
Telecommunications
■
Receivers
■
Cellular Base Stations
■
Spectrum Analysis
■
ꢀmaging Systems
■
ATE
U
TYPICAL APPLICATIO
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –1dBFS, PGA = 0
3.3V
0
–10
–20
–30
–±0
SENSE
OV
DD
1.25V
COMMON MODE
BꢀAS VOLTAGE
ꢀNTERNAL ADC
REFERENCE
GENERATOR
V
0.5V TO 3.6V
CM
1μF
2.2μF
–50
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
OF
CLKOUT+
CLKOUT–
+
A
ꢀN
+
16-BꢀT
PꢀPELꢀNED
ADC CORE
OUTPUT
DRꢀVERS
CORRECTꢀON
LOGꢀC AND
SHꢀFT REGꢀSTER
ANALOG
ꢀNPUT
S/H
AMP
CMOS
OUTPUTS
D15
•
•
–
–
A
ꢀN
•
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
3.3V
1μF
V
DD
1μF
1μF
GND
0
2
±
6
8
10
12
FREQUENCY(MHz)
22032 GO7
CLK
PGA SHDN DꢀTH MODE
ADC CONTROL ꢀNPUTS
RAND
OE
22032 TA01
22032fb
1
LTC2203/LTC2202
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
OVDD = VDD (Notes 1 and 2)
TOP VꢀEW
Supply Voltage (V )...................................–0.3V to ±V
DD
Digital Output Supply Voltage (OV )..........–0.3V to ±V
DD
Digital Output Ground Voltage (OGND)........–0.3V to 1V
SENSE 1
36 OV
DD
Analog ꢀnput Voltage (Note 3) ..... –0.3V to (V + 0.3V)
DD
V
V
V
2
3
±
35 D11
3± D10
33 D9
CM
Digital ꢀnput Voltage .................... –0.3V to (V + 0.3V)
DD
DD
DD
Digital Output Voltage................–0.3V to (OV + 0.3V)
DD
GND 5
32 D8
+
Power Dissipation............................................ 2000mW
A
A
6
7
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D7
27 D6
26 D5
ꢀN
±9
–
ꢀN
Operating Temperature Range
GND 8
GND 9
CLK 10
GND 11
LTC2203C/LTC2202C............................... 0°C to 70°C
LTC2203ꢀ/LTC2202ꢀ.............................–±0°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
V
DD
12
25 OV
DD
UK PACKAGE
±8-LEAD (7mm × 7mm) PLASTꢀC QFN
EXPOSED PAD ꢀS GND (PꢀN ±9)
MUST BE SOLDERED TO PCB BOARD
T
JMAX
= 125°C, θ = 29°C/W
JA
T
= 150°C, OPTꢀON AVAꢀLABLE, CONSULT FACTORY
JMAX
ORDER PART
NUMBER
UK PART*
MARKꢀNG
LTC2203CUK
LTC2202CUK
LTC2203UK
LTC2202UK
LTC2203UK
LTC2202UK
LTC2203ꢀUK
LTC2202ꢀUK
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No missing codes)
Integral Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
16
Differential Analog Input (Note 5) T = 25°C
±1ꢀ2
±1ꢀ5
±0ꢀ3
±2
±±ꢀ0
±±ꢀ5
±1
LSB
LSB
A
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
●
●
●
LSB
±10
mV
Offset Drift
±10
±0ꢀ2
μV/°C
%FS
Gain Error
External Reference
●
±1ꢀ5
Full-Scale Drift
Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise
External Reference (2ꢀ5V Range, PGA = 0)
1ꢀ92
LSB
RMS
22032fb
2
LTC2203/LTC2202
U
U
A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1ꢀ667 or 2ꢀ5
1ꢀ25
MAX
UNITS
+
–
V
IN
Analog Input Range (A
Analog Input Common Mode
–
A
IN
)
3ꢀ135V ≤ V ≤ 3ꢀ±65V
V
P-P
IN
DD
V
I
Differential Input (Note 7)
●
●
●
1
–1
–3
1ꢀ5
1
3
V
μA
μA
μA
μA
IN, CM
+
–
Analog Input Leakage Current
SENSE Input Leakage Current
MODE Pin Pull-Down Current to GND
OE Pin Pull-Down Current to GND
Analog Input Capacitance
0V ≤ A
,
A
IN
≤ V (Note 9)
IN
IN
DD
I
I
I
0V ≤ SENSE ≤ V (Note 10)
SENSE
MODE
OE
DD
10
10
10ꢀ5
1ꢀ±
C
IN
Sample Mode CLK = 0
Hold Mode CLK = 0
pF
pF
t
t
Sample-and-Hold
0ꢀ9
200
80
ns
fs RMS
dB
AP
Acquisition Delay Time
Sample-and-Hold
Acquisition Delay Time Jitter
Analog Input
Common Mode Rejection Ratio
JITTER
+
–
CMRR
1V < (A = A ) <1ꢀ5V
IN
IN
Rs < 20Ω
380
MHz
BW-3dB U W Full Power Bandwidth
DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
LTC2203
TYP
LTC2202
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SNR
Signal-to-Noise Ratio
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
81ꢀ6
79ꢀ±
81ꢀ6
79ꢀ±
dBFS
dBFS
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
●
●
80ꢀ0
81ꢀ6
79ꢀ±
81ꢀ±
79ꢀ3
80ꢀ8
78ꢀ9
80ꢀ0
81ꢀ6
79ꢀ±
81ꢀ±
79ꢀ3
80ꢀ8
78ꢀ9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
77ꢀ5
77ꢀ5
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA =1 )
78ꢀ3
77ꢀ2
78ꢀ3
77ꢀ2
dBFS
dBFS
SFDR
Spurious Free
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
100
100
100
100
100
95
100
90
95
100
100
100
100
100
95
100
90
95
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Dynamic Range
nd
rd
2
or 3 Harmonic
●
●
85
90
85
90
85
85
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA = 1)
85
90
85
90
dBc
dBc
SFDR
Spurious Free
Dynamic Range
th
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
±
Harmonic
●
●
90
90
90
90
or Higher
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA = 1)
90
90
90
90
dBc
dBc
22032fb
3
LTC2203/LTC2202
U W
DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
LTC2203
LTC2202
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
S/(N+D)
Signal-to-Noise
Plus Distortion Ratio
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
81ꢀ5
79ꢀ3
81ꢀ5
79ꢀ3
dBFS
dBFS
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
●
●
79ꢀ7
81ꢀ5
79ꢀ3
79ꢀ7
81ꢀ5
79ꢀ3
dBFS
dBFS
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
81ꢀ3
79ꢀ2
81ꢀ3
79ꢀ2
dBFS
dBFS
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
80ꢀ6
78ꢀ6
80ꢀ6
78ꢀ6
dBFS
dBFS
77ꢀ2
77ꢀ2
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA = 1)
78ꢀ1
77
78ꢀ1
77
dBFS
dBFS
SFDR
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
Spurious Free
Dynamic Range
at –25dBFS
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
Dither “OFF”
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
SFDR
1MHz Input (2ꢀ5V Range, PGA = 0)
1MHz Input (1ꢀ667V Range, PGA = 1)
115
115
115
115
dBFS
dBFS
Spurious Free
Dynamic Range
at –25dBFS
5MHz Input (2ꢀ5V Range, PGA = 0)
5MHz Input (1ꢀ667V Range, PGA = 1)
●
100
115
115
100
115
115
dBFS
dBFS
Dither “ON”
12ꢀ5MHz Input (2ꢀ5V Range, PGA = 0)
12ꢀ5MHz Input (1ꢀ667V Range, PGA = 1)
115
115
115
115
dBFS
dBFS
30MHz Input (2ꢀ5V Range, PGA = 0)
30MHz Input (1ꢀ667V Range, PGA = 1)
115
115
115
115
dBFS
dBFS
70MHz Input (2ꢀ5V Range, PGA = 0)
70MHz Input (1ꢀ667V Range, PGA = 1)
110
110
110
110
dBFS
dBFS
U U U U U U U
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
The ● denotes the specifications which apply over
CO
O ODE BIAS CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
1ꢀ25
±±0
1
MAX
UNITS
V
V
CM
V
CM
V
CM
V
CM
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
1ꢀ15
1ꢀ35
OUT
OUT
ppm/°C
mV/V
Ω
3ꢀ135V ≤ V ≤ 3ꢀ±65V
DD
1mA ≤ | I
| ≤ 1mA
2
OUT
22032fb
4
LTC2203/LTC2202
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS
LOGIC INPUTS (CLK, OE, DITH, PGA, SHDN, RAND)
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 3ꢀ3V
= 3ꢀ3V
●
●
●
2
V
V
IH
IL
DD
DD
IN
0ꢀ8
I
IN
= 0V to V
±10
μA
pF
DD
C
IN
Digital Input Capacitance
(Note 7)
1ꢀ5
LOGIC OUTPUTS
OV = 3.3V
DD
V
High Level Output Voltage
Low Level Output Voltage
V
V
= 3ꢀ3V
= 3ꢀ3V
I = –10μA
I = –200μA
O
3ꢀ299
3ꢀ29
V
V
OH
DD
DD
O
●
●
3ꢀ1
V
I = 160μA
0ꢀ01
0ꢀ10
V
V
OL
O
I = 1ꢀ6mA
O
0ꢀ±
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–50
50
mA
mA
SOURCE
OUT
OUT
= 3ꢀ3V
SINK
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
V
V
= 3ꢀ3V
= 3ꢀ3V
I = –200μA
2ꢀ±9
0ꢀ1
V
V
OH
OL
DD
DD
O
I = 1ꢀ60mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
V
V
= 3ꢀ3V
= 3ꢀ3V
I = –200μA
1ꢀ79
0ꢀ1
V
V
OH
DD
DD
O
I = 1ꢀ60mA
O
OL
W U
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
LTC2203
TYP
LTC2202
TYP
SYMBOL
PARAMETER
CONDITIONS
SHDN = V , CLK = V
DD
MIN
MAX
MIN
MAX
UNITS
V
V
P
Analog Supply Voltage
Shutdown Power
●
3ꢀ135
3ꢀ3
2
3ꢀ±65
3ꢀ135
3ꢀ3
2
3ꢀ±65
DD
mW
V
SHDN
DD
OV
Output Supply Voltage
Analog Supply Current
Power Dissipation
●
●
●
0ꢀ5
3ꢀ6
80
0ꢀ5
3ꢀ6
50
DD
I
66
±2
mA
mW
VDD
P
220
26±
1±0
165
DIS
22032fb
5
LTC2203/LTC2202
W U
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2203
TYP
LTC2202
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
f
S
t
L
Sampling Frequency
CLK Low Time
●
1
25
1
10
MHz
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
18ꢀ9
5
20
20
500
500
±0
5
50
50
500
500
ns
ns
t
t
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
18ꢀ9
5
20
20
500
500
±0
5
50
50
500
500
ns
ns
H
Sample-and-Hold
Aperture Delay
0ꢀ9
0ꢀ9
ns
AP
t
t
t
CLK to DATA Delay
C = 5pF (Note 7)
●
●
●
1ꢀ3
1ꢀ3
3ꢀ1
3ꢀ1
0
±ꢀ9
±ꢀ9
0ꢀ6
1ꢀ3
1ꢀ3
3ꢀ1
3ꢀ1
0
±ꢀ9
±ꢀ9
0ꢀ6
ns
ns
ns
D
L
CLK to CLKOUT Delay
C = 5pF (Note 7)
L
C
DATA to CLKOUT Skew C = 5pF (Note 7)
–0ꢀ6
–0ꢀ6
SKEW
L
DATA Access Time
Bus Relinquish Time
C = 5pF (Note 7)
(Note 7)
●
●
5
5
15
15
5
5
15
15
ns
ns
L
Pipeline
Latency
7
7
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 5: ꢀntegral nonlinearity is defined as the deviation of a code from a
“best fit straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: Dynamic current from switched capacitor inputs is large compared
to DC leakage current, and will vary with sample rate.
Note 10: Leakage current will experience transient at power up. Keep
resistance < 1K Ω.
DD
of greater than 100mA below GND or above V without latchup.
DD
Note 4: V = 3.3V, f
= 25MHz (LTC2203), 10MHz (LTC2202),
DD
SAMPLE
input range = 2.5V with differential drive (PGA = 0), unless otherwise
P-P
specified.
W U
W
TI I G DIAGRA
t
AP
N + 1
N + ±
ANALOG
ꢀNPUT
N + 3
N
N + 2
t
L
t
H
CLK
t
D
N – 7
N – 6
N – 5
N – ±
N – 3
D0-D15, OF
t
C
CLKOUT+
CLKOUT–
22032 TD01
22032fb
6
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: Integral Nonlinearity
(INL) vs Output Code
LTC2203: Differential Nonlinearity
(DNL) vs Output Code
LTC2203: AC Grounded Input
Histogram (256k Samples)
60000
1.0
0.8
2.0
1.5
50000
0.6
1.0
0.±
±0000
30000
0.5
0.2
0.0
0.0
–0.2
–0.±
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
20000
10000
0
32768
CODE
0
1638±
32768
CODE
65536
0
1638±
±9152
65536
±9152
32812 32816 32820 3282± 32828 32832
OUTPUT CODE
22032 G01
22032 G02
22032 G03
LTC2203: 128K Point FFT,
fIN = 1MHz, –1dBFS, PGA = 0
LTC2203: 128K Point FFT,
fIN = 1MHz, –10dBFS, PGA = 0
LTC2203: 128K Point FFT,
fIN = 1MHz, –20dBFS, PGA = 0
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
0
2
±
6
8
10
12
FREQUENCY(MHz)
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 GO±
22032 GO5
22032 GO6
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –20dBFS, PGA = 0,
Internal Dither “Off”
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –1dBFS, PGA = 0
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –10dBFS, PGA = 0
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
2
±
6
8
10
12
8
8
0
2
±
6
10
12
0
2
±
6
10
12
FREQUENCY(MHz)
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 GO7
22032 GO8
22032 GO9
22032fb
7
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –20dBFS, PGA = 0,
Internal Dither “On”
LTC2203: 32K Point 2-Tone FFT,
fIN = 4.9MHz and 30.1MHz,
–7dBFS, PGA = 0
LTC2203: 32K Point 2-Tone FFT,
fIN = 4.9MHz and 30.1MHz,
–15dBFS, PGA = 0
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
0
2
±
6
8
10
12
FREQUENCY(MHz)
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 G12
22032 G10
22032 G11
LTC2203: SFDR vs Input Level,
fIN = 5MHz, PGA = 0, Dither “Off”
LTC2203: SFDR vs Input Level,
fIN = 5MHz, PGA = 0, Dither “On”
LTC2203: 32K Point FFT,
fIN = 12.4MHz, –1dBFS, PGA = 0
1±0
120
1±0
120
0
–10
–20
–30
–±0
100
100
–50
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
80
60
±0
20
80
60
±0
20
0
0
–60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–70
–70
0
2
±
6
8
10
12
FREQUENCY(MHz)
22032 G15
22032 G13
22032 G1±
LTC2203: SFDR vs Input Level,
fIN = 12.7MHz, PGA = 0,
Dither “Off”
LTC2203: 32K Point FFT,
fIN = 12.4MHz, –10dBFS, PGA = 0
LTC2203: 32K Point FFT,
fIN = 12.4MHz, –20dBFS, PGA = 0
0
–10
–20
0
–10
–20
1±0
120
–30
–30
–±0
–50
–±0
–50
100
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
80
60
±0
20
0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 G16
22032 G17
22032 G18
22032fb
8
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: SFDR vs Input Level,
fIN = 12.7MHz, PGA = 0,
Dither “On”
LTC2203: 32K Point FFT,
fIN = 30MHz, –1dBFS, PGA = 1
LTC2203: 32K Point FFT,
fIN = 30MHz, –10dBFS, PGA = 1
0
–10
0
–10
1±0
120
–20
–20
–30
–30
–±0
–50
–±0
–50
100
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
80
60
±0
20
0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 G20
22032 G21
22032 G19
LTC2203: SFDR vs Input Level,
fIN = 30.1MHz, PGA = 0,
Dither “Off”
LTC2203: SFDR vs Input Level,
fIN = 30.1MHz, PGA = 0,
Dither “On”
LTC2203: 32K Point FFT,
fIN = 30MHz, –20dBFS, PGA = 1
0
–10
–20
1±0
120
1±0
120
–30
–±0
–50
100
100
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
80
60
±0
20
80
60
±0
20
0
0
0
2
±
6
8
10
12
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–80
–70
FREQUENCY(MHz)
22032 G22
22032 G23
22032 G2±
LTC2203: 32K Point FFT,
LTC2203: 32K Point FFT,
fIN = 70.1MHz, –10dBFS, PGA = 1
LTC2203: 32K Point FFT,
fIN = 70.1MHz, –20dBFS, PGA = 1
f
IN = 70.1MHz, –1dBFS, PGA = 1
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
0
2
±
6
8
10
12
FREQUENCY(MHz)
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 G25
22032 G26
22032 G27
22032fb
9
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: SFDR vs Input Level,
fIN = 70.1MHz, PGA = 0,
Dither “Off”
LTC2203: 32K Point 2-Tone FFT,
fIN = 44.9MHz and 70.1MHz,
–7dBFS, PGA = 0
LTC2203: 32K Point 2-Tone FFT,
fIN = 44.9MHz and 70.1MHz,
–15dBFS, PGA = 0
0
–10
–20
0
–10
–20
1±0
120
–30
–30
–±0
–50
–±0
–50
100
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
–60
–70
–80
–90
–100
–110
–120
–130
–1±0
80
60
±0
20
0
0
2
±
6
8
10
12
0
2
±
6
8
10
12
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY(MHz)
FREQUENCY(MHz)
22032 G28
22032 G29
22023 G30
LTC2203: SFDR vs Input Level,
fIN = 70.1MHz, PGA = 0,
Dither “On”
LTC2203: SFDR (HD2 or HD3) vs
Input Frequency
LTC2203: SNR vs Input Frequency
1±0
120
82
81
80
79
78
77
76
75
7±
110
105
100
95
PGA = 0
100
PGA = 1
80
60
±0
20
90
85
PGA = 1
PGA = 0
80
75
70
0
73
20
±0
80
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
0
100
60
0
20
±0
60
1±0
80 100 120
ꢀNPUT FREQUENCY (MHz)
ꢀNPUT FREQUENCY (MHz)
22032 G31
22023 G32
22023 G33
LTC2203: SNR and SFDR vs
Sample Rate
LTC2203: SNR and SFDR vs
Supply Voltage (VDD), fIN = 5MHz
LTC2203: IVDD vs Sample Rate,
5MHz Sine Wave, –1dBFS
110
105
75
70
65
60
55
50
110
105
RATED MAX
SFDR
UPPER LꢀMꢀT
LOWER LꢀMꢀT
SFDR
100
100
95
90
85
80
95
90
85
80
SNR
SNR
75
75
0
15
25 30 35 ±0 ±5 50
5
10
20
2.8 2.9 3.0 3.1 3.2 3.3 3.± 3.5 3.6
0
5
15
SAMPLE RATE (Msps)
20
25
10
SAMPLE RATE (Msps)
SUPPLY VOLTAGE (V)
22023 G36
22023 G3±
22023 G35
22032fb
10
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: Normalized Full
LTC2203: SFDR vs Input Common
Mode Voltage, fIN = 5MHz,
–1dBFS, PGA = 0
Scale vs Temperature, Internal
Reference, 5 Units
LTC2203: Offset Voltage vs
Temperature, 5 Units
6
±
2
0
110
1.01
1.005
1
105
100
95
90
85
80
75
70
65
60
–2
–±
–6
0.995
0.99
±0
TEMPERATURE (˚C)
80
0.5
0.75
1.25 1.50 1.75
2
–±0
–20
0
20
60
1
–±0
–20
0
20
±0
60
80
TEMPERATURE (°C)
ꢀNPUT COMMON MODE VOLTAGE (V)
22023 G38
22023 G39
22023 G37
LTC2202: Integral Nonlinearity
(INL) vs Output Code
LTC2202: Differential Nonlinearity
(DNL) vs Output Code
LTC2202: AC Grounded Input
Histogram (256K Samples)
1.0
0.8
0.6
0.±
0.2
0
2.0
1.5
50000
±5000
±0000
35000
30000
25000
20000
15000
10000
5000
1.0
0.5
0
0.2
0.±
0.6
0.8
1.0
–0.5
–1.0
–1.5
–2.0
0
32768
CODE
0
1638±
±9152
65536
0
1638±
32768
CODE
±9152
65536
32793
32797 32801 32805 32809
OUTPUT CODE
22023 G40
22023 G±1
22023 G±2
LTC2202: 128K Point FFT,
fIN = 5.1MHz, –20dBFS, PGA = 0,
Internal Dither “Off”
LTC2202: 128K Point FFT,
LTC2202: 128K Point FFT,
fIN = 5.1MHz, –10dBFS, PGA = 0
f
IN = 5.1MHz, –1dBFS, PGA = 0
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
1
2
3
±
5
0
1
2
3
±
5
0
1
2
3
±
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
22023 G±5
22023 G±3
22023 G±±
22032fb
11
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: 128K Point FFT,
fIN = 5.1MHz, –20dBFS, PGA = 0,
Internal Dither “On”
LTC2202: 32K Point 2-Tone FFT,
fIN = 5.1MHz and 15.2MHz,
–7dBFS, PGA = 0
LTC2202: 32K Point 2-Tone FFT,
fIN = 5.1MHz and 15.2MHz,
–15dBFS, PGA = 0
0
–10
0
–10
0
–10
–20
–30
–±0
–50
–60
–70
–20
–30
–±0
–50
–60
–70
–20
–30
–±0
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
1
2
3
±
5
0
1
2
3
±
5
0
1
2
3
±
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
22023 G±7
22023 G±8
22023 G±6
LTC2202: SFDR vs Input Level,
fIN = 5MHz, PGA = 0, Dither “Off”
LTC2202: SFDR vs Input Level,
fIN = 5MHz, PGA = 0, Dither “On”
LTC2202: 32K Point FFT,
fIN = 12.4MHz, –1dBFS, PGA = 0
0
–10
–20
–30
–±0
–50
–60
–70
–80
1±0
120
100
80
120
100
80
60
±0
20
0
60
–90
–100
–110
–120
–130
–1±0
±0
20
0
5
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
0
1
2
3
±
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY (MHz)
22023 G±9
22023 G51
22023 G50
LTC2202: SFDR vs Input Level,
fIN = 12.4MHz, PGA = 0,
Dither “Off
LTC2202: 32K Point FFT,
LTC2202: 32K Point FFT,
fIN = 12.4MHz, –10dBFS, PGA = 0
fIN = 12.4MHz, –20dBFS, PGA = 0
0
–10
–20
–30
–±0
–50
–60
–70
–80
0
–10
–20
–30
–±0
–50
–60
–70
–80
120
100
80
60
±0
20
0
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
1
2
3
±
5
0
1
2
3
±
5
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY (MHz)
FREQUENCY (MHz)
22023 G5±
22023 G52
22023 G53
22032fb
12
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: 32K Point FFT,
fIN = 30.5MHz, –1dBFS, PGA = 1
LTC2202: 32K Point FFT,
fIN = 30.5MHz, –10dBFS, PGA = 1
LTC2202: 32K Point FFT,
fIN = 30.5MHz, –20dBFS, PGA = 1
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–±0
–±0
–±0
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
1
2
3
±
5
0
1
2
3
±
5
0
1
2
3
±
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
22023 G55
22023 G56
22023 G57
LTC2202: SFDR vs Input Level,
IN = 30.1MHz, PGA = 0,
Dither “Off”
LTC2202: SFDR vs Input Level,
fIN = 30.1MHz, PGA = 0,
Dither “On”
f
LTC2202: 32K Point FFT,
fIN = 70.1MHz, –1dBFS, PGA = 1
0
–10
–20
–30
–±0
1±0
120
100
80
1±0
120
100
80
–50
–60
–70
–80
60
60
–90
–100
–110
–120
–130
–1±0
±0
±0
20
20
0
0
0
1
2
3
±
5
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–70 –60 –50 –±0 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
FREQUENCY (MHz)
22023 G60
22023 G58
22023 G59
LTC2202: 32K Point FFT,
fIN = 70.1MHz, –10dBFS, PGA = 1
LTC2202: 32K Point FFT,
fIN = 70.1MHz, –20dBFS, PGA = 1
0
–10
0
–10
–20
–20
–30
–30
–±0
–±0
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
0
1
2
3
±
5
0
1
2
3
±
5
FREQUENCY (MHz)
FREQUENCY (MHz)
22023 G61
22023 G62
22032fb
13
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: 32K Point 2-Tone FFT,
fIN = 60.2MHz and 70.1MHz,
–7dBFS, PGA = 0
LTC2202: 32K Point 2-Tone FFT,
fIN = 60.2MHz and 70.1MHz,
–15dBFS, PGA = 0
LTC2202: SFDR vs Input Level,
fIN = 70.1MHz, PGA = 0,
Dither “Off”
0
–10
–20
–30
–±0
–50
–60
–70
0
–10
–20
–30
–±0
–50
–60
–70
1±0
120
100
80
–80
–90
–80
–90
60
–100
–110
–120
–130
–1±0
–100
–110
–120
–130
–1±0
±0
20
0
0
2
±
0
2
±
–30 –20
–80 –70 –60 –50 –±0
–10
0
FREQUENCY (MHz)
FREQUENCY (MHz)
ꢀNPUT LEVEL (dBFS)
22023 G63
22023 G6±
22023 G65
LTC2202: SFDR vs Input Level,
IN = 70.1MHz, PGA = 0,
Dither “On”
f
LTC2202: SFDR (HD2 or HD3) vs
Input Frequency
LTC2202: SNR vs Input Frequency
1±0
120
100
80
82
81
80
79
78
77
76
75
7±
110
105
100
95
PGA = 0
PGA = 1
90
85
60
PGA = 1
PGA = 0
±0
80
75
70
20
0
73
–30 –20
–80 –70 –60 –50 –±0
–10
0
20
±0
80
0
100
60
0
20
±0
60
1±0
80 100 120
ꢀNPUT LEVEL (dBFS)
ꢀNPUT FREQUENCY (MHz)
ꢀNPUT FREQUENCY (MHz)
22023 G66
22023 G67
22023 G68
LTC2202: SNR and SFDR vs
Sample Rate
LTC2202: SNR and SFDR vs
Supply Voltage (VDD), fIN = 5MHz
110
105
110
105
UPPER LꢀMꢀT
LOWER LꢀMꢀT
RATED MAX
SFDR
SFDR
100
100
95
90
85
80
95
90
85
80
SNR
SNR
75
0
75
2.8 2.9 3.0 3.1 3.2 3.3 3.± 3.5 3.6
±
8
12
20
16
SUPPLY VOLTAGE (V)
SAMPLE RATE (Msps)
22023 G70
22023 G69
22032fb
14
LTC2203/LTC2202
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: Normalized Full
Scale vs Temperature, Internal
Reference, 5 Units
LTC2202: IVDD vs Sample Rate,
5MHz Sine Wave, –1dBFS
50
±9
±8
±7
±6
±5
±±
±3
±2
±1
±0
1.01
1.005
1
0.995
0.99
0
2
±
6
8
10
–±0
–20
0
20
±0
60
80
TEMPERATURE (°C)
SAMPLE RATE (Msps)
22023 G72
22023 G71
LTC2202: SFDR vs Input Common
Mode Voltage, fIN = 5MHz,
–1dBFS, PGA = 0
LTC2202: Offset Voltage vs
Temperature, 5 Units
110
105
100
95
6
±
2
0
90
85
80
–2
–±
–6
75
70
65
60
0.5
0.75
1.25 1.50 1.75
2
1
±0
TEMPERATURE (˚C)
80
–±0
–20
0
20
60
ꢀNPUT COMMON MODE VOLTAGE (V)
22023 G7±
22023 G73
22032fb
15
LTC2203/LTC2202
U
U
U
PI FU CTIO S
SENSE(Pin1):ReferenceModeSelectandExternalRefer-
Drivers. Bypass to ground with 0.1µF capacitor.
ence ꢀnput. Tie SENSE to V with 1k Ω or less to select
–
–
DD
CLKOUT (Pin29):DataValidOutput.CLKOUT willtoggle
theinternal2.5Vbandgapreference.Anexternalreference
of 2.5V or 1.25V may be used; both reference values will
set a full scale ADC range of 2.5V (PGA = 0).
at the sample rate. Latch the data on the falling edge of
–
CLKOUT .
+
+
CLKOUT (Pin 30): ꢀnverted Data Valid Output. CLKOUT
V
CM
(Pin2):1.25VOutput.Optimumvoltageforinputcom-
will toggle at the sample rate. Latch the data on the rising
mon mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
+
edge of CLKOUT .
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under flow has occurred.
V
(Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
DD
Bypass to GND with 0.1µF ceramic chip capacitors.
OE (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
GND (Pins 5, 8, 9, 11, 15, 48, 49): ADC Power
Ground.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
+
A
IN
A
IN
(Pin 6): Positive Differential Analog ꢀnput.
(Pin 7): Negative Differential Analog ꢀnput.
–
cyclestabilizer.ConnectingMODEto1/3V selectsoffset
DD
CLK (Pin 10): Clock ꢀnput. The hold phase of the sample-
and-hold circuit begins on the falling edge. The output
data may be latched on the rising edge of CLK.
binary output format and enables the clock duty cycle sta-
bilizer.ConnectingMODEto2/3V selects2’scomplement
DD
output format and enables the clock duty cycle stabilizer.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
Connecting MODE to V selects 2’s complement output
DD
format and disables the clock duty cycle stabilizer.
RAND(Pin46):DigitalOutputRandomizationSelectionPin.
RAND low results in normal operation. RAND high selects
D1-D15 to be EXCLUSꢀVE-ORed with D0 (the LSB). The
outputcanbedecodedbyagainapplyinganXORoperation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
DITH (Pin 17): ꢀnternal Dither Enable Pin. DꢀTH = low
disables internal dither. DꢀTH = high enables internal
dither. Refer to ꢀnternal Dither section of this data sheet
for details on dither operation.
D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital
PGA(Pin47):ProgrammableGainAmplifierControlPin.Low
Outputs. D15 is the MSB.
selects a front-end gain of 1, input range of 2.5V . High
P-P
selects a front-end gain of 1.5, input range of 1.667V
.
OGND (Pins 23, 31 and 38): Output Driver Ground.
P-P
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
OV (Pins24,25,36,37):PositiveSupplyfortheOutput
DD
22032fb
16
LTC2203/LTC2202
W
BLOCK DIAGRA
+
A
A
ꢀN
ꢀN
V
DD
ꢀNPUT
S/H
FꢀRST PꢀPELꢀNED
ADC STAGE
SECOND PꢀPELꢀNED
ADC STAGE
THꢀRD PꢀPELꢀNED
ADC STAGE
FOURTH PꢀPELꢀNED
ADC STAGE
FꢀFTH PꢀPELꢀNED
ADC STAGE
–
GND
DꢀTHER
SꢀGNAL
GENERATOR
CORRECTꢀON LOGꢀC
AND
SHꢀFT REGꢀSTER
ADC CLOCKS
RANGE
SELECT
OV
DD
CLKOUT+
CLKOUT–
OF
SENSE
LOW JꢀTTER
CLOCK
DRꢀVER
ADC
REFERENCE
PGA
D15
D1±
CONTROL
LOGꢀC
OUTPUT
DRꢀVERS
•
•
•
V
CM
BUFFER
D1
D0
VOLTAGE
REFERENCE
22032 F01
OGND
CLK
SHDN PGA RAND M0DE DꢀTH
OE
Figure 1. Functional Block Diagram
22032fb
17
LTC2203/LTC2202
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APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
ꢀf two pure sine waves of frequencies fa and fb are applied
totheADCinput,nonlinearitiesintheADCtransferfunction
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order ꢀMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order ꢀMD is
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order ꢀMD product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
The signal-to-noise (SNR) is the ratio between the RMS
amplitudeofthefundamentalinputfrequencyandtheRMS
amplitude of all other frequency components, except the
first five harmonics.
Full Power Bandwidth
Total Harmonic Distortion
The Full Power bandwidth is that input frequency at which
theamplitudeofthereconstructedfundamentalisreduced
by 3dB for a full scale input signal.
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
Aperture Delay Time
The time from when CLK reaches 0.±5 of VDD to the
instant that the input signal is held by the sample-and-
hold circuit.
2
2
2
2
THD = –20Log
(
√
(V + V + V + ... V )/V
)
2
3
±
N
1
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
Aperture Delay Jitter
2
N
through nth harmonics.
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
Intermodulation Distortion
ꢀf the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (ꢀMD) in addition to
THD. ꢀMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
SNR
= –20log (2
π
• f • t
ꢀN JꢀTTER
)
JꢀTTER
22032fb
18
LTC2203/LTC2202
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
TheLTC2203/LTC2202areCMOSpipelinedmultistepcon-
verterswithafront-endPGA.AsshowninFigure1,thecon-
verterhasfivepipelinedADCstages;asampledanaloginput
will result in a digitized value seven cycles later (see the
TimingDiagramsection).Theanaloginputisdifferentialfor
improvedcommonmodenoiseimmunityandtomaximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample-and-hold
circuit.
Figure 2 shows an equivalent circuit for the LTC2203/
LTC2202 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (C
) through NMOS transitors. The
SAMPLE
capacitors shown attached to each input (C
) are
PARASꢀTꢀC
the summation of all other capacitance associated with
each input.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. ꢀn
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
LTC2203/02
V
DD
C
C
SAMPLE
9.1pF
+
A
ꢀN
C
PARASꢀTꢀC
1.±pF
V
DD
SAMPLE
9.1pF
–
A
ꢀN
C
1.±pF
PARASꢀTꢀC
The phase of operation is determined by the state of the
CLK input pin.
When CLK is high, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that CLK transitions from high to low, the voltage
on the sample capacitors is held. While CLK is low, the
held input voltage is buffered by the S/H amplifier which
drivesthefirstpipelinedADCstage.Thefirststageacquires
the output of the S/H amplifier during the low phase of
CLK. When CLK goes back high, the first stage produces
its residue which is acquired by the second stage. At the
sametime,theinputS/Hgoesbacktoacquiringtheanalog
input. When CLK goes low, the second stage produces its
residue which is acquired by the third stage. An identi-
cal process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
CLK
22032 F02
Figure 2. Equivalent Input Circuit
During the sample phase when CLK is high, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When CLK transitions from high to low, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when CLK is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As CLK
transitions from low to high, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time at the input of
the converter. ꢀf the change between the last sample and
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
22032fb
19
LTC2203/LTC2202
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APPLICATIO S I FOR ATIO
the new sample is small, the charging glitch seen at the
input will be small. ꢀf the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
than 50Ω can reduce the input bandwidth and increase
high frequency distortion. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input may
swing ±0.625V for the 2.5V range (PGA = 0) or ±0.±17V
for the 1.667V range (PGA = 1), around a common mode
V
CM
voltage of 1.25V. The V output pin (Pin 3) is designed
CM
T1
1:1
+
A
to provide the common mode bias level. V can be tied
ꢀN
ANALOG
ꢀNPUT
CM
LTC2203/02
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
12pF
12pF
driver circuit. The V pin must be bypassed to ground
CM
–
A
ꢀN
close to the ADC with 2.2µF or greater.
T1 = COꢀLCRAFT WBCꢀ-ꢀT OR
MA/COM ETC1-1T.
12pF
22032 F03
Input Drive Impedence
RESꢀSTORS, CAPACꢀTORS ARE
0±02 PACKAGE SꢀZE, EXCEPT 2.2μF.
As with all high performance, high speed ADCs the
dynamic performance of the LTC2203/LTC2202 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and
input reactance can influence SFDR. At the rising edge of
CLK the sample and hold circuit will connect the 9.1pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when CLK falls, hold-
ing the sampled input on the sampling capacitor. ꢀdeally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 1MHz to 100MHz
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure ± shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
muchbetterhighfrequencyresponseandbalancethanflux
coupled center tap transformers. Coupling capacitors are
added at the ground and input primary terminals to allow
the secondary terminals to be biased at 1.25V.
1/(2F ); however, this is not always possible and the
CLK
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
V
CM
Forthebestperformanceitisrecomendedtohaveasource
impedence of 100Ω or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
2.2μF
0.1μF
+
–
A
A
ꢀN
ꢀN
ANALOG
ꢀNPUT
LTC2203/02
0.1μF
±.7pF
T1
1:1
±.7pF
0.1μF
INPUT DRIVE CIRCUITS
±.7pF
T1 = MA/COM ETC1-1-13.
RESꢀSTORS, CAPACꢀTORS
ARE 0±02 PACKAGE SꢀZE,
EXCEPT 2.2F.
22032 F0±
Figure 3 shows the LTC2203/LTC2202 being driven by
an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with V , setting the
ADC input signal at its optimum DC level. Figure 3 shows
Figure 4. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 50MHz to 250MHz
CM
22032fb
20
LTC2203/LTC2202
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Figure 5 demonstrates the use of an LTC199± differential
amplifier to convert a single ended input signal into a
differential input signal. The advantage of this method is
that it provides low frequency input response; however,
the limited gain bandwidth of any op amp will limit the
SFDR at high input frequencies.
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
LTC2203/02
RANGE
SELECT
V
CM
AND GAꢀN
CONTROL
TꢀE TO V TO USE
DD
2.2 μF
ꢀNTERNAL
ADC
REFERENCE
ꢀNTERNAL 2.5V
REFERENCE
±99Ω
S
100pF
OR ꢀNPUT FOR
EXTERNAL 2.5V
REFERENCE
LTC2203/02
SENSE
+
523Ω
A
A
ꢀN
PGA
–
+
OR ꢀNPUT FOR
EXTERNAL 1.25V
REFERENCE
100pF
CM LT199±
–
±99Ω
–
+
ꢀN
2.5V
BANDGAP
REFERENCE
53.6Ω
100pF
22032 F05
±99Ω
V
CM
1.25V
BUFFER
2.2μF
Figure 5. DC Coupled Input with Differential Amplifier
22032 F07
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
Figure 6. Reference Circuit
TheSENSEpincanbedriven±5ꢁaroundthenominal2.5V
or 1.25V external reference input. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
Reference Operation
Figure 6 shows the LTC2203/LTC2202 reference circuitry
consisting of a 2.5V bandgap reference, a programmable
gain amplifier and control circuit. The LTC2203/LTC2202
has three modes of reference operation: ꢀnternal Refer-
ence, 1.25V external reference or 2.5V external reference.
SENSE pin should be tied to V as close to the converter
DD
as possible. ꢀf the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with at least a 1µF ceramic capacitor.
To use the internal reference, tie the SENSE pin to V . To
DD
use the external reference, simply apply either a 1.25V or
2.5V referencevoltagetotheSENSEinputpin. Both1.25V
and 2.5V applied to SENSE will result in a full scale range
V
CM
1.25V
2.2μF
of 2.5V (PGA = 0). A 1.25V output, V , is provided
P-P
CM
LTC2203/02
for a common mode bias for input drive circuitry. An
SENSE
6
2
3.3V
1μF
LT1±61-2.5
±
external bypass capacitor is required for the V output.
CM
2.2μF
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stablewithoutthiscapacitor. Theminimumvaluerequired
for stability is 2.2µF.
22032 F08
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
22032fb
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LTC2203/LTC2202
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PGA Pin
ꢀn applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. ꢀt is also helpful to drive the CLK pin with a
low-jitter high frequency source which has been divided
down to the appropriate sample rate. ꢀf the ADC is clocked
with a sinusoidal signal, filter the CLK signal to reduce
wideband noise and distortion products generated by
the source.
ThePGApinselectsbetweentwogainsettingsfortheADC
front-end.PGA=0selectsaninputrangeof2.5V ;PGA=
P-P
1selectsaninputrangeof1.667V . The2.5Vinputrange
P-P
hasthebestSNR;however, thedistortionwillbehigherfor
inputfrequenciesabove100MHz.Forapplicationswithhigh
input frequencies, the low input range will have improved
distortion; however, the SNR will be 2.±dB worse. See the
Typical Performance Characteristics section.
Maximum and Minimum Conversion Rates
Driving the Clock Input
ThemaximumconversionratefortheLTC2203is25Msps.
ThemaximumconversionratefortheLTC2202is10Msps.
FortheADCtooperateproperlytheCLKsignalshouldhave
a50ꢁ(±5ꢁ)dutycycle. Eachhalfcyclemusthaveatleast
18.9ns for the LTC2203 internal circuitry to have enough
settling time for proper operation. For the LTC2202, each
half cycle must be at least ±0ns.
The CLK input can be driven directly with a CMOS or TTL
levelsignal.Asinusoidalclockcanalsobeusedalongwitha
low-jitter squaring circuit before the CLK pin (Figure 8).
CLEAN 3.3V
SUPPLY
±.7μF
An on-chip clock duty cycle stabilizer may be activated if
theinputclockdoesnothavea50ꢁdutycycle.Thiscircuit
usesthefallingedgeofCLKpintosampletheanaloginput.
The rising edge of CLK is ignored and an internal rising
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30ꢁ to 70ꢁ and the clock duty
cycle stabilizer will maintain a constant 50ꢁ internal duty
cycle. ꢀf the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
FERRꢀTE
BEAD
0.1μF
1k
0.1μF
SꢀNUSOꢀDAL
CLOCK
CLK
LTC2203/02
ꢀNPUT
56Ω
NC7SVU0±
1k
22032 F09
Figure 8. Sinusoidal Single-Ended CLK Drive
connected to 1/3V or 2/3V using external resistors.
DD
DD
The noise performance of the LTC2203/2202 can depend
on the clock signal quality as much as on the analog
input. Any noise present on the clock signal will result in
additional aperture jitter that will be RMS summed with
the inherent ADC aperture jitter.
The lower limit of the LTC2203/LTC2202 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
dischargethecapacitors.Thespecifiedminimumoperating
frequency for the LTC2203/LTC2202 is 1Msps.
22032fb
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DIGITAL OUTPUTS
Data Format
Digital Output Buffers
The LTC2203/LTC2202 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS Mode. Each buffer is powered by OVDD
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as 50Ω
to external circuitry and eliminates the need for external
damping resistors.
level logic input, centered at 0, 1/3V , 2/3V and V .
DD
DD
DD
An external resistor divider can be user to set the 1/3V
DD
and 2/3V logic levels. Table 1 shows the logic states
DD
for the MODE pin.
Table 1. MODE Pin Function
Clock Duty
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2203/LTC2202 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required
since the ADC has a series resistor of ±3Ω on chip.
MODE
Output Format
Offset Binary
Cycle Stabilizer
0(GND)
Off
On
On
Off
1/3V
Offset Binary
DD
2/3V
2’s Complement
2’s Complement
DD
V
DD
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
Lower OV voltages will also help reduce interference
DD
Output Clock
from the digital outputs.
The ADC has a delayed version of the CLK input available
+
as a digital output. Both a noninverted version, CLKOUT
LTC2203/02
–
OV
DD
and an inverted version CLKOUT are provided. The
0.5V
+
–
TO 3.6V
V
V
CLKOUT /CLKOUT can be used to synchronize the con-
verter data to the digital system. This is necesary when
using a sinusoidal clock. Data can be latched on the ris-
ing edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
DD
DD
0.1μF
OV
DD
DATA
FROM
LATCH
PREDRꢀVER
LOGꢀC
±3Ω
TYPꢀCAL
DATA
OUTPUT
OGND
22032 F10
Figure 9. Equivalent Circuit for a Digital Output Buffer
22032fb
23
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Digital Output Randomizer
The digital output is “Randomized” by applying an exclu-
sive-ORlogicoperationbetweentheLSBandallotherdata
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
ꢀnterference from the ADC digital outputs is sometimes
unavoidable. ꢀnterference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
offchip,theseunwantedtonescanberandomized,trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
LTC2203/02
CLKOUT
CLKOUT
OF
OF
D15
D15/D0
D1±/D0
D1±
•
•
•
D2
D1
D2/D0
D1/D0
RAND = HꢀGH,
RAND
SCRAMBLE
ENABLED
D0
D0
22032 F11
Figure 10. Functional Equivalent of Digital Output Randomizer
22032fb
24
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
a 1.8V supply, then OV should be tied to that same 1.8V
DD
supply.ꢀnCMOSmodeOV canbepoweredwithanylogic
DD
supply for the digital output buffers, OV , should be tied
voltage up to 3.6V. OGND can be powered with any voltage
DD
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered by
from ground up to 1V and must be less than OV . The
DD
logic outputs will swing between OGND and OV .
DD
PC BOARD
FPGA
CLKOUT
OF
D15/D0
D15
D1±
LTC2203/02
D1±/D0
•
•
•
D2/D0
D1/D0
D2
D1
D0
D0
22032 F12
Figure 11. Descrambling a Scrambled Digital Output
22032fb
25
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
Grounding and Bypassing
Internal Dither
TheLTC2203/LTC2202requireaprintedcircuitboardwitha
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2203/LTC2202 has been optimized for a flowthrough
layout so that the interaction between inputs and digital
outputs is minimized. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. ꢀn particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
The LTC2203/LTC2202 are 16-bit ADCs with very linear
transfer functions; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the
input’s location on the ADC transfer curve, resulting in
improved SFDR for low signal levels.
As shown in Figure 12, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. ꢀf the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
thatdoesleakthroughwillappearaswhitenoise.Thedither
DAC is calibrated to result in less than 0.5dB elevation in
the noise floor of the ADC, as compared to the noise floor
with dither off.
High quality ceramic bypass capacitors should be used
at the V
V
, and OV pins. Bypass capacitors must
DD, CM DD
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2203/LTC2202 differential inputs should run
parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
LTC2203/02
CLKOUT+
CLKOUT–
Heat Transfer
+
OF
D15
•
A
ꢀN
16-BꢀT
PꢀPELꢀNED
ADC CORE
DꢀGꢀTAL
SUMMATꢀON
Most of the heat generated by the LTC2203/LTC2202 is
transferred from the die through the bottom-side exposed
pad. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. ꢀt is critical that the exposed pad and all
ground pins are connected to a ground plane of sufficient
area with as many vias as possible.
ANALOG
ꢀNPUT
OUTPUT
DRꢀVERS
S/H
•
AMP
•
D0
–
A
ꢀN
CLOCK/DUTY
CYCLE
CONTROL
MULTꢀBꢀT DEEP
PSEUDO-RANDOM
NUMBER
PRECꢀSꢀON
DAC
GENERATOR
22032 F13
CLK
DꢀTH
DꢀTHER ENABLE
HꢀGH = DꢀTHER ON
LOW = DꢀTHER OFF
Figure 12. Functional Equivalent Block Diagram of
Internal Dither Circuit
22032fb
26
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
G N D
± 9
2 ±
D D
D D
O V
O V
3 7
O G N D
O G N D
2 3
2 2
2 1
2 0
3 8
3 9
± 0
± 1
D 1 2
D ±
D 3
D 2
D 1
D 1 3
D 1 ±
D 1 5
1 9
± 2
O F
D 0
1 8
1 7
± 3
± ±
O E
D ꢀ T H
S H D N
G N D
M O D E
R A N D
1 6
1 5
± 5
± 6
D D
V
P G A
G N D
1 ±
1 3
± 7
± 8
D D
V
22032fb
27
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
Silkscreen Top
Silkscreen Topside
22032fb
28
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
Inner Layer 2
Inner Layer 3
22032fb
29
LTC2203/LTC2202
U
W U U
APPLICATIO S I FOR ATIO
Silkscreen Bottom Side
Silkscreen Bottom
22032fb
30
LTC2203/LTC2202
U
PACKAGE DESCRIPTIO
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-170±)
0.70 0.05
5.15 0.05
5.50 REF
6.10 0.05 7.50 0.05
(± SꢀDES)
5.15 0.05
PACKAGE OUTLꢀNE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PꢀTCH AND DꢀMENSꢀONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.115
TYP
7.00 0.10
(± SꢀDES)
R = 0.10
TYP
±7 ±8
0.±0 0.10
PꢀN 1 TOP MARK
(SEE NOTE 6)
1
2
PꢀN 1
CHAMFER
C = 0.35
5.15 0.10
5.50 REF
(±-SꢀDES)
5.15 0.10
(UK±8) QFN 0±06 REV C
0.200 REF
0.25 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWꢀNG CONFORMS TO JEDEC PACKAGE OUTLꢀNE MO-220 VARꢀATꢀON (WKKD-2)
2. DRAWꢀNG NOT TO SCALE
BOTTOM VꢀEW—EXPOSED PAD
3. ALL DꢀMENSꢀONS ARE ꢀN MꢀLLꢀMETERS
±. DꢀMENSꢀONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT ꢀNCLUDE
MOLD FLASH. MOLD FLASH, ꢀF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SꢀDE, ꢀF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA ꢀS ONLY A REFERENCE FOR PꢀN 1 LOCATꢀON ON THE TOP AND BOTTOM OF PACKAGE
22032fb
ꢀnformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2203/LTC2202
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PART NUMBER DESCRIPTION
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1±-Bit, 125Msps, 3V ADC, Lowest Power
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±80mW, 79.1dB SNR, 100dB SFDR, ±8-Pin QFN
610mW, 79dB SNR, 100dB SFDR, ±8-Pin QFN
725mW, 77.9dB SNR, 100dB SFDR, ±8-Pin QFN
900mW, 77.9dB SNR, 100dB SFDR, ±8-Pin QFN
1250mW, 77.1dB SNR, 100dB SFDR, 6±-Pin QFN
910mW, 67.7dB SNR, 80dB SFDR, 6±-Pin QFN
630mW, 67.6dB SNR, 8±dB SFDR, ±8-Pin QFN
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DC to 3GHz, 21dBm ꢀꢀP3, ꢀntegrated LO Buffer
DC-3GHz High Signal Level
Downconverting Mixer
LT551±
LT5515
LT5516
LT5517
LT5522
Ultralow Distortion ꢀF Amplifier/ADC Driver
with Digitally Controlled Gain
1.5GHz to 2.5GHz Direct Conversion
Quadrature Demodulator
800MHz to 1.5GHz Direct Conversion
Quadrature Demodulator
±0MHz to 900MHz Direct Conversion
Quadrature Demodulator
±50MHz to 1dB BW, ±7dB OꢀP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
High ꢀꢀP3: 20dBm at 1.9GHz, ꢀntegrated LO Quadrature Generator
High ꢀꢀP3: 21.5dBm at 900MHz, ꢀntegrated LO Quadrature Generator
High ꢀꢀP3: 21dBm at 800MHz, ꢀntegrated LO Quadrature Generator
600MHz to 2.7GHz High Linearity
Downconverting Mixer
±.5V to 5.25V Supply, 25dBm ꢀꢀP3 at 900MHz. NF = 12.5dB, 50Ω Single Ended
RF and LO Ports
22032fb
LT 0507 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7±17
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(±08) ±32-1900 FAX: (±08) ±3±-0507 www.linear.com
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