LTC2217IUP-TRPBF_技术文档

LTC2217

16-Bit, 105Msps

Low Noise ADC

FEATURES

DESCRIPTION

■

Sample Rate: 105Msps

TheLTC^®2217isa105Mspssampling16-bitA/Dconverter

designedfordigitizinghighfrequency,widedynamicrange

signals with input frequencies up to 400MHz. The input

■

81.3dBFS Noise Floor

■

100dB SFDR

■

SFDR >90dB at 70MHz

range of the ADC is ﬁxed at 2.75V

.

P-P

■

85fs

Jitter

RMS

The LTC2217 is perfect for demanding communications

applications,withACperformancethatincludes81.3dBFS

Noise Floor and 100dB spurious free dynamic range

■

2.75V Input Range

P-P

400MHz Full Power Bandwidth S/H

Optional Internal Dither

(SFDR). Ultra low jitter of 85fs

allows undersampling

RMS

Optional Data Output Randomizer

LVDS or CMOS Outputs

Single 3.3V Supply

Power Dissipation: 1.19W

Clock Duty Cycle Stabilizer

Pin Compatible with LTC2208

64-Pin (9mm × 9mm) QFN Package

ofhighinputfrequencieswhilemaintainingexcellentnoise

performance.MaximumDCspeciﬁcationsinclude 3.5LSB

INL, 1LSB DNL (no missing codes).

The digital output can be either differential LVDS or

single-ended CMOS. There are two format options for the

CMOS outputs: a single bus running at the full data rate or

demultiplexed buses running at half data rate. A separate

output power supply allows the CMOS output swing to

range from 0.5V to 3.6V.

APPLICATIONS

■

Telecommunications

+

–

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed with a wide range of

clock duty cycles.

■

Receivers

■

Cellular Base Stations

■

Spectrum Analysis

■

Imaging Systems

■

ATE

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Patents Pending.

TYPICAL APPLICATION

3.3V

SENSE

64k Point FFT,

F_IN= 4.9MHz, –1dBFS

OV

DD

1.575V

COMMON MODE

BIAS VOLTAGE

INTERNAL ADC

REFERENCE

GENERATOR

V

0.5V TO 3.6V

1μF

CM

0

–10

2.2μF

–20

–30

–40

–50

–60

–70

–80

OF

CLKOUT

D15

+

AIN

+

16-BIT

PIPELINED

ADC CORE

OUTPUT

DRIVERS

CORRECTION

LOGIC AND

SHIFT REGISTER

CMOS

OR

LVDS

ANALOG

INPUT

S/H

AMP

•

–

AIN

D0

–90

OGND

–100

–110

–120

–130

CLOCK/DUTY

CYCLE

CONTROL

3.3V

1μF

V

DD

1μF

GND

2217 TA01

0

10

20

30

40

50

FREQUENCY (MHz)

+

–

ENC

SHDN DITH MODE LVDS RAND

ADC CONTROL INPUTS

2217 TA01b

2217f

1

LTC2217

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

OV_DD= V_DD(Notes 1 and 2)

TOP VIEW

Supply Voltage (V )...................................–0.3V to 4V

DD

Digital Output Ground Voltage (OGND)........–0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V + 0.3V)

DD

+

SENSE 1

GND 2

48 D11 /DA6

Digital Input Voltage .................... –0.3V to (V + 0.3V)

DD

–

47 D11 /DA5

+

V

3

46 D10 /DA4

Digital Output Voltage................–0.3V to (OV + 0.3V)

CM

GND 4

DD

–

45 D10 /DA3

+

V

5

6

44 D9 /DA2

43 D9 /DA1

42 D8 /DA0

41 D8 /CLKOUTA

40 CLKOUT /CLKOUTB

39 CLKOUT /OFB

38 D7 /DB15

37 D7 /DB14

36 D6 /DB13

35 D6 /DB12

34 D5 /DB11

33 D5 /DB10

Power Dissipation............................................ 2000mW

DD

–

DD

+

GND 7

Operating Temperature Range

+

–

AIN

8

9

65

–

+

LTC2217C ................................................ 0°C to 70°C

LTC2217I .............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 150°C

–

GND 10

GND 11

+

–

ENC 12

–

+

ENC 13

–

GND 14

+

Digital Output Supply Voltage (OV )..........–0.3V to 4V

V

DD

V

DD

15

16

DD

–

T

= 150°C, θ = 20°C/W

JA

JMAX

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

64-Lead (9mm × 9mm) Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

–40°C to 85°C

LTC2217CUP#PBF

LTC2217IUP#PBF

LTC2217CUP#TRPBF

LTC2217IUP#TRPBF

LTC2217UP

LEAD BASED FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC2217CUP

LTC2217IUP

LTC2217CUP#TR

LTC2217IUP#TR

LTC2217UP

64-Lead (9mm × 9mm) Plastic QFN

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

CONVERTER CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

3.5

4

UNITS

LSB

Integral Linearity Error

Differential Linearity Error

Offset Error

Differential Analog Input (Note 5) T = 25°C

1.3

A

●

Differential Analog Input (Note 5)

Differential Analog Input

(Note 6)

1.3

LSB

0.18/–0.22

1

LSB

1.3

4

6

mV

Offset Drift

μV/°C

%FS

●

Gain Error

External Reference

0.3

1

ppm/°C

Full-Scale Drift

Internal Reference

External Reference

–65

12

Transition Noise

External Reference

2

LSB

RMS

2217f

2

LTC2217

ANALOG INPUT ^The● denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

2.75

MAX

UNITS

+

–

V

IN

3.135V ≤ V ≤ 3.465V

V

Analog Input Range (A

–

A

)

IN

DD

P-P

IN

●

V

I

Analog Input Common Mode

Differential Input (Note 7)

1.2

–1

–3

1.575

1.8

1

V

μA

IN, CM

+

–

Analog Input Leakage Current

SENSE Input Leakage Current

0V ≤ A

,

A

≤ V

IN DD

IN

I

0V ≤ SENSE ≤ V

3

SENSE

MODE

LVDS

DD

MODE Pin Pull-Down Current to GND

LVDS Pin Pull-Down Current to GND

Analog Input Capacitance

10

+

–

C

Sample Mode ENC < ENC

9.1

1.8

pF

IN

+

–

Hold Mode ENC > ENC

t

Sample-and-Hold

0.35

ns

fs RMS

dB

AP

Acquisition Delay Time

Sample-and-Hold

Aperture Jitter

85

JITTER

+

–

CMRR

Analog Input

Common Mode Rejection Ratio

1.2V < (A = A ) <1.8V

80

IN

BW-3dB

Full Power Bandwidth

R < 25Ω

S

400

MHz

DYNAMIC ACCURACY ^The● denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS with 2.75V range unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SNR

Signal-to-Noise Ratio

5MHz Input

81.2

dBFS

15MHz Input, T = 25°C

80.4

80.1

81.1

80.7

dBFS

A

●

15MHz Input

30MHz Input, T = 25°C

81.1

dBFS

A

70MHz Input, T = 25°C

79.6

79.3

80.4

80.1

dBFS

A

70MHz Input

140MHz Input

5MHz Input

78.8

100

dBFS

dBc

SFDR

Spurious Free

Dynamic Range

2nd or 3rd Harmonic

15MHz Input, T = 25°C

88

87

100

99

dBc

A

●

15MHz Input

30MHz Input

95

dBc

70MHz Input, T = 25°C

85

83

92

88

dBc

A

70MHz Input

140MHz Input

5MHz Input

85

105

103

95

dBc

Spurious Free Dynamic Range

4th Harmonic or Higher

●

15MHz Input

30MHz Input

70MHz Input

140MHz Input

93

2217f

3

LTC2217

DYNAMIC ACCURACY ^The● denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS with 2.75V range unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

S/(N+D)

Signal-to-Noise

5MHz Input

81.2

dBFS

Plus Distortion Ratio

15MHz Input, T = 25°C

15MHz Input

79.9

79.7

81

80.6

dBFS

A

●

30MHz Input

81.1

dBFS

70MHz Input, T = 25°C

78.7

78.2

80

79.5

dBFS

A

70MHz Input

140MHz Input

5MHz Input

78.8

105

100

115

110

dBFS

SFDR

IMD

Spurious Free Dynamic Range

at –25dBFS

Dither “OFF”

15MHz Input

30MHz Input

70MHz Input

140MHz Input

5MHz Input

Spurious Free Dynamic Range

at –25dBFS

Dither “ON”

●

15MHz Input

30MHz Input

70MHz Input

140MHz Input

100

Intermodulation Distortion

f

IN1

f

IN1

= 14MHz, f = 21MHz, –7dBFS

= 67MHz, f = 74MHz, –7dBFS

100

90

dBc

IN2

COMMON MODE BIAS CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

PARAMETER

CONDITIONS

MIN

TYP

1.575

60

MAX

UNITS

V

CM

V

CM

V

CM

V

CM

Output Voltage

Output Tempco

Line Regulation

Output Resistance

I

= 0

1.475

1.675

OUT

ppm/°C

3.135V ≤ V ≤ 3.465V

2.4

mV/V

DD

Ω

| I

| ≤ 0.8mA

1.1

OUT

2217f

4

LTC2217

DIGITAL INPUTS AND DIGITAL OUTPUTS ^The● denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Encode Inputs (ENC , ENC )

●

V

Differential Input Voltage

(Note 7)

0.2

1.2

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 7)

1.6

V

ICM

3

R

Input Resistance

Input Capacitance

(See Figure 2)

(Note 7)

6

3

k

Ω

IN

C

IN

pF

Logic Inputs

●

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

2

V

IH

IL

DD

IN

0.8

10

I

IN

= 0V to V

μA

pF

DD

C

Digital Input Capacitance

(Note 7)

1.5

IN

LOGIC OUTPUTS (CMOS MODE)

OV = 3.3V

DD

V

High Level Output Voltage

V

= 3.3V

I = –10μA

I = –200μA

O

3.299

3.29

V

OH

DD

O

●

3.1

V

Low Level Output Voltage

I = 160μA

0.01

0.10

V

OL

O

I = 1.6mA

O

0.4

I

Output Source Current

Output Sink Current

V

= 0V

–50

50

mA

SOURCE

OUT

= 3.3V

SINK

OV = 2.5V

DD

V

High Level Output Voltage

Low Level Output Voltage

V

= 3.3V

I = –200μA

2.49

0.1

V

OH

OL

DD

O

I = 1.60mA

O

OV = 1.8V

DD

V

High Level Output Voltage

Low Level Output Voltage

V

= 3.3V

I = –200μA

1.79

0.1

V

OH

OL

DD

O

I = 1.60mA

O

LOGIC OUTPUTS (LVDS MODE)

STANDARD LVDS

●

V

Differential Output Voltage

100Ω Differential Load

247

350

1.2

454

mV

V

OD

OS

Output Common Mode Voltage 100Ω Differential Load

1.125

1.375

Low Power LVDS

●

V

Differential Output Voltage

100Ω Differential Load

125

175

1.2

250

mV

V

OD

OS

V

Output Common Mode Voltage 100Ω Differential Load

1.125

1.375

2217f

5

LTC2217

POWER REQUIREMENTS ^The● denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

3.3

17

MAX

UNITS

V

●

V

P

Analog Supply Voltage

Shutdown Power

(Note 8)

3.135

3.465

DD

SHDN = V

(Note 8)

mW

SHDN

DD

Standard LVDS Output Mode

●

OV

Output Supply Voltage

Analog Supply Current

Output Supply Current

Power Dissipation

3

3.3

365

75

3.6

430

90

V

mA

DD

I

VDD

OVDD

mA

P

1450

1716

mW

DIS

Low Power LVDS Output Mode

●

OV

Output Supply Voltage

Analog Supply Current

Output Supply Current

Power Dissipation

(Note 8)

3.3

363

42

3.6

430

50

V

mA

DD

I

VDD

OVDD

mA

P

1335

1584

mW

DIS

CMOS Output Mode

OV

●

Output Supply Voltage

Analog Supply Current

Power Dissipation

0.5

3.6

430

V

mA

DD

I

360

VDD

P

DIS

1190

1420

mW

TIMING CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

f

Sampling Frequency

ENC Low Time

(Note 8)

1

105

MHz

S

L

●

t

Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

4.52

3.1

4.762

500

ns

●

t

ENC High Time

Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

4.52

3.1

4.762

500

ns

H

LVDS Output Mode (Standard and Low Power)

●

t

ENC to DATA Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Output Rise Time

Output Fall Time

(Note 7)

1.3

2.5

0

3.8

0.6

ns

D

C

(t -t ) (Note 7)

C D

–0.6

ns

SKEW

RISE

FALL

0.5

7

ns

Data Latency

Cycles

CMOS Output Mode

●

t

ENC to DATA Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Data Latency

(Note 7)

1.3

2.7

0

4

ns

D

C

(t -t ) (Note 7)

C D

–0.6

0.6

SKEW

Data Latency

Full Rate CMOS

Demuxed

7

Cycles

2217f

6

LTC2217

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: Integral nonlinearity is deﬁned as the deviation of a code from a “best

ﬁt straight line” to the transfer curve. The deviation is measured from the

center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code ﬂickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 2: All voltage values are with respect to GND, with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

will be clamped by internal diodes. This product can handle input currents

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

DD

of greater than 100mA below GND or above V without latchup.

DD

+

Note 4: V = 3.3V, f

= 105MHz, LVDS outputs, differential ENC /

DD

SAMPLE

–

ENC = 2V sine wave with 1.6V common mode, input range = 2.75V

P-P

with differential drive, unless otherwise speciﬁed.

TIMING DIAGRAM

LVDS Output Mode Timing

All Outputs are Differential and Have LVDS Levels

t

AP

N + 1

N + 4

ANALOG

INPUT

N + 3

N

N + 2

t

H

t

L

–

ENC

+

ENC

t

D

N – 7

N – 6

N – 5

N – 4

N – 3

D0-D15, OF

t

C

+

CLKOUT

2217 TD01

–

CLKOUT

2217f

7

LTC2217

TIMING DIAGRAMS

Full-Rate CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

t

AP

N + 1

N + 4

ANALOG

INPUT

N + 3

N

N + 2

t

H

t

L

–

ENC

+

ENC

t

D

N – 7

N – 6

N – 5

N – 4

N – 3

DA0-DA15, OFA

t

C

CLKOUTA

CLKOUTB

HIGH IMPEDANCE

DB0-DB15, OFB

2217 TD02

Demultiplexed CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

t

AP

N + 1

N + 4

ANALOG

INPUT

N + 3

N

N + 2

t

H

t

L

–

ENC

+

ENC

t

D

N – 8

N – 6

N – 4

DA0-DA15, OFA

DB0-DB15, OFB

N – 7

N – 5

N – 3

t

C

CLKOUTA

CLKOUTB

2217 TD03

2217f

8

LTC2217

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) vs

Output Code - Dither “Off“

Integral Nonlinearity (INL) vs

Output Code - Dither “On“

Differential Nonlinearity (DNL) vs

Output Code

2.0

1.5

2.0

1.5

1.0

0.8

0.6

1.0

0.4

0.5

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0

16384

32768

49152

65536

0

16384

32768

49152

65536

0

16384

32768

49152

65536

OUTPUT CODE

2217 G03

2217 G01

2217 G02

64k Point FFT, f_IN= 4.9MHz,

–1dBFS

64k Point FFT, f_IN= 15.1MHz,

–1dBFS

AC Grounded Input Histogram

14000

12000

10000

8000

6000

4000

2000

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

32736

32745

32754

0

10

20

30

40

50

0

10

20

30

40

50

OUTPUT CODE

FREQUENCY (MHz)

2217 G06

2217 G04

2217 G05

64k Point 2-Tone FFT,

f_IN= 14.25MHz and 21.5MHz,

–7dBFS

64k Point FFT, f_IN= 15.1MHz,

–20dBFS, Dither “Off”

64k Point FFT, f_IN= 15.1MHz,

–20dBFS, Dither “On”

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2217 G07

2217 G08

2217 G09

2217f

9

LTC2217

TYPICAL PERFORMANCE CHARACTERISTICS

64k Point 2-Tone FFT,

f_IN= 14.25MHz and 21.5MHz,

–25dBFS, Dither “On”

SFDR vs Input Level,

f_IN= 15.2MHz, Dither “Off”

SFDR vs Input Level,

f_IN= 15.2MHz, Dither “On”

0

–10

–20

–30

–40

140

130

120

110

100

90

140

130

120

110

100

90

–50

–60

–70

80

–80

–90

–100

–110

–120

–130

70

60

50

40

30

0

10

20

30

40

50

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

FREQUENCY (MHz)

2217 G10

2217 G12

2217 G11

64k Point FFT, f_IN= 30.1MHz,

–20dBFS, Dither “On”

64k Point FFT, f_IN= 28.7MHz,

–1dBFS

SNR vs Input Level, f_IN= 15.2MHz

82

81

80

79

78

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2217 G13

2217 G14

2217 G15

64k Point FFT, f_IN= 70.1MHz,

–20dBFS, Dither “Off”

64k Point FFT, f_IN= 70.1MHz,

–10dBFS, Dither “Off”

64k Point FFT, f_IN= 70.2MHz,

–1dBFS

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2217 G16

2217 G17

2217 G18

2217f

10

LTC2217

TYPICAL PERFORMANCE CHARACTERISTICS

64k Point FFT, f_IN= 70.1MHz,

–20dBFS, Dither “On”

SFDR vs Input Level,

f_IN= 70.5MHz, Dither “Off”

SFDR vs Input Level,

f_IN= 70.5MHz, Dither “On”

0

–10

–20

–30

–40

140

130

120

110

100

90

140

130

120

110

100

90

–50

–60

–70

80

–80

–90

–100

–110

–120

–130

70

60

50

40

30

0

10

20

30

40

50

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

FREQUENCY (MHz)

2217 G21

2217 G19

2217 G20

64k Point 2-Tone FFT,

f_IN= 67.2MHz and 74.4MHz,

–15dBFS, Dither “On”

64k Point 2-Tone FFT,

f_IN= 67.2MHz and 74.4MHz,

–7dBFS

SNR vs Input Level, F_IN= 70.5MHz

82

81

80

79

78

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2217 G24

2217 G22

2217 G23

64k Point 2-Tone FFT,

f_IN= 67.2MHz and 74.4MHz,

–25dBFS, Dither “On”

64k Point FFT, f_IN= 140.5MHz,

–1dBFS

64k Point FFT, f_IN= 140.1MHz,

–20dBFS, Dither “On”

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2217 G25

2217 G26

2217 G27

2217f

11

LTC2217

TYPICAL PERFORMANCE CHARACTERISTICS

SFDR vs Input Level,

f_IN= 140.5MHz, Dither “Off”

SFDR vs Input Level,

f_IN= 140.5MHz, Dither “On”

SNR vs Input Level,

f_IN= 140.5MHz

140

130

120

110

100

90

140

130

120

110

100

90

82

81

80

79

78

80

70

60

50

40

30

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

2217 G30

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

2217 G28

2217 G29

SFDR (HD2 and HD3) vs

Input Frequency

SNR and SFDR vs Sample Rate,

f_IN= 5.2MHz

SNR vs Input Frequency

110

105

100

95

82

81

80

79

78

77

76

110

105

100

95

LIMIT

SFDR

HD2

90

HD3

SFDR

85

SNR

80

75

70

0

40

80

120

160

0

50

100

150

200

250

0

50

100

150

200

250

INPUT FREQUENCY (MHz)

SAMPLE RATE (MSPS)

2217 G31

2217 G32

2217 G33

SNR and SFDR vs Supply

Voltage (V_DD), f_IN= 5.1MHz

I_VDDvs Sample Rate and Supply

Voltage, f_IN= 5MHz, –1dBFS

SNR and SFDR vs Clock Duty

Cycle, f_IN= 5.2MHz

110

105

100

95

110

100

90

450

425

400

375

350

325

300

LOWER LIMIT

V

= 3.3V

DD

SFDR

UPPER LIMIT

90

V

= 3.135V

V

= 3.465V

DD

80

DD

85

SNR

80

SFDR DCS OFF

SNR DCS OFF

SFDR DCS ON

SNR DCS ON

70

75

70

2.8

60

3.0

3.2

3.4

3.6

0

50

100

150

200

30

40

50

60

70

SUPPLY VOLTAGE (V)

SAMPLE RATE (Msps)

DUTY CYCLE (%)

2217 G34

2217 G35

2217 G36

2217f

12

LTC2217

TYPICAL PERFORMANCE CHARACTERISTICS

Normalized Full Scale vs

Temperature, Internal Reference,

5 Units

Input Offset Voltage vs

Temperature, Internal Reference,

5 Units

1.005

1.004

1.003

1.002

1.001

1

5

4

3

2

1

0

0.999

0.998

0.997

0.996

0.995

–1

–2

–3

–4

–5

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

2217 G37

2217 G38

Normalized Full Scale vs

Temperature, External Reference,

5 Units

Input Offset Voltage vs

Temperature, External Reference,

5 Units

1.005

1.004

1.003

1.002

1.001

1

5

4

3

2

1

0

0.999

0.998

0.997

0.996

0.995

–1

–2

–3

–4

–5

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

2217 G39

2217 G40

SFDR vs Analog Input Common

Mode Voltage, 5MHz and 70MHz,

–1dBFS

Mid-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

Full-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

110

105

100

95

0.5

0.4

0.5

0.4

WAKE-UP

0.3

5MHz

0.2

90

0.1

85

0.0

CLOCK START

80

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

70MHz

75

70

65

60

0.5 0.75

1

1.25 1.5

1.75

2

0

400

800

1200

1600

2000

0

300

600

900

1200

1500

ANALOG INPUT COMMON MODE VOLTAGE (V)

TIME AFTER WAKE-UP OR CLOCK START (μs)

2217 G41

2217 G42

2217 G43

2217f

13

LTC2217

PIN FUNCTIONS

For CMOS Mode. Full Rate or Demultiplexed

CLKOUTB(Pin40):DataValidOutput.CLKOUTBwilltoggle

at the sample rate in full rate CMOS mode or at 1/2 the

sample rate in demultiplexed mode. Latch the data on the

falling edge of CLKOUTB.

SENSE (Pin 1): Reference Mode Select and External

Reference Input. Tie SENSE to V to select the internal

DD

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full

scale ADC range of 2.75V.

CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA

will toggle at the sample rate in full rate CMOS mode or

at 1/2 the sample rate in demultiplexed mode. Latch the

data on the rising edge of CLKOUTA.

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

V

(Pin3):1.575VOutput.Optimumvoltageforinputcom-

CM

DA0-DA15(Pins42-48and51-59):DigitalOutputs,ABus.

DA15 is the MSB. Output bus for full rate CMOS mode

and demultiplexed mode.

mon mode. Must be bypassed to ground with a minimum

of 2.2μF. Ceramic chip capacitors are recommended.

V

(Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.

DD

OFA (Pin 60): Over/Under Flow Digital Output for the A

Bus. OFA is high when an over or under ﬂow has occurred

on the A bus.

Bypass to GND with 1μF ceramic chip capacitors.

+

A

(Pin 8): Positive Differential Analog Input.

(Pin 9): Negative Differential Analog Input.

IN

–

LVDS (Pin 61): Data Output Mode Select Pin. Connecting

+

LVDSto0VselectsfullrateCMOSmode.ConnectingLVDS

ENC (Pin 12): Positive Differential Encode Input. The

+

to1/3V selectsdemultiplexedCMOSmode. Connecting

sampled analog input is held on the rising edge of ENC .

DD

LVDS to 2/3V selects Low Power LVDS mode. Connect-

Internally biased to 1.6V through a 6.2kΩ resistor. Output

DD

+

ing LVDS to V selects Standard LVDS mode.

data can be latched on the rising edge of ENC .

DD

–

MODE (Pin 62): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and disables the clock duty

ENC (Pin 13): Negative Differential Encode Input. The

–

sampled analog input is held on the falling edge of ENC .

Internally biased to 1.6V through a 6.2kΩ resistor. By-

pass to ground with a 0.1μF capacitor for a single-ended

Encode signal.

cyclestabilizer.ConnectingMODEto1/3V selects offset

DD

binary output format and enables the clock duty cycle sta-

bilizer.ConnectingMODEto2/3V selects2’scomplement

DD

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results

in normal operation. SHDN = high results in powered

down analog circuitry and the digital outputs are placed

in a high impedance state.

output format and enables the clock duty cycle stabilizer.

Connecting MODE to V selects 2’s complement output

DD

format and disables the clock duty cycle stabilizer.

RAND (Pin 63): Digital Output Randomization Selection

Pin. RAND low results in normal operation. RAND high

selects D1-D15 to be EXCLUSIVE-ORed with D0 (the

LSB). The output can be decoded by again applying an

XOR operation between the LSB and all other bits. This

mode of operation reduces the effects of digital output

interference.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low

disables internal dither. DITH = high enables internal

dither. Refer to Internal Dither section of this data sheet

for details on dither operation.

DB0-DB15(Pins21-30and33-38):DigitalOutputs,BBus.

DB15istheMSB. Activeindemultiplexedmode. TheBbus

is in high impedance state in full rate CMOS mode.

NC(Pin64):NotConnectedInternally.Forpincompatibility

OGND (Pins 31 and 50): Output Driver Ground.

with the LTC2208 this pin should be connected to GND or

V

DD

as required. Otherwise no connection.

OV (Pins 32 and 49): Positive Supply for the Output

DD

Drivers. Bypass to ground with 1μF capacitor.

GND (Exposed Pad): ADC Power Ground. The exposed

pad on the bottom of the package must be soldered to

ground.

OFB(Pin39):Over/UnderFlowDigitalOutputfortheBBus.

OFBishighwhenanoverorunderﬂowhasoccurredonthe

B bus. At high impedance state in full rate CMOS mode.

2217f

14

LTC2217

PIN FUNCTIONS

For LVDS Mode. STANDARD or LOW POWER

OGND (Pins 31 and 50): Output Driver Ground.

SENSE (Pin 1): Reference Mode Select and External

OV (Pins 32 and 49): Positive Supply for the Output

DD

Reference Input. Tie SENSE to V to select the internal

Drivers. Bypass to ground with 0.1μF capacitor.

DD

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full

scale ADC range of 2.75V.

–

+

CLKOUT /CLKOUT (Pins 39 and 40): LVDS Data Valid

+

0utput. Latch data on the rising edge of CLKOUT , falling

edge of CLKOUT .

–

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

–

+

OF /OF (Pins59and60):Over/UnderFlowDigitalOutput

OF is high when an over or under ﬂow has occurred.

V

CM

(Pin 3): 1.575V Output. Optimum voltage for input

common mode. Must be bypassed to ground with a

minimum of 2.2μF. Ceramic chip capacitors are recom-

mended.

LVDS (Pin 61): Data Output Mode Select Pin. Connecting

LVDSto0VselectsfullrateCMOSmode.ConnectingLVDS

to1/3V selectsdemultiplexedCMOSmode. Connecting

DD

V

DD

(Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.

LVDS to 2/3V selects Low Power LVDS mode. Connect-

DD

Bypass to GND with 1μF ceramic chip capacitors.

ing LVDS to V selects Standard LVDS mode.

DD

+

A

(Pin 8): Positive Differential Analog Input.

(Pin 9): Negative Differential Analog Input.

MODE (Pin 62): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and disables the clock duty

IN

–

+

ENC (Pin 12): Positive Differential Encode Input. The

cyclestabilizer.ConnectingMODEto1/3V selectsoffset

DD

+

sampled analog input is held on the rising edge of ENC .

binary output format and enables the clock duty cycle sta-

Internally biased to 1.6V through a 6.2kΩ resistor. Output

bilizer.ConnectingMODEto2/3V selects2’scomplement

DD

+

data can be latched on the rising edge of ENC .

output format and enables the clock duty cycle stabilizer.

–

Connecting MODE to V selects 2’s complement output

DD

ENC (Pin 13): Negative Differential Encode Input. The

sampled analog input is held on the falling edge of ENC .

–

format and disables the clock duty cycle stabilizer.

Internally biased to 1.6V through a 6.2kΩ resistor. By-

pass to ground with a 0.1μF capacitor for a single-ended

Encode signal.

RAND(Pin63):DigitalOutputRandomizationSelectionPin.

RAND low results in normal operation. RAND high selects

D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The

outputcanbedecodedbyagainapplyinganXORoperation

between the LSB and all other bits. The mode of operation

reduces the effects of digital output interference.

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results

in normal operation. SHDN = high results in powered

down analog circuitry and the digital outputs are set in

high impedance state.

NC (Pin 64): Not Connected Internally. For pin compat-

ibility with the LTC2208 this pin should be connected to

DITH (Pin 20): Internal Dither Enable Pin. DITH = low

disablesinternaldither.DITH=highenablesinternaldither.

Refer to Internal Dither section of the data sheet for details

on dither operation.

GND or V as required. Otherwise no connection.

DD

GND (Exposed Pad Pin 65): ADC Power Ground. The

exposed pad on the bottom of the package must be sol-

dered to ground.

–

+

–

+

D0 /D0 to D15 /D15 (Pins 21-30, 33-38, 41-48 and

51-58): LVDS Digital Outputs. All LVDS outputs require

differential100ΩterminationresistorsattheLVDSreceiver.

+

–

D15 /D15 is the MSB.

2217f

15

LTC2217

BLOCK DIAGRAM

+

A

IN

V

DD

INPUT

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

–

GND

DITHER

SIGNAL

GENERATOR

CORRECTION LOGIC

AND

SHIFT REGISTER

ADC CLOCKS

RANGE

SELECT

OV

DD

CLKOUT+

CLKOUT–

+

SENSE

OF

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

–

OF

ADC

REFERENCE

+

–

PGA

CONTROL

LOGIC

D15

OUTPUT

DRIVERS

•

V

CM

BUFFER

+

D0

–

D0

VOLTAGE

REFERENCE

2217 F01

OGND

+

–

ENC

SHDN RAND M0DE LVDS DITH

Figure 1. Functional Block Diagram

2217f

16

LTC2217

OPERATION

DYNAMIC PERFORMANCE

by the presence of another sinusoidal input at a different

frequency.

Signal-to-Noise Plus Distortion Ratio

If two pure sine waves of frequencies fa and fb are applied

totheADCinput,nonlinearitiesintheADCtransferfunction

can create distortion products at the sum and difference

frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 3rd order IMD terms include (2fa + fb),

(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is

deﬁned as the ratio of the RMS value of either input tone

to the RMS value of the largest 3rd order IMD product.

The signal-to-noise plus distortion ratio [S/(N+D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band lim-

ited to frequencies above DC to below half the sampling

frequency (Nyquist Frequency).

Signal-to-Noise Ratio

Spurious Free Dynamic Range (SFDR)

The signal-to-noise (SNR) is the ratio between the RMS

amplitudeofthefundamentalinputfrequencyandtheRMS

amplitude of all other frequency components, except the

ﬁrst ﬁve harmonics.

The ratio of the RMS input signal amplitude to the RMS

value of the peak spurious spectral component expressed

in dBc. SFDR may also be calculated relative to full scale

and expressed in dBFS.

Total Harmonic Distortion

Full Power Bandwidth

Total harmonic distortion is the ratio of the RMS sum of

all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (Nyquist

Frequency). THD is expressed as:

The Full Power bandwidth is that input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB from a full scale input signal.

Aperture Delay Time

⎛

⎞

2

V + V + V +…V

N

+

–

(

)

2

3

4

ThetimefromwhenarisingENC equalstheENC voltage

to the instant that the input signal is held by the sample-

and-hold circuit.

⎜

⎟

THD= –20Log

V₁

⎜

⎝

⎟

⎠

Aperture Delay Jitter

where V is the RMS amplitude of the fundamental fre-

1

quencyandV throughV aretheamplitudesofthesecond

2

N

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

whensamplinganACinput.Thesignal-to-noiseratioterm

due to the jitter alone will be:

through nth harmonics.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

SNR

= –20log (2π • f • t

)

JITTER

IN JITTER

ThisformulastatesSNRduetojitteraloneatanyamplitude

in terms of dBc.

2217f

17

LTC2217

APPLICATIONS INFORMATION

CONVERTER OPERATION

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

TheLTC2217isaCMOSpipelinedmultistepconverterwith

a low noise front-end. As shown in Figure 1, the converter

has ﬁve pipelined ADC stages; a sampled analog input

will result in a digitized value seven cycles later (see the

TimingDiagramsection).Theanaloginputisdifferentialfor

improvedcommonmodenoiseimmunityandtomaximize

the input range. Additionally, the differential input drive

will reduce even order harmonics of the sample and hold

circuit. The encode input is also differential for improved

common mode noise immunity.

Figure2showsanequivalentcircuitfortheLTC2217CMOS

differentialsampleandhold. Thedifferentialanaloginputs

are sampled directly onto sampling capacitors (C

through NMOS transitors. The capacitors shown attached

)

SAMPLE

to each input (C

) are the summation of all other

PARASITIC

capacitance associated with each input.

During the sample phase when ENC is low, the NMOS

transistors connect the analog inputs to the sampling

capacitors and they charge to, and track the differential

input voltage. When ENC transitions from low to high, the

sampled input voltage is held on the sampling capacitors.

During the hold phase when ENC is high, the sampling

capacitors are disconnected from the input and the held

voltage is passed to the ADC core for processing. As ENC

transitions for high to low, the inputs are reconnected to

the sampling capacitors to acquire a new sample. Since

the sampling capacitors still hold the previous sample,

a charging glitch proportional to the change in voltage

between samples will be seen at this time. If the change

between the last sample and the new sample is small,

the charging glitch seen at the input will be small. If the

The LTC2217 has two phases of operation, determined

+

–

by the state of the differential ENC /ENC input pins. For

–

brevity, the text will refer to ENC greater than ENC as

+

ENC high and ENC less than ENC as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage ampliﬁer. In

operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is ampliﬁed and

output by the residue ampliﬁer. Successive stages oper-

ate out of phase so that when odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

When ENC is low, the analog input is sampled differen-

tially directly onto the input sample-and-hold capacitors,

inside the “input S/H” shown in the block diagram. At the

instant that ENC transitions from low to high, the voltage

on the sample capacitors is held. While ENC is high, the

held input voltage is buffered by the S/H ampliﬁer which

drivestheﬁrstpipelinedADCstage.Theﬁrststageacquires

the output of the S/H ampliﬁer during the high phase of

ENC. When ENC goes back low, the ﬁrst stage produces

its residue which is acquired by the second stage. At

the same time, the input S/H goes back to acquiring the

analog input. When ENC goes high, the second stage

produces its residue which is acquired by the third stage.

An identical process is repeated for the third and fourth

stages, resulting in a fourth stage residue that is sent to

the ﬁfth stage for ﬁnal evaluation.

LTC2217

V

DD

C

SAMPLE

7.3pF

R

20Ω

PARASITIC

3Ω

ON

+

A

IN

C

1.8pF

PARASITIC

V

DD

SAMPLE

7.3pF

R

ON

PARASITIC

3Ω

20Ω

–

A

IN

C

1.8pF

PARASITIC

V

DD

1.6V

6k

+

–

ENC

Each ADC stage following the ﬁrst has additional range to

accommodate ﬂash and ampliﬁer offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

6k

1.6V

2217 F02

Figure 2. Equivalent Input Circuit

2217f

18

LTC2217

APPLICATIONS INFORMATION

input change is large, such as the change seen with input

frequencies near Nyquist, then a larger charging glitch

will be seen.

has a very broadband S/H circuit, DC to 400MHz; it can

be used in a wide range of applications; therefore, it is not

possible to provide a single recommended RC ﬁlter.

Figures3and4showtwoexamplesofinputRCﬁlteringfor

two ranges of input frequencies. In general it is desirable

to make the capacitors as large as can be tolerated—this

will help suppress random noise as well as noise coupled

fromthedigitalcircuitry.TheLTC2217doesnotrequireany

input ﬁlter to achieve data sheet speciﬁcations; however,

no ﬁltering will put more stringent noise requirements on

the input drive circuitry.

Common Mode Bias

TheADCsample-and-holdcircuitrequiresdifferentialdrive

toachievespeciﬁedperformance.Eachinputshouldswing

0.6875V for the 2.75V range, around a common mode

voltage of 1.575V. The V output pin (Pin 3) is designed

to provide the common mode bias level. V can be tied

CM

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The V pin must be bypassed to ground

CM

Transformer Coupled Circuits

close to the ADC with 2.2μF or greater.

Figure 3 shows the LTC2217 being driven by an RF trans-

former with a center-tapped secondary. The secondary

Input Drive Impedance

center tap is DC biased with V , setting the ADC input

CM

Aswithallhighperformance,highspeedADCsthedynamic

performanceoftheLTC2217canbeinﬂuencedbytheinput

drivecircuitry,particularlythesecondandthirdharmonics.

SourceimpedanceandinputreactancecaninﬂuenceSFDR.

At the falling edge of ENC the sample and hold circuit will

connectthesamplingcapacitortotheinputpinandstartthe

samplingperiod.ThesamplingperiodendswhenENCrises,

holding the sampled input on the sampling capacitor. Ide-

ally,theinputcircuitryshouldbefastenoughtofullycharge

the sampling capacitor during the sampling period

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratiotransformer.Otherturnsratioscanbeused;however,

astheturnsratioincreasessodoestheimpedanceseenby

the ADC. Source impedance greater than 50Ω can reduce

the input bandwidth and increase high frequency distor-

tion. A disadvantage of using a transformer is the loss of

lowfrequencyresponse.MostsmallRFtransformershave

poor performance at frequencies below 1MHz.

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

1/(2 • f ); however, this is not always possible and

ENCODE

the incomplete settling may degrade the SFDR. The sam-

pling glitch has been designed to be as linear as possible

to minimize the effects of incomplete settling.

V

CM

For the best performance it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

2.2μF

5Ω

10Ω

+

5Ω

A

IN

T1

8.2pF

LTC2217

35Ω

8.2pF

0.1μF

10Ω

INPUT DRIVE CIRCUITS

Input Filtering

–

5Ω

8.2pF

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

2217 F03

A ﬁrst-order RC low-pass ﬁlter at the input of the ADC can

servetwofunctions:limitthenoisefrominputcircuitryand

provide isolation from ADC S/H switching. The LTC2217

Figure 3. Single-Ended to Differential Conversion

Using a Transformer. Recommended for Input

Frequencies from 5MHz to 100MHz

2217f

19

LTC2217

APPLICATIONS INFORMATION

Figure 4 shows transformer coupling using a transmis-

sion line balun transformer. This type of transformer has

much better high-frequency response and balance than

ﬂuxcoupledcenter-taptransformers.Couplingcapacitors

are added at the ground and input primary terminals to

allow the secondary terminals to be biased at 1.575V.

V

CM

2.2μF

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

+

–

25Ω

A

IN

LTC2217

ANALOG

INPUT

+

12pF

CM

–

A

V

CM

12pF

AMPLIFIER = LTC6600-20,

LTC1993, ETC.

2217 F05

2.2μF

5Ω

0.1μF

+

–

10Ω

A

IN

Figure 5. DC Coupled Input with Differential Ampliﬁer

ANALOG

INPUT

LTC2217

0.1μF

25Ω

4.7pF

reference, tie the SENSE pin to V . To use an external

DD

T1

1:1

reference, simply apply either a 1.25V or 2.5V reference

4.7pF

10Ω

5Ω

voltage to the SENSE input pin. Both 1.25V and 2.5V ap-

4.7pF

pliedtoSENSEwillresultinafullscalerangeof2.75V .A

T1 = MA/COM ETC1-1-13

P-P

2217 F04

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

1.575V output, V , is provided for a common mode bias

CM

for input drive circuitry. An external bypass capacitor is

requiredfortheV output.Thisprovidesahighfrequency

Figure 4. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 100MHz to 250MHz

CM

low impedance path to ground for internal and external

circuitry. This is also the compensation capacitor for the

reference; which will not be stable without this capacitor.

The minimum value required for stability is 2.2μF.

Direct Coupled Circuits

Figure 5 demonstrates the use of a differential ampliﬁer to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides

low frequency input response; however, the limited gain

bandwidth of any op amp or closed-loop ampliﬁer will de-

gradetheADCSFDRathighinputfrequencies.Additionally,

wideband op amps or differential ampliﬁers tend to have

high noise. As a result, the SNR will be degraded unless

the noise bandwidth is limited prior to the ADC input.

RANGE

SELECT

AND GAIN

CONTROL

TIE TO V TO USE

DD

INTERNAL

ADC

REFERENCE

INTERNAL 2.5V

REFERENCE

OR INPUT AN

EXTERNAL 2.5V

REFERENCE

SENSE

PGA

OR INPUT AN

EXTERNAL 1.25V

REFERENCE

2.5V

BANDGAP

REFERENCE

Reference Operation

V

CM

Figure6showstheLTC2217referencecircuitryconsisting

of a 2.5V bandgap reference, a programmable gain ampli-

ﬁer and control circuit. The LTC2217 has three modes of

reference operation: Internal Reference, 1.25V external

reference or 2.5V external reference. To use the internal

1.575V

BUFFER

2.2μF

2217 F06

Figure 6. Reference Circuit

2217f

20

LTC2217

APPLICATIONS INFORMATION

3. If the ADC is clocked with a ﬁxed-frequency sinusoidal

signal, ﬁlter the encode signal to reduce wideband

noise.

The internal programmable gain ampliﬁer provides the

internal reference voltage for the ADC. This ampliﬁer has

very stringent settling requirements and therefore is not

accessible for external use.

4. Balance the capacitance and series resistance at both

encode inputs such that any coupled noise will appear

at both inputs as common mode noise.

TheSENSEpincanbedriven 5%aroundthenominal2.5V

or 1.25V external reference inputs. This adjustment range

can be used to trim the ADC gain error or other system

gain errors. When selecting the internal reference, the

The encode inputs have a common mode range of 1.2V

to V . Each input may be driven from ground to V for

DD

SENSE pin should be tied to V as close to the converter

DD

single-ended drive.

as possible. If the sense pin is driven externally it should

be bypassed to ground as close to the device as possible

with 1μF ceramic capacitor.

LTC2217

V

DD

TO INTERNAL

ADC CLOCK

DRIVERS

V

CM

1.575V

1.6V

6k

2.2μF

V

DD

LTC2217

SENSE

6

2

+

3.3V

1μF

LTC1461-2.5

4

ENC

2.2μF

1.6V

6k

V

DD

2217 F07

–

ENC

Figure 7. A 2.75V Range ADC with

an External 2.5V Reference

Driving the Encode Inputs

2217 F08a

The noise performance of the LTC2217 can depend on

the encode signal quality as much as on the analog input.

The encode inputs are intended to be driven differentially,

primarily for noise immunity from common mode noise

sources. Each input is biased through a 6k resistor to a

1.6V bias. The bias resistors set the DC operating point

fortransformercoupleddrivecircuitsandcansetthelogic

threshold for single-ended drive circuits.

Figure 8a. Equivalent Encode Input Circuit

0.1μF

+

T1

ENC

50Ω

100Ω

8.2pF

LTC2217

0.1μF

–

0.1μF

ENC

Any noise present on the encode signal will result in ad-

ditional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

2217 F08b

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

In applications where jitter is critical (high input frequen-

cies), take the following into consideration:

Figure 8b. Balun-Driven Encode

1. Differential drive should be used.

2. Use as large an amplitude possible. If using trans-

former coupling, use a higher turns ratio to increase the

amplitude.

2217f

21

LTC2217

APPLICATIONS INFORMATION

+

The lower limit of the LTC2217 sample rate is determined

by droop affecting the sample and hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

dischargethecapacitors.Thespeciﬁedminimumoperating

frequency for the LTC2217 is 1Msps.

ENC

V

= 1.6V

THRESHOLD

–

LTC2217

1.6V

ENC

0.1μF

2217 F09

Figure 9. Single-Ended ENC Drive,

Not Recommended for Low Jitter

DIGITAL OUTPUTS

3.3V

Digital Output Modes

3.3V

MC100LVELT22

D0

The LTC2217 can operate in four digital output modes:

standard LVDS, low power LVDS, full rate CMOS, and

demultiplexed CMOS. The LVDS pin selects the mode of

operation. This pin has a four level logic input, centered at

130Ω

Q0

130Ω

ENC

+

–

LTC2217

ENC

Q0

0,1/3V_DD,2/3V andV_DD.Anexternalresistordividercan

DD

83Ω

be used to set the 1/3V_DDand 2/3V_DDlogic levels. Table 1

shows the logic states for the LVDS pin.

2217 F10

Table 1. LVDS Pin Function

LVDS

Figure 10. ENC Drive Using a CMOS to PECL Translator

DIGITAL OUTPUT MODE

Full-Rate CMOS

Demultiplexed CMOS

Low Power LVDS

LVDS

0V(GND)

Maximum and Minimum Encode Rates

1/3V

2/3V

DD

The maximum encode rate for the LTC2217 is 105Msps.

For the ADC to operate properly the encode signal should

have a 50% ( 5%) duty cycle. Each half cycle must have

at least 4.5ns for the ADC internal circuitry to have enough

settlingtimeforproperoperation.Achievingaprecise50%

duty cycle is easy with differential sinusoidal drive using

a transformer or using symmetric differential logic such

as PECL or LVDS. When using a single-ended ENCODE

signal asymmetric rise and fall times can result in duty

cycles that are far from 50%.

V

DD

Digital Output Buffers (CMOS Modes)

Figure 11 shows an equivalent circuit for a single output

buffer in CMOS Mode, Full-Rate or Demultiplexed. Each

buffer is powered by OV_DDand OGND, isolated from the

ADCpowerandground.TheadditionalN-channeltransistor

intheoutputdriverallowsoperationdowntolowvoltages.

The internal resistor in series with the output makes the

output appear as 50Ω to external circuitry and eliminates

the need for external damping resistors.

An optional clock duty cycle stabilizer can be used if the

input clock does not have a 50% duty cycle. This circuit

usestherisingedgeofENCpintosampletheanaloginput.

The falling edge of ENC is ignored and an internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2217 should drive a minimum

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as a ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

connected to 1/3V or 2/3V using external resistors.

DD

2217f

22

LTC2217

APPLICATIONS INFORMATION

output may be used, but is not required since the ADC

has a series resistor of 43Ω on-chip.

+

–

resistor, even if the signal is not used (such as OF /OF or

+

–

CLKOUT /CLKOUT ). To minimize noise the PC board

traces for each LVDS output pair should be routed close

together. TominimizeclockskewallLVDSPCboardtraces

should have about the same length.

Lower OV voltages will also help reduce interference

DD

from the digital outputs.

In Low Power LVDS Mode 1.75mA is steered between

the differential outputs, resulting in 175mV at the LVDS

receiver’s 100Ω termination resistor. The output com-

mon mode voltage is 1.20V, the same as standard LVDS

Mode.

LTC2217

OV

DD

0.5V

TO 3.6V

V

DD

0.1μF

OV

DD

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

TYPICAL

DATA

OUTPUT

Data Format

The LTC2217 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MODE pin. This pin has a four level

OGND

2217 F11

logic input, centered at 0, 1/3V , 2/3V and V . An

DD

external resistor divider can be user to set the 1/3V

Figure 11. Equivalent Circuit for a Digital Output Buffer

DD

and 2/3V logic levels. Table 2 shows the logic states

DD

for the MODE pin.

Digital Output Buffers (LVDS Modes)

Table 2. MODE Pin Function

CLOCK DUTY

Figure 12 shows an equivalent circuit for an LVDS output

+

–

pair. A 3.5mA current is steered from OUT to OUT or

vice versa, which creates a 350mV differential voltage

acrossthe100ΩterminationresistorattheLVDSreceiver.

A feedback loop regulates the common mode output volt-

age to 1.20V. For proper operation each LVDS output pair

must be terminated with an external 100Ω termination

MODE

OUTPUT FORMAT

CYCLE STABILIZER

0(GND)

Offset Binary

Off

On

Off

1/3V

2/3V

Offset Binary

DD

2’s Complement

V

DD

LTC2217

OV

DD

3.3V

3.5mA

0.1μF

V

DD

V

DD

OV

DD

43Ω

DATA

FROM

LATCH

10k

PREDRIVER

LOGIC

LVDS

RECEIVER

OV

DD

100Ω

+

–

1.20V

OGND

2217 F12

Figure 12. Equivalent Output Buffer in LVDS Mode

2217f

23

LTC2217

APPLICATIONS INFORMATION

Overﬂow Bit

LSB and all other bits. The LSB, OF and CLKOUT output

are not affected. The output Randomizer function is active

when the RAND pin is high.

An overﬂow output bit (OF) indicates when the converter

is over-ranged or under-ranged. In CMOS mode, a logic

high on the OFA pin indicates an overﬂow or underﬂow on

the A data bus, while a logic high on the OFB pin indicates

an overﬂow on the B data bus. In LVDS mode, a differ-

ential logic high on OF /OF pins indicates an overﬂow

or underﬂow.

LTC2217

CLKOUT

OF

+

–

OF

Output Clock

D15

The ADC has a delayed version of the encode input avail-

able as a digital output, CLKOUT. The CLKOUT pin can

be used to synchronize the converter data to the digital

system. This is necessary when using a sinusoidal en-

code. In both CMOS modes, A bus data will be updated

as CLKOUTA falls and CLKOUTB rises. In demultiplexed

CMOS mode the B bus data will be updated as CLKOUTA

falls and CLKOUTB rises.

D15 ⊕ D0

D14 ⊕ D0

D14

•

D2

D1

D2 ⊕ D0

D1 ⊕ D0

In Full Rate CMOS Mode, only the A data bus is active;

data may be latched on the rising edge of CLKOUTA or

the falling edge of CLKOUTB.

RAND = HIGH,

SCRAMBLE

ENABLED

RAND

D0

In demultiplexed CMOS mode CLKOUTA and CLKOUTB

will toggle at 1/2 the frequency of the encode signal. Both

the A bus and the B bus may be latched on the rising edge

of CLKOUTA or the falling edge of CLKOUTB.

D0

2217 F13

Figure 13. Functional Equivalent of Digital Output Randomizer

Digital Output Randomizer

Output Driver Power

Interference from the ADC digital outputs is sometimes

unavoidable. Interference from the digital outputs may be

fromcapacitiveorinductivecoupling, orcouplingthrough

the ground plane. Even a tiny coupling factor can result in

discernible unwanted tones in the ADC output spectrum.

By randomizing the digital output before it is transmitted

offchip,theseunwantedtonescanberandomized,trading

a slight increase in the noise ﬂoor for a large reduction in

unwanted tone amplitude.

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV , should be tied

DD

to the same power supply as for the logic being driven.

For example, if the converter is driving a DSP powered

by a 1.8V supply, then OV should be tied to that same

DD

1.8V supply. In CMOS mode OV can be powered with

DD

any logic voltage up to the 3.6V. OGND can be powered

with any voltage from ground up to 1V and must be less

The digital output is “Randomized” by applying an exclu-

sive-ORlogicoperationbetweentheLSBandallotherdata

output bits. To decode, the reverse operation is applied;

that is, an exclusive-OR operation is applied between the

than OV . The logic outputs will swing between OGND

DD

and OV . In LVDS Mode, OV should be connected to

DD

a 3.3V supply and OGND should be connected to GND.

2217f

24

LTC2217

APPLICATIONS INFORMATION

Internal Dither

PC BOARD

FPGA

The LTC2217 is a 16-bit ADC with a very linear transfer

function;however,atlowinputlevelsevenslightimperfec-

tions in the transfer function will result in unwanted tones.

Small errors in the transfer function are usually a result

of ADC element mismatches. An optional internal dither

mode can be enabled to randomize the input location on

the ADC transfer curve, resulting in improved SFDR for

low signal levels.

CLKOUT

OF

D15 ⊕ D0

D15

D14 ⊕ D0

As shown in Figure 15, the output of the sample-and-hold

ampliﬁer is summed with the output of a dither DAC. The

dither DAC is driven by a long sequence pseudo-random

numbergenerator;therandomnumberfedtotheditherDAC

is also subtracted from the ADC result. If the dither DAC

is precisely calibrated to the ADC, very little of the dither

signalwillbeseenattheoutput.Thedithersignalthatdoes

leak through will appear as white noise. The dither DAC is

calibrated to result in typically less than 0.5dB elevation

in the noise ﬂoor of the ADC as compared to the noise

ﬂoor with dither off, when a suitable input termination is

provided (see Demo Board schematic DC996B).

D14

•

LTC2217

D2 ⊕ D0

D1 ⊕ D0

D2

D1

D0

2217 F14

Figure 14. Descrambling a Scrambled Digital Output

LTC2217

CLKOUT

OF

+

D15

AIN

16-BIT

PIPELINED

ADC CORE

•

DIGITAL

SUMMATION

ANALOG

INPUT

OUTPUT

DRIVERS

S/H

AMP

–

AIN

D0

CLOCK/DUTY

CYCLE

CONTROL

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

PRECISION

DAC

GENERATOR

2217 F15

+

–

ENC

DITH

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit

2217f

25

LTC2217

APPLICATIONS INFORMATION

Grounding and Bypassing

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The LTC2217 requires a printed circuit board with a

clean unbroken ground plane; a multilayer board with an

internal ground plane is recommended. The pinout of the

LTC2217 has been optimized for a ﬂowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated

as much as possible. In particular, care should be taken

not to run any digital track alongside an analog signal

track or underneath the ADC.

The LTC2217 differential inputs should run parallel and

close to each other. The input traces should be as short

as possible to minimize capacitance and to minimize

noise pickup.

Heat Transfer

Most of the heat generated by the LTC2217 is transferred

from the die through the bottom-side exposed pad. For

good electrical and thermal performance, the exposed

pad must be soldered to a large grounded pad on the PC

board. It is critical that the exposed pad and all ground

pins are connected to a ground plane of sufﬁcient area

with as many vias as possible.

High quality ceramic bypass capacitors should be used

at the V

V

, and OV pins. Bypass capacitors must

DD, CM DD

be located as close to the pins as possible. The traces

2217f

26

LTC2217

APPLICATIONS INFORMATION

Layer 1 Component Side

Layer 2 GND Plane

2217f

27

LTC2217

APPLICATIONS INFORMATION

Layer 3 GND

Layer 4 GND

2217f

28

LTC2217

APPLICATIONS INFORMATION

Layer 5 GND

Layer 6 Bottom Side

2217f

29

LTC2217

APPLICATIONS INFORMATION

V C 5

V C 4

V C 3

V C 2

V C 1

V E 5

V E 4

V E 3

V E 2

V E 1

V C 5

V C 4

V C 3

V C 2

V C 1

V E 5

V E 4

V E 3

V E 2

V E 1

4 8

4 7

2 6

2 5

1 2

3 7

3 6

2 3

4 8

4 7

2 6

2 5

1 2

3 7

3 6

2 3

2

1

2

1

6 5

O V D D 4 9

O G N D 5 0

O V D D 3 2

3 2

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

O G N D 3 1

3 1

D 4 +

3 0

D 1 2 –

D 1 2 +

D 1 3 –

D 1 3 +

D 1 4 –

D 1 4 +

D 1 5 –

D 1 5 +

D 4 –

2 9

D 3 +

2 7

D 3 –

2 7

D 2 +

2 6

D 2 –

2 5

D 1 +

2 4

D 1 –

2 3

O F –

O F +

L V D S

D 0 +

2 2

D 0 –

2 1

D I T H

2 0

S H D N

M O D E

R A N D

1 9

G N D 1 8

1 8

V D D 1 7

N C

1 7

•

2217f

30

LTC2217

PACKAGE DESCRIPTION

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 0.05

7.15 0.05

7.50 REF

8.10 0.05 9.50 0.05

(4 SIDES)

7.15 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.10

TYP

R = 0.115

TYP

9 .00 0.10

(4 SIDES)

63 64

0.40 0.10

PIN 1 TOP MARK

(SEE NOTE 5)

1

2

PIN 1

CHAMFER

C = 0.35

7.15 0.10

7.50 REF

(4-SIDES)

7.15 0.10

(UP64) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

2217f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC2217

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2217f

LT 0108 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2217IUP-TRPBF
厂家：	Linear
描述：	16-Bit, 105Msps Low Noise ADC 16位，105Msps低噪声ADC
文件：	总32页 (文件大小：1276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2217IUP-TRPBF [Linear]

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