LTC2256IUJ-12-PBF_技术文档

Electrical Specifications Subject to Change

LTC2258-12

LTC2257-12/LTC2256-12

12-Bit, 65/40/2 5Msps

Ultralow Power 1.8V ADCs

FEATURES

DESCRIPTION

The LTC^®2258-12/LTC2257-12/LTC2256-12 are sam-

pling 12-bit A/D converters designed for digitizing high

frequency, wide dynamic range signals. They are perfect

for demanding communications applications with AC

performancethatincludes71.1dBSNRand85dBspurious

n

71.1dB SNR

n

88dB SFDR

n

Low Power: 79mW/47mW/34mW

Single 1.8V Supply

n

CMOS, DDR CMOS or DDR LVDS Outputs

n

free dynamic range (SFDR). Ultralow jitter of 0.17ps

Selectable Input Ranges: 1V to 2V

RMS

P-P

n

allows undersampling of IF frequencies with excellent

800MHz Full-Power Bandwidth S/H

noise performance.

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

DC specs include 0.3LSB INL (typical), 0.1LSB DNL

(typical) and no missing codes over temperature. The

transition noise is a low 0.3LSB

Serial SPI Port for Conﬁguration

.

RMS

Pin Compatible 14-Bit and 12-Bit Versions

The digital outputs can be either full rate CMOS, double

data rate CMOS, or double data rate LVDS. A separate

output power supply allows the CMOS output swing to

range from 1.2V to 1.8V.

40-Pin (6mm × 6mm) QFN Package

APPLICATIONS

n

+

–

Communications

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

n

Cellular Base Stations

n

Software Deﬁned Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

Nondestructive Testing

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

1.8V

2-Tone FFT, f_IN= 68MHz and 69MHz

1.2V

TO 1.8V

V

DD

0

OV

DD

–10

–20

–30

–40

–50

–60

–70

D11

+

–

12-BIT

PIPELINED

ADC CORE

CMOS

OR

LVDS

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

INPUT

S/H

D0

OGND

–80

–90

CLOCK/DUTY

CYCLE

CONTROL

–100

–110

–120

225812 TA01a

GND

0

20

10

FREQUENCY (MHz)

30

65MHz

CLOCK

225812 TA01b

225812p

1

LTC2258-12

LTC2257-12/LTC2256-12

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1, 2)}

Supply Voltages (V , OV )....................... –0.3V to 2V

Digital Output Voltage ................ –0.3V to (OV + 0.3V)

DD

+

–

Analog Input Voltage (A , A

,

Operating Temperature Range:

IN

PAR/SER, SENSE) (Note 3)...........–0.3V to (V + 0.2V)

LTC2258C, LTC2257C, LTC2256C............. 0°C to 70°C

LTC2258I, LTC2257I, LTC2256I............ –40°C to 85°C

Storage Temperature Range................... –65°C to 150°C

DD

+

–

Digital Input Voltage (ENC , ENC , CS,

SDI, SCK) (Note 4).................................... –0.3V to 3.9V

SDO (Note 4) ............................................ –0.3V to 3.9V

PIN CONFIGURATIONS

DOUBLE DATA RATE CMOS OUTPUT MODE

TOP VIEW

FULL-RATE CMOS OUTPUT MODE

TOP VIEW

40 39 38 37 36 35 34 33 32 31

+

40 39 38 37 36 35 34 33 32 31

+

A

1

2

30

29

28

D7

IN

A

1

2

30

29

28

D6_7

IN

–

D6

IN

DNC

IN

+

–

+

–

GND

REFH

3

CLKOUT

GND

REFH

3

CLKOUT

4

27 CLKOUT

4

27 CLKOUT

REFH

5

26 OV

DD

REFH

5

26 OV

DD

41

REFL

6

25

OGND

24 D5

23

REFL

6

25

OGND

REFL

7

REFL

7

24 D4_5

PAR/SER

8

D4

22 D3

21

PAR/SER

8

23

22

21

DNC

D2_3

DNC

V

DD

9

V

DD

9

V

10

D2

DD

V

DD

10

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

= 150°C, θ = 32°C/W

JA

JMAX

T

= 150°C, θ = 32°C/W

JMAX JA

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

DOUBLE DATA RATE LVDS OUTPUT MODE

TOP VIEW

40 39 38 37 36 35 34 33 32 31

+

–

+

–

A

1

2

30

29

28

D6_7

IN

+

–

GND

REFH

3

CLKOUT

4

27 CLKOUT

REFH

5

26 OV

DD

41

REFL

6

25

OGND

+

REFL

7

24 D4_5

–

+

–

PAR/SER

8

23

D4_5

22 D2_3

21

V

DD

9

V

DD

10

D2_3

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

JMAX

= 150°C, θ = 32°C/W

JA

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

225812p

2

LTC2258-12

LTC2257-12/LTC2256-12

ORDER INFORMATION

LEAD FREE FINISH

LTC2258CUJ-12#PBF

LTC2258IUJ-12#PBF

LTC2257CUJ-12#PBF

LTC2257IUJ-12#PBF

LTC2256CUJ-12#PBF

LTC2256IUJ-12#PBF

TAPE AND REEL

PART MARKING*

LTC2258UJ-12

LTC2257UJ-12

LTC2256UJ-12

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2258CUJ-12#TRPBF

LTC2258IUJ-12#TRPBF

LTC2257CUJ-12#TRPBF

LTC2257IUJ-12#TRPBF

LTC2256CUJ-12#TRPBF

LTC2256IUJ-12#TRPBF

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

CONVERTER CHARACTERISTICS _{The l denotes the speciﬁcations which apply over the full operating}

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

LTC2261-12

TYP

LTC2260-12

TYP

LTC2259-12

TYP MAX

PARAMETER

CONDITIONS

MIN

12

MAX

MIN

12

MAX

MIN

12

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

–1

0.3

0.1

1.5

1

0.4

9

–1

0.3

0.1

1.5

1

0.4

9

–1

0.3

0.1

1.5

1

0.4

9

LSB

mV

–0.4

–9

–0.4

–9

–0.4

–9

Gain Error

Internal Reference

External Reference

1.5

0.4

1.5

0.4

1.5

0.4

%FS

l

–1.5

1.5

–1.5

1.5

–1.5

1.5

Offset Drift

20

μV/°C

Full-Scale Drift

Internal Reference

External Reference

30

10

30

10

30

10

ppm/°C

Transition Noise

External Reference

0.3

LSB

RMS

225812p

3

LTC2258-12

LTC2257-12/LTC2256-12

ANALOG INPUT ^Thel denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.7V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

l

V

Analog Input Range (A – A

)

1 to 2

V

P-P

IN

DD

+

–

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

V

– 100mV

0.625

V

CM

V

+ 100mV

1.300

V

IN(CM)

SENSE

INCM

IN

CM

External Voltage Reference Applied to SENSE External Reference Mode

1.250

V

I

Analog Input Common Mode Current

Per Pin, 125Msps

Per Pin, 105Msps

Per Pin, 80Msps

155

130

100

μA

+

–

l

I

t

Analog Input Leakage Current

0 < A , A < V , No Encode

–1

–3

–6

1

3

6

μA

ns

IN1

IN

DD

PAR/SER Input Leakage Current

SENSE Input Leakage Current

0 < PAR/SER < V

IN2

0.625V < SENSE < 1.3V

IN3

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

0

AP

0.17

80

ps

RMS

JITTER

CMRR

BW-3B

dB

Figure 6 Test Circuit

800

MHz

DYNAMIC ACCURACY ^Thel denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

LTC2258-12

TYP

LTC2257-12

TYP

LTC2256-12

TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

SNR

Signal-to-Noise Ratio

5MHz Input

71.1

71

70.8

70.6

70.4

70.5

70

dB

l

70MHz Input

140MHz Input

69.4

69.1

70.8

69.7

SFDR

Spurious Free Dynamic Range 5MHz Input

2nd or 3rd Harmonic

91.7

91.5

81.1

91.7

91.3

85.7

91.9

95.4

89.8

dB

70MHz Input

140MHz Input

76

83

76

82

79

85

Spurious Free Dynamic Range 5MHz Input

4th Harmonic or Higher

98.5

99.1

98.3

97.8

97.4

95.6

98.3

98.4

88.1

dB

70MHz Input

140MHz Input

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

70MHz Input

140MHz Input

71

70.9

70.3

70.7

70.6

70.2

70.4

69.8

69.5

dB

68.6

68.8

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

0.5 • V

25

MAX

UNITS

V

CM

V

CM

V

CM

V

REF

V

REF

V

REF

V

REF

Output Voltage

I

0.5 • V – 25mV

0.5 • V + 25mV

OUT

DD

Output Temperature Drift

Output Resistance

Output Voltage

ppm/°C

Ω

–600μA < I

< 1mA

4

OUT

I

= 0

1.225

1.250

25

1.275

V

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400μA < I

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

225812p

4

LTC2258-12

LTC2257-12/LTC2256-12

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

–

Differential Encode Mode (ENC Not Tied to GND)

l

V

Differential Input Voltage

(Note 8)

0.2

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

l

1.1

0.2

1.6

3.6

+

–

V

IN

Input Voltage Range

Input Resistance

ENC , ENC to GND

(See Figure 10)

(Note 8)

V

kΩ

pF

R

10

IN

C

Input Capacitance

3.5

–

Single-Ended Encode Mode (ENC Tied to GND)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Voltage Range

Input Resistance

V

= 1.8V

1.2

0

V

IH

IL

IN

DD

0.6

3.6

DD

+

ENC to GND

(See Figure 11)

(Note 8)

V

R

30

kΩ

pF

IN

C

Input Capacitance

3.5

DIGITAL INPUTS (CS, SDI, SCK)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

= 1.8V

0.6

10

I

= 0V to 3.6V

–10

μA

pF

IN

C

Input Capacitance

(Note 8)

3

200

4

IN

SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

DD

= 1.8V, SDO = 0V

Ω

μA

pF

OL

l

I

OH

SDO = 0V to 3.6V

(Note 8)

–10

10

C

OUT

DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)

OV = 1.8V

DD

l

V

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.750

1.790

0.010

V

OH

OL

O

I = 500μA

O

0.050

OV = 1.5V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.488

0.010

V

O

I = 500μA

O

OV = 1.2V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.185

0.010

V

O

I = 500μA

O

DIGITAL DATA OUTPUTS (LVDS MODE)

l

V

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

350

175

454

mV

OD

V

OS

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

V

R

Termination Enabled, OV = 1.8V

100

Ω

TERM

DD

225812p

5

LTC2258-12

LTC2257-12/LTC2256-12

POWER REQUIREMENTS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 9)

LTC2258-12

TYP

LTC2257-12

TYP

LTC2256-12

TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

CMOS Output Modes: Full Data Rate and Double Data Rate

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

(Note 10)

1.7

1.1

1.8

1.9

1.7

1.1

1.8

1.9

1.7

1.1

1.8

1.9

V

DD

OV

DD

I

DC Input

Sine Wave Input

43.6

44.2

81.1

26.3

27.2

67.4

18.9 56.6

19.1

mA

VDD

I

Digital Supply Current

Power Dissipation

Sine Wave Input, OV =1.2V

2.3

1.5

0.9

mA

OVDD

DD

l

P

DC Input

78.5

82.3

146

47.3

50.8

122

34

35.5

102

mW

DISS

Sine Wave Input, OV =1.2V

DD

LVDS Output Mode

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Digital Supply Current

(Note 10)

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DD

OV

(Note 10)

DD

I

Sine Wave Input

48.1

86.9

30.6

73.1

22.7 62.2

mA

VDD

OVDD

l

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

21.7

36.2

22.2

43.3

21.4

35.5

22.2

43.3

21.6 22.2

35.9 43.3

mA

(0V = 1.8V)

DD

l

P

DISS

Power Dissipation

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

125.6 196

151.7 235

93.6

119

172

210

79.7

152

mW

105.5 190

All Output Modes

P

Sleep Mode Power

Nap Mode Power

0.5

9

0.5

9

0.5

9

mW

SLEEP

NAP

Power Increase with Differential Encode Mode Enabled

(No increase for Nap or Sleep Modes)

10

DIFFCLK

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

LTC2258-12

TYP

LTC2257-12

TYP

LTC2256-12

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

TYP MAX UNITS

l

f

t

Sampling Frequency

(Note 10)

1

65

1

40

1

25

MHz

S

L

l

ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2.0

7.69

500

11.8

2.00

12.5

500

19

2.00

20

500

ns

l

t

ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2.0

7.69

500

11.8

2.00

12.5

500

19

2.00

20

500

ns

H

Sample-and-Hold

Acquisition Delay Time

0

ns

AP

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.1

1

1.7

1.4

0.3

3.1

2.6

0.6

ns

D

L

C = 5pF (Note 8)

L

C

t – t (Note 8)

0

SKEW

D

C

Full Data Rate Mode

Double Data Rate Mode

5.0

5.5

Cycles

225812p

6

LTC2258-12

LTC2257-12/LTC2256-12

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (LVDS Mode)

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.1

1

1.8

1.5

0.3

5.5

3.2

2.7

0.6

ns

D

L

C = 5pF (Note 8)

L

C

t – t (Note 8)

0

ns

SKEW

D

C

Cycles

SPI Port Timing (Note 8)

l

t

SCK Period

Write Mode

40

ns

SCK

Readback Mode, C

= 20pF, R

= 2k

250

SDO

PULLUP

l

t

CS to SCK Setup Time

SCK to CS Setup Time

SDI Setup Time

5

ns

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Readback Mode, C

125

SDO

PULLUP

+

–

termination disabled, differential ENC /ENC = 2V sine wave, input

P-P

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

range = 2V with differential drive, unless otherwise noted.

P-P

Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a

best ﬁt straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

will be clamped by internal diodes. This product can handle input currents

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code ﬂickers between 0000 0000 0000 and 1111 1111 1111 in

2’s complement output mode.

DD

of greater than 100mA below GND or above V without latchup.

DD

Note 8: Guaranteed by design, not subject to test.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above V

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 9: V = 1.8V, f

or 80MHz (LTC2259), ENC = single-ended 1.8V square wave, ENC = 0V,

= 125MHz (LTC2261), 105MHz (LTC2260),

DD

SAMPLE

+

–

DD

input range = 2V with differential drive, 5pF load on each digital output

P-P

unless otherwise noted.

Note 5: V = OV = 1.8V, f

105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal

= 125MHz (LTC2261),

DD

SAMPLE

Note 10: Recommended operating conditions.

TIMING DIAGRAMS

Full-Rate CMOS Output Mode Timing

All Outputs Are Single-Ended and Have CMOS Levels

t

AP

N + 4

N + 2

ANALOG

INPUT

N

N + 3

t

H

N + 1

t

L

–

ENC

+

ENC

t

D

N – 5

N – 4

N – 3

N – 2

N – 1

D0-D11, OF

t

C

+

CLKOUT

–

CLKOUT

225812 TD01

225812p

7

LTC2258-12

LTC2257-12/LTC2256-12

TIMING DIAGRAMS

Double Data Rate CMOS Output Mode Timing

All Outputs Are Single-Ended and Have CMOS Levels

t

AP

N + 4

N + 2

ANALOG

INPUT

N

N + 3

t

H

N + 1

t

L

–

ENC

+

ENC

t

D

t

D

D0_1

D0

D1

D0

D1

D0

D1

D0

N-2

D1

N-2

N-5

N-4

N-3

•

D10_11

OF

D10

D11

D10

OF

D11

D10

D11

D10

D11

N-2

N-5

N-4

N-3

N-2

OF

N-2

N-5

N-4

N-3

t

C

+

CLKOUT

–

CLKOUT

225812 TD02

Double Data Rate LVDS Output Mode Timing

All Outputs Are Differential and Have LVDS Levels

t

AP

N + 4

N + 2

ANALOG

INPUT

N

N + 3

t

H

N + 1

t

L

–

ENC

+

ENC

t

D

t

D

+

D0_1

D0

D1

D0

D1

N-4

D0

N-3

D1

D0

D1

N-2

N-5

N-4

N-3

N-2

–

D0_1

•

+

D10_11

D10

D11

D10

D11

D10

D11

D10

D11

N-2

N-5

N-4

N-3

N-2

–

D10_11

+

OF

N-3

N-5

N-4

N-3

–

OF

t

C

t

C

+

CLKOUT

–

CLKOUT

225812 TD03

225812p

8

LTC2258-12

LTC2257-12/LTC2256-12

TIMING DIAGRAMS

SPI Port Timing (Readback Mode)

t

DS

t

H

S

DH

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

225812 TD04

HIGH IMPEDANCE

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2258-12: Integral

Nonlinearity (INL)

LTC2258-12: Differential

Nonlinearity (DNL)

LTC2258-12: 8k Point FFT, f_IN= 5MHz

–1dBFS, 65Msps

1.0

0.8

1.0

0.8

0.6

0

–10

–20

–30

–40

–50

–60

–70

0.6

0.4

0.2

0

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–80

–90

–100

–110

–120

–0.8

–1.0

0

10

20

30

0

2048

3072

4096

0

2048

3072

4096

1024

OUTPUT CODE

FREQUENCY (MHz)

225812 G01

225812 G02

225812 G03

225812p

9

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2258-12: 8k Point FFT, f_IN= 30MHz

–1dBFS, 65Msps

LTC2258-12: 8k Point FFT, f_IN= 70MHz

–1dBFS, 65Msps

LTC2258-12: 8k Point FFT, f_IN= 140MHz

–1dBFS, 65Msps

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

20

10

FREQUENCY (MHz)

30

0

20

10

FREQUENCY (MHz)

30

0

10

20

30

FREQUENCY (MHz)

225812 G05

225812 G06

225812 G04

LTC2258-12: SNR vs Input

Frequency, –1dB, 2V Range,

65Msps

LTC2258-12: 8k Point 2-Tone FFT,

f_IN= 68MHz, 69MHz, –1dBFS,

65Msps

LTC2258-12: Shorted Input

Histogram

18000

16000

14000

12000

10000

8000

0

–10

–20

–30

–40

–50

–60

–70

72

71

70

69

68

67

66

6000

4000

2000

0

–80

–90

–100

–110

–120

2049

2051

2053

0

20

10

FREQUENCY (MHz)

30

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

50

OUTPUT CODE

225812 G08

225812 G07

225812 G09

LTC2258-12: SFDR vs Input

Frequency, –1dB, 2V Range,

65Msps

LTC2258-12: SFDR vs Input Level,

LTC2258-12: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dB

f

_IN= 70MHz, 2V Range, 65Msps

50

45

40

95

90

85

80

75

70

65

110

100

90

dBFS

LVDS OUTPUTS

80

70

dBc

60

50

40

30

20

10

0

CMOS OUTPUTS

35

30

0

20

40

60

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

50

–80

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

SAMPLE RATE (Msps)

225812 G13

225812 G10

225812 G12

225812p

10

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2258-12: IO_VDDvs Sample

Rate, 5MHz Sine Wave Input,

–1dB, 5pF on Each Data Output

LTC2258-12: SNR vs SENSE,

_IN= 5MHz, –1dB

LTC2257-12: Integral Nonlinearity

(INL)

f

45

40

35

30

25

20

15

1.0

0.8

0.6

0.4

0.2

0

72

71

70

69

68

67

66

3.5mA LVDS

1.75mA LVDS

–0.2

–0.4

–0.6

–0.8

–1.0

10

5

1.8V CMOS

20

1.2V CMOS

0

40

60

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

2048

3072

4096

1024

SAMPLE RATE (Msps)

SENSE PIN (V)

OUTPUT CODE

225812 G14

225812 G15

225812 G21

LTC2257-12: 8k Point FFT, f_IN= 5MHz

–1dBFS, 40Msps

LTC2257-12: 8k Point FFT, f_IN= 30MHz

–1dBFS, 40Msps

LTC2257-12: Differential

Nonlinearity (DNL)

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

–80

–90

–100

–110

–120

0

20

10

0

20

0

2048

3072

4096

10

1024

FREQUENCY (MHz)

OUTPUT CODE

225812 G23

225812 G24

225812 G22

LTC2257-12: 8k Point 2-Tone FFT,

f_IN= 68MHz, 69MHz, –1dBFS,

40Msps

LTC2257-12: 8k Point FFT, f_IN= 70MHz

–1dBFS, 40Msps

LTC2257-12: 8k Point FFT, f_IN= 137MHz

–1dBFS, 40Msps

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

20

0

20

0

20

10

FREQUENCY (MHz)

225812 G25

225812 G26

225812 G27

225812p

11

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2257-12: SNR vs Input

Frequency, –1dB, 2V Range,

40Msps

LTC2257-12: SFDR vs Input

Frequency, –1dB, 2V Range,

40Msps

LTC2257-12: Shorted Input

Histogram

72

71

70

69

68

67

66

18000

16000

14000

12000

95

90

85

80

75

70

65

10000

8000

6000

4000

2000

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

2049

2051

OUTPUT CODE

2053

50

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

50

225812 G29

225812 G28

225812 G30

LTC2257-12: IO_VDDvs Sample

Rate, 5MHz Sine Wave Input,

–1dB, 5pF on Each Data Output

LTC2257-12: SFDR vs Input Level,

LTC2257-12: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dB

f

_IN= 70MHz, 2V Range, 40Msps

45

40

35

30

25

20

15

110

100

90

35

30

25

20

3.5mA LVDS

dBFS

80

70

LVDS OUTPUTS

60

dBc

1.75mA LVDS

50

40

30

20

10

0

CMOS OUTPUTS

10

5

1.2V CMOS

1.8V CMOS

0

–80

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

20

40

–70

0

20

40

SAMPLE RATE (Msps)

225812 G34

225812 G32

225812 G33

LTC2257-12: SNR vs SENSE,

f_IN= 5MHz, –1dB

LTC2256-12: Integral Nonlinearity

(INL)

LTC2256-12: Differential

Nonlinearity (DNL)

72

1.0

0.8

0.6

0.4

0.2

0

1.0

0.8

0.6

71

70

69

68

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

67

66

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

2048

3072

4096

1024

0

2048

3072

4096

1024

SENSE PIN (V)

OUTPUT CODE

225812 G35

225812 G41

225812 G42

225812p

12

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2256-12: 8k Point FFT, f_IN= 30MHz

–1dBFS, 25Msps

LTC2256-12: 8k Point FFT, f_IN= 70MHz

–1dBFS, 25Msps

LTC2256-12: 8k Point FFT, f_IN= 5MHz

–1dBFS, 25Msps

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

10

0

10

5

0

10

5

FREQUENCY (MHz)

225812 G45

225812 G43

225812 G44

LTC2256-12: 8k Point 2-Tone FFT,

f_IN= 68MHz, 69MHz, –1dBFS,

25Msps

LTC2256-12: 8k Point FFT, f_IN= 140MHz

–1dBFS, 25Msps

LTC2256-12: Shorted Input

Histogram

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

18000

16000

14000

12000

10000

8000

–80

–90

–100

–110

–120

–80

–90

–100

–110

–120

6000

4000

2000

0

5

0

5

10

2049

2051

2053

FREQUENCY (MHz)

OUTPUT CODE

225814 G46

225814 G47

225812 G48

LTC2256-12: SNR vs Input

Frequency, –1dB, 2V Range,

25Msps

LTC2256-12: SFDR vs Input

Frequency, –1dB, 2V Range,

25Msps

LTC2256-12: SFDR vs Input Level,

f_IN= 70MHz, 2V Range, 25Msps

72

71

70

69

68

67

110

100

90

95

90

85

80

75

70

65

dBFS

80

70

dBc

60

50

40

30

20

10

0

66

–80

–70

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

50

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

50

225812 G52

225812 G49

225812 G50

225812p

13

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2256-12: IO_VDDvs Sample Rate,

LTC2256-12: SNR vs SENSE,

f_IN= 5MHz, –1dB

LTC2256-12: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dB

5MHz Sine Wave Input, –1dB, 5pF

on Each Data Output

72

71

25

20

15

10

45

40

35

30

25

20

15

3.5mA LVDS

1.75mA LVDS

LVDS OUTPUTS

CMOS OUTPUTS

70

69

68

67

66

10

5

1.2V CMOS

1.8V CMOS

0

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

SENSE PIN (V)

0

10

20

0

10

20

SAMPLE RATE (Msps)

225812 G55

226112 G53

225812 G54

PIN FUNCTIONS

PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT

MODES

V

(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass

DD

to ground with 0.1μF ceramic capacitors. Pins 9 and 10

can share a bypass capacitor.

+

A

(Pin 1): Positive Differential Analog Input.

(Pin 2): Negative Differential Analog Input.

IN

+

ENC (Pin 11): Encode Input. Conversion starts on the

rising edge.

–

GND (Pin 3): ADC Power Ground.

–

ENC (Pin 12): Encode Complement Input. Conversion

starts on the falling edge.

REFH (Pins 4, 5): ADC High Reference. Bypass to Pins

6, 7 with a 2.2μF ceramic capacitor and to ground with a

0.1μF ceramic capacitor.

CS (Pin 13): In serial programming mode, (PAR/SER =

0V), CS is the serial interface chip select input. When

CS is low, SCK is enabled for shifting data on SDI into

the mode control registers. In the parallel programming

REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins

4, 5 with a 2.2μF ceramic capacitor and to ground with a

0.1μF ceramic capacitor.

mode (PAR/SER = V ), CS controls the clock duty cycle

DD

stabilizer. When CS is low, the clock duty cycle stabilizer is

turned off. When CS is high, the clock duty cycle stabilizer

is turned on. CS can be driven with 1.8V to 3.3V logic.

PAR/SER(Pin8):ProgrammingModeSelectionPin.Con-

nect to ground to enable the serial programming mode.

CS, SCK, SDI, SDO become a serial interface that control

SCK (Pin 14): In serial programming mode, (PAR/SER =

the A/D operating modes. Connect to V to enable the

DD

0V), SCK is the serial interface clock input. In the parallel

parallel programming mode where CS, SCK, SDI become

parallel logic inputs that control a reduced set of the A/D

operating modes. PAR/SER should be connected directly

programming mode (PAR/SER = V ), SCK controls the

DD

digital output mode. When SCK is low, the full-rate CMOS

output mode is enabled. When SCK is high, the double

to ground or the V of the part and not be driven by a

DD

logic signal.

225812p

14

LTC2258-12

LTC2257-12/LTC2256-12

PIN FUNCTIONS

data rate LVDS output mode (with 3.5mA output current)

FULL-RATE CMOS OUTPUT MODE

is enabled. SCK can be driven with 1.8V to 3.3V logic.

All Pins Below Have CMOS Output Levels (OGND to

SDI (Pin 15): In serial programming mode, (PAR/SER =

0V), SDI is the serial interface data input. Data on SDI is

clocked into the mode control registers on the rising edge

of SCK. In the parallel programming mode (PAR/SER =

OV )

DD

D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is

the MSB.

V ), SDI can be used to power down the part. When SDI

–

+

DD

CLKOUT (Pin 27): Inverted version of CLKOUT .

is low, the part operates normally. When SDI is high, the

part enters sleep mode. SDI can be driven with 1.8V to

3.3V logic.

+

CLKOUT (Pin 28): Data Output Clock. The digital outputs

normally transition at the same time as the falling edge

+

of CLKOUT . The phase of CLKOUT can also be delayed

relative to the digital outputs by programming the mode

control registers.

SDO (Pin 16): In serial programming mode, (PAR/SER

= 0V), SDO is the optional serial interface data output.

Data on SDO is read back from the mode control registers

and can be latched on the falling edge of SCK. SDO is an

open-drain NMOS output that requires an external 2k

pull-up resistor to 1.8V-3.3V. If read back from the mode

control registers is not needed, the pull-up resistor is not

necessaryandSDOcanbeleftunconnected.Intheparallel

DNC (Pins 17, 18, 35): Do not connect these pins.

OF (Pin 36): Over/Under Flow Digital Output. OF is high

when an overﬂow or underﬂow has occurred.

DOUBLE DATA RATE CMOS OUTPUT MODE

programming mode (PAR/SER = V ), SDO is not used

DD

and should not be connected.

All Pins Below Have CMOS Output Levels (OGND to

OGND (Pin 25): Output Driver Ground.

OV )

DD

OV (Pin 26): Output Driver Supply. Bypass to ground

D0_1toD10_11(Pins20,22,24,30,32,34):DoubleData

Rate Digital Outputs. Two data bits are multiplexed onto

each output pin. The even data bits (D0, D2, D4, D6, D8,

DD

with a 0.1μF ceramic capacitor.

V

(Pin 37): Common Mode Bias Output, Nominally

CM

+

D10) appear when CLKOUT is low. The odd data bits (D1,

Equal to V /2. V should be used to bias the common

DD

CM

+

D3, D5, D7, D9, D11) appear when CLKOUT is high.

mode of the analog inputs. Bypass to ground with a 0.1μF

ceramic capacitor.

–

+

CLKOUT (Pin 27): Inverted version of CLKOUT .

+

V

(Pin38):ReferenceVoltageOutput.Bypasstoground

REF

CLKOUT (Pin 28): Data Output Clock. The digital outputs

with a 1μF ceramic capacitor, nominally 1.25V.

normally transition at the same time as the falling and ris-

+

ing edges of CLKOUT . The phase of CLKOUT can also

be delayed relative to the digital outputs by programming

the mode control registers.

SENSE(Pin39):ReferenceProgrammingPin.Connecting

SENSEtoV selectstheinternalreferenceanda 1Vinput

DD

range. Connecting SENSE to ground selects the internal

reference and a 0.5V input range. An external reference

between 0.625V and 1.3V applied to SENSE selects an

DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not

connect these pins.

input range of 0.8 • V

.

SENSE

OF (Pin 36): Over/Under Flow Digital Output. OF is high

when an overﬂow or underﬂow has occurred.

225812p

15

LTC2258-12

LTC2257-12/LTC2256-12

PIN FUNCTIONS

DOUBLE DATA RATE LVDS OUTPUT MODE

+

appear when CLKOUT is low. The odd data bits (D1, D3,

+

D5, D7, D9, D11) appear when CLKOUT is high.

All Pins Below Have LVDS Output Levels. The Output

Current Level is Programmable. There is an Optional

Internal 100Ω Termination Resistor Between the Pins

of Each LVDS Output Pair.

–

+

CLKOUT /CLKOUT (Pins 27/28): Data Output Clock.

The digital outputs normally transition at the same time

+

as the falling and rising edges of CLKOUT . The phase of

+

CLKOUT canalsobedelayedrelativetothedigitaloutputs

–

+

–

+

D0_1 /D0_1 to D10_11 /D10_11 (Pins 19/20, 21/22,

23/24, 29/30, 31/32, 33/34): Double Data Rate Digital

Outputs. Two data bits are multiplexed onto each dif ferential

output pair. The even data bits (D0, D2, D4, D6, D8, D10)

by programming the mode control registers.

–

+

OF /OF (Pins35/36):Over/UnderFlowDigitalOutput.OF

is high when an overﬂow or underﬂow has occurred.

FUNCTIONAL BLOCK DIAGRAM

+

A

IN

V

DD

INPUT

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

–

GND

V

CM

V

DD

/2

0.1μF

V

REF

1.25V

REFERENCE

SHIFT REGISTER

AND CORRECTION

1μF

RANGE

SELECT

REFH

REFL INTERNAL CLOCK SIGNALS

REF

BUF

OV

OF

DD

SENSE

D11

•

DIFF

CLOCK/DUTY

CYCLE

CONTROL

MODE

OUTPUT

DRIVERS

REF

CONTROL

AMP

REGISTERS

D0

+

–

CLKOUT

225812 F01

0.1μF

2.2μF

REFH

REFL

OGND

+

–

PAR/SER

SCK SDI

SDO

ENC

CS

0.1μF

Figure 1. Functional Block Diagram

225812p

16

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

CONVERTER OPERATION

inputs should swing from V – 0.5V to V + 0.5V. There

CM CM

should be 180° phase difference between the inputs.

The LTC2258-12/LTC2257-12/LTC2256-12 are low power

12-bit 65Msps/40Msps/25Msps A/D converters that are

poweredbyasingle1.8Vsupply. Theanaloginputsshould

be driven differentially. The encode input can be driven

differentially or single-ended for lower power consump-

tion. The digital outputs can be CMOS, double data rate

CMOS (to halve the number of output lines), or double

data rate LVDS (to reduce digital noise in the system.)

Many additional features can be chosen by programming

the mode control registers through a serial SPI port. See

the Serial Programming Mode section.

INPUT DRIVE CIRCUITS

Input ﬁltering

If possible, there should be an RC lowpass ﬁlter right at

the analog inputs. This lowpass ﬁlter isolates the drive

circuitry from the A/D sample-and-hold switching, and

alsolimitswidebandnoisefromthedrivecircuitry.Figure 3

showsanexampleofaninputRCﬁlter. TheRCcomponent

values should be chosen based on the application’s input

frequency.

ANALOG INPUT

Transformer Coupled Circuits

The analog input is a differential CMOS sample-and-hold

circuit(Figure2).Theinputsshouldbedrivendifferentially

around a common mode voltage set by the V output

pin, which is nominally V /2. For the 2V input range, the

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

CM

tap is biased with V , setting the A/D input at its optimal

CM

DD

DC level. At higher input frequencies a transmission line

50Ω

V

CM

LTC2258-12

V

0.1μF

DD

C

SAMPLE

3.5pF

0.1μF

R

T1

1:1

ON

+

25Ω

A

10Ω

10ꢀ

IN

25Ω

ANALOG

INPUT

+

–

A

IN

LTC2258-12

C

0.1μF

25Ω

PARASITIC

1.8pF

V

DD

12pF

SAMPLE

3.5pF

R

25Ω

ON

–

25Ω

A

IN

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

C

PARASITIC

225812 F03

1.8pF

V

DD

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

1.2V

10k

+

–

ENC

10k

1.2V

225812 F02

Figure 2. Equivalent Input Circuit

225812p

17

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

balun transformer (Figures 4 to 6) has better balance,

resulting in lower A/D distortion.

At very high frequencies an RF gain block will often have

lower distortion than a differential ampliﬁer. If the gain

blockissingle-ended,thenatransformercircuit(Figures 4

to 6) should convert the signal to differential before driv-

ing the A/D.

Ampliﬁer Circuits

Figure 7 shows the analog input being driven by a high

speeddifferentialampliﬁer.TheoutputoftheampliﬁerisAC

coupledtotheA/Dsotheampliﬁer’soutputcommonmode

voltage can be optimally set to minimize distortion.

50Ω

V

CM

0.1μF

+

A

ANALOG

INPUT

IN

T2

50Ω

V

CM

LTC2258-12

T1

0.1μF

25Ω

0.1μF

1.8pF

0.1μF

+

–

A

ANALOG

INPUT

IN

T2

A

IN

LTC2258-12

T1

0.1μF

25Ω

225812 F05

4.7pF

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1LB

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

–

A

IN

225812 F04

Figure 5. Recommended Front-End Circuit for Input

Frequencies from 170MHz to 270MHz

T1: MA/COM MABA-007159-000000

T2: MA/COM MABAES0060

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

Figure 4. Recommended Front-End Circuit for Input

Frequencies from 70MHz to 170MHz

50Ω

V

CM

0.1μF

2.7nH

0.1μF

+

–

A

IN

ANALOG

INPUT

LTC2258-12

25Ω

T1

2.7nH

T1: MA/COM ETC1-1-13

225812 F06

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

Figure 6. Recommended Front-End Circuit for Input

Frequencies Above 270MHz

225812p

18

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

Reference

The V , REFH and REFL pins should be bypassed as

REF

shown in Figure 8. The 0.1μF capacitor between REFH and

REFL should be as close to the pins as possible (not on

the back side of the circuit board).

The LTC2258-12/2257-12/2256-12 has an internal 1.25V

voltage reference. For a 2V input range using the internal

reference, connect SENSE to V . For a 1V input range

DD

using the external reference, connect SENSE to ground.

For a 2V input range with an external reference, apply a

1.25V reference voltage to SENSE (Figure 9.)

LTC2258-12

5Ω

V

REF

1.25V BANDGAP

REFERENCE

1.25V

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

1μF

0.625V

will then be 1.6 • V

.

SENSE

RANGE

DETECT

AND

CONTROL

TIE TO V FOR 2V RANGE;

DD

TIE TO GND FOR 1V RANGE;

SENSE

V

CM

RANGE = 1.6 • V

FOR

SENSE

BUFFER

0.65V < V

< 1.300V

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

SENSE

0.1μF

200Ω 200Ω

INTERNAL ADC

HIGH REFERENCE

0.1μF

+

–

0.1μF

25Ω

A

IN

REFH

0.1μF

LTC2258-12

ANALOG

INPUT

+

12pF

2.2μF

–

0.8x

DIFF AMP

25Ω

A

IN

0.1μF

225812 F07

REFL

Figure 7. Front-End Circuit Using a High Speed

Differential Ampliﬁer

INTERNAL ADC

LOW REFERENCE

225812 F08

Figure 8. Reference Circuit

V

REF

1μF

LTC2258-12

1.25V

EXTERNAL

REFERENCE

SENSE

1μF

225812 F09

Figure 9. Using an External 1.25V Reference

225812p

19

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

Encode Input

The single-ended encode mode should be used with CMOS

–

encode inputs. To select this mode, ENC is connected

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10) and the single-ended encode mode

(Figure 11).

+

to ground and ENC is driven with a square wave encode

+

input. ENC can be taken above V (up to 3.6V) so 1.8V

DD

+

to3.3VCMOSlogiclevelscanbeused.TheENC threshold

+

is0.9V. ForgoodjitterperformanceENC should have fast

rise and fall times.

Clock Duty Cycle Stabilizer

The differential encode mode is recommended for sinu-

soidal, PECL or LVDS encode inputs (Figures 12, 13). The

encode inputs are internally biased to 1.2V through 10k

equivalent resistance. The encode inputs can be taken

For good performance the encode signal should have a

50%( 5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency or is turned off, the duty cycle

stabilizer circuit requires one hundred clock cycles to lock

onto the input clock. The duty cycle stabilizer is enabled

by mode control register A2 (serial programming mode),

or by CS (parallel programming mode).

above V (up to 3.6V), and the common mode range

DD

is from 1.1V to 1.6V. In the differential encode mode,

–

ENC should stay at least 200mV above ground to avoid

falselytriggeringthesingle-endedencodemode.Forgood

+

–

jitter performance ENC and ENC should have fast rise

and fall times.

0.1μF

LTC2258-12

+

25Ω

V

DD

ENC

T1

1:4

DIFFERENTIAL

COMPARATOR

100Ω

D1

V

DD

LTC2258-12

100Ω

–

ENC

15k

30k

+

–

0.1μF

ENC

225812 F12

T1: COILCRAFT WBC4 - 1WL

D1: AVAGO HSMS - 2822

ENC

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

Figure 12. Sinusoidal Encode Drive

225812 F10

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

0.1μF

+

ENC

LTC2258-12

+

PECL OR

LTC2258-12

LVDS

CLOCK

0.1μF

1.8V TO 3.3V

0V

ENC

–

ENC

–

30k

CMOS LOGIC

BUFFER

225812 F13

225812 F11

Figure 13. PECL or LVDS Encode Drive

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

225812p

20

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

thedutycyclestabilizerisdisabled,careshouldbetakento

makethesamplingclockhavea50%( 5%)dutycycle.The

duty cycle stabilizer should not be used below 5Msps.

When using double data rate CMOS at high sample rates

the SNR will degrade slightly (see Typical Performance

Characteristics section). DDR CMOS is not recommended

for sample frequencies above 100MHz.

Double Data Rate LVDS Mode

DIGITAL OUTPUTS

In double data rate LVDS mode, two data bits are mul-

tiplexed and output on each differential output pair.

Digital Output Modes

+

–

There are 6 LVDS output pairs (D0_1 /D0_1 through

+

–

D10_11 /D10_11 ) for the digital output data. Overﬂow

The LTC2258-12/LTC2257-12/LTC2256-12 can operate in

three digital output modes: full rate CMOS, double data

rate CMOS (to halve the number of output lines), or double

data rate LVDS (to reduce digital noise in the system). The

output mode is set by mode control register A3 (serial

programming mode), or by SCK (parallel programming

mode). Note that double data rate CMOS cannot be selected

in the parallel programming mode.

+

–

(OF /OF )andthedataoutputclock(CLKOUT /CLKOUT )

each have an LVDS output pair.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100ꢀ differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

Full-Rate CMOS Mode

The outputs are powered by OV and OGND which are

DD

In full-rate CMOS mode the 12 digital outputs (D0-D11),

+

isolated from the A/D core power and ground. In LVDS

overﬂow (OF), and the data output clocks (CLKOUT ,

–

mode, OV must be 1.8V.

CLKOUT ) have CMOS output levels. The outputs are

DD

powered by OV and OGND which are isolated from the

DD

Programmable LVDS Output Current

A/D core power and ground. OV can range from 1.1V to

DD

1.9V, allowing 1.2V through 1.8V CMOS logic outputs.

In LVDS mode, the default output driver current is 3.5mA.

This current can be adjusted by serially programming mode

control register A3. Available current levels are 1.75mA,

2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

For good performance the digital outputs should drive

minimal capacitive loads. If the load capacitance is larger

than 10pF a digital buffer should be used.

Optional LVDS Driver Internal Termination

Double Data Rate CMOS Mode

In most cases using just an external 100ꢀ termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100ꢀ termination resistor can

beenabledbyseriallyprogrammingmodecontrolregister

A3. The internal termination helps absorb any reﬂections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is increased by 1.6x to maintain about the same output

voltage swing.

In double data rate CMOS mode, two data bits are

multiplexed and output on each data pin. This reduces

the number of data lines by seven, simplifying board

routing and reducing the number of input pins needed

to receive the data. The 6 digital outputs (D0_1, D2_3,

D4_5, D6_7, D8_9, D10_11), overﬂow (OF), and the data

+

–

output clocks (CLKOUT , CLKOUT ) have CMOS output

levels.TheoutputsarepoweredbyOV andOGNDwhich

DD

are isolated from the A/D core power and ground. OV

DD

can range from 1.1V to 1.9V, allowing 1.2V through 1.8V

CMOS logic outputs.

For good performance the digital outputs should drive

minimal capacitive loads. If the load capacitance is larger

than 10pF a digital buffer should be used.

225812p

21

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

on. Another control register bit can invert the polarity of

Overﬂow Bit

+

–

CLKOUT and CLKOUT , independently of the phase shift.

The combination of these two features enables phase

shifts of 45° up to 315° (Figure 14).

The overﬂow output bit (OF) outputs a logic high when

the analog input is either overranged or underranged.

The overﬂow bit has the same pipeline latency as the

data bits.

DATA FORMAT

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overﬂow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

Phase Shifting the Output Clock

In full-rate CMOS mode the data output bits normally

+

change at the same time as the falling edge of CLKOUT ,

+

so the rising edge of CLKOUT can be used to latch the

output data. In double data rate CMOS and LVDS modes

the data output bits normally change at the same time as

Table 1. Output Codes vs Input Voltage

+

–

A

IN

– A

D11-D0

IN

+

thefallingandrisingedgesofCLKOUT . Toallowadequate

setup-and-hold time when latching the data, the CLKOUT

signal may need to be phase shifted relative to the data

outputbits.MostFPGAshavethisfeature;thisisgenerally

the best place to adjust the timing.

(2V RANGE)

>+1.000000V

+0.999512V

+0.999024V

+0.000488V

0.000000V

OF (OFFSET BINARY)

(2’s COMPLEMENT)

+

1

0

1

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

The LTC2261-12/LTC2260-12/LTC2259-12 can also phase

–0.000488V

–0.000976V

–0.999512V

–1.000000V

≤–1.000000V

+

–

shift the CLKOUT /CLKOUT signals by serially program-

ming mode control register A2. The output clock can be

shifted by 0°, 45°, 90° or 135°. To use the phase shifting

feature the clock duty cycle stabilizer must be turned

+

ENC

D0-D11, OF

MODE CONTROL BITS

PHASE

SHIFT

CLKINV

CLKPHASE1 CLKPHASE0

0°

0

1

0

1

0

1

0

1

0

1

0

1

0

1

45°

90°

135°

180°

225°

270°

315°

+

CLKOUT

225812 F14

Figure 14. Phase Shifting CLKOUT

225812p

22

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

Digital Output Randomizer

Alternate Bit Polarity

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

Anotherfeaturethatreducesdigitalfeedbackonthecircuit

board is the alternate bit polarity mode. When this mode

is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11)

are inverted before the output buffers. The even bits (D0,

D2, D4, D6, D8, D10), OF and CLKOUT are not affected.

Thiscanreducedigitalcurrentsinthecircuitboardground

plane and reduce digital noise, particularly for very small

analog input signals.

The digital output is “randomized” by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is ap-

plied—an exclusive-OR operation is applied between the

LSB and all other bits. The LSB, OF and CLKOUT outputs

are not affected. The output randomizer is enabled by

serially programming mode control register A4.

When there is a very small signal at the input of the A/D

thatiscenteredaroundmidscale,thedigitaloutputstoggle

between mostly 1s and mostly 0s. This simultaneous

switching of most of the bits will cause large currents in

the ground plane. By inverting every other bit, the alter-

nate bit polarity mode makes half of the bits transition

high while half of the bits transition low. To ﬁrst order,

this cancels current ﬂow in the ground plane, reducing

the digital noise.

CLKOUT

OF

PC BOARD

OF

FPGA

CLKOUT

D11

D11/D0

D10/D0

OF

D10

D2

D11/D0

D11

D10

•

D10/D0

D2/D0

D1/D0

LTC2258-12

•

RANDOMIZER

ON

D2/D0

D1/D0

D1

D2

D1

D0

225812 F15

D0

Figure 15. Functional Equivalent of Digital Output Randomizer

225812 F15

Figure 16. Unrandomizing a Randomized Digital

Output Signal

225812p

23

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

REFH, and REFL. For the suggested values in Figure 8,

the A/D will stabilize after 2ms.

The digital output is decoded at the receiver by inverting

the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit

polaritymodeisindependentofthedigitaloutputrandom-

izer—either,bothorneitherfunctioncanbeonatthesame

time. When alternate bit polarity mode is on, the data

format is offset binary and the 2’s complement control bit

has no effect. The alternate bit polarity mode is enabled

by serially programming mode control register A4.

In nap mode the A/D core is powered down while the

internal reference circuits stay active, allowing faster

wake-up than from sleep mode. Recovering from nap

mode requires at least 100 clock cycles. If the application

demands very accurate DC settling then an additional

50μs should be allowed so the on-chip references can

settle from the slight temperature shift caused by the

change in supply current as the A/D leaves nap mode.

Nap mode is enabled by mode control register A1 in the

serial programming mode.

Digital Output Test Patterns

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes that force the A/D data

outputs (OF, D11-D0) to known values:

DEVICE PROGRAMMING MODES

All 1s: All outputs are 1

All 0s: All outputs are 0

The operating modes of the LTC2258-12 can be pro-

grammed by either a parallel interface or a simple serial

interface. The serial interface has more ﬂexibility and

can program all available modes. The parallel interface

is more limited and can only program some of the more

commonly used modes.

Alternating: Outputs change from all 1s to all 0s on

alternating samples

Checkerboard: Outputs change from 1010101010101

to 0101010101010 on alternating samples

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement, randomizer, alternate-bit-polarity.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to V . The CS, SCK and SDI pins are binary logic

DD

inputs that set certain operating modes. These pins can

Output Disable

be tied to V or ground, or driven by 1.8V, 2.5V or 3.3V

DD

CMOS logic. Table 2 shows the modes set by CS, SCK

The digital outputs may be disabled by serially program-

mingmodecontrolregisterA3.Alldigitaloutputsincluding

OFandCLKOUTaredisabled.Thehighimpedancedisabled

state is intended for long periods of inactivity—it is too

slow to multiplex a data bus between multiple converters

at full speed.

and SDI.

Table 2. Parallel Programming Mode Control Bits (PAR/SER = V_DD

)

DESCRIPTION

CS

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

Digital Output Mode Control Bit

0 = Full-Rate CMOS Output Mode

Sleep and Nap Modes

SCK

SDI

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire A/D converter is powered

down,resultingin0.5mWpowerconsumption.Sleepmode

is enabled by mode control register A1 (serial program-

ming mode), or by SDI (parallel programming mode).

The amount of time required to recover from sleep mode

1 = Double Data Rate LVDS Output Mode

(3.5mA LVDS Current, Internal Termination Off)

Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

depends on the size of the bypass capacitors on V

,

REF

225812p

24

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

Serial Programming Mode

diagrams). During a read back command the register is

not updated and data on SDI is ignored.

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

The SDO pin is an open-drain output that pulls to ground

with a 200ꢀ impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and read back is not needed,

then SDO can be left ﬂoating and no pull-up resistor is

needed.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the ﬁrst 16 rising edges of

SCK. Any SCK rising edges after the ﬁrst 16 are ignored.

The data transfer ends when CS is taken high again.

Table 3 shows a map of the mode control registers.

Software Reset

If serial programming is used, the mode control registers

should be programmed as soon as possible af ter the power

supplies turn on and are stable. The ﬁrst serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset is

complete, bit D7 is automatically set back to zero.

The ﬁrst bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The ﬁnal eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the timing

Table 3. Serial Programming Mode Register Map

REGISTER A0: RESET REGISTER (ADDRESS 00h)

D7

D6

X

D5

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

X

Bit 7

RESET

0 = Not Used

Software Reset Bit

1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete

Bits 6-0

Unused, Don’t Care Bits.

REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)

D7

X

D6

D5

X

D4

X

D3

X

D2

X

D1

D0

X

PWROFF1

PWROFF0

Bits 7-2

Bits 1-0

Unused, Don’t Care Bits.

PWROFF1:PWROFF0

00 = Normal Operation

01 = Nap Mode

10 = Not Used

11 = Sleep Mode

Power Down Control Bits

225812p

25

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

X

D6

D5

X

D4

X

D3

D2

D1

D0

X

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused, Don’t Care Bits.

Bit 3

CLKINV

Output Clock Invert Bit

0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1:CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (As Shown in the Timing Diagrams)

01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)

10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)

11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)

Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On

Bit 0

DCS

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

X

D6

D5

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

OUTMODE1

OUTMODE0

Bit 7

Unused, Don’t Care Bit.

Bits 6-4

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 3

TERMON

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0

LVDS Internal Termination Bit

Bit 2

OUTOFF

Output Disable Bit

0 = Digital Outputs are Enabled

1 = Digital Outputs are Disabled and Have High Output Impedance

Bits 1-0

OUTMODE1:OUTMODE0

Digital Output Mode Control Bits

00 = Full-Rate CMOS Output Mode

01 = Double Data Rate LVDS Output Mode

10 = Double Data Rate CMOS Output Mode

11 = Not Used

225812p

26

LTC2258-12

LTC2257-12/LTC2256-12

APPLICATIONS INFORMATION

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

X

D6

X

D5

D4

D3

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

RAND

TWOSCOMP

Bit 7-6

Unused, Don’t Care Bits.

Bits 5-3

OUTTEST2:OUTTEST0

Digital Output Test Pattern Bits

000 = Digital Output Test Patterns Off

001 = All Digital Outputs = 0

011 = All Digital Outputs = 1

101 = Checkerboard Output Pattern. OF, D11-D0 Alternate Between 1 0101 1010 0101 and 0 1010 0101 1010

111 = Alternating Output Pattern. OF, D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111

Note: Other Bit Combinations are not Used

Bit 2

Bit 1

Bit 0

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

Note: ABP = 1 forces the output format to be Offset Binary

GROUNDING AND BYPASSING

The V capacitor should be located as close to the pin

CM

as possible. To make space for this the capacitor on V

REF

The LTC2258-12 requires a printed circuit board with a

clean unbroken ground plane. A multilayer board with

an internal ground plane is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

can be further away or on the back of the PC board. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground ﬁll and

grounded vias should be used as barriers to isolate these

signals from each other.

High quality ceramic bypass capacitors should be used at

the V , OV , V , V , REFH and REFL pins. Bypass

DD

DD CM REF

HEAT TRANSFER

capacitors must be located as close to the pins as possible.

Of particular importance is the 0.1μF capacitor between

REFH and REFL. This capacitor should be on the same

side of the circuit board as the A/D, and as close to the

device as possible (1.5mm or less). Size 0402 ceramic

capacitors are recommended. The larger 2.2μF capacitor

between REFH and REFL can be somewhat further away.

Most of the heat generated by the LTC2258-12 is trans-

ferred from the die through the bottom-side exposed pad

andpackageleadsontotheprintedcircuitboard. Forgood

electricalandthermalperformance,theexposedpadmust

be soldered to a large grounded pad on the PC board.

225812p

27

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL APPLICATIONS

LTC2258 Schematic

T2

MABAES0060

R9 10Ω

SENSE

•

C23

1μF

R39

ANALOG INPUT

33.2Ω

1%

R14

1k

C51

4.7pF

R40

33.2Ω

1%

C17

1μF

R10 10Ω

R16

100Ω

R15 100Ω

C12

0.1μF

C13

1μF

C19

0.1μF

DIGITAL

OUTPUTS

40

39

38

37

36

+

35

–

34

33

32

31

V

SENSE V

V

CM

OF

OF D11 D10 D9 D8

DD

REF

R27 10Ω

R28 10Ω

1

2

30

29

28

27

26

25

24

23

22

21

+

–

AIN

D7

D6

+

3

GND

CLKOUT

4

–

REFH

REFL

CLKOUT

5

C15

0.1μF

LTC2258CUJ

0V

DD

OV

DD

C20

2.2μF

C37

0.1μF

6

OGND

7

D5

D4

D3

D2

8

PAR/SER

C21

0.1μF

PAR/SER

9

V

DD

10

C18

0.1μF

+

–

GND ENC ENC CS SCK SDI SDO DNC DNC D0 D1

DIGITAL

OUTPUTS

41

11

12

13

14

15

16

17

18

19

20

R13

100Ω

ENCODE CLOCK

225812 TA02

SPI BUS

225812p

28

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL APPLICATIONS

Silkscreen Top

Top Side

225812 TA04

225812 TA03

Inner Layer 2 GND

Inner Layer 3

225812 TA05

225812 TA06

225812p

29

LTC2258-12

LTC2257-12/LTC2256-12

TYPICAL APPLICATIONS

Inner Layer 4

Inner Layer 5 Power

225812 TA07

225812 TA08

Bottom Side

225812 TA09

225812p

30

LTC2258-12

LTC2257-12/LTC2256-12

PACKAGE DESCRIPTION

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 0.05

6.50 0.05

5.10 0.05

4.42 0.05

4.50 0.05

(4 SIDES)

4.42 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.115

TYP

6.00 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 s 45°

CHAMFER

4.42 0.10

4.50 REF

(4-SIDES)

4.42 0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

225812p

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-

t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.

31

LTC2258-12

LTC2257-12/LTC2256-12

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220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN

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225812p

LT 1208 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2256IUJ-12-PBF
厂家：	Linear
描述：	12-Bit, 65/40/2 5Msps Ultralow Power 1.8V ADCs 12位65/40/2 5Msps的符号超低功耗1.8V的ADC
文件：	总32页 (文件大小：819K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2256IUJ-12-PBF [Linear]

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