LTC2301IMSXPBF [Linear]
1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface; 单/双通道, 12位ADC, I2C兼容接口型号: | LTC2301IMSXPBF |
厂家: | Linear |
描述: | 1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface |
文件: | 总24页 (文件大小:957K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2301/LTC2305
1-/2-Channel, 12-Bit ADCs
2
with I C Compatible Interface
FEATURES
DESCRIPTION
The LTC®2301/LTC2305 are low noise, low power, 1-/2-
n
12-Bit Resolution
2
n
Low Power: 1.5mW at 1ksps, 35μW Sleep Mode
channel,12-bitsuccessiveapproximationADCswithanI C
n
14ksps Throughput Rate
compatibleserialinterface.TheseADCsincludeaninternal
reference and a fully differential sample-and-hold circuit
to reduce common-mode noise. The LTC2301/LTC2305
operate from an internal clock to achieve a fast 1.3μs
conversion time.
n
Internal Reference
n
Low Noise: SNR = 73.5dB
n
Guaranteed No Missing Codes
n
Single 5V Supply
2
n
2-wire I C Compatible Serial Interface with 9
The LTC2301/LTC2305 operate from a single 5V supply
and draw just 300μA at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing the
power dissipation.
Addresses Plus One Global for Synchronization
n
Fast Conversion Time: 1.3ꢀs
n
1-Channel (LTC2301) and 2-Channel (LTC2305)
Versions
n
The LTC2301/LTC2305 are available in small 12-pin
4mm × 3mm DFN and 12-pin MSOP packages. The in-
ternal 2.5V reference further reduces PCB board space
requirements.
Unipolar or Bipolar Input Ranges (Software
Selectable)
Internal Conversion Clock
n
n
Guaranteed Operation from –40°C to 125°C
(MSOP Package)
The low power consumption and small size make the
LTC2301/LTC2305 ideal for battery operated and portable
n
12-Pin 4mm × 3mm DFN and 12-Pin MSOP
Packages
2
applications,whilethe2-wireI Ccompatibleserialinterface
makes these ADCs a good match for space-constrained
systems.
APPLICATIONS
n
Industrial Process Control
2
12-Bit I C ADC Famly
n
Motor Control
n
Input Channels
Part Number
1
2
8
Accelerometer Measurements
n
LTC2301
LTC2305
LTC2309
Battery Operated Instruments
Isolated and/or Remote Data Acquisition
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Power Supply Monitoring
BLOCK DIAGRAM
Integral Nonlinearity vs Output Code (LTC2305)
5V
1.00
10μF
V
0.1μF
0.75
AD1
AD0
LTC2301
LTC2305
DD
0.50
0.25
+
+
–
CH0(IN )
ANALOG
INPUT
MUX
12-BIT
SCL
SDA
2
ANALOG INPUT
0V TO 4.096V UNIPOLAR
2.048V BIPOLAR
I C
0.00
SAR ADC
+
PORT
CH1(IN )
–0.25
–0.50
–0.75
–1.00
V
REF
INTERNAL
2.5V REF
2.2μF
PIN NAMES IN PARENTHESES
REFER TO LTC2301
REFCOMP
10μF
0
1024
2048
3072
4096
GND
0.1μF
OUTPUT CODE
23015 TA01a
23015 TA01b
23015f
1
LTC2301/LTC2305
(Notes 1,2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ................................ –0.3V to 6.0V
Power Dissipation...............................................500mW
Operating Temperature Range
LTC2301C/LTC2305C ............................... 0°C to 70°C
LTC2301I/LTC2305I..............................–40°C to 85°C
LTC2301H/LTC2305H (Note 13).........–40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
DD
Analog Input Voltage
+
–
CH0(IN ), CH1(IN ), REF,
REFCOMP .....................(GND – 0.3V) to (V + 0.3V)
DD
Digital Input Voltage..........(GND – 0.3V) to (V + 0.3V)
DD
Digital Output Voltage .......(GND – 0.3V) to (V + 0.3V)
DD
PIN CONFIGURATION
LTC2305
LTC2301
TOP VIEW
TOP VIEW
GND
SDA
SCL
GND
CH0
CH1
1
2
3
4
5
6
12 AD0
11 AD1
GND
SDA
SCL
GND
1
2
3
4
5
6
12 AD0
11 AD1
10
9
V
10
9
V
DD
DD
13
13
GND
GND
+
8
REFCOMP
IN
8
REFCOMP
–
7
V
REF
IN
7
V
REF
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 43°C/W
T
= 150°C, θ = 43°C/W
JMAX
JA
JMAX JA
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC2305
LTC2301
TOP VIEW
TOP VIEW
1
2
3
4
5
6
GND
SDA
SCL
GND
CH0
CH1
12 AD0
11 AD1
1
2
3
4
5
6
GND
SDA
SCL
GND
12 AD0
11 AD1
10
9
V
GND
10
9
V
GND
DD
DD
+
8
REFCOMP
IN
8
REFCOMP
–
7
V
IN
7
V
REF
REF
MS PACKAGE
12-LEAD PLASTIC MSOP
MS PACKAGE
12-LEAD PLASTIC MSOP
T
= 150°C, θ = 130°C/W
T
= 150°C, θ = 130°C/W
JMAX
JA
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC2301CDE#PBF
LTC2301IDE#PBF
LTC2305CDE#PBF
LTC2305IDE#PBF
LTC2301CMS#PBF
LTC2301IMS#PBF
LTC2301HMS#PBF
LTC2305CMS#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2301CDE#TRPBF
LTC2301IDE#TRPBF
LTC2305CDE#TRPBF
LTC2305IDE#TRPBF
LTC2301CMS#TRPBF
LTC2301IMS#TRPBF
LTC2301HMS#TRPBF
LTC2305CMS#TRPBF
2301
2301
2305
2305
2301
2301
2301
2305
12-Lead (3mm × 4mm) Plastic DFN
12-Lead (3mm × 4mm) Plastic DFN
12-Lead (3mm × 4mm) Plastic DFN
12-Lead (3mm × 4mm) Plastic DFN
12-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
12-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
23015f
2
LTC2301/LTC2305
ORDER INFORMATION
LEAD FREE FINISH
LTC2305IMS#PBF
LTC2305HMS#PBF
TAPE AND REEL
PART MARKING*
2305
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC2305IMS#TRPBF
LTC2305HMS#TRPBF
12-Lead Plastic MSOP
12-Lead Plastic MSOP
2305
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER AND MULTIPLEXER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
l
l
l
l
12
(Note 5)
0.4
0.3
1
1
8
LSB
LSB
(Note 6)
0.5
LSB
Bipolar Zero Error Drift
Unipolar Zero Error
0.002
0.7
LSB/°C
LSB
l
(Note 6)
6
Unipolar Zero Error Drift
Unipolar Zero Error Match (LTC2305)
Bipolar Full-Scale Error
0.002
0.1
LSB/°C
LSB
1
l
l
External Reference (Note 7)
REFCOMP = 4.096V (Note 7)
1
0.9
10
9
LSB
LSB
Bipolar Full-Scale Error Drift
Unipolar Full-Scale Error
External Reference
0.05
LSB/°C
l
l
External Reference (Note 7)
REFCOMP = 4.096V (Note 7)
0.5
0.7
10
6
LSB
LSB
Unipolar Full-Scale Error Drift
External Reference
0.05
0.1
LSB/°C
LSB
Unipolar Full-Scale Error Match (LTC2305)
2
ANALOG INPUT The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
V +
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Absolute Input Range (CH0, CH1, IN+)
Absolute Input Range (CH0, CH1, IN–)
(Note 8)
–0.05
REFCOMP
V
IN
V –
IN
Unipolar (Note 8)
Bipolar (Note 8)
–0.05
–0.05
0.25 • REFCOMP
0.75 • REFCOMP
V
V
l
l
V + – V –
Input Differential Voltage Range
V
V
= V + – V – (Unipolar)
0 to REFCOMP
REFCOMP/2
V
V
IN
IN
IN
IN
IN
IN
= V + – V – (Bipolar)
IN
IN
I
IN
Analog Input Leakage Current
Analog Input Capacitance
1
μA
C
IN
Sample Mode
Hold Mode
55
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
70
dB
23015f
3
LTC2301/LTC2305
DYNAMIC ACCURACY
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C and A = –1dBFS. (Notes 4,9)
A
IN
SYMBOL
SINAD
SNR
PARAMETER
CONDITIONS
MIN
71
TYP
73.4
73.5
–91
92
MAX
UNITS
dB
l
l
l
l
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 1kHz
= 1kHz
71
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Full Linear Bandwidth
= 1kHz
–77
dB
SFDR
= 1kHz, First 5 Harmonics
79
dB
= 1kHz
= 1kHz
–109
700
25
dB
kHz
MHz
ns
–3dB Input Linear Bandwidth
Aperture Delay
(Note 10)
13
Transient Response
Full-Scale Step
240
ns
INTERNAL REFERENCE CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4)
A
PARAMETER
CONDITIONS
MIN
TYP
2.50
25
MAX
UNITS
V
l
V
V
V
V
V
Output Voltage
Output Tempco
Output Impedance
I
= 0
= 0
2.46
2.54
REF
OUT
OUT
I
ppm/°C
kΩ
REF
–0.1mA ≤ I
≤ 0.1mA
8
REF
OUT
Output Voltage
I
= 0
4.096
0.8
V
REFCOMP
OUT
Line Regulation
V
DD
= 4.75V to 5.25V
mV/V
REF
I2C INPUTS AND DIGITAL OUTPUTS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4)
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
V
V
V
V
High Level Input Voltage
2.85
V
V
IH
Low Level Input Voltage
1.5
IL
High Level Input Voltage for Address Pins A1, A0
Low Level Input Voltage for Address Pins A1, A0
4.75
V
IHA
ILA
0.25
10
V
R
R
R
Resistance from A1, A0 to V to Set Chip
Address Bit to 1
kꢁ
INH
INL
INF
DD
l
l
Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
10
kꢁ
Resistance from A1, A0 to GND or V to Set
Chip Address Bit to Float
2
Mꢁ
DD
l
l
l
l
l
l
I
Digital Input Current
V
= V
DD
–10
10
ꢀA
V
I
IN
V
V
Hysteresis of Schmitt Trigger Inputs
Low Level Output Voltage (SDA)
(Note 8)
I = 3mA
0.25
HYS
OL
0.4
250
50
V
t
t
Output Fall Time V
to V
Bus Load C 10pF to 400pF (Note 11)
20 + 0.1C
B
ns
ns
pF
OF
SP
IN(MIN)
IL(MAX)
B
Input Spike Suppression
C
External Capacitance Load on Chip Address Pins
(A1, A0) for Valid Float
10
CAX
23015f
4
LTC2301/LTC2305
POWER REQUIREMENTS
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
DD
Supply Voltage
4.75
5
5.25
V
l
l
l
I
Supply Current
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
2.3
225
7
3.5
400
15
mA
μA
μA
DD
l
l
l
P
D
Power Dissipation
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
11.5
1.125
35
17.5
2
75
mW
mW
μW
I2C TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
μs
l
l
l
l
l
f
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Pin
High Period of the SCL Pin
0.6
1.3
0.6
0.6
HD(SDA)
LOW
μs
μs
HIGH
Set-Up Time for a Repeated Start
Condition
μs
SU(STA)
l
l
l
l
l
l
t
t
t
t
t
t
Data Hold Time
0
100
0.9
μs
ns
ns
ns
μs
μs
HD(DAT)
Data Set-Up Time
SU(DAT)
Rise Time for SDA/SCL Signals
Fall Time for SDA/SCL Signals
Set-Up Time for Stop Condition
(Note 11)
(Note 11)
20 + 0.1C
20 + 0.1C
0.6
300
300
r
B
f
B
SU(STO)
BUF
Bus Free Time Between a Second Start
Condition
1.3
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.3
MAX
14
UNITS
ksps
μs
l
l
l
f
t
t
t
Throughput Rate (Successive Reads)
Conversion Time
SMPL
CONV
1.6
Acquisition Time
(Note 8)
240
ns
ACQ
REFCOMP Wakeup Time (Note 12)
C
= 10μF, C = 2.2μF
200
ms
REFWAKE
REFCOMP
REF
23015f
5
LTC2301/LTC2305
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: Full-scale bipolar error is the worst-case of –FS or FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 2: All voltage values are with respect to ground.
Note 8: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below ground or above V
,
Note 9: All specifications in dB are referred to a full-scale 2.048V input
with a 2.5V reference voltage.
Note 10: Full linear bandwidth is defined as the full-scale input frequency
DD
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above V without latchup.
DD
Note 4: V = 5V, f
= 14kHz, internal reference unless otherwise
at which the SINAD degrades to 60dB or 10 bits of accuracy.
DD
SMPL
noted.
Note 11: C = capacitance of one bus line in pF (10pF ≤ C ≤ 400pF)
B
B
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin
to settle within 0.5LSB at 12-bit resolution of its final value after waking up
from sleep mode.
Note 6: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
23015f
6
LTC2301/LTC2305
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2301) T = 25°C, V = 5V, f
= 14ksps, unless otherwise noted.
A
DD
SMPL
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
1.00
0.75
1.00
0
–10
–20
–30
SNR = 73.2 dB
SINAD = 73.1 dB
THD = –80dB
0.75
0.50
0.50
–40
–50
–60
0.25
0.25
–70
0.00
0.00
–80
–90
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–110
–120
–130
–140
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1
2
3
4
5
6
7
OUTPUT CODE
OUTPUT CODE
FREQUENCY (kHz)
23015 G01
23015 G02
23015 G03
Supply Current
vs Sampling Frequency
Offset Error vs Temperature
Full-Scale Error vs Temperature
2.5
2.0
1.5
1.0
0.5
0
4
2
1.5
1.0
UNIPOLAR
BIPOLAR
0
0.5
BIPOLAR
–2
–4
–6
0.0
UNIPOLAR
–0.5
–1.0
0.1
1
10
100
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
SAMPLING FREQUENCY (ksps)
TEMPERATURE (°C)
TEMPERATURE (°C)
23015 G04
23015 G06
23015 G05
Analog Input Leakage Current
vs Temperature
Supply Current vs Temperature
Sleep Current vs Temperature
2.4
2.2
1.8
1.6
1.4
10
8
1000
900
800
700
600
500
400
300
200
100
0
6
4
2
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
23015 G07
23015 G08
23015 G09
23015f
7
LTC2301/LTC2305
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2305) T = 25°C, V = 5V, f
= 14ksps, unless otherwise noted.
A
DD
SMPL
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
1.00
1.00
0.75
0
–10
–20
–30
–40
SNR = 73.2 dB
SINAD = 73.1 dB
THD = –80dB
0.75
0.50
0.50
–50
–60
0.25
0.25
0.00
–70
0.00
–80
–90
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–110
–120
–130
–140
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1
2
3
4
5
6
7
OUTPUT CODE
OUTPUT CODE
FREQUENCY (kHz)
23015 G11
23015 G10
23015 G12
Supply Current
vs Sampling Frequency
Offset Error vs Temperature
Full-Scale Error vs Temperature
4
1.0
0.5
2.5
2.0
1.5
1.0
0.5
0
2
0
BIPOLAR
BIPOLAR
UNIPOLAR
–2
–4
–6
0.0
UNIPOLAR
–0.5
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0.1
1
10
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SAMPLING FREQUENCY (ksps)
23015 G15
23015 G14
23015 G13
Analog Input Leakage Current
vs Temperature
Supply Current vs Temperature
Sleep Current vs Temperature
2.4
2.2
1.8
1.6
1.4
1000
900
800
700
600
500
400
300
200
100
0
10
8
6
4
CH(ON)
CH(OFF)
2
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
23015 G16
23015 G18
23015 G17
23015f
8
LTC2301/LTC2305
PIN FUNCTIONS
(LTC2301)
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with a 10μF low ESR ceramic or tantalum and 0.1μF
ceramic capacitor in parallel. Nominal output voltage is
4.096V. The internal reference buffer driving this pin is
nected to a solid ground plane.
2
SDA (Pin 2): Bidirectional Serial Data Line of the I C In-
terface. Intransmittermode(Read), theconversionresult
is output at the SDA pin, while in receiver mode (Write),
disabled by grounding V , allowing REFCOMP to be
REF
overdriven by an external source (see Figure 5c).
the D word is input at the SDA pin to configure the ADC.
IN
The pin is high impedance during the data input mode and
V
(Pin10): 5VAnalogSupply. TherangeofV is4.75V
DD DD
to 5.25V. Bypass V to GND with a 0.1μF ceramic and a
is an open drain output (requires an appropriate pull-up
DD
device to V ) during the data output mode.
10μF low ESR ceramic or tantalum capacitor in parallel.
DD
2
SCL (Pin 3): Serial Clock Pin of the I C Interface. The
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
LTC2301 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pinontherisingedgesoftheSCLclockandoutputthrough
the SDA pin on the falling edges of the SCL clock.
figured as a three-state (LOW, HIGH, Floating) address
2
control bit for the device I C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
+
–
IN+, IN– (Pins 5, 6): Positive (IN ) and negative (IN )
figured as a three-state (LOW, HIGH, Floating) address
2
differential analog inputs.
control bit for the device I C address. See Table 2 for
address selection.
V
REF
(Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2μF tantalum capacitor or low ESR ceramic
capacitor. The internal reference may be overdriven by an
external 2.5V reference at this pin.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
23015f
9
LTC2301/LTC2305
PIN FUNCTIONS
(LTC2305)
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with a 10μF low ESR ceramic or tantalum and 0.1μF
ceramic capacitor in parallel. Nominal output voltage is
4.096V. The internal reference buffer driving this pin is
nected to a solid ground plane.
2
SDA (Pin 2): Bidirectional Serial Data Line of the I C In-
terface. In transmitter mode (Read), the conversion result
is output at the SDA pin, while in receiver mode (Write),
disabled by grounding V , allowing REFCOMP to be
REF
overdriven by an external source (see Figure 5c).
the D word is input at the SDA pin to configure the ADC.
IN
The pin is high impedance during the data input mode and
V
(Pin10): 5VAnalogSupply. TherangeofV is4.75V
DD DD
to 5.25V. Bypass V to GND with a 0.1μF ceramic and a
is an open drain output (requires an appropriate pull-up
DD
device to V ) during the data output mode.
10μF low ESR ceramic or tantalum capacitor in parallel.
DD
2
SCL (Pin 3): Serial Clock Pin of the I C Interface. The
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
LTC2305 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pinontherisingedgesoftheSCLclockandoutputthrough
the SDA pin on the falling edges of the SCL clock.
figured as a three-state (LOW, HIGH, Floating) address
2
control bit for the device I C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
CH0-CH1 (Pins 5, 6): Channel 0 and Channel 1 Analog
Inputs. CH0 and CH1 can be configured as single-ended
or differential input channels. See the Analog Input Multi-
plexer section.
figured as a three-state (LOW, HIGH, Floating) address
2
control bit for the device I C address. See Table 2 for
address selection.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
V
REF
(Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2μF tantalum capacitor or low ESR ceramic
capacitor. The internal reference may be overdriven by an
external 2.5V reference at this pin.
23015f
10
LTC2301/LTC2305
FUNCTIONAL BLOCK DIAGRAM
V
DD
AD1
AD0
LTC2301
LTC2305
+
+
–
CH0(IN )
SCL
SDA
2
ANALOG
INPUT
MUX
12-BIT
SAR ADC
I C
PORT
–
CH1(IN )
V
REF
8k
INTERNAL
2.5V REF
GAIN = 1.6384x
PIN NAMES IN PARENTHESES
REFER TO LTC2301
REFCOMP
GND
23015 BD
TIMING DIAGRAM
2
Definition of Timing for Fast/Standard Mode Devices on the I C Bus
SDA
SCL
t
t
SU(DAT)
t
t
t
BUF
LOW
HD(SDA)
r
t
t
f
t
SP
t
f
r
t
t
t
SU(STO)
HD(SDA)
SU(STA)
t
t
HIGH
S
Sr
P
S
HD(DAT)
23015 TD
S = START, Sr = REPEATED START, P = STOP
23015f
11
LTC2301/LTC2305
APPLICATIONS INFORMATION
Overview
(a 12-bit data word) that represent the sampled analog
input are loaded into 12 output latches that allow the data
The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit
successive approximation register (SAR) A/D converters
2
to be shifted out via the I C interface.
2
with an I C compatible serial interface. The LTC2301/
Programming the LTC2301 and LTC2305
LTC2305 both include a precision internal reference. The
LTC2305 includes a 2-channel analog input multiplexer
(MUX)whiletheLTC2301includesaninputMUXthatallows
the polarity of the differential input to be selected. These
ADCs can operate in either unipolar or bipolar mode. Uni-
polarmodeshouldbeusedforsingle-endedoperationwith
the LTC2305, since single-ended input signals are always
referenced to GND. A sleep mode option is also provided
to further reduce power during inactive periods.
ThesoftwarecompatibleLTC2301/LTC2305/LTC2309fam-
ily features a 6-bit D word to program various modes of
IN
operation. Don’t care bits (X) are ignored. The SDA data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the first rising edge
and the SLP bit on the sixth rising edge (see Figure 7b
2
in the I C Interface section). The input data word for the
LTC2305 is defined as follows:
The LTC2301/LTC2305 communicate through a 2-wire
2
S/D O/S
X
X
UNI SLP
I C compatible serial interface. Conversions are initiated
by signaling a stop condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge an external request until the
conversion is finished. After a conversion is finished, the
device is ready to accept a read/write request. Once the
LTC2301/LTC2305 is addressed for a read operation, the
device begins outputting the conversion result under the
control of the serial clock (SCL). There is no latency in the
conversionresult.Thereare12bitsofoutputdatafollowed
by four trailing zeros. Data is updated on the falling edges
of SCL, allowing the user to reliably latch data on the ris-
ing edge of SCL. A write operation may follow the read
operation by using a repeat start or a stop condition may
be given to start a new conversion. By selecting a write
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
For the LTC2301, the input word is defined as:
X
O/S
X
X
UNI SLP
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and
O/S bits of the D word for the LTC2305 and the O/S
IN
operation, these ADCs can be programmed by a 6-bit D
IN
bit of the D word for the LTC2301. Table 1 and Table 2
IN
word. The D word configures the MUX and programs
IN
list the MUX configurations for all combinations of the
configuration bits. Figure 1a shows several possible MUX
configurations and Figure 1b shows how the MUX can be
reconfigured from one conversion to the next.
various modes of operation.
Duringaconversion, theinternal12-bitcapacitivecharge-
redistribution DAC output is sequenced through a succes-
siveapproximationalgorithmbytheSARstartingfromthe
mostsignificantbit(MSB)totheleastsignificantbit(LSB).
The sampled input is successively compared with binary
weighted charges supplied by the capacitive DAC using
a differential comparator. At the end of a conversion, the
DAC output balances the analog input. The SAR contents
Table 1. Channel Configuration for the LTC2305
S/D
0
O/S
0
CH0
+
CH1
–
0
1
–
+
1
0
+
1
1
+
23015f
12
LTC2301/LTC2305
APPLICATIONS INFORMATION
Table 2. Channel Configuration for the LTC2301
Driving the Analog Inputs
O/S
0
IN+
+
IN–
–
The analog inputs of the LTC2301/LTC2305 are easy to
drive. Each of the analog inputs of the LTC2305 (CH0 and
CH1) can be used as single-ended input relative to GND
or as a differential pair. The analog inputs of the LTC2301
1
–
+
+
–
(IN , IN ) are always configured as a differential pair.
Regardless of the MUX configuration, the “+” and “–“
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample-and-hold cir-
cuit. The inputs draw only one small current spike while
chargingthesample-and-holdcapacitorsduringtheacquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
drivingcircuitislow, theADCinputscanbedrivendirectly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
1 Differential
2 Single-Ended
CH0
CH1
+ (
)
)
CH0
CH1
+
+
–
{
(
+
–
LTC2305
LTC2305
GND (
)
–
1 Differential
CH0
CH1
+ (–)
{
– (+)
Input Filtering
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
should be filtered prior to the analog inputs to minimize
noise. A simple 1-pole RC filter is sufficient for many
applications.
LTC2301
23015 F01a
Figure 1a. Example MUX Configurations
TheanaloginputsoftheLTC2301/LTC2305canbemodeled
as a 55pF capacitor (C ) in series with a 100Ω resistor
IN
(R ) as shown in Figure 2a. C gets switched to the
ON
IN
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
1st Conversion
2nd Conversion
+
CH0
CH1
–
+
CH0
CH1
12-bit resolution within the acquisition time (t ) if DC
{
{
ACQ
–
accuracy is important.
LTC2305
LTC2305
When using a filter with a large C
value (e.g. 1μF),
FILTER
GND (
)
–
theinputsdonotcompletelysettleandthecapacitiveinput
23015 F01b
switchingcurrentsareaveragedintoanetDCcurrent(I ).
Inthiscase, theanaloginputcanbemodeledbyanequiva-
DC
Figure 1b. Changing the MUX Assignment “On the Fly”
lent resistance (R = 1/(f
• C )) in series with an
EQ
SMPL
IN
ideal voltage source (V
/2) as shown in Figure 2b.
REFCOMP
23015f
13
LTC2301/LTC2305
APPLICATIONS INFORMATION
ThemagnitudeoftheDCcurrentisthenapproximatelyI
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems.
DC
=(V –V
IN
/2)/R ,whichisroughlyproportionalto
IN
REFCOMP
EQ
V . To prevent large DC drops across the resistor R
,
FILTER
a filter with a small resistor and large capacitor should be
Dynamic Performance
chosen. When running at the maximum throughput rate
of 14ksps, the input current equals 1.5μA at V = 4.096V,
IN
Fast Fourier Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
whichamountstoafull-scaleerrorof0.5LSBswhenusing
a filter resistor (R
) of 333Ω. Applications requiring
FILTER
lower sample rates can tolerate a larger filter resistor for
the same amount of full-scale error.
Figures 3a and 3b show respective examples of input
filtering for single-ended and differential inputs. For the
single-ended case in Figure 4a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica type
dielectriccapacitorshaveexcellentlinearity.Carbonsurface
mount resistors can generate distortion from self heating
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
50ꢁ
ANALOG
INPUT
CH0, CH1
INPUT
2000pF
CH0, CH1,
R
=
LTC2301
LTC2305
ON
+
–
LTC2305
IN , IN
R
SOURCE
100ꢁ
V
IN
C
=
IN
REFCOMP
C
FILTER
55pF
10μF
0.1μF
23015 F03a
23015 F02a
Figure 2a. Analog Input Equivalent Circuit
Figure 3a. Optional RC Input Filtering for Single-Ended Input
1000pF
50ꢁ
INPUT
+
(CH0, CH1,
CH0, IN
I
+
–
DC
C
DIFFERENTIAL
R
FILTER
IN , IN )
LTC2301
ANALOG
INPUTS
1000pF
1000pF
LTC2301
LTC2305
V
IN
LTC2305
–
50ꢁ
R
=
EQ
CH1, IN
FILTER
1/(f
• C )
IN
SMPL
+
V
/2
REFCOMP
–
REFCOMP
10μF
0.1μF
23015 F02b
23015 F03b
Figure 2b. Analog Input Equivalent
Circuit for Large Filter Capacitances
Figure 3b. Optional RC Input Filtering for Differential Inputs
23015f
14
LTC2301/LTC2305
APPLICATIONS INFORMATION
frequency. Figure 4 shows a typical SINAD of 73.2dB with
a 14kHz sampling rate and a 1kHz input. A SNR of 73.3dB
can be achieved with the LTC2301/LTC2305.
a0.1ꢀFceramiccapacitorforbestnoiseperformance. The
internal reference buffer can also be overdriven from 1V
to V with an external reference at REFCOMP as shown
DD
in Figure 5c. To do so, V must be grounded to disable
REF
0
–10
–20
–30
–40
SNR = 73.2dB
the reference buffer. This will result in an input range of
SINAD = 73.1dB
THD = –80dB
0V to V
in unipolar mode and 0.5 • V
in
REFCOMP
bipolar mode.
REFCOMP
–50
–60
–70
–80
–90
R1
8k
V
REF
BANDGAP
2.5V
REFERENCE
–100
–110
–120
–130
–140
2.2μF
REFCOMP
4.096V
10μF
REFERENCE
AMP
+
0
1
2
3
4
5
6
7
FREQUENCY (kHz)
23015 F04
R2
0.1μF
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot
R3
GND
LTC2301
LTC2305
Total Harmonic Distortion (THD)
23015 F05a
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
Figure 5a. LTC2301/LTC2305 Reference Circuit
bandbetweenDCandhalfthesamplingfrequency(f
THD is expressed as:
/2).
SMPL
5V
0.1μF
V
IN
2
2
2
2
V2 + V3 + V4 ...+ VN
LT1790A-2.5
V
THD= 20log
V1
V
OUT
REF
2.2μF
0.1μF
LTC2301
LTC2305
where V1 is the RMS amplitude of the fundamental fre-
REFCOMP
quencyandV2throughV aretheamplitudesofthesecond
N
+
10μF
through Nth harmonics.
GND
Internal Reference
23015 F05b
The LTC2301/LTC2305 have an on-chip, temperature
compensated bandgap reference that is factory trimmed
to 2.5V (Refer to Figure 5a). It is internally connected
Figure 5b. Using the LT1790A-2.5 as an External Reference
to a reference amplifier and is available at V
(Pin 7).
5V
REF
V
should be bypassed to GND with a 2.2ꢀF tantalum
REF
V
REF
V
IN
capacitor to minimize noise. An 8k resistor is in series
with the output so that it can be easily overdriven by an
external reference if more accuracy and/or lower drift are
required as shown in Figure 5b. The reference amplifier
0.1μF
LTC2301
LTC2305
LT1790A-4.096
V
OUT
REFCOMP
+
0.1μF
10μF
GND
gains the V
voltage by 1.638 to 4.096V at REFCOMP.
REF
23015 F05c
To compensate the reference amplifier, bypass REFCOMP
with a 10ꢀF ceramic or tantalum capacitor in parallel with
Figure 5c. Overdriving REFCOMP Using the LT1790A-4.096
23015f
15
LTC2301/LTC2305
APPLICATIONS INFORMATION
Internal Conversion Clock
Start Condition
Stop Condition
SDA
SCL
The internal conversion clock is factory trimmed to
achieve a typical conversion time (t
) of 1.3ꢀs and a
SDA
SCL
CONV
S
P
maximum conversion time of 1.6ꢀs over the full operating
temperature range.
23015 F06
2
I C Interface
Figure 6. Timing Diagrams of Start and Stop Conditions
2
The LTC2301/LTC2305 communicate through an I C in-
2
terface. The I C interface is a 2-wire open-drain interface
When the bus is in use, it stays busy if a Repeated Start
(Sr)isgeneratedinsteadofaStopcondition.TheRepeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
supporting multiple devices and multiple masters on a
single bus. The connected devices can only pull the serial
data line (SDA) low and can never drive it high. SDA is
required to be externally connected to the supply through
a pull-up resistor. When the data line is not being driven
low, it is high. Data on the I C bus can be transferred at
rates up to 100kbits/s in the standard mode and up to
400kbits/s in the fast mode.
2
Data Transferring
2
After the Start condition, the I C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the SCL line is low.
2
Each device on the I C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function of
the device. A device can also be considered as a master
or a slave when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit the transfer. Devices
addressed by the master are considered slaves.
The LTC2301/LTC2305 can only be addressed as slaves.
Data Format
Once addressed, they can receive configuration bits (D
IN
word)ortransmitthelastconversionresult.Theserialclock
line (SCL) is always an input to the LTC2301/LTC2305 and
the serial data line (SDA) is bidirectional. These devices
support the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit
address matches one of the LTC2301/LTC2305’s 9 pin-
selectable addresses (see Table 2), the ADC is selected.
When the ADC is addressed during a conversion, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2301/LTC2305 issues an ACK by pulling the SDA
line low. The LTC2301/LTC2305 has two registers. The
12-bit wide output register contains the last conversion
result. The 6-bit wide input register configures the input
MUX and the operating mode of the ADC.
2
section for definition of the I C timing).
The Start and Stop Conditions
Referring to Figure 6, a Start (S) condition is generated
by transitioning SDA from high to low while SCL is high.
The bus is considered to be busy after the Start condition.
When the data transfer is finished, a Stop (P) condition
is generated by transitioning SDA from low to high while
SCL is high. The bus is free after a Stop condition is gen-
erated. Start and Stop conditions are always generated
by the master.
23015f
16
LTC2301/LTC2305
APPLICATIONS INFORMATION
Output Data Format
result. The remaining four bits are zero. Figures 13 and 14
arethetransfercharacteristicsforthebipolarandunipolar
modes. Data is output on the SDA line in 2’s complement
format for bipolar readings and in straight binary for
unipolar readings.
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2301/LTC2305 is addressed for
a read operation, it acknowledges by pulling SDA low and
acts as a transmitter. The master/receiver can read up to
two bytes from the LTC2301/LTC2305. After a complete
read operation of 2 bytes, a Stop condition is needed to
initiate a new conversion. The device will NAK subsequent
read operations while a conversion is being performed.
Input Data Format
When the LTC2301/LTC2305 is addressed for a write
operation, it acknowledges by pulling SDA low during
the low period before the 9th cycle and acts as a receiver.
The master/transmitter can then send 1 byte to program
the device. The input byte consists of the 6-bit D word
IN
followed by two bits that are ignored by the ADC and are
considered don’t cares (X) (see Figure 7b). The input bits
are latched on the rising edge of SCL during the write
operation.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 7a). The first bit
is the MSB and the 12th bit is the LSB of the conversion
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
• • •
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10 B9
B8
B7
B6
B5 B4
• • •
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
MOST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
1
2
3
4
5
6
7
8
9
SCL
• • •
• • •
(CONTINUED)
CONVERSION
INITIATED
SDA
(CONTINUED)
STOP
BY MASTER
B3
B2
B1
B0
NAK BY
MASTER
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
23015 F07a
Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305
NOTE: S/D BIT IS A DON’T CARE (X) FOR THE LTC2301
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
CONVERSION
INITIATED
A6
A5
A4
A3
A2
A1
A0 R/W
S/D O/S
X
X
UNI SLP
X
X
STOP BY
MASTER
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
D
WORD
IN
23015 F07b
ADDRESS FRAME
WRITE 1 BYTE
Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305
23015f
17
LTC2301/LTC2305
APPLICATIONS INFORMATION
Table 2. Address Assignment
After power-up, the ADC initiates an internal reset cycle
which sets the D word to all 0s (S/D=O/S=UNI=SLP=0).
AD1
LOW
AD0
LOW
ADDRESS
0001000
0001001
0001010
0001011
0011000
0011001
0011010
0011011
0101000
IN
A write operation may be performed if the default state
of the ADC’s configuration is not desired. Otherwise, the
ADC must be properly addressed and followed by a Stop
condition to initiate a conversion.
LOW
FLOAT
HIGH
HIGH
FLOAT
LOW
LOW
FLOAT
FLOAT
FLOAT
HIGH
HIGH
HIGH
Initiating a New Conversion
LOW
The LTC2301/LTC2305 awakens from either nap or sleep
when properly addressed for a read/write operation. A
Stop command may then be issued after performing the
read/write operation to trigger a new conversion.
FLOAT
HIGH
Continuous Read
Issuing a Stop command after the 8th SCL clock pulse of
theaddressframeandbeforethecompletionofaread/write
operation will also initiate new conversion, but the output
result may not be valid due to lack of adequate acquisition
time (see Acquisition section).
In applications where the same input channel is sampled
each cycle, conversions can be continuously performed
and read without a write cycle (see Figure 8). The D word
IN
remains unchanged from the last value written into the
device. If the device has not been written to since power-
LTC2301/LTC2305 Address
up, theD worddefaultstoall0s(S/D=O/S=UNI=SLP=0).
IN
At the end of a read operation, a Stop condition may be
given to start a new conversion. At the conclusion of the
conversion cycle, the next result may be read using the
method described above. If the conversion cycle is not
concluded and a valid address selects the device, the
LTC2301/LTC2305 generates a NAK signal indicating the
conversion cycle is in progress.
The LTC2301/LTC2305 have two address pins (AD0 and
AD1) that may be tied high, low or left floating to enable
one of the 9 possible addresses (see Table 2).
In addition to the configurable addresses listed in Table 2,
the LTC2301/LTC2305 also contain a global address
(1110111) which may be used for synchronizing multiple
2
LTC2301/LTC2305s or other I C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2301/LTC2305s with Global
Address Call section).
S
7-BIT ADDRESS
NAP
R
ACK
READ
P
S
7-BIT ADDRESS
NAP
R
ACK
READ
P
CONVERSION
DATA OUTPUT
CONVERSION
DATA
OUTPUT
CONVERSION
23015 F08
Figure 8. Consecutive Reading with the Same Configuration
23015f
18
LTC2301/LTC2305
APPLICATIONS INFORMATION
Continuous Read/Write
the request. The master then sends a write byte (optional)
followed by the Stop command. This will update the
channel selection (optional) and simultaneously initiate
a conversion for all ADCs on the bus (see Figure 10).
Inordertosynchronizemultipleconverterswithoutchang-
ing the channel, a Stop command may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NAK a global read request.
Once the conversion cycle is complete, the LTC2301/
LTC2305 can be written to and then read from using the
RepeatedStart(Sr)command.Figure9showsacyclewhich
begins with a data Write, a repeated Start, followed by a
Read and concluded with a Stop command. The following
conversionbeginsafterall16bitsarereadoutofthedevice
or after a Stop command. The following conversion will
be performed using the newly programmed data.
Nap Mode
Synchronizing Multiple LTC2301/LTC2305s with a
Global Address Call
The ADCs enter nap mode after a conversion is complete
(t ) if the SLP bit is set to a logic 0. The supply current
CONV
In applications where several LTC2301/LTC2305s or other
decreases to 225ꢀA in nap mode between conversions,
thereby reducing the average power dissipation as the
sampleratedecreases.Forexample,theLTC2301/LTC2305
draw an average of 300μA at a 1ksps sampling rate. The
2
I C SAR ADCs from Linear Technology Corporation are
2
used on the same I C bus, all converters can be synchro-
nized through the use of a global address call. Prior to
issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
Start, followed by the global address 1110111, and a write
request. All converters will be selected and acknowledge
LTC2301/LTC2305 keep only the reference (V ) and
REF
reference buffer (REFCOMP) circuitry active when in nap
mode.
S
7-BIT ADDRESS
NAP
W
ACK
WRITE
Sr
7-BIT ADDRESS
CONVERSION
R
ACK
READ
P
CONVERSION
DATA OUTPUT
DATA
OUTPUT
CONVERSION
23015 F09
Figure 9. Write, Read, Start Conversion
SCL
SDA
LTC2301/LTC2305
LTC2301/LTC2305
LTC2301/LTC2305
S
GLOBAL ADDRESS
NAP
W
ACK
WRITE (OPTIONAL)
P
CONVERSION
DATA OUTPUT
CONVERSION OF ALL LTC2301/05s
23015 F10
Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call
23015f
19
LTC2301/LTC2305
APPLICATIONS INFORMATION
Sleep Mode
performed, acquisition of the input signal begins on the
rising edge of the 9th clock pulse following the address
frame as shown in Figure 12a.
The ADCs enter sleep mode after a conversion is complete
(t ) if the SLP bit is set to a logic 1. The ADCs draw
CONV
only 7μA in sleep mode, provided that none of the digital
inputs are switching. When the LTC2301/LTC2305 are
properly addressed, the ADCs are released from sleep
If a write operation is being performed, acquisition of the
input signal begins on the falling edge of the sixth clock
cycle after the D word has been shifted in as shown in
IN
modeandrequire200ms(t
)towakeupandcharge
Figure 12b. The LTC2301/LTC2305 will acquire the signal
REFWAKE
the respective 2.2ꢀF and 10ꢀF bypass capacitors on the
fromtheinputchannelthatwasmostrecentlyprogrammed
V
and REFCOMP pins. A new conversion should not
bytheD word.Aminimumof240nsisrequiredtoacquire
REF
IN
be initiated before this time as shown in Figure 11.
the input signal before initiating a new conversion.
Acquisition
Board Layout and Bypassing
The LTC2301/LTC2305 begin acquiring the input signal at
different instances depending on whether a read or write
operation is being performed. If a read operation is being
Toobtainthebestperformance,aprintedcircuitboardwith
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
S
7-BIT ADDRESS
SLEEP
R/W
ACK
P
CONVERSION
t
CONVERSION
REFWAKE
23015 F11
Figure 11. Exiting Sleep Mode and Starting a New Conversion
1
2
3
4
5
6
7
8
9
1
2
SCL
SDA
ACQUISITION BEGINS
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10
23015 F12a
t
ACQ
Figure 12a. Timing Diagram Showing Acquisition During a Read Operation
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
ACQUISITION BEGINS
A2
A1
A0 R/W
S/D O/S
X
X
UNI SLP
X
X
23015 F12b
t
ACQ
Figure 12b. Timing Diagram Showing Acquisition During a Write Operation
23015f
20
LTC2301/LTC2305
APPLICATIONS INFORMATION
separated as much as possible. Care should be taken not
to run any digital signals alongside an analog signal. All
for the common return of these bypass capacitors is es-
sential to the low noise operation of the ADC. These traces
should be as wide as possible. See Figure 15a–15e for a
suggested layout.
analoginputsshouldbeshieldedbyGND.V ,REFCOMP
REF
and V should be bypassed to the ground plane as close
DD
to the pin as possible. Maintaining a low impedance path
011...111
111...111
111...110
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
100...000
UNIPOLAR
011...111
ZERO
011...110
FS = 4.096V
1LSB = FS/2
FS = 4.096V
1LSB = FS/2
100...001
100...000
000...001
000...000
n
n
1LSB = 1mV
1LSB = 1mV
–1 0V
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
23015 F13
23015 F14
Figure 13. Bipolar Transfer Characteristics (2’s Complement)
Figure 14. Unipolar Transfer Characteristics (Straight Binary)
Figure 15a. Top Silkscreen
23015f
21
LTC2301/LTC2305
APPLICATIONS INFORMATION
Figure 15c. Layer 2 Ground Plane
Figure 15b. Topside
Figure 15d. Layer 3 Power Plane
Figure 15e. Bottomside
23015f
22
LTC2301/LTC2305
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.40 ± 0.10
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
7
12
0.70 ±0.05
R = 0.05
TYP
3.30 ±0.05
1.70 ± 0.05
3.30 ±0.10
3.60 ±0.05
2.20 ±0.05
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
PIN 1
PIN 1 NOTCH
TOP MARK
(NOTE 6)
R = 0.20 OR
PACKAGE
OUTLINE
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV
D
6
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
2.50 REF
0.50 BSC
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.65
0.42 p 0.038
(.0165 p .0015)
TYP
(.0256)
0.406 p 0.076
BSC
(.016 p .003)
12 11 10 9 8 7
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0o – 6o TYP
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0.254
(.010)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1
2 3 4 5 6
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
MSOP (MS12) 1107 REV Ø
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
23015f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2301/LTC2305
TYPICAL APPLICATION
Driving the LTC2305 with 10V Input Signals Using a Precision Attenuator
5V
IN
OUT
1μF
0.1μF
LT1790-2.5
5V
GND
10V
7
10μF
0.1μF
450k
50k
AD1 AD0
V
1.7k 1.7k
DD
8
9
150k
LTC2305
–
+
10
4pF
100ꢁ
47pF
450k
450k
SCL
SDA
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC)
6
CH0
CH1
ANALOG
INPUT
MUX
LT1991
+
–
2
12-BIT
SAR ADC
I C
1
2
3
PORT
450k
150k
50k
10V
INPUT
SIGNAL
4pF
INTERNAL
2.5V REF
V
REF
4
5
2.2μF
–10V
REFCOMP
GND
0.1μF
10μF
23015 TA02
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COMMENTS
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1468/LT1469
LTC1609
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
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10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
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60ꢀA Supply Current, 10ppm/°C, SOT-23 Package
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850ꢀA at 250ksps, 2ꢀA at 1ksps, SO-8 and MSOP Packages
450ꢀA at 150ksps, 10ꢀA at 1ksps, SO-8 and MSOP Packages
6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
850ꢀA at 250ksps, 2ꢀA at 1ksps, SO-8 and MSOP Packages
450ꢀA at 150ksps, 10ꢀA at 1ksps, SO-8 and MSOP Packages
14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC
LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADC
LTC1863L/LTC1867L 3V, 12-/16-Bit, 8-Channel 175ksps ADC
LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
LTC2302/LTC2306
12-Bit, 1-/2-Channel 500ksps SPI ADCs in
3mm × 3mm DFN
LTC2308
12-Bit, 8-Channel 500ksps SPI ADC
5V, Internal Reference, 4mm × 4mm QFN Package, Software Compatible
with LTC2302/LTC2306
2
LTC2309
12-Bit, 8-Channel ADC with I C Interface
5V, Internal Reference, 4mm × 4mm QFN and 20-Pin TSSOP Packages,
Software Compatible with LTC2301/LTC2305
2
LTC2451/LTC2453
Easy-to-Use, Ultra-Tiny 16-Bit I C Delta Sigma ADCs 2 LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm × 2mm DFN
Package, Single-Ended/Differential Inputs
2
LTC2487/LTC2489/
LTC2493
2-/4-Channel Easy Drive I C Delta Sigma ADCs
16-/24-Bits, PGA and Temp Sensor, 4mm × 3mm DFN Packages
16-/24-Bits, PGA and Temp Sensor, 5mm × 7mm QFN Packages
2
LTC2495/LTC2497/
LTC2499
8-/16-Channel Easy Drive I C Delta Sigma ADCs
23015f
LT 0808 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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