LTC2309CUF#PBF [Linear]
LTC2309 - 8-Channel, 12-Bit SAR ADC with I<sup>2</sup>C Interface; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C;
| 型号： | LTC2309CUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2309 - 8-Channel, 12-Bit SAR ADC with I<sup>2</sup>C Interface; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C 转换器 |
| 文件： | 总26页 (文件大小：1651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2309
8-Channel, 12-Bit SAR ADC
2
with I C Interface
FeAtuRes
DesCRIptIOn
TheꢀLTC®2309ꢀisꢀaꢀlowꢀnoise,ꢀlowꢀpower,ꢀ8-channel,ꢀ12-bitꢀ
n
ꢀ 12-Bit Resolution
2
n
successiveꢀapproximationꢀADCꢀwithꢀanꢀI Cꢀcompatibleꢀ
ꢀ Low Power: 1.5mW at 1ksps, 35µW Sleep Mode
n
serialꢀinterface.ꢀThisꢀADCꢀincludesꢀanꢀinternalꢀreferenceꢀ
andꢀaꢀfullyꢀdifferentialꢀsample-and-holdꢀcircuitꢀtoꢀreduceꢀ
commonꢀ modeꢀ noise.ꢀ Theꢀ LTC2309ꢀ operatesꢀ fromꢀ anꢀ
internalꢀclockꢀtoꢀachieveꢀaꢀfastꢀ1.3µsꢀconversionꢀtime.
ꢀ 14ksps Throughput Rate
n
ꢀ Low Noise: SNR = 73.4dB
n
ꢀ GuaranteedꢀNoꢀMissingꢀCodes
n
ꢀ Singleꢀ5VꢀSupply
2
n
ꢀ 2-WireꢀI CꢀCompatibleꢀSerialꢀInterfaceꢀwithꢀNineꢀ
Theꢀ LTC2309ꢀ operatesꢀ fromꢀ aꢀ singleꢀ 5Vꢀ supplyꢀ andꢀ
drawsꢀjustꢀ300µAꢀatꢀaꢀthroughputꢀrateꢀofꢀ1ksps.ꢀTheꢀ
ADCꢀentersꢀnapꢀmodeꢀwhenꢀnotꢀconverting,ꢀreducingꢀ
theꢀpowerꢀdissipation.
AddressesꢀPlusꢀOneꢀGlobalꢀforꢀSynchronization
n
ꢀ FastꢀConversionꢀTime:ꢀ1.3µs
n
ꢀ InternalꢀReference
n
ꢀ Internalꢀ8-ChannelꢀMultiplexer
TheꢀLTC2309ꢀisꢀavailableꢀinꢀbothꢀaꢀsmallꢀ24-pinꢀ4mmꢀ×ꢀ
4mmꢀQFNꢀandꢀaꢀ20-pinꢀTSSOPꢀpackage.ꢀTheꢀinternalꢀ2.5Vꢀ
referenceꢀandꢀ8-channelꢀmultiplexerꢀfurtherꢀreduceꢀPCBꢀ
boardꢀspaceꢀrequirements.
n
ꢀ InternalꢀConversionꢀClock
n
ꢀ UnipolarꢀorꢀBipolarꢀInputꢀRangesꢀ(SoftwareꢀSelectable)
n
ꢀ GuaranteedꢀOperationꢀfromꢀ–40°Cꢀtoꢀ125°Cꢀꢀ
(TSSOPꢀPackage)
n
ꢀ 24-Pinꢀ4mmꢀ×ꢀ4mmꢀQFNꢀandꢀ20-PinꢀTSSOPꢀPackages
Theꢀ lowꢀ powerꢀ consumptionꢀ andꢀ smallꢀ sizeꢀ makeꢀ theꢀ
LTC2309ꢀidealꢀforꢀbattery-operatedꢀandꢀportableꢀapplica-
AppLICAtIOns
2
tions,ꢀwhileꢀtheꢀ2-wireꢀI Cꢀcompatibleꢀserialꢀinterfaceꢀmakesꢀ
n
n
n
n
n
n
thisꢀADCꢀaꢀgoodꢀmatchꢀforꢀspace-constrainedꢀsystems.
ꢀ IndustrialꢀProcessꢀControl
L,ꢀLT,ꢀLTC,ꢀLTM,ꢀLinearꢀTechnologyꢀandꢀtheꢀLinearꢀlogoꢀareꢀregisteredꢀtrademarksꢀandꢀꢀ
EasyꢀDriveꢀisꢀaꢀtrademarkꢀofꢀLinearꢀTechnologyꢀCorporation.ꢀAllꢀotherꢀtrademarksꢀareꢀtheꢀ
propertyꢀofꢀtheirꢀrespectiveꢀowners.
ꢀ MotorꢀControl
ꢀ AccelerometerꢀMeasurements
ꢀ Battery-OperatedꢀInstruments
ꢀ Isolatedꢀand/orꢀRemoteꢀDataꢀAcquisition
ꢀ PowerꢀSupplyꢀMonitoring
BLOCK DIAGRAM
5V
Integral Nonlinearity
vs Output Code
0.1µF
10µF
1.00
V
0.75
DD
CH0
CH1
CH2
AD1
AD0
LTC2309
0.50
0.25
ANALOG
CH3
SCL
SDA
+
–
2
12-ꢁIT
SAR ADC
I C
ANALOG INPUTS
INPUT
0
CH4
CH5
CH6
CH7
COM
PORT
0V TO 4.096V UNIPOLAR
2.04ꢀV ꢁIPOLAR
MUX
–0.25
–0.50
–0.75
–1.00
V
REF
INTERNAL
2.5V REF
2.2µF
0
1024
2048
3072
4096
OUTPUT CODE
REFCOMP
2309 G01
GND
0.1µF
10µF
2309 TA01
2309fd
ꢀ
(Noteꢀ3)............................ (GNDꢀ–ꢀ0.3V)ꢀtoꢀ(V ꢀ+ꢀ0.3V)
LTC2309
ABsOLute MAxIMuM RAtInGs (Notes 1, 2)
SupplyꢀVoltage
PowerꢀDissipationꢀ.............................................. 500mW
ꢀ V ꢀ.......................................................... –0.3Vꢀtoꢀ6V
OperatingꢀTemperatureꢀRange
D
D
AnalogꢀInputꢀVoltageꢀ(Noteꢀ3)ꢀ
ꢀ CH0-CH7,ꢀCOM,ꢀV ,ꢀ
ꢀ LTC2309Cꢀ................................................ 0°Cꢀtoꢀ70°C
ꢀ LTC2309Iꢀ.............................................–40°Cꢀtoꢀ85°C
ꢀ LTC2309H.......................................... –40°Cꢀtoꢀ125°C
StorageꢀTemperatureꢀRangeꢀ.................. –65°Cꢀtoꢀ150°C
LeadꢀTemperatureꢀ(Soldering,ꢀ10ꢀsec)
ꢀ TSSOPꢀ..............................................................300°C
REFꢀ
ꢀ REFCOMPꢀ.................... (GNDꢀ–ꢀ0.3V)ꢀtoꢀ(V ꢀ+ꢀ0.3V)
DD
DigitalꢀInputꢀVoltageꢀ
DD
DD
DigitalꢀOutputꢀVoltageꢀ...... (GNDꢀ–ꢀ0.3V)ꢀtoꢀ(V ꢀ+ꢀ0.3V)
pIn COnFIGuRAtIOn
TOP VIEW
TOP VIEW
REFCOMP
GND
1
2
20
19
18
17
16
15
14
13
12
11
V
REF
24 23 22 21 20 19
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
18 GND
V
3
DD
SDA
SCL
17
16
AD0
AD1
SCL
SDA
GND
GND
4
25
5
15 AD1
6
14
13
AD0
7
V
DD
8
7
8
9 10 11 12
9
V
10
DD
F PACKAGE
20-LEAD PLASTIC TSSOP
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
ꢀ
ꢀ
T
JMAX
ꢀ=ꢀ150°C,ꢀθ ꢀ=ꢀ90°C/W,ꢀθ ꢀ=ꢀ20°C/W
JA JC
T
ꢀ=ꢀ150°C,ꢀθ ꢀ=ꢀ37°C/Wꢀ
JMAX JA
EXPOSEDꢀPADꢀ(PINꢀ25)ꢀISꢀGND,ꢀMUSTꢀBEꢀSOLDEREDꢀTOꢀPCB
ORDeR InFORMAtIOn
LEAD FREE FINISH
LTC2309CUF#PBF
LTC2309IUF#PBF
LTC2309CF#PBF
LTC2309IF#PBF
LTC2309HF#PBF
TAPE AND REEL
PART MARKING*
2309
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°Cꢀtoꢀ70°C
LTC2309CUF#TRPBF
LTC2309IUF#TRPBF
LTC2309CF#TRPBF
LTC2309IF#TRPBF
LTC2309HF#TRPBF
24-Leadꢀ(4mmꢀ×ꢀ4mm)ꢀPlasticꢀQFN
24-Leadꢀ(4mmꢀ×ꢀ4mm)ꢀPlasticꢀQFN
20-LeadꢀPlasticꢀTSSOP
2309
–40°Cꢀtoꢀ85°C
0°Cꢀtoꢀ70°C
LTC2309F
LTC2309F
LTC2309F
20-LeadꢀPlasticꢀTSSOP
–40°Cꢀtoꢀ85°C
–40°Cꢀtoꢀ125°C
20-LeadꢀPlasticꢀTSSOP
ConsultꢀLTCꢀMarketingꢀforꢀpartsꢀspecifiedꢀwithꢀwiderꢀoperatingꢀtemperatureꢀranges.ꢀꢀ*Theꢀtemperatureꢀgradeꢀisꢀidentifiedꢀbyꢀaꢀlabelꢀonꢀtheꢀshippingꢀcontainer.
ConsultꢀLTCꢀMarketingꢀforꢀinformationꢀonꢀnon-standardꢀleadꢀbasedꢀfinishꢀparts.
Forꢀmoreꢀinformationꢀonꢀleadꢀfreeꢀpartꢀmarking,ꢀgoꢀto:ꢀhttp://www.linear.com/leadfree/ꢀ
Forꢀmoreꢀinformationꢀonꢀtapeꢀandꢀreelꢀspecifications,ꢀgoꢀto:ꢀhttp://www.linear.com/tapeandreel/
2309fd
ꢁ
LTC2309
COnVeRteR AnD MuLtIpLexeR CHARACteRIstICs The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
l
l
l
l
Resolutionꢀ(NoꢀMissingꢀCodes)
IntegralꢀLinearityꢀError
DifferentialꢀLinearityꢀError
BipolarꢀZeroꢀError
(Noteꢀ6)
0.45
0.35
1
1
1
8
(Noteꢀ7)
BipolarꢀZeroꢀErrorꢀDrift
BipolarꢀZeroꢀErrorꢀMatch
UnipolarꢀZeroꢀError
0.002
0.1
0.4
LSB/°C
LSB
3
6
l
(Noteꢀ7)
LSB
UnipolarꢀZeroꢀErrorꢀDrift
UnipolarꢀZeroꢀErrorꢀMatch
BipolarꢀFull-ScaleꢀError
0.002
0.2
0.5ꢀ
0.4
LSB/°C
LSB
1
10ꢀ
9
l
l
ExternalꢀReferenceꢀ(Noteꢀ8)ꢀ
REFCOMPꢀ=ꢀ4.096V
LSBꢀ
LSB
BipolarꢀFull-ScaleꢀErrorꢀDrift
BipolarꢀFull-ScaleꢀErrorꢀMatch
UnipolarꢀFull-ScaleꢀError
ExternalꢀReference
0.05
0.4
0.4ꢀ
0.5
LSB/°C
LSB
3
10ꢀ
12
l
l
QFNꢀExternalꢀReferenceꢀ(Noteꢀ8)ꢀ
TSSOPꢀExternalꢀReferenceꢀ(Noteꢀ8)
LSBꢀ
LSB
l
REFCOMPꢀ=ꢀ4.096V
ExternalꢀReference
0.3
0.05
0.3
6
LSB
LSB/°C
LSB
UnipolarꢀFull-ScaleꢀErrorꢀDrift
UnipolarꢀFull-ScaleꢀErrorꢀMatch
2
AnALOG Input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
AbsoluteꢀInputꢀRangeꢀ(CH0ꢀtoꢀCH7)
AbsoluteꢀInputꢀRangeꢀ(CH0ꢀtoꢀCH7,ꢀCOM) Unipolarꢀ(Noteꢀ9)ꢀ
Bipolarꢀ(Noteꢀ9)
InputꢀDifferentialꢀVoltageꢀRange
CONDITIONS
(Noteꢀ9)
MIN
–0.05
–0.05ꢀ
–0.05
TYP
MAX
REFCOMP
0.25ꢀ•ꢀREFCOMPꢀ
0.75ꢀ•ꢀREFCOMP
UNITS
+
l
V
V
V
Vꢀ
V
Vꢀ
V
IN
IN
–
l
l
+
–
+
–
–
l
l
V
ꢀ–ꢀV
V ꢀ=ꢀV ꢀ–ꢀV ꢀ(Unipolar)ꢀ
IN
0ꢀtoꢀREFCOMPꢀ
REFCOMP/2
IN
IN
IN
IN
IN
IN
+
V ꢀ=ꢀV ꢀ–ꢀV ꢀ(Bipolar)
IN
l
I
C
AnalogꢀInputꢀLeakageꢀCurrent
AnalogꢀInputꢀCapacitance
1
µA
pFꢀ
pF
IN
SampleꢀModeꢀ
HoldꢀMode
55ꢀ
5
IN
CMRRꢀ
InputꢀCommonꢀModeꢀRejectionꢀRatio
70
dB
DYnAMIC ACCuRACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
SYMBOL
SINAD
SNR
THD
SFDR
PARAMETER
Signal-to-(Noiseꢀ+ꢀDistortion)ꢀRatio
Signal-to-NoiseꢀRatio
TotalꢀHarmonicꢀDistortion
SpuriousꢀFreeꢀDynamicꢀRange
Channel-to-ChannelꢀIsolation
FullꢀLinearꢀBandwidth
–3dBꢀInputꢀLinearꢀBandwidth
ApertureꢀDelay
CONDITIONS
f ꢀ=ꢀ1kHz
MIN
71
71
TYP
73.3
73.4
–88
90
–109
700
25
MAX
UNITS
dB
l
l
l
l
IN
f ꢀ=ꢀ1kHz
dB
dB
dB
dB
kHz
MHz
ns
IN
f ꢀ=ꢀ1kHz,ꢀFirstꢀ5ꢀHarmonics
–77
IN
f ꢀ=ꢀ1kHz
79
IN
f ꢀ=ꢀ1kHz
IN
(Noteꢀ11)
13
TransientꢀResponse
Full-ScaleꢀStep
240
ns
2309fd
ꢂ
LTC2309
InteRnAL ReFeRenCe CHARACteRIstICs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Vꢀ
V
ppm/°C
kΩ
l
l
V
ꢀOutputꢀVoltage
REF
I
I
ꢀ=ꢀ0ꢀ(QFN)ꢀ
2.47ꢀ
2.46
2.50ꢀ
2.50
2.53ꢀ
2.54
OUT
OUT
ꢀ=ꢀ0ꢀ(TSSOP)
V
V
V
V
ꢀOutputꢀTempco
I
ꢀ=ꢀ0
OUT
25
8
REF
ꢀOutputꢀImpedance
REF
–0.1mAꢀ≤ꢀI ꢀ≤ꢀ0.1mA
OUT
ꢀOutputꢀVoltage
REFCOMP
I
ꢀ=ꢀ0
OUT
4.096
0.8
V
ꢀLineꢀRegulation
REF
V
ꢀ=ꢀ4.75Vꢀtoꢀ5.25V
DD
mV/V
I2C Inputs AnD DIGItAL Outputs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
V
V
V
V
HighꢀLevelꢀInputꢀVoltage
2.85
V
V
IH
LowꢀLevelꢀInputꢀVoltage
1.5
IL
HighꢀLevelꢀInputꢀVoltageꢀforꢀAddressꢀPinsꢀA1,ꢀA0
LowꢀLevelꢀInputꢀVoltageꢀforꢀAddressꢀPinsꢀA1,ꢀA0
4.75
V
IHA
ILA
0.25
10
V
R
R
R
ResistanceꢀfromꢀA1,ꢀA0,ꢀtoꢀV ꢀtoꢀSetꢀChipꢀ
AddressꢀBitꢀtoꢀ1
kΩ
INH
INL
INF
DD
l
l
ResistanceꢀfromꢀA1,ꢀA0ꢀtoꢀGNDꢀtoꢀSetꢀChipꢀ
AddressꢀBitꢀtoꢀ0
10
kΩ
ResistanceꢀfromꢀA1,ꢀA0ꢀtoꢀGNDꢀorꢀV ꢀtoꢀSetꢀ
ChipꢀAddressꢀBitꢀtoꢀFloat
2
MΩ
DD
l
l
l
l
l
l
I
DigitalꢀInputꢀCurrent
V ꢀ=ꢀV
DD
–10
10
µA
V
I
IN
V
V
HysteresisꢀofꢀSchmittꢀTriggerꢀInputs
LowꢀLevelꢀOutputꢀVoltageꢀ(SDA)
(Noteꢀ9)
Iꢀ=ꢀ3mA
(Noteꢀ12)
0.25
HYS
OL
0.4
250
50
V
t
t
OutputꢀFallꢀTimeꢀV ꢀtoꢀV
20ꢀ+ꢀ0.1C
B
ns
ns
pF
OF
SP
H
IL(MAX)
InputꢀSpikeꢀSuppression
C
ExternalꢀCapacitanceꢀLoadꢀOn-ChipꢀAddressꢀPinsꢀ
(A1,ꢀA0)ꢀforꢀValidꢀFloat
10
CAX
pOWeR ReQuIReMents The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
SupplyꢀVoltage
SupplyꢀCurrentꢀ
NapꢀMode
CONDITIONS
MIN
TYP
5
MAX
5.25
3
UNITS
V
l
l
l
l
l
l
l
V
4.75
DD
I
14kspsꢀSampleꢀRate
2.3
210
7
mA
µA
DD
SLPꢀBitꢀ=ꢀ0,ꢀConversionꢀDone
SLPꢀBitꢀ=ꢀ1,ꢀConversionꢀDone
14kspsꢀSampleꢀRate
350
15
SleepꢀMode
µA
P
PowerꢀDissipation
NapꢀMode
11.5
1.05
35
15
mW
mW
µW
D
SLPꢀBitꢀ=ꢀ0,ꢀConversionꢀDone
SLPꢀBitꢀ=ꢀ1,ꢀConversionꢀDone
1.75
75
SleepꢀMode
2309fd
ꢃ
LTC2309
I2C tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
µs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCLꢀClockꢀFrequency
400
SCL
HoldꢀTimeꢀ(Repeated)ꢀSTARTꢀCondition
LOWꢀPeriodꢀofꢀtheꢀSCLꢀPin
0.6
1.3
HD(SDA)
LOW
µs
HIGHꢀPeriodꢀofꢀtheꢀSCLꢀPin
0.6
µs
HIGH
Set-UpꢀTimeꢀforꢀaꢀRepeatedꢀSTARTꢀCondition
DataꢀHoldꢀTime
0.6
µs
SU(STA)
HD(DAT)
0
0.9
µs
ꢀ
DataꢀSet-UpꢀTime
100
ns
SU(DAT)
RiseꢀTimeꢀforꢀSDA/SCLꢀSignals
FallꢀTimeꢀforꢀSDA/SCLꢀSignals
Set-UpꢀTimeꢀforꢀSTOPꢀCondition
BusꢀFreeꢀTimeꢀBetweenꢀaꢀSTOPꢀandꢀSTARTꢀCondition
(Noteꢀ12)
(Noteꢀ12)
20ꢀ+ꢀ0.1C
20ꢀ+ꢀ0.1C
0.6
300
300
ns
r
B
B
ns
f
µs
SU(STO)
BUF
1.3
µs
ADC tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
14
UNITS
ksps
µs
l
l
l
f
t
t
t
ThroughputꢀRateꢀ(SuccessiveꢀReads)
ConversionꢀTime
SMPL
CONV
(Noteꢀ9)
(Noteꢀ9)
1.3
1.8
AcquisitionꢀTime
240
ns
ACQ
REFCOMPꢀWake-UpꢀTimeꢀ(Noteꢀ13)
C
ꢀ=ꢀ10µF,ꢀC ꢀ=ꢀ2.2µF
REFCOMP
200
ms
REFWAKE
REF
1111.ꢀUnipolarꢀzeroꢀerrorꢀisꢀtheꢀoffsetꢀvoltageꢀmeasuredꢀfromꢀ+0.5LSBꢀ
whenꢀtheꢀoutputꢀcodeꢀflickersꢀbetweenꢀ0000ꢀ0000ꢀ0000ꢀandꢀ0000ꢀ0000ꢀ
0001.
Note 8:ꢀFull-scaleꢀbipolarꢀerrorꢀisꢀtheꢀworst-caseꢀofꢀ–FSꢀorꢀ+FSꢀuntrimmedꢀ
deviationꢀfromꢀidealꢀfirstꢀandꢀlastꢀcodeꢀtransitionsꢀandꢀincludesꢀtheꢀeffectꢀ
ofꢀoffsetꢀerror.ꢀUnipolarꢀfull-scaleꢀerrorꢀisꢀtheꢀdeviationꢀofꢀtheꢀlastꢀcodeꢀ
transitionꢀfromꢀidealꢀandꢀincludesꢀtheꢀeffectꢀofꢀoffsetꢀerror.ꢀ
Note 1:ꢀStressesꢀbeyondꢀthoseꢀlistedꢀunderꢀAbsoluteꢀMaximumꢀRatingsꢀ
mayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀExposureꢀtoꢀanyꢀAbsoluteꢀ
MaximumꢀRatingꢀconditionꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀdeviceꢀ
reliabilityꢀandꢀlifetime.
Note 2:ꢀAllꢀvoltageꢀvaluesꢀareꢀwithꢀrespectꢀtoꢀground.
Note 3:ꢀWhenꢀtheseꢀpinꢀvoltagesꢀareꢀtakenꢀbelowꢀgroundꢀorꢀaboveꢀV ,ꢀ
DD
theyꢀwillꢀbeꢀclampedꢀbyꢀinternalꢀdiodes.ꢀTheseꢀproductsꢀcanꢀhandleꢀinputꢀ
Note 9:ꢀGuaranteedꢀbyꢀdesign,ꢀnotꢀsubjectꢀtoꢀtest.
currentsꢀgreaterꢀthanꢀ100mAꢀbelowꢀgroundꢀorꢀaboveꢀV ꢀwithoutꢀlatchup.
DD
Note 10:ꢀAllꢀspecificationsꢀinꢀdBꢀareꢀreferredꢀtoꢀaꢀfull-scaleꢀ 2.048Vꢀinputꢀ
Note 4:ꢀV ꢀ=ꢀ5V,ꢀf
ꢀ=ꢀ14kspsꢀinternalꢀreferenceꢀunlessꢀotherwiseꢀ
SMPL
DD
withꢀaꢀ2.5Vꢀreferenceꢀvoltage.
noted.
Note 11:ꢀFullꢀlinearꢀbandwidthꢀisꢀdefinedꢀasꢀtheꢀfull-scaleꢀinputꢀfrequencyꢀ
Note 5:ꢀLinearity,ꢀoffsetꢀandꢀfull-scaleꢀspecificationsꢀapplyꢀforꢀaꢀꢀ
atꢀwhichꢀtheꢀSINADꢀdegradesꢀtoꢀ60dBꢀorꢀ10ꢀbitsꢀofꢀaccuracy.
single-endedꢀanalogꢀinputꢀwithꢀrespectꢀtoꢀCOM.
Note 12:ꢀC ꢀ=ꢀcapacitanceꢀofꢀoneꢀbusꢀlineꢀinꢀpFꢀ(10pFꢀ≤ꢀC ꢀ≤ꢀ400pF).ꢀ
Note 6:ꢀIntegralꢀnonlinearityꢀisꢀdefinedꢀasꢀtheꢀdeviationꢀofꢀaꢀcodeꢀfromꢀaꢀ
straightꢀlineꢀpassingꢀthroughꢀtheꢀactualꢀendpointsꢀofꢀtheꢀtransferꢀcurve.ꢀ
Theꢀdeviationꢀisꢀmeasuredꢀfromꢀtheꢀcenterꢀofꢀtheꢀquantizationꢀband.
B
B
Note 13:ꢀREFCOMPꢀwake-upꢀtimeꢀisꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀREFCOMPꢀ
pinꢀtoꢀsettleꢀwithinꢀ0.5LSBꢀatꢀ12-bitꢀresolutionꢀofꢀitsꢀfinalꢀvalueꢀafterꢀ
wakingꢀupꢀfromꢀSLEEPꢀmode.
Note 7:ꢀBipolarꢀzeroꢀerrorꢀisꢀtheꢀoffsetꢀvoltageꢀmeasuredꢀfromꢀ–0.5LSBꢀ
whenꢀtheꢀoutputꢀcodeꢀflickersꢀbetweenꢀ0000ꢀ0000ꢀ0000ꢀandꢀ1111ꢀ1111ꢀ
2309fd
ꢄ
LTC2309
tYpICAL peRFORMAnCe CHARACteRIstICs
TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
0
–20
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
–40
–60
–80
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–120
–140
2048
0
1
2
4
5
6
7
0
1024
3072
4096
3
2048
0
1024
3072
4096
FREQUENCY (kHz)
OUTPUT CODE
OUTPUT CODE
2309 G01
2309 G02
2309 G03
Supply Current
vs Sampling Frequency
Offset Error vs Temperature
Full-Scale Error vs Temperature
4
2
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
UNIPOLAR
BIPOLAR
0.5
0
0
UNIPOLAR
BIPOLAR
–2
–4
–6
–0.5
–1.0
–0.5
–2.0
–50 –25
0
25
50
75 100 125
0.1
1
10
100
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
SAMPLING FREQUENCY (ksps)
TEMPERATURE (°C)
2309 G06
3209 G04
2309 G05
Analog Input Leakage Current
vs Temperature
Supply Current vs Temperature
Sleep Current vs Temperature
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
10
8
1000
900
800
700
600
500
400
300
200
100
0
6
4
CH (ON)
CH (OFF)
2
0
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
–25
–50 –25
0
25
75 100
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
2309 G07
2309 G08
2309 G09
2309fd
ꢅ
LTC2309
pIn FunCtIOns (QFN)
CH3-CH7 (Pins 1-5):ꢀChannelꢀ3ꢀtoꢀChannelꢀ7ꢀAnalogꢀ
Inputs.ꢀCH3-CH7ꢀcanꢀbeꢀconfiguredꢀasꢀsingle-endedꢀ
orꢀ differentialꢀ inputꢀ channels.ꢀ Seeꢀ theꢀ Analogꢀ Inputꢀ
Multiplexerꢀsection.
AD1 (Pin 15):ꢀChipꢀAddressꢀControlꢀPin.ꢀThisꢀpinꢀisꢀ
configuredꢀ asꢀ aꢀ three-stateꢀ (LOW,ꢀ HIGH,ꢀ floating)ꢀ
2
addressꢀ controlꢀ bitꢀ forꢀ theꢀ deviceꢀ I Cꢀ address.ꢀ Seeꢀ
Tableꢀ2ꢀforꢀaddressꢀselection.
2
COM (Pin 6):ꢀCommonꢀInput.ꢀThisꢀisꢀtheꢀreferenceꢀ
pointꢀforꢀallꢀsingle-endedꢀinputs.ꢀItꢀmustꢀbeꢀfreeꢀofꢀ
noiseꢀandꢀshouldꢀbeꢀconnectedꢀtoꢀgroundꢀforꢀunipolarꢀ
conversionsꢀandꢀmidwayꢀbetweenꢀGNDꢀandꢀREFCOMPꢀ
forꢀbipolarꢀconversions.
SCL (Pin 16):ꢀSerialꢀClockꢀPinꢀofꢀtheꢀI CꢀInterface.ꢀTheꢀ
LTC2309ꢀcanꢀonlyꢀactꢀasꢀaꢀslaveꢀandꢀtheꢀSCLꢀpinꢀonlyꢀ
acceptsꢀanꢀexternalꢀserialꢀclock.ꢀDataꢀisꢀshiftedꢀintoꢀ
theꢀSDAꢀpinꢀonꢀtheꢀrisingꢀedgesꢀofꢀtheꢀSCLꢀclockꢀandꢀ
outputꢀthroughꢀtheꢀSDAꢀpinꢀonꢀtheꢀfallingꢀedgesꢀofꢀtheꢀ
SCLꢀclock.
V
(Pin 7):ꢀ2.5VꢀReferenceꢀOutput.ꢀBypassꢀtoꢀGNDꢀ
REF
2
withꢀaꢀminimumꢀ2.2µFꢀceramicꢀcapacitor.ꢀTheꢀinternalꢀ
referenceꢀmayꢀbeꢀoverdrivenꢀbyꢀanꢀexternalꢀ2.5Vꢀrefer-
enceꢀatꢀthisꢀpin.ꢀ
SDA (Pin 17):ꢀBidirectionalꢀSerialꢀDataꢀLineꢀofꢀtheꢀI Cꢀ
Interface.ꢀInꢀtransmitterꢀmodeꢀ(read),ꢀtheꢀconversionꢀ
resultꢀisꢀoutputꢀatꢀtheꢀSDAꢀpin,ꢀwhileꢀinꢀreceiverꢀmodeꢀ
(write),ꢀtheꢀD ꢀwordꢀisꢀinputꢀatꢀtheꢀSDAꢀpinꢀtoꢀcon-
IN
REFCOMP (Pin 8):ꢀReferenceꢀBufferꢀOutput.ꢀBypassꢀ
toꢀ GNDꢀ withꢀ 10µFꢀ andꢀ 0.1µFꢀ ceramicꢀ capacitorsꢀ inꢀ
parallel.ꢀNominalꢀoutputꢀvoltageꢀisꢀ4.096V.ꢀTheꢀinternalꢀ
referenceꢀbufferꢀdrivingꢀthisꢀpinꢀisꢀdisabledꢀbyꢀground-
figureꢀtheꢀADC.ꢀTheꢀpinꢀisꢀhighꢀimpedanceꢀduringꢀtheꢀ
dataꢀinputꢀmodeꢀandꢀisꢀanꢀopen-drainꢀoutputꢀ(requiresꢀ
anꢀappropriateꢀpull-upꢀdeviceꢀtoꢀV )ꢀduringꢀtheꢀdataꢀ
DD
outputꢀmode.
ingꢀV ,ꢀallowingꢀREFCOMPꢀtoꢀbeꢀoverdrivenꢀbyꢀanꢀ
REFꢀ
externalꢀsource.
CH0-CH2 (Pins 22-24):ꢀChannelꢀ0ꢀtoꢀChannelꢀ2ꢀAnalogꢀ
Inputs.ꢀCH0-CH2ꢀcanꢀbeꢀconfiguredꢀasꢀsingle-endedꢀ
orꢀ differentialꢀ inputꢀ channels.ꢀ Seeꢀ theꢀ Analogꢀ Inputꢀ
Multiplexerꢀsection.
GND (Pins 9-11, 18-20):ꢀGround.ꢀAllꢀGNDꢀpinsꢀmustꢀ
beꢀconnectedꢀtoꢀaꢀsolidꢀgroundꢀplane.ꢀ
V
(Pins 12, 13, 21):ꢀ5VꢀSupply.ꢀTheꢀrangeꢀofꢀV ꢀisꢀ
DD
DD
Exposed Pad (Pin 25):ꢀ Ground.ꢀ Mustꢀ beꢀ solderedꢀ
4.75Vꢀtoꢀ5.25V.ꢀBypassꢀV ꢀtoꢀGNDꢀwithꢀaꢀ10µFꢀceramicꢀ
DD
directlyꢀtoꢀgroundꢀplane.
capacitorꢀinꢀparallelꢀwithꢀthreeꢀ0.1µFꢀceramicꢀcapacitors,ꢀ
oneꢀlocatedꢀasꢀcloseꢀasꢀpossibleꢀtoꢀeachꢀpin.ꢀ
AD0 (Pin 14):ꢀChipꢀAddressꢀControlꢀPin.ꢀThisꢀpinꢀisꢀ
configuredꢀasꢀaꢀthree-stateꢀ(LOW,ꢀHIGH,ꢀfloating)ꢀad-
2
dressꢀcontrolꢀbitꢀforꢀtheꢀdeviceꢀI Cꢀaddress.ꢀSeeꢀTableꢀ2ꢀ
forꢀaddressꢀselection.
2309fd
ꢆ
LTC2309
pIn FunCtIOns (TSSOP)
2
REFCOMP (Pin 1):ꢀReferenceꢀBufferꢀOutput.ꢀBypassꢀ
toꢀ GNDꢀ withꢀ 10µFꢀ andꢀ 0.1µFꢀ ceramicꢀ capacitorsꢀ inꢀ
parallel.ꢀNominalꢀoutputꢀvoltageꢀisꢀ4.096V.ꢀTheꢀinternalꢀ
referenceꢀbufferꢀdrivingꢀthisꢀpinꢀisꢀdisabledꢀbyꢀground-
SDA (Pin 7):ꢀBidirectionalꢀSerialꢀDataꢀLineꢀofꢀtheꢀI Cꢀ
Interface.ꢀInꢀtransmitterꢀmodeꢀ(read),ꢀtheꢀconversionꢀ
resultꢀisꢀoutputꢀatꢀtheꢀSDAꢀpin,ꢀwhileꢀinꢀreceiverꢀmodeꢀ
(write),ꢀtheꢀD ꢀwordꢀisꢀinputꢀatꢀtheꢀSDAꢀpinꢀtoꢀcon-
IN
ingꢀV ,ꢀallowingꢀREFCOMPꢀtoꢀbeꢀoverdrivenꢀbyꢀanꢀ
figureꢀtheꢀADC.ꢀTheꢀpinꢀisꢀhighꢀimpedanceꢀduringꢀtheꢀ
REFꢀ
externalꢀsource.
dataꢀinputꢀmodeꢀandꢀisꢀanꢀopen-drainꢀoutputꢀ(requiresꢀ
anꢀappropriateꢀpull-upꢀdeviceꢀtoꢀV )ꢀduringꢀtheꢀdataꢀ
DD
GND (Pins 2, 8 , 9):ꢀGround.ꢀAllꢀGNDꢀpinsꢀmustꢀbeꢀ
connectedꢀtoꢀaꢀsolidꢀgroundꢀplane.ꢀ
outputꢀmode.
CH0-CH7 (Pins 11-18):ꢀChannelꢀ0ꢀtoꢀChannelꢀ7ꢀAnalogꢀ
Inputs.ꢀCH0-CH7ꢀcanꢀbeꢀconfiguredꢀasꢀsingle-endedꢀ
orꢀ differentialꢀ inputꢀ channels.ꢀ Seeꢀ theꢀ Analogꢀ Inputꢀ
Multiplexerꢀsection.ꢀꢀ
V
(Pins 3, 10):ꢀ5VꢀSupply.ꢀTheꢀrangeꢀofꢀV ꢀisꢀ4.75Vꢀ
DD
DD
toꢀ5.25V.ꢀBypassꢀV ꢀtoꢀGNDꢀwithꢀaꢀ10µFꢀceramicꢀca-
DD
pacitorꢀinꢀparallelꢀwithꢀtwoꢀ0.1µFꢀceramicꢀcapacitors,ꢀ
oneꢀlocatedꢀasꢀcloseꢀasꢀpossibleꢀtoꢀeachꢀpin.
COM (Pin 19):ꢀCommonꢀInput.ꢀThisꢀisꢀtheꢀreferenceꢀ
pointꢀforꢀallꢀsingle-endedꢀinputs.ꢀItꢀmustꢀbeꢀfreeꢀofꢀ
noiseꢀandꢀshouldꢀbeꢀconnectedꢀtoꢀgroundꢀforꢀunipolarꢀ
conversionsꢀandꢀmidwayꢀbetweenꢀGNDꢀandꢀREFCOMPꢀ
forꢀbipolarꢀconversions.
AD0 (Pin 4):ꢀChipꢀAddressꢀControlꢀPin.ꢀThisꢀpinꢀisꢀcon-
figuredꢀasꢀaꢀthree-stateꢀ(LOW,ꢀHIGH,ꢀfloating)ꢀaddressꢀ
2
controlꢀbitꢀforꢀtheꢀdeviceꢀI Cꢀaddress.ꢀSeeꢀTableꢀ2ꢀforꢀ
addressꢀselection.
AD1 (Pin 5):ꢀChipꢀAddressꢀControlꢀPin.ꢀThisꢀpinꢀisꢀ
V
(Pin 20):ꢀ2.5VꢀReferenceꢀOutput.ꢀBypassꢀtoꢀGNDꢀ
REF
configuredꢀ asꢀ aꢀ three-stateꢀ (LOW,ꢀ HIGH,ꢀ floating)ꢀ
withꢀaꢀminimumꢀ2.2µFꢀceramicꢀcapacitor.ꢀTheꢀinternalꢀ
referenceꢀmayꢀbeꢀoverdrivenꢀbyꢀanꢀexternalꢀ2.5Vꢀrefer-
enceꢀatꢀthisꢀpin.ꢀꢀ
2
addressꢀ controlꢀ bitꢀ forꢀ theꢀ deviceꢀ I Cꢀ address.ꢀ Seeꢀ
Tableꢀ2ꢀforꢀaddressꢀselection.
2
SCL (Pin 6):ꢀSerialꢀClockꢀPinꢀofꢀtheꢀI CꢀInterface.ꢀTheꢀ
LTC2309ꢀcanꢀonlyꢀactꢀasꢀaꢀslaveꢀandꢀtheꢀSCLꢀpinꢀonlyꢀ
acceptsꢀanꢀexternalꢀserialꢀclock.ꢀDataꢀisꢀshiftedꢀintoꢀ
theꢀSDAꢀpinꢀonꢀtheꢀrisingꢀedgesꢀofꢀtheꢀSCLꢀclockꢀandꢀ
outputꢀthroughꢀtheꢀSDAꢀpinꢀonꢀtheꢀfallingꢀedgesꢀofꢀtheꢀ
SCLꢀclock.
2309fd
ꢇ
LTC2309
FunCtIOnAL BLOCK DIAGRAM
V
DD
LTC2309
CH0
CH1
CH2
AD1
AD0
ANALOG
INPUT
MUX
CH3
CH4
CH5
CH6
CH7
COM
SCL
SDA
+
–
2
12-BIT
SAR ADC
I C
PORT
V
REF
8k
INTERNAL
2.5V REF
GAIN = 1.6384x
REFCOMP
2308 BD
GND
tIMInG DIAGRAM
Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
SCL
t
t
SU(DAT)
t
t
BUF
r
LOW
HD(SDA)
t
t
f
t
SP
t
t
f
r
t
t
t
SU(STO)
HD(SDA)
SU(STA)
t
t
HIGH
S
Sr
P
S
HD(DAT)
2309 TD
S = START, Sr = REPEATED START, P = STOP
2309fd
ꢈ
LTC2309
AppLICAtIOns InFORMAtIOn
Overview
Programming the LTC2309
TheꢀvariousꢀmodesꢀofꢀoperationꢀofꢀtheꢀLTC2309ꢀareꢀ
TheꢀLTC2309ꢀisꢀaꢀlowꢀnoise,ꢀ8-channel,ꢀ12-bitꢀsucces-
siveꢀapproximationꢀregisterꢀ(SAR)ꢀA/Dꢀconverterꢀwithꢀanꢀ
programmedꢀbyꢀaꢀ6-bitꢀD ꢀword.ꢀTheꢀSDIꢀinputꢀdataꢀ
IN
2
bitsꢀareꢀloadedꢀonꢀtheꢀrisingꢀedgeꢀofꢀSCLꢀduringꢀaꢀwriteꢀ
operation,ꢀwithꢀtheꢀS/Dꢀbitꢀloadedꢀonꢀtheꢀfirstꢀrisingꢀedgeꢀ
andꢀtheꢀSLPꢀbitꢀonꢀtheꢀsixthꢀrisingꢀedgeꢀ(seeꢀFigureꢀ8bꢀ
I Cꢀcompatibleꢀserialꢀinterface.ꢀTheꢀLTC2309ꢀincludesꢀaꢀ
precisionꢀinternalꢀreferenceꢀandꢀaꢀconfigurableꢀ8-chan-
nelꢀanalogꢀinputꢀmultiplexerꢀ(MUX).ꢀTheꢀADCꢀmayꢀbeꢀ
configuredꢀtoꢀacceptꢀsingle-endedꢀorꢀdifferentialꢀsignalsꢀ
andꢀcanꢀoperateꢀinꢀeitherꢀunipolarꢀorꢀbipolarꢀmode.ꢀAꢀ
sleepꢀmodeꢀoptionꢀisꢀalsoꢀprovidedꢀtoꢀfurtherꢀreduceꢀ
powerꢀduringꢀinactiveꢀperiods.
2
inꢀtheꢀI CꢀInterfaceꢀsection).ꢀTheꢀinputꢀdataꢀwordꢀisꢀ
definedꢀasꢀfollows:
S/D O/S S1 S0 UNI SLP
ꢀ
2
ꢀ S/Dꢀ=ꢀSINGLE-ENDED/DIFFERENTIALꢀBIT
ꢀ O/Sꢀ=ꢀODD/SIGNꢀBIT
Theꢀ LTC2309ꢀ communicatesꢀ throughꢀ aꢀ 2-wireꢀ I Cꢀ
compatibleꢀserialꢀinterface.ꢀConversionsꢀareꢀinitiatedꢀ
byꢀsignalingꢀaꢀSTOPꢀconditionꢀafterꢀtheꢀpartꢀhasꢀbeenꢀ
successfullyꢀaddressedꢀforꢀaꢀread/writeꢀoperation.ꢀTheꢀ
deviceꢀwillꢀnotꢀacknowledgeꢀ(NACK)ꢀanꢀexternalꢀrequestꢀ
untilꢀtheꢀconversionꢀisꢀfinished.ꢀAfterꢀaꢀconversionꢀisꢀ
finished,ꢀ theꢀ deviceꢀ isꢀ readyꢀ toꢀ acceptꢀ aꢀ read/writeꢀ
request.ꢀOnceꢀtheꢀLTC2309ꢀisꢀaddressedꢀforꢀaꢀreadꢀ
operation,ꢀ theꢀ deviceꢀ beginsꢀ outputtingꢀ theꢀ conver-
sionꢀresultꢀunderꢀtheꢀcontrolꢀofꢀtheꢀserialꢀclockꢀ(SCL).ꢀ
Thereꢀisꢀnoꢀlatencyꢀinꢀtheꢀconversionꢀresult.ꢀThereꢀareꢀ
12ꢀbitsꢀofꢀoutputꢀdataꢀfollowedꢀbyꢀ4ꢀtrailingꢀzeros.ꢀDataꢀ
isꢀupdatedꢀonꢀtheꢀfallingꢀedgesꢀofꢀSCL,ꢀallowingꢀtheꢀ
userꢀtoꢀreliablyꢀlatchꢀdataꢀonꢀtheꢀrisingꢀedgeꢀofꢀSCL.ꢀAꢀ
writeꢀoperationꢀmayꢀfollowꢀtheꢀreadꢀoperationꢀbyꢀusingꢀ
aꢀrepeatꢀSTARTꢀorꢀaꢀSTOPꢀconditionꢀmayꢀbeꢀgivenꢀtoꢀ
startꢀaꢀnewꢀconversion.ꢀByꢀselectingꢀaꢀwriteꢀoperation,ꢀ
ꢀ S1ꢀ=ꢀCHANNELꢀSELECTꢀBITꢀ1
ꢀ S0ꢀ=ꢀCHANNELꢀSELECTꢀBITꢀ0
ꢀ UNIꢀ=ꢀUNIPOLAR/BIPOLARꢀBIT
ꢀ SLPꢀ=ꢀSLEEPꢀMODEꢀBIT
Analog Input Multiplexer
Theꢀ analogꢀ inputꢀ MUXꢀ isꢀ programmedꢀ byꢀ theꢀ S/D,ꢀ
O/S,ꢀS1ꢀandꢀS0ꢀbitsꢀofꢀtheꢀD ꢀword.ꢀTableꢀ1ꢀlistsꢀtheꢀ
IN
MUXꢀconfigurationsꢀforꢀallꢀcombinationsꢀofꢀtheꢀcon-
figurationꢀbits.ꢀFigureꢀ1aꢀshowsꢀseveralꢀpossibleꢀMUXꢀ
configurationsꢀandꢀFigureꢀ1bꢀshowsꢀhowꢀtheꢀMUXꢀcanꢀ
beꢀreconfiguredꢀfromꢀoneꢀconversionꢀtoꢀtheꢀnext.
theꢀADCꢀcanꢀbeꢀprogrammedꢀwithꢀaꢀ6-bitꢀD ꢀword.ꢀTheꢀ
D ꢀwordꢀconfiguresꢀtheꢀMUXꢀandꢀprogramsꢀvariousꢀ
IN
Driving the Analog Inputs
IN
TheꢀanalogꢀinputsꢀofꢀtheꢀLTC2309ꢀareꢀeasyꢀtoꢀdrive.ꢀ
Eachꢀofꢀtheꢀanalogꢀinputsꢀcanꢀbeꢀusedꢀasꢀaꢀsingle-endedꢀ
inputꢀrelativeꢀtoꢀtheꢀCOMꢀpinꢀ(CH0-COM,ꢀCH1-COM,ꢀ
etc.)ꢀorꢀinꢀdifferentialꢀinputꢀpairsꢀ(CH0ꢀandꢀCH1,ꢀCH2ꢀ
andꢀCH3,ꢀCH4ꢀandꢀCH5,ꢀCH6ꢀandꢀCH7).ꢀFigureꢀ2ꢀshowsꢀ
howꢀtoꢀdriveꢀCOMꢀforꢀsingle-endedꢀinputsꢀinꢀunipolarꢀ
andꢀbipolarꢀmodes.ꢀRegardlessꢀofꢀtheꢀMUXꢀconfigura-
tion,ꢀtheꢀ“+”ꢀandꢀ“–”ꢀinputsꢀareꢀsampledꢀatꢀtheꢀsameꢀ
instant.ꢀAnyꢀunwantedꢀsignalꢀthatꢀisꢀcommonꢀtoꢀbothꢀ
inputsꢀwillꢀbeꢀreducedꢀbyꢀtheꢀcommonꢀmodeꢀrejectionꢀ
ofꢀtheꢀsample-and-holdꢀcircuit.ꢀTheꢀinputsꢀdrawꢀonlyꢀ
oneꢀsmallꢀcurrentꢀspikeꢀwhileꢀchargingꢀtheꢀsample-and-
holdꢀcapacitorsꢀduringꢀtheꢀacquireꢀmode.ꢀInꢀconversionꢀ
modesꢀofꢀoperationꢀofꢀtheꢀADC.
Duringꢀ aꢀ conversion,ꢀ theꢀ internalꢀ 12-bitꢀ capacitiveꢀ
chargeꢀredistributionꢀDACꢀoutputꢀisꢀsequencedꢀthroughꢀ
aꢀsuccessiveꢀapproximationꢀalgorithmꢀbyꢀtheꢀSARꢀstart-
ingꢀfromꢀtheꢀmostꢀsignificantꢀbitꢀ(MSB)ꢀtoꢀtheꢀleastꢀ
significantꢀbitꢀ(LSB).ꢀTheꢀsampledꢀinputꢀisꢀsuccessivelyꢀ
comparedꢀwithꢀbinaryꢀweightedꢀchargesꢀsuppliedꢀbyꢀ
theꢀcapacitiveꢀDACꢀusingꢀaꢀdifferentialꢀcomparator.ꢀAtꢀ
theꢀendꢀofꢀaꢀconversion,ꢀtheꢀDACꢀoutputꢀbalancesꢀtheꢀ
analogꢀinput.ꢀTheꢀSARꢀcontentsꢀ(aꢀ12-bitꢀdataꢀword)ꢀ
thatꢀrepresentꢀtheꢀsampledꢀanalogꢀinputꢀareꢀloadedꢀintoꢀ
12ꢀoutputꢀlatchesꢀthatꢀallowꢀtheꢀdataꢀtoꢀbeꢀshiftedꢀoutꢀ
2
viaꢀtheꢀI Cꢀinterface.
2309fd
ꢀ0
LTC2309
AppLICAtIOns InFORMAtIOn
4 Differential
8 Single-Ended
1st Conversion
2nd Conversion
CH0
CH1
+ (
)
)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+
+
+
+
+
+
+
+
–
{
{
{
{
(
+
–
+
–
+
–
CH2
CH3
–
+
CH2
CH3
{
{
{
{
+ (
)
)
CH2
CH3
–
(
+
–
CH4
CH5
+
+
CH4
CH5
+ (
)
)
CH4
CH5
–
(
+
–
COM
(UNUSED)
COM (
)
–
CH6
CH7
+ (
)
)
–
2328 F01b
(
+
COM (
)
–
–
Figure 1b. Changing the MUX Assignments “On the Fly”
Combinations of Differential
and Single-Ended
CH0
+
{
CH1
–
Unipolar Mode
Bipolar Mode
CH2
–
{
CH3
+
COM
COM
+
+
+
+
CH4
CH5
CH6
CH7
+
REFCOMP/2
–
2328 F02
COM (
)
–
Figure 2. Driving COM in Unipolar and Bipolar Modes
2309 F01a
Figure 1a. Example of MUX Configurations
mode,ꢀtheꢀanalogꢀinputsꢀdrawꢀonlyꢀaꢀsmallꢀleakageꢀcur-
rent.ꢀIfꢀtheꢀsourceꢀimpedanceꢀofꢀtheꢀdrivingꢀcircuitꢀisꢀ
low,ꢀtheꢀADCꢀinputsꢀcanꢀbeꢀdrivenꢀdirectly.ꢀOtherwise,ꢀ
moreꢀacquisitionꢀtimeꢀshouldꢀbeꢀallowedꢀforꢀaꢀsourceꢀ
withꢀhigherꢀimpedance.
Table 1. Channel Configuration
S/D O/S S1 S0
0
1
2
3
4
5
6
+
–
+
7
–
+
COM
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
Input Filtering
–
+
+
Theꢀ noiseꢀ andꢀ distortionꢀ ofꢀ theꢀ inputꢀ amplifierꢀ andꢀ
otherꢀcircuitryꢀmustꢀbeꢀconsideredꢀsinceꢀtheyꢀwillꢀaddꢀ
toꢀtheꢀADCꢀnoiseꢀandꢀdistortion.ꢀTherefore,ꢀnoisyꢀinputꢀ
circuitryꢀshouldꢀbeꢀfilteredꢀpriorꢀtoꢀtheꢀanalogꢀinputsꢀtoꢀ
minimizeꢀnoise.ꢀAꢀsimpleꢀ1-poleꢀRCꢀfilterꢀisꢀsufficientꢀ
forꢀmanyꢀapplications.
–
+
+
–
+
+
–
–
–
–
–
–
–
–
TheꢀanalogꢀinputsꢀofꢀtheꢀLTC2309ꢀcanꢀbeꢀmodeledꢀasꢀ
aꢀ55pFꢀcapacitorꢀ(C )ꢀinꢀseriesꢀwithꢀaꢀ100Ωꢀresistorꢀ
IN
(R ),ꢀasꢀshownꢀinꢀFigureꢀ3a.ꢀC ꢀgetsꢀswitchedꢀtoꢀtheꢀ
ON
IN
+
selectedꢀinputꢀonceꢀduringꢀeachꢀconversion.ꢀLargeꢀfilterꢀ
RCꢀtimeꢀconstantsꢀwillꢀslowꢀtheꢀsettlingꢀofꢀtheꢀinputs.ꢀ
ItꢀisꢀimportantꢀthatꢀtheꢀoverallꢀRCꢀtimeꢀconstantsꢀbeꢀ
shortꢀenoughꢀtoꢀallowꢀtheꢀanalogꢀinputsꢀtoꢀcompletelyꢀ
settleꢀtoꢀ12-bitꢀresolutionꢀwithinꢀtheꢀacquisitionꢀtimeꢀ
+
+
+
(t )ꢀifꢀDCꢀaccuracyꢀisꢀimportant.ꢀ
ACQ
2309fd
ꢀꢀ
LTC2309
AppLICAtIOns InFORMAtIOn
WhenꢀusingꢀaꢀfilterꢀwithꢀaꢀlargeꢀC
ꢀvalueꢀ(e.g.ꢀ1µF),ꢀ
50Ω
FILTER
ANALOG
INPUT
CH0
theꢀinputsꢀdoꢀnotꢀcompletelyꢀsettleꢀandꢀtheꢀcapacitiveꢀ
LTC2309
2000pF
10µF
inputꢀswitchingꢀcurrentsꢀareꢀaveragedꢀintoꢀaꢀnetꢀDCꢀ
COM
currentꢀ(I ).ꢀInꢀthisꢀcase,ꢀtheꢀanalogꢀinputꢀcanꢀbeꢀmod-
DC
eledꢀbyꢀanꢀequivalentꢀresistanceꢀ(R ꢀ=ꢀ1/(f
inꢀseriesꢀwithꢀanꢀidealꢀvoltageꢀsourceꢀ(V
ꢀ•ꢀC ))ꢀ
REFCOMP
EQ
SMPL
IN
/2),ꢀasꢀ
REFCOMP
0.1µF
2309 F04a
shownꢀinꢀFigureꢀ3b.ꢀTheꢀmagnitudeꢀofꢀtheꢀDCꢀcurrentꢀ
isꢀthenꢀapproximatelyꢀI ꢀ=ꢀ(V ꢀ–ꢀV /2)/R ,ꢀ
DC
IN
REFCOMP
EQ
Figure 4a. Optional RC Input Filtering for Single-Ended Input
whichꢀisꢀroughlyꢀproportionalꢀtoꢀV .ꢀToꢀpreventꢀlargeꢀ
IN
DCꢀdropsꢀacrossꢀtheꢀresistorꢀR
,ꢀaꢀfilterꢀwithꢀaꢀsmallꢀ
FILTER
resistorꢀandꢀlargeꢀcapacitorꢀshouldꢀbeꢀchosen.ꢀWhenꢀ
1000pF
50Ω
runningꢀatꢀtheꢀmaximumꢀthroughputꢀrateꢀofꢀ14ksps,ꢀ
CH0
theꢀinputꢀcurrentꢀequalsꢀ1.5µAꢀatꢀV ꢀ=ꢀ4.096V,ꢀwhichꢀ
DIFFERENTIAL
IN
LTC2309
ANALOG
INPUTS
1000pF
1000pF
amountsꢀtoꢀaꢀfull-scaleꢀerrorꢀofꢀ0.5LSBꢀwhenꢀusingꢀaꢀ
50Ω
CH1
filterꢀresistorꢀ(R
)ꢀofꢀ333Ω.ꢀApplicationsꢀrequiringꢀ
FILTER
lowerꢀsampleꢀratesꢀcanꢀtolerateꢀaꢀlargerꢀfilterꢀresistorꢀ
REFCOMP
forꢀtheꢀsameꢀamountꢀofꢀfull-scaleꢀerror.ꢀ
0.1µF
10µF
2309 F04b
INPUT
CH0-CH7
R
LTC2309
ON
Figure 4b. Optional RC Input Filtering for Differential Inputs
R
SOURCE
100Ω
V
IN
C
IN
C
FILTER
55pF
selfꢀheatingꢀandꢀfromꢀdamageꢀthatꢀmayꢀoccurꢀduringꢀ
soldering.ꢀMetalꢀfilmꢀsurfaceꢀmountꢀresistorsꢀareꢀmuchꢀ
lessꢀsusceptibleꢀtoꢀbothꢀproblems.
2309 F03a
Figure 3a. Analog Input Equivalent Circuit
Dynamic Performance
INPUT
I
DC CH0-CH7
R
FILTER
FastꢀFourierꢀTransformꢀ(FFT)ꢀtestꢀtechniquesꢀareꢀusedꢀtoꢀ
testꢀtheꢀADC’sꢀfrequencyꢀresponse,ꢀdistortionꢀandꢀnoiseꢀ
atꢀtheꢀratedꢀthroughput.ꢀByꢀapplyingꢀaꢀlowꢀdistortionꢀ
sineꢀwaveꢀandꢀanalyzingꢀtheꢀdigitalꢀoutputꢀusingꢀanꢀFFTꢀ
algorithm,ꢀtheꢀADC’sꢀspectralꢀcontentꢀcanꢀbeꢀexaminedꢀ
forꢀfrequenciesꢀoutsideꢀtheꢀfundamental.
V
IN
LTC2309
R
EQ
SMPL
C
FILTER
1/(f
• C )
IN
+
V
/2
REFCOMP
–
2309 F03b
Figure 3b. Analog Input Equivalent
Circuit for Large Filter Capacitances
Signal-to-Noise and Distortion Ratio (SINAD)
Figuresꢀ4aꢀandꢀ4bꢀshowꢀexamplesꢀofꢀinputꢀfilteringꢀforꢀ Theꢀsignal-to-noiseꢀandꢀdistortionꢀratioꢀ(SINAD)ꢀisꢀtheꢀ
single-endedꢀ andꢀ differentialꢀ inputs.ꢀ Forꢀ theꢀ single- ratioꢀbetweenꢀtheꢀRMSꢀamplitudeꢀofꢀtheꢀfundamentalꢀ
endedꢀcaseꢀinꢀFigureꢀ4a,ꢀaꢀ50Ωꢀsourceꢀresistorꢀandꢀaꢀ inputꢀfrequencyꢀtoꢀtheꢀRMSꢀamplitudeꢀofꢀallꢀotherꢀfre-
2000pFꢀcapacitorꢀtoꢀgroundꢀonꢀtheꢀinputꢀwillꢀlimitꢀtheꢀ quencyꢀcomponentsꢀatꢀtheꢀA/Dꢀoutput.ꢀTheꢀoutputꢀisꢀ
inputꢀbandwidthꢀtoꢀ1.6MHz.ꢀHighꢀqualityꢀcapacitorsꢀandꢀ band-limitedꢀtoꢀfrequenciesꢀfromꢀaboveꢀDCꢀandꢀbelowꢀ
resistorsꢀshouldꢀbeꢀusedꢀinꢀtheꢀRCꢀfilterꢀsinceꢀtheseꢀ halfꢀtheꢀsamplingꢀfrequency.ꢀFigureꢀ5ꢀshowsꢀaꢀtypicalꢀ
componentsꢀcanꢀaddꢀdistortion.ꢀNPOꢀandꢀsilverꢀmicaꢀ SINADꢀofꢀ73.3dBꢀwithꢀaꢀ14kHzꢀsamplingꢀrateꢀandꢀaꢀ
typeꢀdielectricꢀcapacitorsꢀhaveꢀexcellentꢀlinearity.ꢀCarbonꢀ 1kHzꢀinput.ꢀAnꢀSNRꢀofꢀ73.4dBꢀcanꢀbeꢀachievedꢀwithꢀ
surfaceꢀmountꢀresistorsꢀcanꢀgenerateꢀdistortionꢀfromꢀ theꢀLTC2309.
2309fd
ꢀꢁ
referenceꢀamplifierꢀandꢀisꢀavailableꢀatꢀV
.ꢀV ꢀshouldꢀ
LTC2309
AppLICAtIOns InFORMAtIOn
0
internalꢀreferenceꢀbufferꢀcanꢀalsoꢀbeꢀoverdrivenꢀfromꢀ
1VꢀtoꢀV ,ꢀasꢀshownꢀinꢀFigureꢀ6c.ꢀToꢀdoꢀso,ꢀV ꢀmustꢀ
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
DD
REF
–20
beꢀgroundedꢀtoꢀdisableꢀtheꢀreferenceꢀbuffer.
–40
–60
–80
R1
8k
V
REF
BANDGAP
REFERENCE
2.5V
2.2µF
0.1µF
–100
–120
–140
REFCOMP
4.096V
10µF
REFERENCE
AMP
0
1
2
3
4
5
6
7
FREQUENCY (kHz)
R2
2309 G03
R3
GND
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
LTC2309
2309 F06a
Total Harmonic Distortion (THD)
Figure 6a. LTC2309 Reference Circuit
Totalꢀ harmonicꢀ distortionꢀ (THD)ꢀ isꢀ theꢀ ratioꢀ ofꢀ theꢀ
RMSꢀsumꢀofꢀallꢀharmonicsꢀofꢀtheꢀinputꢀsignalꢀtoꢀtheꢀ
fundamentalꢀitself.ꢀTheꢀout-of-bandꢀharmonicsꢀaliasꢀintoꢀ
theꢀfrequencyꢀbandꢀbetweenꢀDCꢀandꢀhalfꢀtheꢀsamplingꢀ
5V
0.1µF
V
IN
frequencyꢀ(
/2).ꢀTHDꢀisꢀexpressedꢀas:
fSMPL
LT1790A-2.5
V
V 2 + V 2 + V42...+ V 2
V
OUT
REF
2
3
N
2.2µF
0.1µF
THD= 20log
LTC2309
V
ꢀ
1
REFCOMP
10µF
whereꢀV ꢀisꢀtheꢀRMSꢀamplitudeꢀofꢀtheꢀfundamentalꢀ
1
GND
frequencyꢀandꢀV ꢀthroughꢀV ꢀareꢀtheꢀamplitudesꢀofꢀtheꢀ
2
N
secondꢀthroughꢀNthꢀharmonics.ꢀ
2309 F06b
Figure 6b. Using the LT®1790A-2.5 as an External Reference
Internal Reference
TheꢀLTC2309ꢀhasꢀanꢀon-chip,ꢀtemperatureꢀcompen-
satedꢀ bandgapꢀ referenceꢀ thatꢀ isꢀ factoryꢀ trimmedꢀ toꢀ
2.5Vꢀ(ReferꢀtoꢀFigureꢀ6a).ꢀItꢀisꢀinternallyꢀconnectedꢀtoꢀaꢀ
5V
REF REF
V
REF
0.1µF
V
IN
beꢀbypassedꢀtoꢀGNDꢀwithꢀaꢀ2.2μFꢀceramicꢀcapacitorꢀtoꢀ
minimizeꢀnoise.ꢀAnꢀ8kꢀresistorꢀisꢀinꢀseriesꢀwithꢀtheꢀoutputꢀ
soꢀthatꢀitꢀcanꢀbeꢀeasilyꢀoverdrivenꢀbyꢀanꢀexternalꢀrefer-
enceꢀifꢀmoreꢀaccuracyꢀand/orꢀlowerꢀdriftꢀareꢀrequired,ꢀ
asꢀshownꢀinꢀFigureꢀ6b.ꢀTheꢀreferenceꢀamplifierꢀgainsꢀ
LTC2309
LT1790A-4.096
V
REFCOMP
OUT
10µF
0.1µF
GND
2309 F06c
theꢀV ꢀvoltageꢀbyꢀ1.638ꢀtoꢀ4.096VꢀatꢀREFCOMP.ꢀToꢀ
REF
compensateꢀtheꢀreferenceꢀamplifier,ꢀbypassꢀREFCOMPꢀ
withꢀaꢀ10μFꢀceramicꢀcapacitorꢀinꢀparallelꢀwithꢀaꢀ0.1μFꢀ
ceramicꢀ capacitorꢀ forꢀ bestꢀ noiseꢀ performance.ꢀ Theꢀ
Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
2309fd
ꢀꢂ
LTC2309
AppLICAtIOns InFORMAtIOn
Internal Conversion Clock
The START and STOP Conditions
ReferringꢀtoꢀFigureꢀ7,ꢀaꢀSTARTꢀ(S)ꢀconditionꢀisꢀgener-
atedꢀbyꢀtransitioningꢀSDAꢀfromꢀHIGHꢀtoꢀLOWꢀwhileꢀ
SCLꢀisꢀHIGH.ꢀTheꢀbusꢀisꢀconsideredꢀtoꢀbeꢀbusyꢀafterꢀtheꢀ
STARTꢀcondition.ꢀWhenꢀtheꢀdataꢀtransferꢀisꢀfinished,ꢀaꢀ
STOPꢀ(P)ꢀconditionꢀisꢀgeneratedꢀbyꢀtransitioningꢀSDAꢀ
fromꢀLOWꢀtoꢀHIGHꢀwhileꢀSCLꢀisꢀHIGH.ꢀTheꢀbusꢀisꢀfreeꢀ
afterꢀaꢀSTOPꢀconditionꢀisꢀgenerated.ꢀSTARTꢀandꢀSTOPꢀ
conditionsꢀareꢀalwaysꢀgeneratedꢀbyꢀtheꢀmaster.
Theꢀinternalꢀconversionꢀclockꢀisꢀfactoryꢀtrimmedꢀtoꢀ
achieveꢀaꢀtypicalꢀconversionꢀtimeꢀ(t
)ꢀofꢀ1.3μsꢀandꢀ
CONV
aꢀ maximumꢀ conversionꢀ timeꢀ ofꢀ 1.8μsꢀ overꢀ theꢀ fullꢀ
operatingꢀtemperatureꢀrange.
2
I C Interface
2
TheꢀLTC2309ꢀcommunicatesꢀthroughꢀanꢀI Cꢀinterface.ꢀ
2
TheꢀI Cꢀinterfaceꢀisꢀaꢀ2-wireꢀopen-drainꢀinterfaceꢀsup-
portingꢀ multipleꢀ devicesꢀ andꢀ multipleꢀ mastersꢀ onꢀ aꢀ
singleꢀbus.ꢀTheꢀconnectedꢀdevicesꢀcanꢀonlyꢀpullꢀtheꢀ
serialꢀdataꢀlineꢀ(SDA)ꢀLOWꢀandꢀcanꢀneverꢀdriveꢀitꢀHIGH.ꢀ
SDAꢀisꢀrequiredꢀtoꢀbeꢀexternallyꢀconnectedꢀtoꢀtheꢀsup-
plyꢀthroughꢀaꢀpull-upꢀresistor.ꢀWhenꢀtheꢀdataꢀlineꢀisꢀnotꢀ
Whenꢀtheꢀbusꢀisꢀinꢀuse,ꢀitꢀstaysꢀbusyꢀifꢀaꢀrepeatedꢀ
STARTꢀ(Sr)ꢀisꢀgeneratedꢀinsteadꢀofꢀaꢀSTOPꢀcondition.ꢀ
TheꢀrepeatedꢀSTARTꢀtimingꢀisꢀfunctionallyꢀidenticalꢀtoꢀ
theꢀSTARTꢀandꢀisꢀusedꢀforꢀwritingꢀandꢀreadingꢀfromꢀtheꢀ
deviceꢀbeforeꢀtheꢀinitiationꢀofꢀaꢀnewꢀconversion.
2
beingꢀdrivenꢀLOW,ꢀitꢀisꢀHIGH.ꢀDataꢀonꢀtheꢀI Cꢀbusꢀcanꢀ
beꢀtransferredꢀatꢀratesꢀupꢀtoꢀ100kbits/sꢀinꢀtheꢀstandardꢀ
START Condition
STOP Condition
modeꢀandꢀupꢀtoꢀ400kbits/sꢀinꢀtheꢀfastꢀmode.ꢀTheꢀV ꢀ
DD
SDA
powerꢀshouldꢀnotꢀbeꢀremovedꢀfromꢀtheꢀLTC2309ꢀwhenꢀ
2
2
SDA
SCL
theꢀI CꢀbusꢀisꢀactiveꢀtoꢀavoidꢀloadingꢀtheꢀI Cꢀbusꢀlinesꢀ
throughꢀtheꢀinternalꢀESDꢀprotectionꢀdiodes.
S
P
2309 F07
SCL
2
EachꢀdeviceꢀonꢀtheꢀI Cꢀbusꢀisꢀrecognizedꢀbyꢀaꢀuniqueꢀ
addressꢀstoredꢀinꢀtheꢀdeviceꢀandꢀcanꢀonlyꢀoperateꢀeitherꢀ
asꢀaꢀtransmitterꢀorꢀreceiver,ꢀdependingꢀonꢀtheꢀfunctionꢀ
ofꢀtheꢀdevice.ꢀAꢀdeviceꢀcanꢀalsoꢀbeꢀconsideredꢀasꢀaꢀ
masterꢀorꢀaꢀslaveꢀwhenꢀperformingꢀdataꢀtransfers.ꢀAꢀ
masterꢀisꢀtheꢀdeviceꢀwhichꢀinitiatesꢀaꢀdataꢀtransferꢀonꢀ
theꢀbusꢀandꢀgeneratesꢀtheꢀclockꢀsignalsꢀtoꢀpermitꢀtheꢀ
transfer.ꢀDevicesꢀaddressedꢀbyꢀtheꢀmasterꢀareꢀconsid-
eredꢀslaves.
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
2
AfterꢀtheꢀSTARTꢀcondition,ꢀtheꢀI Cꢀbusꢀisꢀbusyꢀandꢀ
dataꢀtransferꢀcanꢀbeginꢀbetweenꢀtheꢀmasterꢀandꢀtheꢀ
addressedꢀslave.ꢀDataꢀisꢀtransferredꢀoverꢀtheꢀbusꢀinꢀ
groupsꢀ ofꢀ nineꢀ bits,ꢀ oneꢀ byteꢀ followedꢀ byꢀ oneꢀ ac-
knowledgeꢀ(ACK)ꢀbit.ꢀTheꢀmasterꢀreleasesꢀtheꢀSDAꢀ
lineꢀduringꢀtheꢀninthꢀSCLꢀclockꢀcycle.ꢀTheꢀslaveꢀdeviceꢀ
canꢀissueꢀanꢀACKꢀbyꢀpullingꢀSDAꢀLOWꢀorꢀissueꢀaꢀNotꢀ
Acknowledgeꢀ(NACK)ꢀbyꢀleavingꢀtheꢀSDAꢀlineꢀhighꢀ
impedanceꢀ(theꢀexternalꢀpull-upꢀresistorꢀwillꢀholdꢀtheꢀ
lineꢀhigh).ꢀChangeꢀofꢀdataꢀonlyꢀoccursꢀwhileꢀtheꢀSCLꢀ
lineꢀisꢀLOW.
TheꢀLTC2309ꢀcanꢀonlyꢀbeꢀaddressedꢀasꢀaꢀslaveꢀ(seeꢀ
Tableꢀ2).ꢀOnceꢀaddressed,ꢀitꢀcanꢀreceiveꢀconfigurationꢀ
bitsꢀ(D ꢀword)ꢀorꢀtransmitꢀtheꢀlastꢀconversionꢀresult.ꢀTheꢀ
IN
serialꢀclockꢀlineꢀ(SCL)ꢀisꢀalwaysꢀanꢀinputꢀtoꢀtheꢀLTC2309ꢀ
andꢀtheꢀserialꢀdataꢀlineꢀ(SDA)ꢀisꢀbidirectional.ꢀTheꢀdeviceꢀ
supportsꢀtheꢀstandardꢀmodeꢀandꢀtheꢀfastꢀmodeꢀforꢀdataꢀ
transferꢀspeedsꢀupꢀtoꢀ400kbits/sꢀ(seeꢀtheꢀTimingꢀDiagramꢀ
2
sectionꢀforꢀdefinitionꢀofꢀtheꢀI Cꢀtiming).
Data Format
Afterꢀ aꢀ STARTꢀ condition,ꢀ theꢀ masterꢀ sendsꢀ aꢀ 7-bitꢀ
addressꢀfollowedꢀbyꢀaꢀread/writeꢀ(R/W)ꢀbit.ꢀTheꢀR/Wꢀ
bitꢀisꢀ1ꢀforꢀaꢀreadꢀrequestꢀandꢀ0ꢀforꢀaꢀwriteꢀrequest.ꢀ
Ifꢀ theꢀ 7-bitꢀ addressꢀ matchesꢀ oneꢀ ofꢀ theꢀ LTC2309’sꢀ
9ꢀpin-selectableꢀaddresses,ꢀtheꢀADCꢀisꢀselected.ꢀWhenꢀ
2309fd
ꢀꢃ
LTC2309
AppLICAtIOns InFORMAtIOn
theꢀADCꢀisꢀaddressedꢀduringꢀaꢀconversion,ꢀitꢀwillꢀnotꢀ
acknowledgeꢀR/WꢀrequestsꢀandꢀwillꢀissueꢀaꢀNACKꢀbyꢀ
leavingꢀtheꢀSDAꢀlineꢀHIGH.ꢀIfꢀtheꢀconversionꢀisꢀcom-
plete,ꢀtheꢀLTC2309ꢀissuesꢀanꢀACKꢀbyꢀpullingꢀtheꢀSDAꢀ
lineꢀLOW.ꢀTheꢀLTC2309ꢀhasꢀtwoꢀregisters.ꢀTheꢀ12-bitꢀ
wideꢀoutputꢀregisterꢀcontainsꢀtheꢀlastꢀconversionꢀresult.ꢀ
aꢀ readꢀ operation,ꢀ itꢀ acknowledgesꢀ byꢀ pullingꢀ SDAꢀ
LOWꢀandꢀactsꢀasꢀaꢀtransmitter.ꢀTheꢀmaster/receiverꢀ
canꢀreadꢀupꢀtoꢀtwoꢀbytesꢀfromꢀtheꢀLTC2309.ꢀAfterꢀaꢀ
completeꢀreadꢀoperationꢀofꢀ2ꢀbytes,ꢀaꢀSTOPꢀconditionꢀ
isꢀneededꢀtoꢀinitiateꢀaꢀnewꢀconversion.ꢀTheꢀdeviceꢀwillꢀ
NACKꢀsubsequentꢀreadꢀoperationsꢀwhileꢀaꢀconversionꢀ
Theꢀ6-bitꢀwideꢀinputꢀregisterꢀconfiguresꢀtheꢀinputꢀMUXꢀ isꢀbeingꢀperformed.
andꢀtheꢀoperatingꢀmodeꢀofꢀtheꢀADC.
Theꢀdataꢀoutputꢀstreamꢀisꢀ16ꢀbitsꢀlongꢀandꢀisꢀshiftedꢀ
outꢀonꢀtheꢀfallingꢀedgesꢀofꢀSCLꢀ(seeꢀFigureꢀ8a).ꢀTheꢀ
firstꢀbitꢀisꢀtheꢀMSBꢀandꢀtheꢀ12thꢀbitꢀisꢀtheꢀLSBꢀofꢀtheꢀ
conversionꢀresult.ꢀTheꢀremainingꢀfourꢀbitsꢀareꢀzero.ꢀ
Figuresꢀ14ꢀandꢀ15ꢀareꢀtheꢀtransferꢀcharacteristicsꢀforꢀ
theꢀbipolarꢀandꢀunipolarꢀmodes.ꢀDataꢀisꢀoutputꢀonꢀtheꢀ
SDAꢀlineꢀinꢀ2’sꢀcomplementꢀformatꢀforꢀbipolarꢀreadingsꢀ
orꢀinꢀstraightꢀbinaryꢀforꢀunipolarꢀreadings.
Output Data Format
Theꢀoutputꢀregisterꢀcontainsꢀtheꢀlastꢀconversionꢀresult.ꢀ
Afterꢀeachꢀconversionꢀisꢀcompleted,ꢀtheꢀdeviceꢀauto-
maticallyꢀentersꢀeitherꢀnapꢀorꢀsleepꢀmodeꢀdependingꢀ
onꢀtheꢀsettingꢀofꢀtheꢀSLPꢀbitꢀ(seeꢀNapꢀModeꢀandꢀSleepꢀ
Modeꢀsections).ꢀWhenꢀtheꢀLTC2309ꢀisꢀaddressedꢀforꢀ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
• • •
• • •
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10 B9
B8
B7
B6
B5 B4
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
MOST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
1
2
3
4
5
6
7
8
9
SCL
• • •
• • •
(CONTINUED)
CONVERSION
INITIATED
SDA
(CONTINUED)
STOP
BY MASTER
B3
B2
B1
B0
NACK BY
MASTER
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
2309 F08a
Figure 8a. Timing Diagram for Reading from the LTC2309
2309fd
ꢀꢄ
LTC2309
AppLICAtIOns InFORMAtIOn
Input Data Format
read/writeꢀoperationꢀwillꢀalsoꢀinitiateꢀnewꢀconversion,ꢀ
butꢀtheꢀoutputꢀresultꢀmayꢀnotꢀbeꢀvalidꢀdueꢀtoꢀlackꢀofꢀ
adequateꢀacquisitionꢀtimeꢀ(seeꢀAcquisitionꢀsection).ꢀ
WhenꢀtheꢀLTC2309ꢀisꢀaddressedꢀforꢀaꢀwriteꢀoperation,ꢀ
itꢀacknowledgesꢀbyꢀpullingꢀSDAꢀLOWꢀduringꢀtheꢀLOWꢀ
periodꢀbeforeꢀtheꢀ9thꢀcycleꢀandꢀactsꢀasꢀaꢀreceiver.ꢀTheꢀ
master/transmitterꢀcanꢀthenꢀsendꢀ1ꢀbyteꢀtoꢀprogramꢀtheꢀ
LTC2309 Address
TheꢀLTC2309ꢀhasꢀtwoꢀaddressꢀpinsꢀ(AD0ꢀandꢀAD1)ꢀthatꢀ
mayꢀbeꢀtiedꢀHIGH,ꢀLOW,ꢀorꢀleftꢀfloatingꢀtoꢀenableꢀoneꢀ
ofꢀ9ꢀpossibleꢀaddressesꢀ(seeꢀTableꢀ2).
device.ꢀTheꢀinputꢀbyteꢀconsistsꢀofꢀtheꢀ6-bitꢀD ꢀwordꢀ
IN
followedꢀbyꢀtwoꢀbitsꢀthatꢀareꢀignoredꢀbyꢀtheꢀADCꢀandꢀ
areꢀconsideredꢀdon’tꢀcaresꢀ(X)ꢀ(seeꢀFigureꢀ8b).ꢀTheꢀ
inputꢀbitsꢀareꢀlatchedꢀonꢀtheꢀrisingꢀedgeꢀofꢀSCLꢀduringꢀ
theꢀwriteꢀoperation.
Inꢀ additionꢀ toꢀ theꢀ configurableꢀ addressesꢀ listedꢀ inꢀ
Tableꢀ2,ꢀtheꢀLTC2309ꢀalsoꢀcontainsꢀaꢀglobalꢀaddressꢀ
(1101011)ꢀwhichꢀmayꢀbeꢀusedꢀforꢀsynchronizingꢀmul-
Afterꢀ power-up,ꢀ theꢀ ADCꢀ initiatesꢀ anꢀ internalꢀ resetꢀ
2
tipleꢀLTC2309sꢀorꢀotherꢀI CꢀLTC230XꢀSARꢀADCsꢀ(seeꢀ
cycleꢀwhichꢀsetsꢀtheꢀD ꢀwordꢀtoꢀallꢀ0sꢀ(S/Dꢀ=ꢀO/Sꢀ=ꢀ
IN
SynchronizingꢀMultipleꢀLTC2309sꢀwithꢀGlobalꢀAddressꢀ
Callꢀsection).
S0ꢀ=ꢀS1ꢀ=ꢀUNIꢀ=ꢀSLPꢀ=ꢀ0).ꢀAꢀwriteꢀoperationꢀmayꢀbeꢀ
performedꢀifꢀtheꢀdefaultꢀstateꢀofꢀtheꢀADC’sꢀconfigurationꢀ
isꢀnotꢀdesired.ꢀOtherwise,ꢀtheꢀADCꢀmustꢀbeꢀproperlyꢀ
addressedꢀandꢀfollowedꢀbyꢀaꢀSTOPꢀconditionꢀtoꢀinitiateꢀ
aꢀconversion.
Table 2. Address Assignment
AD1
LOW
LOW
LOW
Float
Float
Float
HIGH
HIGH
HIGH
AD0
LOW
Float
HIGH
HIGH
Float
LOW
LOW
Float
HIGH
ADDRESS
0001000
0001001
0001010
0001011
0011000
0011001
0011010
0011011
0101000
Initiating a New Conversion
TheꢀLTC2309ꢀawakensꢀfromꢀeitherꢀnapꢀorꢀsleepꢀwhenꢀ
properlyꢀaddressedꢀforꢀaꢀread/writeꢀoperation.ꢀAꢀSTOPꢀ
commandꢀmayꢀthenꢀbeꢀissuedꢀafterꢀperformingꢀtheꢀ
read/writeꢀoperationꢀtoꢀtriggerꢀaꢀnewꢀconversion.ꢀ
IssuingꢀaꢀSTOPꢀcommandꢀafterꢀtheꢀ8thꢀSCLꢀclockꢀpulseꢀ
ofꢀtheꢀaddressꢀframeꢀandꢀbeforeꢀtheꢀcompletionꢀofꢀaꢀ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
CONVERSION
INITIATED
A6
A5
A4
A3
A2
A1
A0 R/W
S/D O/S S1
S0 UNI SLP
WORD
X
X
STOP BY
MASTER
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
D
IN
2309 F08b
ADDRESS FRAME
WRITE 1 BYTE
Figure 8b. Timing Diagram for Writing to the LTC2309
2309fd
ꢀꢅ
LTC2309
AppLICAtIOns InFORMAtIOn
Continuous Read
atesꢀaꢀNACKꢀsignalꢀindicatingꢀtheꢀconversionꢀcycleꢀisꢀ
inꢀprogress.
Inꢀapplicationsꢀwhereꢀtheꢀsameꢀinputꢀchannelꢀisꢀsampledꢀ
eachꢀcycle,ꢀconversionsꢀcanꢀbeꢀcontinuouslyꢀperformedꢀ
Continuous Read/Write
andꢀreadꢀwithoutꢀaꢀwriteꢀcycleꢀ(seeꢀFigureꢀ9).ꢀTheꢀD ꢀ
IN
Onceꢀtheꢀconversionꢀcycleꢀisꢀcomplete,ꢀtheꢀLTC2309ꢀ
canꢀbeꢀwrittenꢀtoꢀandꢀthenꢀreadꢀfromꢀusingꢀtheꢀrepeatedꢀ
STARTꢀ(Sr)ꢀcommand.ꢀFigureꢀ10ꢀshowsꢀaꢀcycleꢀwhichꢀ
beginsꢀwithꢀaꢀdataꢀwrite,ꢀaꢀrepeatedꢀSTART,ꢀfollowedꢀ
byꢀaꢀreadꢀandꢀconcludedꢀwithꢀaꢀSTOPꢀcommand.ꢀAfterꢀ
allꢀ16ꢀbitsꢀareꢀreadꢀout,ꢀaꢀconversionꢀmayꢀbeꢀinitiatedꢀ
byꢀissuingꢀaꢀSTOPꢀcommand.ꢀTheꢀfollowingꢀconver-
sionꢀwillꢀbeꢀperformedꢀusingꢀtheꢀnewlyꢀprogrammedꢀ
data.
wordꢀremainsꢀunchangedꢀfromꢀtheꢀlastꢀvalueꢀwrittenꢀ
intoꢀtheꢀdevice.ꢀIfꢀtheꢀdeviceꢀhasꢀnotꢀbeenꢀwrittenꢀtoꢀ
sinceꢀpower-up,ꢀtheꢀD ꢀwordꢀdefaultsꢀtoꢀallꢀ0sꢀ(S/Dꢀ=ꢀ
IN
O/Sꢀ=ꢀS0ꢀ=ꢀS1ꢀ=ꢀUNIꢀ=ꢀSLPꢀ=ꢀ0).ꢀAtꢀtheꢀendꢀofꢀaꢀreadꢀ
operation,ꢀaꢀSTOPꢀconditionꢀmayꢀbeꢀgivenꢀtoꢀstartꢀaꢀnewꢀ
conversion.ꢀAtꢀtheꢀconclusionꢀofꢀtheꢀconversionꢀcycle,ꢀ
theꢀnextꢀresultꢀmayꢀbeꢀreadꢀusingꢀtheꢀmethodꢀdescribedꢀ
above.ꢀIfꢀtheꢀconversionꢀcycleꢀisꢀnotꢀconcludedꢀandꢀaꢀ
validꢀaddressꢀselectsꢀtheꢀdevice,ꢀtheꢀLTC2309ꢀgener-
S
7-BIT ADDRESS R ACK READ
P
S
7-BIT ADDRESS R ACK READ
P
CONVERSION
NAP
DATA OUTPUT CONVERSION
NAP
DATA
OUTPUT
CONVERSION
2309 F09
Figure 9. Consecutive Reading with the Same Configuration
S
7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ
P
CONVERSION
NAP
DATA INPUT
ADDRESS
DATA
OUTPUT
CONVERSION
2309 F10
Figure 10. Write, Read, START Conversion
2309fd
ꢀꢆ
LTC2309
AppLICAtIOns InFORMAtIOn
Synchronizing Multiple LTC2309s with a Global
Address Call
Nap Mode
TheꢀADCꢀentersꢀnapꢀmodeꢀafterꢀaꢀconversionꢀisꢀcom-
2
InꢀapplicationsꢀwhereꢀseveralꢀLTC2309sꢀorꢀotherꢀI CꢀSARꢀ pleteꢀ(t
)ꢀifꢀtheꢀSLPꢀbitꢀisꢀsetꢀtoꢀaꢀlogicꢀ0.ꢀTheꢀsup-
CONV
ADCsꢀfromꢀLinearꢀTechnologyꢀCorporationꢀareꢀusedꢀonꢀ plyꢀcurrentꢀdecreasesꢀtoꢀ210μAꢀinꢀnapꢀmodeꢀbetweenꢀ
2
theꢀsameꢀI Cꢀbus,ꢀallꢀconvertersꢀcanꢀbeꢀsynchronizedꢀ conversions,ꢀ therebyꢀ reducingꢀ theꢀ averageꢀ powerꢀ
throughꢀtheꢀuseꢀofꢀaꢀglobalꢀaddressꢀcall.ꢀPriorꢀtoꢀissu- dissipationꢀasꢀtheꢀsampleꢀrateꢀdecreases.ꢀForꢀexample,ꢀ
ingꢀtheꢀglobalꢀaddressꢀcall,ꢀallꢀconvertersꢀmustꢀhaveꢀ theꢀLTC2309ꢀdrawsꢀanꢀaverageꢀofꢀ300µAꢀatꢀaꢀ1kspsꢀ
completedꢀaꢀconversionꢀcycle.ꢀTheꢀmasterꢀthenꢀissuesꢀ samplingꢀrate.ꢀTheꢀLTC2309ꢀkeepsꢀonlyꢀtheꢀreferenceꢀ
aꢀSTART,ꢀfollowedꢀbyꢀtheꢀglobalꢀaddressꢀ1101011,ꢀandꢀ (V )ꢀandꢀreferenceꢀbufferꢀ(REFCOMP)ꢀcircuitryꢀactiveꢀ
REF
aꢀwriteꢀrequest.ꢀAllꢀconvertersꢀwillꢀbeꢀselectedꢀandꢀac- whenꢀinꢀnapꢀmode.
knowledgeꢀtheꢀrequest.ꢀTheꢀmasterꢀthenꢀsendsꢀaꢀwriteꢀ
Sleep Mode
byteꢀ(optional)ꢀfollowedꢀbyꢀtheꢀSTOPꢀcommand.ꢀThisꢀwillꢀ
updateꢀtheꢀchannelꢀselectionꢀ(optional)ꢀandꢀsimultane-
ouslyꢀinitiateꢀaꢀconversionꢀforꢀallꢀADCsꢀonꢀtheꢀbusꢀ(seeꢀ
Figureꢀ11).ꢀInꢀorderꢀtoꢀsynchronizeꢀmultipleꢀconvertersꢀ
withoutꢀchangingꢀtheꢀchannel,ꢀaꢀSTOPꢀcommandꢀmayꢀ
beꢀissuedꢀafterꢀacknowledgementꢀofꢀtheꢀglobalꢀwriteꢀ
command.ꢀGlobalꢀreadꢀcommandsꢀareꢀnotꢀallowedꢀandꢀ
theꢀconvertersꢀwillꢀNACKꢀaꢀglobalꢀreadꢀrequest.
TheꢀADCꢀentersꢀsleepꢀmodeꢀafterꢀaꢀconversionꢀisꢀcom-
pleteꢀ(t )ꢀifꢀtheꢀSLPꢀbitꢀisꢀsetꢀtoꢀaꢀlogicꢀ1.ꢀTheꢀADCꢀ
CONV
drawsꢀonlyꢀ7µAꢀinꢀsleepꢀmode,ꢀprovidedꢀthatꢀnoneꢀofꢀ
theꢀdigitalꢀinputsꢀareꢀswitching.ꢀWhenꢀtheꢀLTC2309ꢀisꢀ
properlyꢀaddressed,ꢀtheꢀADCꢀisꢀreleasedꢀfromꢀsleepꢀmodeꢀ
andꢀrequiresꢀ200msꢀ(t
theꢀrespectiveꢀ2.2μFꢀandꢀ10μFꢀbypassꢀcapacitorsꢀonꢀtheꢀ
)ꢀtoꢀwakeꢀupꢀandꢀchargeꢀ
REFWAKE
V
ꢀandꢀREFCOMPꢀpins.ꢀAꢀnewꢀconversionꢀshouldꢀnotꢀ
REF
beꢀinitiatedꢀbeforeꢀthisꢀtime,ꢀasꢀshownꢀinꢀFigureꢀ12.
SCL
SDA
LTC2309
LTC2309
LTC2309
S
GLOBAL ADDRESS W ACK WRITE (OPTIONAL)
P
CONVERSION
NAP
DATA OUTPUT
CONVERSION OF ALL LTC2309s
2309 F11
Figure 11. Synchronous Multiple LTC2309s with a Global Address Call
S
7-BIT ADDRESS R/W ACK
P
CONVERSION
SLEEP
t
CONVERSION
2309 F12
REFWAKE
Figure 12. Exiting Sleep Mode and Starting a New Conversion
2309fd
ꢀꢇ
LTC2309
AppLICAtIOns InFORMAtIOn
Acquisition
Ifꢀaꢀwriteꢀoperationꢀisꢀbeingꢀperformed,ꢀacquisitionꢀofꢀ
theꢀinputꢀsignalꢀbeginsꢀonꢀtheꢀfallingꢀedgeꢀofꢀtheꢀsixthꢀ
TheꢀLTC2309ꢀbeginsꢀacquiringꢀtheꢀinputꢀsignalꢀatꢀdif-
ferentꢀinstancesꢀdependingꢀonꢀwhetherꢀaꢀreadꢀorꢀwriteꢀ
operationꢀisꢀbeingꢀperformed.ꢀIfꢀaꢀreadꢀoperationꢀisꢀ
beingꢀperformed,ꢀacquisitionꢀofꢀtheꢀinputꢀsignalꢀbeginsꢀ
onꢀtheꢀrisingꢀedgeꢀofꢀtheꢀ9thꢀclockꢀpulseꢀfollowingꢀtheꢀ
addressꢀframe,ꢀasꢀshownꢀinꢀFigureꢀ13a.ꢀ
clockꢀcycleꢀafterꢀtheꢀD ꢀwordꢀhasꢀbeenꢀshiftedꢀin,ꢀasꢀ
IN
shownꢀinꢀFigureꢀ13b.ꢀTheꢀLTC2309ꢀwillꢀacquireꢀtheꢀ
signalꢀfromꢀtheꢀinputꢀchannelꢀthatꢀwasꢀmostꢀrecentlyꢀ
programmedꢀbyꢀtheꢀD ꢀword.ꢀAꢀminimumꢀofꢀ240nsꢀisꢀ
IN
requiredꢀtoꢀacquireꢀtheꢀinputꢀsignalꢀbeforeꢀinitiatingꢀaꢀ
newꢀconversion.ꢀ
1
2
3
4
5
6
7
8
9
1
2
SCL
SDA
ACQUISITION BEGINS
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10
2309 F13a
t
ACQ
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
ACQUISITION BEGINS
A2
A1
A0 R/W
S/D O/S S1 S0 UNI SLP
X
X
2309 F13b
t
ACQ
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
111...111
011...111
011...110
111...110
BIPOLAR
ZERO
100...001
100...000
011...111
011...110
000...001
000...000
111...111
111...110
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2
000...001
000...000
FS = 4.096V
1LSB = FS/2
100...001
100...000
12
12
1LSB = 1mV
1LSB = 1mV
–1 0V
1
0V
FS – 1LSB
–FS/2
FS/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2309 F15
2309 F14
Figure 14. Bipolar Transfer Characteristics (2’s Complement)
Figure 15. Unipolar Transfer Characteristics (Straight Binary)
2309fd
ꢀꢈ
LTC2309
AppLICAtIOns InFORMAtIOn
Board Layout and Bypassing
andꢀV ꢀshouldꢀbeꢀbypassedꢀtoꢀtheꢀgroundꢀplaneꢀasꢀcloseꢀ
DD
toꢀtheꢀpinꢀasꢀpossible.ꢀMaintainingꢀaꢀlowꢀimpedanceꢀpathꢀ
forꢀ theꢀ commonꢀ returnꢀ ofꢀ theseꢀ bypassꢀ capacitorsꢀ isꢀ
essentialꢀtoꢀtheꢀlowꢀnoiseꢀoperationꢀofꢀtheꢀADC.ꢀTheseꢀ
tracesꢀshouldꢀbeꢀasꢀwideꢀasꢀpossible.ꢀSeeꢀFiguresꢀ16a-eꢀ
forꢀaꢀsuggestedꢀlayout.
Toꢀobtainꢀtheꢀbestꢀperformance,ꢀaꢀprintedꢀcircuitꢀboardꢀwithꢀ
aꢀsolidꢀgroundꢀplaneꢀisꢀrequired.ꢀLayoutꢀforꢀtheꢀprintedꢀ
boardꢀshouldꢀensureꢀdigitalꢀandꢀanalogꢀsignalꢀlinesꢀareꢀ
separatedꢀasꢀmuchꢀasꢀpossible.ꢀCareꢀshouldꢀbeꢀtakenꢀnotꢀ
toꢀrunꢀanyꢀdigitalꢀsignalsꢀalongsideꢀanꢀanalogꢀsignal.ꢀAllꢀ
analogꢀinputsꢀshouldꢀbeꢀshieldedꢀbyꢀGND.ꢀV ,ꢀREFCOMPꢀ
REFꢀ
2309 F16a
Figure 16a. Top Silkscreen
2309fd
ꢁ0
LTC2309
AppLICAtIOns InFORMAtIOn
2309 F16b
Figure 16b. Layer 1 Component Side
2309 F16c
Figure 16c. Layer 2 Ground Plane
2309fd
ꢁꢀ
LTC2309
AppLICAtIOns InFORMAtIOn
2309 F16d
Figure 16d. Layer 3 Power Plane
2309 F16e
Figure 16e. Layer Back Solder Side
2309fd
ꢁꢁ
LTC2309
pACKAGe DesCRIptIOn
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(ReferenceꢀLTCꢀDWGꢀ#ꢀ05-08-1697)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05
0.200 REF
0.25 0.05
0.00 – 0.05
0.50 BSC
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2309fd
ꢁꢂ
LTC2309
pACKAGe DesCRIptIOn
F Package
20-Lead Plastic TSSOP (4.4mm)
(ReferenceꢀLTCꢀDWGꢀ#ꢀ05-08-1650)
6.40 – 6.60*
(.252 – .260)
1.05 0.10
4.50 0.10
20 19 18 17 16 15 14 13 12 11
6.60 0.10
6.40
(.252)
BSC
0.45 0.05
RECOMMENDED SOLDER PAD LAYOUT
0.65 BSC
5
7
8
1
2
3
4
6
9 10
1.10
(.0433)
MAX
4.30 – 4.50**
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
0.50 – 0.75
0.05 – 0.15
(.0035 – .0079)
(.020 – .030)
(.002 – .006)
0.19 – 0.30
(.0075 – .0118)
TYP
F20 TSSOP 0204
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
2309fd
ꢁꢃ
LTC2309
ReVIsIOn HIstORY (Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
7/10
RevisedꢀBlockꢀDiagram
1
2,ꢀ4-9,ꢀ20
5
ChangedꢀAV ꢀandꢀDV ꢀpinsꢀtoꢀV ꢀonly
DD
DD
DD
RevisedꢀNoteꢀ2
ConsolidatedꢀAV ꢀandꢀDV ꢀintoꢀV ꢀandꢀrevisedꢀV ꢀandꢀREFCOMPꢀpinꢀdescriptionsꢀinꢀPinꢀFunctionsꢀsection
7,ꢀ8
DD
DD
DD
REF
2
RevisedꢀFiguresꢀ6bꢀandꢀ6cꢀandꢀInternalꢀReferenceꢀparagraph,ꢀandꢀaddedꢀtextꢀtoꢀI CꢀInterfaceꢀinꢀApplicationsꢀ
Informationꢀsection
13,ꢀ14
ChangedꢀNAKꢀtoꢀNACKꢀinꢀFigureꢀ8a
RevisedꢀTypicalꢀApplication
15
26
2309fd
InformationꢀfurnishedꢀbyꢀLinearꢀTechnologyꢀCorporationꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable.ꢀ
However,ꢀnoꢀresponsibilityꢀisꢀassumedꢀforꢀitsꢀuse.ꢀLinearꢀTechnologyꢀCorporationꢀmakesꢀnoꢀrepresenta-
tionꢀthatꢀtheꢀinterconnectionꢀofꢀitsꢀcircuitsꢀasꢀdescribedꢀhereinꢀwillꢀnotꢀinfringeꢀonꢀexistingꢀpatentꢀrights.
ꢁꢄ
LTC2309
tYpICAL AppLICAtIOn
Driving the LTC2309 with 10V Input Signals Using a Precision Attenuator
5V
IN
OUT
1µF
0.1µF
LT1790-2.5
GND
10V
7
5V
450k
50k
8
9
150k
10µF
0.1µF
–
+
10
4pF
100Ω
47pF
450k
450k
V
AD1 AD0
6
CH0
1.7k 1.7k
DD
LT1991
1
2
3
LTC2309
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
450k
150k
50k
SCL
SDA
CONTROL
LOGIC
ANALOG
INPUT
MUX
10V
INPUT
SIGNAL
+
–
2
12-BIT
SAR ADC
I C
4pF
PORT
(FPGA, CPLD,
DSP, ETC)
4
5
–10V
INTERNAL
2.5V REF
V
REF
2.2µF
REFCOMP
GND
0.1µF
10µF
2309 TA02
ReLAteD pARts
PART NUMBER
LTC1417
DESCRIPTION
14-Bit,ꢀ400kspsꢀSerialꢀADC
COMMENTS
20mW,ꢀUnipolarꢀorꢀBipolar,ꢀInternalꢀReference,ꢀSSOP-16ꢀPackage
LowꢀInputꢀOffset:ꢀ75µV/125µV
LTC1468/LTC1469
Single/Dualꢀ90MHz,ꢀ22V/µs,ꢀ16-BitꢀAccurateꢀꢀ
OpꢀAmps
LTC1609
16-Bit,ꢀ200kspsꢀSerialꢀADC
65mW,ꢀConfigurableꢀBipolarꢀandꢀUnipolarꢀInputꢀRanges,ꢀ5VꢀSupply
60µAꢀSupplyꢀCurrent,ꢀ10ppm/°C,ꢀSOT-23ꢀPackage
LTC1790
MicropowerꢀLowꢀDropoutꢀReference
10-Bit/12-Bit,ꢀ8-Channel,ꢀ1.25MspsꢀADCs
10-Bit/12-Bit,ꢀ8-Channel,ꢀ400kspsꢀADCs
12-Bit,ꢀ1-/2-Channelꢀ250kspsꢀADCsꢀinꢀMSOP
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
ParallelꢀOutput,ꢀProgrammableꢀMUXꢀandꢀSequencer,ꢀ5VꢀSupply
ParallelꢀOutput,ꢀProgrammableꢀMUXꢀandꢀSequencer,ꢀ3Vꢀorꢀ5VꢀSupply
850µAꢀatꢀ250ksps,ꢀ2µAꢀatꢀ1ksps,ꢀSO-8ꢀandꢀMSOPꢀPackages
450µAꢀatꢀ150ksps,ꢀ10µAꢀatꢀ1ksps,ꢀSO-8ꢀandꢀMSOPꢀPackages
6.5mW,ꢀUnipolarꢀorꢀBipolar,ꢀInternalꢀReference,ꢀSSOP-16ꢀPackage
2mW,ꢀUnipolarꢀorꢀBipolar,ꢀInternalꢀReference,ꢀSSOP-16ꢀPackage
850µAꢀatꢀ250ksps,ꢀ2µAꢀatꢀ1ksps,ꢀSO-8ꢀandꢀMSOPꢀPackages
450µAꢀatꢀ150ksps,ꢀ10µAꢀatꢀ1ksps,ꢀSO-8ꢀandꢀMSOPꢀPackages
14mWꢀatꢀ500ksps,ꢀSingleꢀ5VꢀSupply,ꢀSoftwareꢀCompatibleꢀwithꢀLTC2308
LTC1860L/LTC1861L 3V,ꢀ12-bit,ꢀ1-/2-Channelꢀ150kspsꢀADCs
LTC1863/LTC1867 12-/16-Bit,ꢀ8-Channelꢀ200kspsꢀADCs
LTC1863L/LTC1867L 3V,ꢀ12-/16-bit,ꢀ8-Channelꢀ175kspsꢀADCs
LTC1864/LTC1865 16-Bit,ꢀ1-/2-Channelꢀ250kspsꢀADCsꢀinꢀMSOP
LTC1864L/LTC1865L 3V,ꢀ16-Bit,ꢀ1-/2-Channelꢀ150kspsꢀADCsꢀinꢀMSOP
LTC2302/LTC2306
12-Bit,ꢀ1-/2-Channelꢀ500kspsꢀSPIꢀADCsꢀinꢀꢀ
3mmꢀ×ꢀ3mmꢀDFN
LTC2308
12-Bit,ꢀ8-Channelꢀ500kspsꢀSPIꢀADC
5V,ꢀInternalꢀReference,ꢀ4mmꢀ×ꢀ4mmꢀQFNꢀPackage,ꢀSoftwareꢀCompatibleꢀwithꢀ
LTC2302/LTC2306
2
LTC2453
Easy-to-Use,ꢀUltratinyꢀ16-BitꢀI CꢀDeltaꢀSigmaꢀADC
2LSBꢀINL,ꢀ50nAꢀSleepꢀCurrent,ꢀ60HzꢀOutputꢀRate,ꢀ3mmꢀ×ꢀ2mmꢀDFNꢀPackage
2
LTC2487/LTC2489/ 2-/4-ChannelꢀEasyꢀDrive™ꢀI CꢀDeltaꢀSigmaꢀADCs
LTC2493
16-/24ꢀBits,ꢀPGAꢀandꢀTemperatureꢀSensor,ꢀ15HzꢀOutputꢀRate,ꢀ4mmꢀ×ꢀ3mmꢀ
DFNꢀPackages
2
LTC2495/LTC2497/ 8-/16-ChannelꢀEasyꢀDriveꢀI CꢀDeltaꢀSigmaꢀADCs
16-/24-Bits,ꢀPGAꢀandꢀTemperatureꢀSensor,ꢀ15HzꢀOutputꢀRate,ꢀ5mmꢀ×ꢀ7mmꢀ
QFNꢀPackages
LTC2499
2309fd
LT 0710 REV D • PRINTED IN USA
Linear Technology Corporation
1630ꢀ McCarthyꢀ Blvd.,ꢀ Milpitas,ꢀ CAꢀ 95035-7417
ꢀ
ꢁꢅ
●
●ꢀ
LINEAR TECHNOLOGY CORPORATION 2008
(408)ꢀ432-1900ꢀ ꢀFAX:ꢀ(408)ꢀ434-0507ꢀ www.linear.com
相关型号：
©2020 ICPDF网 联系我们和版权申明