LTC2320HUKG-14#PBF_技术文档

LTC2320-14

Octal, 14-Bit + Sign,

1.5Msps/Ch Simultaneous

Sampling ADC

FEATURES

DESCRIPTION

The LTC^®2320-14 is a low noise, high speed octal 14-bit

+ sign successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

Operating from a single 3.3V or 5V supply, the LTC2320-

n

1.5Msps/Ch Throughput Rate

n

Eight Simultaneously Sampling Channels

n

Guaranteed 14-Bit, No Missing Codes

n

8V Differential Inputs with Wide Input

P-P

Common Mode Range

14 has an 8V differential input range, making it ideal

P-P

n

81dB SNR (Typ) at f = 500kHz

for applications which require a wide dynamic range with

high common mode rejection. The LTC2320-14 achieves

1LSB INL typical, no missing codes at 14 bits and 81dB

SNR.

IN

–90dB THD (Typ) at f = 500kHz

Guaranteed Operation to 125°C

Single 3.3V or 5V Supply

Low Drift (20ppm/°C Max) 2.048V or 4.096V

Internal Reference

The LTC2320-14 has an onboard low drift (20ppm/°C

max) 2.048V or 4.096V temperature-compensated

reference. The LTC2320-14 also has a high speed SPI-

compatible serial interface that supports CMOS or LVDS.

The fast 1.5Msps per channel throughput with no latency

makes the LTC2320-14 ideally suited for a wide variety

of high speed applications. The LTC2320-14 dissipates

only 20mW per channel and offers nap and sleep modes

to reduce the power consumption to 26μW for further

power savings during inactive periods.

n

1.8V to 2.5V I/O Voltages

CMOS or LVDS SPI-Compatible Serial I/O

Power Dissipation 20mW/Ch (Typ)

Small 52-Lead (7mm × 8mm) QFN Package

APPLICATIONS

n

High Speed Data Acquisition Systems

n

Communications

n

Optical Networking

Multiphase Motor Control

All registered trademarks and trademarks are the property of their respective owners.

n

TYPICAL APPLICATION

10ꢀꢁ

1ꢀꢁ

1ꢀꢁꢂ ꢃꢄ 2ꢀꢅꢂ

3ꢀ3ꢁ ꢂꢃ ꢄꢁ

32k Point FFT f_SMPL= 1.5Msps,

f_IN= 500kHz

TRUE DIFFERENTIAL INPUTS

NO CONFIGURATION REQUIRED

ꢀ

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁ

ꢂꢂ

ꢀꢀ

ꢃ

ꢀ

ꢁꢂ1

ꢀꢁꢂ

CMOSꢀꢁꢂꢃꢄ

SDRꢀꢁꢁꢂ

ꢀꢁꢂꢃꢄꢂꢁꢅ

ꢀ

14ꢀꢁꢂꢃ

ꢄ ꢅꢂꢆꢇ

ꢅꢈꢉ ꢈꢊꢋ

+

–

ꢀꢁꢂ

IN , IN

0

ꢀ20

ꢃ

ꢀ

ꢀꢁꢂ ꢃ ꢄ1ꢅ1ꢆꢇ

ꢀꢁꢂ ꢃ ꢄꢅ0ꢆ2ꢇꢈ

ꢀꢁꢂꢃꢄ ꢅ ꢆ0ꢇꢆꢈꢉ

ꢀꢁꢂꢃ ꢄ ꢅ4ꢆꢇꢈꢉ

ꢁꢂ2

ꢀꢁꢂ

ꢃ

ꢀ

ꢁꢂ3

ꢀꢁꢂ

ꢀꢁꢂ1

ꢀꢁꢂ2

ꢀꢁꢂ3

ꢀꢁꢂ4

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ

14ꢀꢁꢂꢃ

ꢄ ꢅꢂꢆꢇ

ꢅꢈꢉ ꢈꢊꢋ

ꢀ40

ꢀꢁꢂ

ꢃ

ꢀ

ꢁꢂ4

ꢀꢁꢂ

0

ꢀꢁ0

ꢀꢁꢂ2320ꢃ14

ꢄ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂ

14ꢀꢁꢂꢃ

ꢄ ꢅꢂꢆꢇ

ꢅꢈꢉ ꢈꢊꢋ

ꢀꢁ0

ꢀꢁꢂ

ꢄ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂ

ꢀ100

ꢀ120

ꢀ140

CNV

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢀꢃ

ꢄ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂ

14ꢀꢁꢂꢃ

ꢄ ꢅꢂꢆꢇ

ꢅꢈꢉ ꢈꢊꢋ

ꢀꢁꢂ

ꢄ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂ

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ1 ꢀꢁꢂꢃꢄꢅ2 ꢀꢁꢂꢃꢄꢅ3 ꢀꢁꢂꢃꢄꢅ4

232014 ꢀꢁ01a

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

232014 ꢀꢁ01ꢂ

ꢀꢁꢂꢃꢄ ꢅꢁꢆꢇꢈꢄꢉꢊꢀꢋꢇꢅ

ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢁꢆꢆꢊꢄꢀ

1ꢀꢁ

10ꢀꢁ

232014fa

1

For more information www.linear.com/LTC2320-14

LTC2320-14

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

ꢅꢆꢇ ꢈꢉꢊꢋ

Supply Voltage (V )..................................................6V

DD

Supply Voltage (OV )................................................3V

DD

Analog Input Voltage

ꢁ2 ꢁ1 ꢁ0 4ꢄ 4ꢃ 4ꢂ 4ꢀ 4ꢁ 44 43 42 41

ꢛ

ꢜ

+

–

ꢑ

1

2

40 ꢘꢎꢆꢃꢞꢘꢎꢆꢎ

3ꢄ ꢘꢎꢆꢂꢞꢘꢎꢆꢎ

ꢉꢍꢀ

A

, A (Note 3) ................... –0.3V to (V + 0.3V)

IN

IN DD

ꢜ

ꢉꢍꢀ

REFOUT1,2,3,4........................ .–0.3V to (V + 0.3V)

DD

ꢌꢍꢎ

ꢛ

ꢌꢍꢎ

ꢆꢈ

3

3ꢃ

3ꢂ

CNV........................................ –0.3V to (OV + 0.3V)

ꢑ

4

ꢉꢍꢁ

ꢎꢎ

ꢜ

ꢛ

ꢜ

ꢑ

ꢉꢍꢁ

ꢁ

3ꢀ ꢘꢎꢆꢀꢞꢘꢎꢆꢒ

ꢘꢎꢆꢁꢞꢘꢎꢆꢒ

3ꢁ

Digital Input Voltage

ꢝꢊꢚꢆꢏꢅ3

ꢌꢍꢎ

ꢀ

(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)

ꢛ

DD

ꢂ

34 CꢀꢁOꢂꢃꢄNꢞꢒꢔꢐꢆꢏꢅ

ꢁ3

ꢌꢍꢎ

ꢜ

Digital Output Voltage

ꢝꢊꢚ

ꢃ

33 ꢒꢔꢐꢆꢏꢅꢞꢒꢔꢐꢆꢏꢅ

ꢝꢊꢚꢆꢏꢅ2

ꢛ

ꢄ

32 ꢌꢍꢎ

(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)

DD

ꢑ

10

11

31 ꢆꢈ

ꢎꢎ

ꢉꢍ4

Operating Temperature Range

ꢜ

ꢛ

ꢜ

ꢛ

ꢜ

30 ꢘꢎꢆ4ꢞꢘꢎꢆꢟ

2ꢄ ꢘꢎꢆ3ꢞꢘꢎꢆꢟ

2ꢃ ꢘꢎꢆ2ꢞꢘꢎꢆꢑ

2ꢂ ꢘꢎꢆ1ꢞꢘꢎꢆꢑ

ꢉꢍ4

LTC2320C................................................ 0°C to 70°C

LTC2320I .............................................–40°C to 85°C

LTC2320H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

ꢌꢍꢎ 12

ꢛ

ꢑ

13

14

ꢉꢍ3

ꢜ

ꢑ

ꢉꢍ3

1ꢁ 1ꢀ 1ꢂ 1ꢃ 1ꢄ 20 21 22 23 24 2ꢁ 2ꢀ

ꢏꢐꢌ ꢇꢑꢒꢐꢑꢌꢊ

ꢁ2ꢓꢔꢊꢑꢎ ꢕꢂꢖꢖ × ꢃꢖꢖꢗ ꢇꢔꢑꢘꢅꢉꢒ ꢙꢚꢍ

T

= 150°C, θ = 31°C/W

JA

JMAX

EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC2320-14#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LTC2320UKG-14

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2320CUKG-14#PBF

LTC2320IUKG-14#PBF

LTC2320HUKG-14#PBF

LTC2320CUKG-14#TRPBF

LTC2320IUKG-14#TRPBF

LTC2320HUKG-14#TRPBF

52-Lead (7mm × 8mm) Plastic QFN

–40°C to 85°C

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

232014fa

2

For more information www.linear.com/LTC2320-14

LTC2320-14

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

+

–

l

V

Absolute Input Range (A to A

)

(Note 5)

0

V

DD

V

DD

IN

–

+

Absolute Input Range (A to A

(Note 5)

0

V

IN

–

+

–

– V

Input Differential Voltage Range

Common Mode Input Range

V

= V – V

–REFOUT1,2,3,4

REFOUT1,2,3,4

V

IN

+

–

= (V – V )/2

0

V

DD

V

CM

IN

I

IN

Analog Input DC Leakage Current

Analog Input Capacitance

–1

1

μA

pF

dB

V

C

IN

10

CMRR

Input Common Mode Rejection Ratio

CNV High Level Input Voltage

CNV Low Level Input Voltage

CNV Input Current

f

IN

= 500kHz

102

l

V

1.5

IHCNV

ILCNV

INCNV

0.5

10

V

I

–10

μA

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

MIN

14

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

14

Bits

Transition Noise

0.8

1

LSB

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

Bipolar Zero-Scale Error

Bipolar Zero-Scale Error Drift

Bipolar Full-Scale Error

Bipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–3

–0.99

–3

3

0.99

3

LSB

DNL

BZE

0.4

0

LSB

0.005

0

LSB/°C

LSB

l

FSE

V

= 4.096V (REFBUFEN Grounded) (Note 7)

= 4.096V (REFBUFEN Grounded)

–8

8

REFOUT1,2,3,4

15

ppm/°C

REFOUT1,2,3,4

232014fa

3

For more information www.linear.com/LTC2320-14

LTC2320-14

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS (Notes 4, 8).

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

80

MAX

UNITS

dB

l

SINAD

Signal-to-(Noise + Distortion) Ratio f = 500kHz, V

= 4.096V, Internal Reference

= 5V, External Reference

= 4.096V, Internal Reference

= 5V, External Reference

= 4.096V, Internal Reference

= 5V, External Reference

= 4.096V, Internal Reference

= 5V, External Reference

75.5

IN

REFOUT1,2,3,4

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

= 500kHz, V

84

dB

SNR

Signal-to-Noise Ratio

76.5

77

81

dB

82.5

–90

–91

93

dB

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

–77

dB

SFDR

dB

93

dB

–3dB Input Bandwidth

Aperture Delay

55

MHz

ps

500

1

Aperture Delay Matching

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

3

ns

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Internal Reference Output Voltage

4.75V < V < 5.25V

4.078

2.034

4.096

2.048

4.115

2.064

V

REFOUT1,2,3,4

DD

3.13V < V < 3.47V

DD

l

V

Temperature Coefficient

(Note 14)

3

20

ppm/°C

Ω

REF

REFOUT1,2,3,4 Output Impedance

Line Regulation

0.25

0.3

V

4.75V < V < 5.25V

mV/V

REFOUT1,2,3,4

DD

I

External Reference Current

REFBUFEN = 0V

REFOUT1,2,3,4

REFOUT1,2,3,4 = 4.096V

REFOUT1,2,3,4 = 2.048V

(Notes 9, 10)

385

204

μA

232014fa

4

For more information www.linear.com/LTC2320-14

LTC2320-14

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

CMOS/LVDS = GND

MIN

0.8 • OV

–10

TYP

MAX

UNITS

CMOS Digital Inputs and Outputs

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

IH

IL

DD

0.2 • OV

10

DD

I

V

IN

= 0V to OV

DD

μA

pF

IN

C

IN

Digital Input Capacitance

5

l

V

High Level Output Voltage

Low Level Output Voltage

I = –500μA

OV – 0.2

V

OH

OL

O

DD

I = 500μA

O

0.2

10

l

I

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

V

OUT

V

OUT

V

OUT

= 0V to OV

DD

–10

μA

mA

OZ

= 0V

= OV

–10

10

SOURCE

SINK

DD

LVDS Digital Inputs and Outputs

CMOS/LVDS = OV

DD

l

V

LVDS Differential Input Voltage

LVDS Common Mode Input Voltage

LVDS Differential Output Voltage

LVDS Common Mode Output Voltage

100Ω Differential Termination

DD

240

1

600

1.45

600

1.4

mV

V

ID

OV = 2.5V

100Ω Differential Termination

OV = 2.5V

DD

IS

100Ω Differential Termination

OV = 2.5V

DD

220

0.85

100

0.85

350

1.2

200

1.2

mV

V

OD

100Ω Differential Termination

OV = 2.5V

DD

OS

Low Power LVDS Differential Output Voltage 100Ω Differential Termination

350

1.4

mV

V

OD_LP

OS_LP

OV = 2.5V

DD

Low Power LVDS Common Mode Output Voltage 100Ω Differential Termination

OV = 2.5V

DD

232014fa

5

For more information www.linear.com/LTC2320-14

LTC2320-14

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

5V Operation

3.3V Operation

4.75

3.13

5.25

3.47

V

DD

+

–

l

IV

DD

Supply Current

1.5Msps Sample Rate (IN = IN = 0V)

31

38

mA

CMOS I/O Mode

CMOS/LVDS = GND

Supply Voltage

l

OV

1.71

2.63

7.0

V

mA

µA

DD

OVDD

NAP

I

Supply Current

1.5Msps Sample Rate (C = 5pF)

4.4

5.3

20

L

Nap Mode Current

Sleep Mode Current

Power Dissipation

Conversion Done (I

)

6.2

VDD

Sleep Mode (I

+ I )

OVDD

110

SLEEP

VDD

l

P

V

= 3.3V, 1.5Msps Sample Rate

DD

102

18

20

130

20.6

355

mW

µW

D_3.3V

Nap Mode

Sleep Mode

l

P

D_5V

Power Dissipation

V

= 5V, 1.5Msps Sample Rate

162

27

30

208

31.2

525

mW

µW

DD

Nap Mode

Sleep Mode

LVDS I/O Mode

CMOS/LVDS = OV , OV = 2.5V

DD DD

l

OV

Supply Voltage

Supply Current

2.37

2.63

34

V

mA

µA

DD

OVDD

NAP

I

1.5Msps Sample Rate (C = 5pF, R = 100Ω)

26

5.3

20

L

Nap Mode Current

Sleep Mode Current

Power Dissipation

Conversion Done (I

)

6.2

VDD

Sleep Mode (I

+ I )

OVDD

110

SLEEP

VDD

l

P

V

= 3.3V, 1.5Msps Sample Rate

DD

151

52

80

195

58

355

mW

µW

D_3.3V

Nap Mode

Sleep Mode

l

P

D_5V

Power Dissipation

V

= 5V, 1.5Msps Sample Rate

214

60

30

280

68.5

525

mW

µW

DD

Nap Mode

Sleep Mode

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

0.667

30

TYP

MAX

1.5

UNITS

Msps

µs

l

f

t

Maximum Sampling Frequency

Time Between Conversions

Conversion Time

SMPL

(Note 11) t

= t

+ t

READOUT

1000

450

CYC

CNVH

CONV

ns

CONV

CNV High Time

ns

CNVH

Sampling Aperture

(Note 11) t

= t

– t

CONV

215

50

ns

ACQUISITION

WAKE

ACQUISITION

CYC

REFOUT1,2,3,4 Wake-Up Time

C

= 10µF

ms

REFOUT1,2,3,4

CMOS I/O Mode, SDR

CMOS/LVDS = GND, SDR/ DDR = GND

l

t

SCK Period

(Note 13)

9.1

4.1

0

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4.5

HSDO_SDR

DSCKCLKOUT

L

SCK to CLKOUT Delay

(Note 12)

2

232014fa

6

For more information www.linear.com/LTC2320-14

LTC2320-14

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

(Note 11)

MIN

TYP

MAX

UNITS

ns

l

t

Bus Relinquish Time After CNV↑

SDO Valid Delay from CNV↓

SCK Delay Time to CNV↑

3

DCNVSDOZ

DCNVSDOV

DSCKHCNVH

ns

0

ns

CMOS I/O Mode, DDR

CMOS/LVDS = GND, SDR/ DDR = OV

DD

l

t

SCK Period

18.2

8.2

0

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4.5

3

HSDO_DDR

DSCKCLKOUT

DCNVSDOZ

DCNVSDOV

DSCKHCNVH

L

SCK to CLKOUT Delay

(Note 12)

(Note 11)

2

Bus Relinquish Time After CNV↑

SDO Valid Delay from CNV↓

SCK Delay Time to CNV↑

3

0

LVDS I/O Mode, SDR

CMOS/LVDS = OV , SDR/DDR = GND

DD

l

t

SCK Period

3.3

1.5

0

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4

HSDO_SDR

DSCKCLKOUT

DSCKHCNVH

L

SCK to CLKOUT Delay

(Note 12)

(Note 11)

2

SCK Delay Time to CNV↑

0

LVDS I/O Mode, DDR

CMOS/LVDS = OV , SDR/DDR = OV = 2.5V

DD DD

l

t

SCK Period

6.6

3

ns

SCK

SCK High Time

SCK Low Time

SCKH

3

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF

0

1.5

4

HSDO_DDR

DSCKCLKOUT

DSCKHCNVH

L

SCK to CLKOUT Delay

2

SCK Delay Time to CNV↑

(Note 11)

0

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale 4.096V input

with REF = 4.096V.

Note 2: All voltage values are with respect to ground.

Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer

Note 3: When these pin voltages are taken below ground, or above V or

must be turned off by setting REFBUFEN = 0V.

DD

OV , they will be clamped by internal diodes. This product can handle input

DD

Note 10: f

= 1.5MHz, I

varies proportionally with sample rate.

SMPL

REFOUT1,2,3,4

currents up to 100mA below ground, or above V or OV , without latch-up.

DD

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V.

Note 13: t

rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OV

logic levels.

Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.096V, f = 1.5MHz.

SMPL

DD

Note 5: Recommended operating conditions.

of 9.1ns allows a shift clock frequency up to 105MHz for

SCK

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 000 0000 0000 0000 and 111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

DD

232014fa

7

For more information www.linear.com/LTC2320-14

LTC2320-14

ADC TIMING CHARACTERISTICS

0ꢀꢁ ꢂ ꢃꢄ

ꢅꢅ

ꢉ

ꢎꢏꢅꢐꢑ

0ꢀ2 ꢂ ꢃꢄ

ꢅꢅ

ꢆ0ꢇ

ꢉ

ꢅꢊꢋꢌꢍ

232014 ꢈ01

0ꢀꢁ ꢂ ꢃꢄ

0ꢀ2 ꢂ ꢃꢄ

ꢅꢅ

0ꢀ2 ꢂ ꢃꢄ

Figure 1. Voltage Levels for Timing Specifications

232014fa

8

For more information www.linear.com/LTC2320-14

LTC2320-14

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT1,2,3,4

= 4.096V, f_SMPL= 1.5Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

30

2ꢀ0

1ꢀꢁ

1ꢀ0

0ꢀꢁ

σ ꢀ 0ꢁꢂ2

2ꢀ

24

21

1ꢀ

12

ꢀ

1ꢀ0

0ꢀꢁ

0

ꢀ0ꢁꢂ

ꢀ1ꢁ0

ꢀ1ꢁꢂ

ꢀ2ꢁ0

ꢀ0ꢁꢂ

ꢀ

3

0

ꢀ1ꢁ0

ꢀ3

ꢀ2

ꢀ1

0

1

2

3

ꢀ1ꢁ3ꢂ4

ꢀꢁ1ꢂ2

0

ꢀ1ꢁ2

1ꢀ3ꢁ4

ꢀ1ꢁ3ꢂ4

ꢀꢁ1ꢂ2

0

ꢀ1ꢁ2

1ꢀ3ꢁ4

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ

232014 ꢀ03

232014 ꢀ01

232014 ꢀ02

THD, Harmonics vs Input

32k Point FFT, f_SMPL= 1.5Msps,

f_IN= 500kHz

SNR, SINAD vs Input Frequency

(1kHz to 750kHz)

Frequency (1kHz to 750kHz)

ꢀ2ꢁ0

ꢀ1ꢁꢀ

ꢀ1ꢁꢂ

ꢀ1ꢁ4

ꢀ1ꢁ2

ꢀ1ꢁ0

ꢀ0ꢁꢀ

ꢀ0ꢁꢂ

ꢀ0ꢁ4

ꢀ0ꢁ2

ꢀ0ꢁ0

ꢀꢁ0

ꢀꢁ4

0

ꢀ20

ꢀꢁꢂ ꢃ ꢄ1ꢅ1ꢆꢇ

ꢀꢁꢂ ꢃ ꢄꢅ0ꢆ2ꢇꢈ

ꢀꢁꢂꢃꢄ ꢅ ꢆ0ꢇꢆꢈꢉ

ꢀꢁꢂꢃ ꢄ ꢅ4ꢆꢇꢈꢉ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ40

ꢀꢁ2

ꢀꢁꢂ

ꢀꢁ0

ꢀ100

ꢀ104

ꢀ10ꢁ

ꢀ112

ꢀ11ꢁ

ꢀ120

ꢀꢁꢂꢃꢄ

ꢀꢁ3

ꢀꢁ0

ꢀꢁ2

ꢀ100

ꢀ120

ꢀ140

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

232014 ꢀ0ꢁ

232014 ꢀ04

THD, Harmonics vs Input Common

Mode

SNR, SINAD vs Reference Voltage,

f_IN= 500kHz

32k Point FFT, IMD, f_SMPL=1.5Msps,

A_IN⁺= 490kHz, A_IN^–= 510kHz

ꢀ3

ꢀ2

ꢀ1

ꢀ0

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ4

ꢀ3

ꢀ2

ꢀ1

ꢀ0

ꢀꢁ

0

ꢀ20

ꢀꢁ0

ꢀꢁ4

ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ

f

ꢀ ꢁ00ꢂꢃꢄ

f

ꢀ ꢁ00ꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀ 20ꢁꢂꢃꢄ 4ꢅ

ꢀꢁ

ꢆꢇꢆ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ40

ꢀꢁ2

ꢀꢁꢂ

ꢀꢁ0

ꢀ100

ꢀ104

ꢀ10ꢁ

ꢀ112

ꢀ11ꢁ

ꢀ120

ꢀꢁ2

ꢀꢁ3

ꢀꢁ0

ꢀ100

ꢀ120

ꢀ140

0ꢀꢁ

1

1ꢀꢁ

2

2ꢀꢁ

3

3ꢀꢁ

4

4ꢀꢁ

ꢀ

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

1ꢀꢁ 1ꢀꢁ 1ꢀꢁ 2ꢀ1 2ꢀ3 2ꢀꢁ 2ꢀꢁ 2ꢀꢁ 3ꢀ1 3ꢀ3

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢇꢆꢁ ꢇꢆꢈꢉ ꢊꢋꢌ

232014 ꢀ0ꢁ

232014fa

9

For more information www.linear.com/LTC2320-14

LTC2320-14

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT1,2,3,4

= 4.096V, f_SMPL= 1.5Msps, unless otherwise noted.

Step Response

(Large Signal Settling)

1ꢀ3ꢁ4

CMRR vs Input Frequency

Crosstalk vs Input Frequency

120

11ꢀ

110

10ꢀ

100

ꢀꢁ

ꢀꢁ0

ꢀꢁ1

ꢀꢁ2

ꢀꢁ3

ꢀꢁ4

ꢀꢁꢂ

ꢀꢁꢁ

ꢀ100

ꢀ

ꢀ 4ꢁ

ꢂꢃꢂ

ꢀꢁ

122ꢀꢀ

ꢀ1ꢁ2

4ꢀ0ꢁꢂꢃ ꢄꢅꢆꢇꢈ

40ꢀꢁ

0

ꢀꢁꢂ ꢃ 1ꢄꢅꢆꢇꢈ ꢉꢊꢋꢌꢍꢎ ꢏꢌꢐꢎ

ꢀꢁꢂ ꢃ 0ꢄ

ꢀ0

ꢀ40ꢁꢂ

0

ꢀ00

1000

1ꢀ00

ꢀ20 ꢀ10

0

10 20 30 40 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0

0

100 200 300 400 ꢀ00 ꢀ00 ꢀ00

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

ꢀꢁꢂꢂꢃꢄꢅꢆ ꢂꢄꢇꢁ ꢈꢉꢊꢋ

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

232014 ꢀ10

232014 ꢀ12

232014 ꢀ11

Step Response

(Fine Settling)

External Reference Supply

Current vs Sample Frequency

REF Output vs Temperature

400

3ꢀ0

300

2ꢀ0

200

1ꢀ0

100

ꢀ0

1ꢀ0

0ꢀꢁ

12ꢀ

100

ꢀꢁ

ꢀꢁꢂꢃꢄꢂꢁꢅ ꢆ 0ꢇ

ꢀꢁꢂꢃ ꢄꢁꢅ ꢆꢇꢅ

ꢀ

ꢀ 3ꢁ3ꢂ

ꢀꢀ

ꢀꢁꢂꢃꢄꢃꢅꢁꢅꢆꢇ ꢃꢂꢈ ꢉꢊꢈꢋ

0

ꢀ0

ꢀ0ꢁꢂ

ꢀ1ꢁ0

ꢀ1ꢁꢂ

ꢀ2ꢁ0

ꢀ2ꢁꢂ

ꢀ3ꢁ0

2ꢀ

ꢀ

ꢀ 4ꢁ0ꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅ1ꢆ2ꢆ3ꢆ4

0

ꢀ

ꢀ ꢁꢂ

ꢀꢀ

ꢀ2ꢁ

ꢀꢁ0

ꢀꢁꢂ

ꢀ100

ꢀ12ꢁ

4ꢀ0ꢁꢂꢃ ꢄꢅꢆꢇꢈ

ꢀꢁꢂ ꢃ 1ꢄꢅꢆꢇꢈ

ꢉꢊꢋꢌꢍꢎ ꢏꢌꢐꢎ

ꢀ

ꢀ 2ꢁ04ꢂꢃ

ꢀꢁꢂꢃꢄꢅ1ꢆ2ꢆ3ꢆ4

ꢀꢁꢂ ꢃ 0ꢄ

0

0ꢀ3

0ꢀꢁ

1ꢀ2

1ꢀꢁ

ꢀꢁꢁ ꢀ3ꢁ ꢀ1ꢁ

ꢀ

2ꢀ 4ꢀ ꢀꢁ ꢀꢁ 10ꢀ 12ꢀ

ꢀ20 ꢀ10

0

10 20 30 40 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈꢉꢅꢊꢋꢌ ꢍꢂꢎꢏꢎꢐ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

ꢀꢁꢂꢂꢃꢄꢅꢆ ꢂꢄꢇꢁ ꢈꢉꢊꢋ

232014 ꢀ14

232014 ꢀ1ꢁ

232014 ꢀ13

Supply Current

vs Sample Frequency

OV_DDCurrent vs SCK Frequency,

C_LOAD= 10pF

Offset Error vs Temperature

33

31

2ꢀ

23

21

1ꢀ

1ꢀꢁ

1

ꢀ

4

3

2

1

0

32

ꢀꢁꢂꢂ ꢃꢄꢅꢂꢆ ꢃꢇꢈꢁꢃꢉꢇꢊꢅꢂ ꢇꢈꢋꢁꢌ

30

ꢀꢁꢂꢃ ꢄ4 ꢀꢅꢆꢇꢃꢈ 2ꢀ

2ꢀ

24

22

20

1ꢀ

14

12

0ꢀꢁ

0

ꢀꢁꢂꢃ ꢄ2ꢅꢆ ꢈ ꢉ ꢊꢋꢌꢍꢃꢎ

ꢀꢁꢂꢃꢄ1ꢅꢆ ꢈ ꢆ ꢉꢊꢋꢌꢃꢍ

ꢀ

ꢀ ꢁꢂ

ꢀꢀ

ꢀ

ꢀ 3ꢁ3ꢂ

ꢀꢀ

ꢀ0ꢁꢂ

ꢀ1

ꢀꢁꢂ ꢃꢁꢂꢄꢅ ꢀꢆꢇꢈ ꢉ4 ꢀꢊꢋꢄꢈꢌ

ꢀ1ꢁꢂ

0

0ꢀ3

0ꢀꢁ

1ꢀ2

1ꢀꢁ

ꢀꢁꢁ ꢀ3ꢁ ꢀ1ꢁ

ꢀ

2ꢀ 4ꢀ ꢀꢁ ꢀꢁ 10ꢀ 12ꢀ

0

ꢀ0

100

1ꢀ0

200

2ꢀ0

300

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈꢉꢅꢊꢋꢌ ꢍꢂꢎꢏꢎꢐ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

ꢀꢁꢂ ꢃꢄꢅꢆꢇꢅꢈꢁꢉ ꢊꢋꢌꢍꢎ

232014 ꢀ1ꢁ

232014fa

10

For more information www.linear.com/LTC2320-14

LTC2320-14

PIN FUNCTIONS

Pins that are the same for all digital I/O modes.

V (Pins 15, 21, 44, 52): Power Supply. Bypass V to

DD DD

GND with a 10µF ceramic capacitor and a 0.1µF ceramic

capacitor close to the part. The V_DDpins should be shorted

together and driven from the same supply.

+

–

A

, A

(Pins 2, 1): Analog Differential Input Pins.

IN6

Full-scale range (A_IN6– A_IN6^–) is REFOUT3 voltage.

These pins can be driven from V to GND.

+

DD

A_IN2⁺, A_IN2^–(Pins 17, 16): Analog Differential Input Pins.

GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.

These pins and exposed pad (Pin 53) must be tied directly

to a solid ground plane.

+

Full-scale range (A_IN2– A_IN2^–) is REFOUT1 voltage.

These pins can be driven from V to GND.

DD

A_IN1⁺, A_IN1^–(Pins 20, 19): Analog Differential Input Pins.

+

–

A

, A

(Pins 5, 4): Analog Differential Input Pins.

IN5

+

Full-scale range (A_IN1– A_IN1^–) is REFOUT1 voltage.

Full-scale range (A_IN5– A_IN5^–) is REFOUT3 voltage.

+

These pins can be driven from V to GND.

DD

These pins can be driven from V to GND.

DD

REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

SDR/DDR (Pin 23): Double Data Rate Input. Controls the

frequency of SCK and CLKOUT. Tie to GND for the falling

edge of SCK to shift each serial data output (Single Data

Rate, SDR). Tie to OV to shift serial data output on each

edge of SCK (Double^DD^Data Rate, DDR). CLKOUT will be a

delayed version of SCK for both pin states.

REF (Pin 8): Common 4.096V reference output. Decouple

to GND with a 1μF low ESR ceramic capacitor. May be

overdriven with a single external reference to establish a

common reference for ADC cores 1 through 4.

REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

CNV (Pin 24): Convert Input. This pin, when high, defines

the acquisition phase. When this pin is driven low, the

conversion phase is initiated and output data is clocked

out. This input must be driven at OV levels with a low

DD

jitter pulse. This pin is unaffected by the CMOS/LVDS pin.

CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin

A_IN4⁺, A_IN4^–(Pins 11, 10): Analog Differential Input Pins.

to enable CMOS mode, tie to OV to enable LVDS mode.

+

Full-scale range (A_IN4– A_IN4^–) is REFOUT2 voltage.

DD

Float this pin to enable low power LVDS mode.

These pins can be driven from V to GND.

DD

OV_DD(Pins 31, 37): I/O Interface Digital Power. The range

A_IN3⁺, A_IN3^–(Pins 14, 13): Analog Differential Input Pins.

of OV is 1.71V to 2.63V. This supply is nominally set

+

Full-scale range (A_IN3– A_IN3^–) is REFOUT2 voltage.

DD

to the same supply as the host interface (CMOS: 1.8V or

These pins can be driven from V to GND.

DD

2.5V, LVDS: 2.5V). Bypass OV to GND (Pins 32 and 38)

DD

with 0.1µF capacitors.

232014fa

11

For more information www.linear.com/LTC2320-14

LTC2320-14

PIN FUNCTIONS

REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie

SDO3 (Pin 29): CMOS Serial Data Output for ADC Channel

3. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

to V when using the internal reference. Tie to ground

DD

to disable the internal REFOUT1–4 buffers for use with

external voltage references. This pin has a 500k internal

pull-up to V .

data to be read from A on SDO3 in SDR mode, 16 SCK

DD

IN3

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH4, CH5, CH6, CH7, CH8,

CH1, CH2).

REFOUT4 (Pin 45): Reference Buffer 4 Output. An

onboard buffer nominally outputs 4.096V to this pin. This

pin is referred to GND and should be decoupled closely to

the pin with a 10µF (X5R, 0805 size) ceramic capacitor.

The internal buffer driving this pin may be disabled by

grounding the REFBUFEN pin. If the buffer is disabled,

an external reference may drive this pin in the range of

1.25V to 5V.

SDO4 (Pin 30): CMOS Serial Data Output for ADC Channel

4. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

data to be read from A on SDO4 in SDR mode, 16 SCK

IN4

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH5, CH6, CH7, CH8, CH1,

CH2, CH3).

A_IN8⁺, A_IN8^–(Pins 48, 47): Analog Differential Input Pins.

+

Full-scale range (A_IN8– A_IN8^–) is REFOUT4 voltage.

These pins can be driven from V to GND.

DD

CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT pro-

A_IN7⁺, A_IN7^–(Pins 51, 50): Analog Differential Input Pins.

vides a skew-matched clock to latch the SDO output at the

+

Full-scale range (A_IN7– A_IN7^–) is REFOUT4 voltage.

receiver (FPGA). The logic level is determined by OV .

DD

These pins can be driven from V to GND.

DD

This pin echoes the input at SCK with a small delay.

Exposed Pad (Pin 53): Ground. Solder this pad to ground.

CLKOUTEN (Pin 34): CLKOUT can be disabled by tying

Pin 34 to OV for a small power savings. If CLKOUT is

DD

CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)

used, ground this pin.

SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel

1. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

SDO5 (Pin 35): CMOS Serial Data Output for ADC Channel

5. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

data to be read from A on SDO1 in SDR mode, 16 SCK

IN1

data to be read from A on SDO5 in SDR mode, 16 SCK

IN5

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH2, CH3, CH4, CH5, CH6,

CH7, CH8).

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH6, CH7, CH8, CH1, CH2,

CH3, CH4).

SDO2 (Pin 28): CMOS Serial Data Output for ADC Channel

2. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

SDO6 (Pin 36): CMOS Serial Data Output for ADC Channel

6. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

data to be read from A on SDO2 in SDR mode, 16 SCK

IN2

data to be read from A on SDO6 in SDR mode, 16 SCK

IN6

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH3, CH4, CH5, CH6, CH7,

CH8, CH1).

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH7, CH8, CH1, CH2, CH3,

CH4, CH5).

232014fa

12

For more information www.linear.com/LTC2320-14

LTC2320-14

PIN FUNCTIONS

SDO7 (Pin 39): CMOS Serial Data Output for ADC Channel

7. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

mode and each SCK edge in DDR mode. 32 SCK edges

are required for 14-bit conversion data to be read from

A

and A on SDOB in SDR mode, 16 SCK edges in

IN3

IN4

DDR mode. Supplying more clocks will yield data from

subsequent channels (CH5, CH6, CH7, CH8, CH1, CH2).

Terminate with a 100Ω resistor at the receiver (FPGA).

CLKOUT⁺, CLKOUT^–(Pins 33, 34): Serial Data Clock

Output. CLKOUT provides a skew-matched clock to latch

the SDO output at the receiver. These pins echo the input

at SCK with a small delay. These pins must be differ-

entially terminated by an external 100Ω resistor at the

receiver (FPGA).

data to be read from A on SDO7 in SDR mode, 16 SCK

IN7

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH8, CH1, CH2, CH3, CH4,

CH5, CH6).

SDO8 (Pin 40): CMOS Serial Data Output for ADC Channel

8. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 14-bit conversion

data to be read from A on SDO8 in SDR mode, 16 SCK

+

–

IN8

SDOC , SDOC (Pins 35, 36): LVDS Serial Data Output

for ADC channels 5 and 6. The conversion result is

shifted CH5 MSB first on each falling edge of SCK in SDR

mode and each SCK edge in DDR mode. 32 SCK edges

are required for 14-bit conversion data to be read from

edges in DDR mode. Supplying more clocks will yield data

from subsequent channels (CH1, CH2, CH3, CH4, CH5,

CH6, CH7).

SCK (Pin 41): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins in SDR mode (DDR = LOW). In DDR mode

(SDR/DDR = HIGH) each edge of this clock shifts the

conversion result MSB first onto the SDO pins. The logic

A

and A on SDOA in SDR mode, 16 SCK edges in

IN5

IN6

DDR mode. Supplying more clocks will yield data from

subsequent channels (CH7, CH8, CH1, CH2, CH3, CH4).

Terminate with a 100Ω resistor at the receiver (FPGA).

level is determined by OV .

+

–

DD

SDOD , SDOD (Pins 39, 40): LVDS Serial Data Output

for ADC Channels 7 and 8. The conversion result is

shifted CH7 MSB first on each falling edge of SCK in SDR

mode and each SCK edge in DDR mode. 32 SCK edges

are required for 14-bit conversion data to be read from

DNC (Pin 42): In CMOS mode do not connect this pin.

LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR

FLOAT)

A

and A on SDOA in SDR mode, 16 SCK edges in

IN7

IN8

+

–

SDOA , SDOA (Pins 27, 28): LVDS Serial Data Output

for ADC Channels 1 and 2. The conversion result is

shifted CH1 MSB first on each falling edge of SCK in SDR

mode and each SCK edge in DDR mode. 32 SCK edges

are required for 14-bit conversion data to be read from

DDR mode. Supplying more clocks will yield data from

subsequent channels (CH1, CH2, CH3, CH4, CH5, CH6).

Terminate with a 100Ω resistor at the receiver (FPGA).

+

–

SCK , SCK (Pins 41, 42): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

first onto the SDO pins in SDR mode (SDR/DDR = LOW).

In DDR mode (SDR/DDR = HIGH) each edge of this clock

shifts the conversion result MSB first onto the SDO pins.

These pins must be differentially terminated by an external

100Ω resistor at the receiver (ADC).

A

and A on SDOA in SDR mode, 16 SCK edges in

IN1

IN2

DDR mode. Supplying more clocks will yield data from

subsequent channels (CH3, CH4, CH5, CH6, CH7, CH8).

Terminate with a 100Ω resistor at the receiver (FPGA).

+

–

SDOB , SDOB (Pins 29, 30): LVDS Serial Data Output

for ADC Channels 3 and 4. The conversion result is

shifted CH3 MSB first on each falling edge of SCK in SDR

232014fa

13

For more information www.linear.com/LTC2320-14

LTC2320-14

FUNCTIONAL BLOCK DIAGRAM

CMOS IO Mode

V

GND

DD

24

CNV

(15, 21, 44, 52)

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

+

–

A

IN1

+

–

20

19

S/H

IN1

SDO1

SDO2

27

28

CMOS

I/O

14-BIT+ SIGN

SAR ADC

+

–

MUX

A

IN2

+

17

16

S/H

IN2

–

REFOUT1

×1

REF

22

+

–

A

IN3

+

–

14

13

S/H

IN3

SDO3

SDO4

29

30

CMOS

I/O

14-BIT+ SIGN

SAR ADC

MUX

+

–

A

IN4

+

11

10

S/H

IN4

–

REFOUT2

×1

REF

9

CLKOUT

SCK

41

42

33

34

CMOS

RECEIVERS

OUTPUT

CLOCK DRIVER

DNC

CꢀꢁOꢂꢃꢄN

+

SDR/DDR

23

A

IN5

+

5

4

–

S/H

–

IN5

SDO6

35

36

CMOS

I/O

14-BIT+ SIGN

SAR ADC

+

–

MUX

A

IN6

+

2

1

S/H

IN6

–

REFOUT3

×1

REF

6

+

–

A

IN7

+

51

50

S/H

–

IN7

SDO7

SDO8

39

40

CMOS

I/O

14-BIT+ SIGN

SAR ADC

MUX

+

–

A

IN8

+

48

47

S/H

IN8

–

REFOUT4

×1

REF

45

250μA

OV (31, 37)

DD

REF

×1.7

×3.4

8

1.2V INT REF

REFBUFEN

43

25

CMOS/LVDS

232014 BDa

232014fa

14

For more information www.linear.com/LTC2320-14

LTC2320-14

FUNCTIONAL BLOCK DIAGRAM

LVDS IO Mode

V

GND

DD

24

CNV

(15, 21, 44, 52)

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

A

+

–

IN1

+

–

20

19

S/H

IN1

+

SDOA

27

LVDS

I/O

14-BIT+ SIGN

SAR ADC

–

MUX

SDOA

A

+

–

IN2

28

+

17

16

S/H

IN2

–

REFOUT1

22

×1

REF

A

+

–

IN3

+

–

14

13

S/H

IN3

+

SDOB

29

LVDS

I/O

14-BIT+ SIGN

SAR ADC

–

MUX

SDOB

A

+

–

IN4

30

+

11

10

S/H

IN4

–

REFOUT2

9

×1

REF

+

–

CLKOUT

SCK

41

42

33

LVDS

RECEIVERS

OUTPUT

CLOCK DRIVER

–

CLKOUT

34

SDR/DDR

23

A

+

–

IN5

+

5

4

S/H

–

IN5

+

SDOC

35

36

LVDS

I/O

14-BIT+ SIGN

SAR ADC

–

SDOC

MUX

A

+

–

IN6

+

2

1

S/H

IN6

–

REFOUT3

×1

REF

6

A

+

–

IN7

+

51

50

S/H

–

IN7

+

SDOD

39

40

LVDS

I/O

14-BIT+ SIGN

SAR ADC

–

MUX

SDOD

A

+

–

IN8

+

48

47

S/H

IN8

–

REFOUT4

×1

REF

45

250μA

OV (31, 37)

DD

REF

×1.7

×3.4

8

1.2V INT REF

REFBUFEN

43

25

CMOS/LVDS

232014 BDb

232014fa

15

For more information www.linear.com/LTC2320-14

LTC2320-14

TIMING DIAGRAM

ꢀꢁꢂꢃꢄꢅ ꢆ

SDR Mode, CMOS (Reading 1 Channel per SDO)

ꢀꢁꢂꢃꢄꢅ ꢆꢇ1

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

1

2

3

4

ꢀ

10 11 12 13 14 1ꢀ 1ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

ꢀꢁꢂ1

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 2

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

232014 ꢀꢁ01

DDR Mode, CMOS (Reading 1 Channel per SDO)

ꢀꢁꢂꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅ ꢆꢇ1

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

1

2

3

4

ꢀ

10 11 12 13 14 1ꢀ 1ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ1

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 2

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

232014 ꢀꢁ02

232014fa

16

For more information www.linear.com/LTC2320-14

LTC2320-14

TIMING DIAGRAM

SDR Mode, LVDS (Reading 2 Channels per SDO Pair)

ꢀꢁꢂꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅ ꢆꢇ1

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

1

2

3

4

ꢀ

10 11 12 13 14 1ꢀ 1ꢀ 1ꢀ 1ꢀ 1ꢀ 20 21 22 23 24 2ꢀ 2ꢀ 2ꢀ 2ꢀ 2ꢀ 30 31 32

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 2

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 3

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢁ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

232014 ꢀꢁ03

DDR Mode, LVDS (Reading 2 Channels per SDO Pair)

ꢀꢁꢂꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅ ꢆꢇ1

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

1

2

3

4

ꢀ

10 11 12 13 14 1ꢀ 1ꢀ 1ꢀ 1ꢀ 1ꢀ 20 21 22 23 24 2ꢀ 2ꢀ 2ꢀ 2ꢀ 2ꢀ 30 31 32

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 2

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 3

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢁ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14 ꢀ13 ꢀ12 ꢀ11 ꢀ10 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0

0

ꢀ14

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ ꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

ꢀꢁꢂꢃꢃꢄꢅ 1

ꢀꢁꢂꢃꢄꢅꢆꢇꢁꢂ ꢂ

232014 ꢀꢁ04

232014fa

17

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

OVERVIEW

inputs, the transfer function spans 2¹⁵codes. When

driven by pseudo differential inputs, the transfer func-

The LTC2320-14 is a low noise, high speed 14-bit succes-

sive approximation register (SAR) ADC with differential

inputs and a wide input common mode range. Operating

from a single 3.3V or 5V supply, the LTC2320-14 has a

4V or 8V differential input range, making it ideal for

14

tion spans 2 codes.

Table 1: Code Ranges for the Analog Input Operational Modes

+

–

MODE

Span (V – V ) Min Code

Max Code

IN

Fully Differential

–REFOUT to

+REFOUT

100 0000 0000 011 1111 1111

P-P

0000

1111

applications which require a wide dynamic range. The

LTC2320-14 achieves 1LSB INL typical, no missing

codes at 14 bits and 81dB SNR.

Pseudo-Differential –REFOUT/2 to

Bipolar +REFOUT/2

110 0000 0000 001 1111 1111

0000 1111

Pseudo-Differential 0 to REFOUT

Unipolar

000 0000 0000 011 1111 1111

0000

1111

The LTC2320-14 has an onboard reference buffer and

low drift (20ppm/°C max) 4.096V temperature-compen-

sated reference. The LTC2320-14 also has a high speed

SPI-compatible serial interface that supports CMOS or

LVDS. The fast 1.5Msps per channel throughput with no

latency makes the LTC2320-14 ideally suited for a wide

variety of high speed applications. The LTC2320-14 dis-

sipates only 20mW per channel. Nap and sleep modes

are also provided to reduce the power consumption

of the LTC2320-14 during inactive periods for further

power savings.

011 1111 1111 1111

011 1111 1111 1110

000 0000 0000 0001

000 0000 0000 0000

111 1111 1111 1111

1ꢇꢑꢒ ꢘ 2 ꢙ ꢎꢊꢏꢆꢃꢄ

32ꢚꢛꢜ

100 0000 0000 0001

100 0000 0000 0000

CONVERTER OPERATION

ꢍꢎꢊꢏꢆꢃꢄꢐ2

ꢍ1

ꢇꢑꢒ

0

1

ꢇꢑꢒ

ꢎꢊꢏꢆꢃꢄꢐ2

ꢍ1ꢇꢑꢒ

The LTC2320-14 operates in two phases. During the

acquisition phase, the sample capacitor is connected to

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ

232014 ꢏ02

Figure 2. LTC2320-14 Transfer Function

+

–

the analog input pins A and A to sample the differ-

IN

Analog Input

ential analog input voltage, as shown in Figure 3. A falling

edge on the CNV pin initiates a conversion. During the

conversion phase, the 14-bit CDAC is sequenced through

a successive approximation algorithm effectively com-

paring the sampled input with binary-weighted fractions

of the reference voltage (e.g., V_REFOUT/2, V_REFOUT/4 …

The differential inputs of the LTC2320-14 provide great

flexibility to convert a wide variety of analog signals with

no configuration required. The LTC2320-14 digitizes the

+

–

difference voltage between the A and A pins while

IN

supporting a wide common mode input range. The analog

V

/32768) using a differential comparator. At the

REFOUT

input signals can have an arbitrary relationship to each

end of conversion, a CDAC output approximates the sam-

pled analog input. The ADC control logic then prepares

the 14-bit digital output code for serial transfer.

other, provided that they remain between V and GND.

DD

The LTC2320-14 can also digitize more limited classes

of analog input signals such as pseudo-differential uni-

polar/bipolar and fully differential with no configuration

required.

TRANSFER FUNCTION

The LTC2320-14 digitizes the full-scale voltage of 2 •

The analog inputs of the LTC2320-14 can be modeled

by the equivalent circuit shown in Figure 3. The back-to-

back diodes at the inputs form clamps that provide ESD

15

REFOUT into 2 levels, resulting in a 15-bit resolution

size of 250µV with REFBUF = 4.096V. The ideal trans-

fer function is shown in Figure 2. The output data is in

2’s complement format. When driven by fully differential

protection. In the acquisition phase, 10pF (C ) from

IN

the sampling capacitor in series with approximately

232014fa

18

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

wide common mode input range relaxes the accuracy

requirements of any signal conditioning circuits prior

to the analog inputs.

V

DD

C

IN

R

15Ω

ON

10pF

+

A

IN

Pseudo-Differential Bipolar Input Range

BIAS

VOLTAGE

V

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typi-

DD

C

IN

R

15Ω

ON

10pF

cally V /2, and applying a signal to the other A pin. In

REF

IN

232014 F03

–

IN

A

this case the analog input swings symmetrically around

the fixed input yielding bipolar two’s complement output

codes with an ADC span of half of full-scale. This con-

figuration is illustrated in Figure 4, and the corresponding

transfer function in Figure 5. The fixed analog input pin

Figure 3. The Equivalent Circuit for the Differential

Analog Input of the LTC2320-14

need not be set at V /2, but at some point within the

REF

15Ω (R_ON) from the on-resistance of the sampling

switch is connected to the input. Any unwanted signal

that is common to both inputs will be reduced by the

common mode rejection of the ADC sampler. The inputs

of the ADC core draw a small current spike while charg-

V

rails allowing the alternate input to swing symmetri-

cally around this voltage. If the input signal (A – A

DD

+

–

)

IN

swings beyond REFOUT1,2,3,4/2, valid codes will be

generated by the ADC and must be clamped by the user,

if necessary.

ing the C capacitors during acquisition.

IN

Pseudo-Differential Unipolar Input Range

Single-Ended Signals

The pseudo-differential unipolar configuration represents

driving one of the analog inputs at ground and applying a

Single-ended signals can be directly digitized by the

LTC2320-14. These signals should be sensed pseudo-

differentially for improved common mode rejection. By

connecting the reference signal (e.g., ground sense) of

signal to the other A pin. In this case, the analog input

IN

swings between ground and V yielding unipolar two’s

REF

complement output codes with an ADC span of half of full-

scale. This configuration is illustrated in Figure 6, and the

corresponding transfer function in Figure 7. If the input

the main analog signal to the other A pin, any noise or

IN

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2320-14 flex-

ibility handles both pseudo-differential unipolar and

bipolar signals, with no configuration required. The

+

–

signal (A – A ) swings negative, valid codes will be

IN

generated by the ADC and must be clamped by the user,

if necessary.

V

REF

LT1819

LTC2320-14

+

25Ω

+

–

0V

A

REFOUT1

IN1

10µF

1µF

V

REF

220pF

10k

V

/2

REF

25Ω

+

–

V

/2

REF

–

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

A

SDO1

CLKOUT

SCK

10k

1µF

ONLY CHANNEL 1 SHOWN FOR CLARITY

232014 F04

Figure 4. Pseudo-Differential Bipolar Application Circuit

232014fa

19

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

ꢐꢉꢖ ꢖꢊꢉꢅ

ꢓ2ꢗꢘ ꢖꢊꢙꢚꢑꢅꢙꢅꢎꢋꢕ

1ꢈ3ꢆ3

ꢆ1ꢇ1

ꢐ

ꢍꢎ

ꢔ

ꢂ

ꢓꢐ ꢂ ꢐ

ꢕ

ꢍꢎ

ꢂꢃ

ꢂꢃ ꢛ2

ꢄꢅꢀ

0

ꢃ

ꢄꢅꢀ

ꢛ2

ꢃ

ꢄꢅꢀ

ꢉꢊꢋꢋꢅꢉ ꢄꢅꢌꢍꢊꢎꢏ ꢐꢃꢐꢍꢑꢐꢒꢑꢅ

ꢂꢆ1ꢇ2

ꢂ1ꢈ3ꢆ4

232014 ꢀ0ꢁ

Figure 5. Pseudo-Differential Bipolar Transfer Function

V

REF

LT1818

LTC2320-14

+

V

REF

25Ω

+

–

0V

A

REFOUT1

IN1

0V

10µF

1µF

REF

220pF

TO CONTROL

LOGIC

–

A

SDO1

CLKOUT

SCK

IN1

(FPGA, CPLD,

DSP, ETC.)

232014 F06

Figure 6. Pseudo-Differential Unipolar Application Circuit

ꢍꢆꢓ ꢓꢇꢆꢅ

ꢐ2ꢔꢕ ꢓꢇꢖꢗꢎꢅꢖꢅꢋꢈꢒ

1ꢛ3ꢙ3

ꢙ1ꢚ1

ꢍ

ꢊꢋ

ꢑ

ꢂ

ꢐꢍ ꢂ ꢍ

ꢒ

ꢊꢋ

ꢂꢃ

ꢂꢃ ꢘ2

ꢄꢅꢀ

0

ꢃ

ꢄꢅꢀ

ꢘ2

ꢃ

ꢄꢅꢀ

ꢆꢇꢈꢈꢅꢆ ꢄꢅꢉꢊꢇꢋꢌ ꢍꢃꢍꢊꢎꢍꢏꢎꢅ

ꢂꢙ1ꢚ2

ꢂ1ꢛ3ꢙ4

232014 ꢀ0ꢁ

Figure 7. Pseudo-Differential Unipolar Transfer Function

232014fa

20

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Single-Ended-to-Differential Conversion

REFOUT1,2,3,4. The common mode input voltage can

span the entire supply range up to V_DD, limited by the

input signal swing. The fully-differential configuration is

illustrated in Figure 10, with the corresponding transfer

function illustrated in Figure 11.

While single-ended signals can be directly digitized as

previously discussed, single-ended to differential conver-

sion circuits may also be used when higher dynamic range

is desired. By producing a differential signal at the inputs

of the LTC2320-14, the signal swing presented to the ADC

is maximized, thus increasing the achievable SNR.

INPUT DRIVE CIRCUITS

The LT^®1819 high speed dual operational amplifier is

recommended for performing single-ended-to-differen-

tial conversions, as shown in Figure 8. In this case, the

first amplifier is configured as a unity-gain buffer and the

single-ended input signal directly drives the high imped-

ance input of this amplifier.

A low impedance source can directly drive the high imped-

ance inputs of the LTC2320-14 without gain error. A high

impedance source should be buffered to minimize set-

tling time during acquisition and to optimize the distor-

tion performance of the ADC. Minimizing settling time is

important even for DC inputs, because the ADC inputs

draw a current spike during acquisition.

Fully-Differential Inputs

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2320-14. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC inputs, which draw a small

current spike during acquisition.

To achieve the best distortion performance of the

LTC2320-14, we recommend driving a fully-differential

signal through LT1819 amplifiers configured as two unity-

gain buffers, as shown in Figure 9. This circuit achieves

the full data sheet THD specification of –90dB at input

frequencies up to 500kHz. A fully-differential input sig-

nal can span the maximum full-scale of the ADC, up to

ꢀ

ꢁꢂꢃ

0ꢀ

ꢆꢇ1ꢈ1ꢉ

V

REF

LT1819

ꢀ

ꢁꢂꢃ

ꢄ

ꢅ

V

REF

+

–

0V

0ꢀ

0V

ꢀ

ꢁꢂꢃ

0ꢀ

ꢀ

ꢁꢂꢃ

ꢄ

ꢅ

V

REF

V

REF

/2

+

–

200Ω

0ꢀ

0V

232014 ꢃ0ꢉ

200Ω

232014 F08

Figure 8. Single-Ended to Differential Driver

Figure 9. LT1819 Buffering a Fully-Differential Signal Source

232014fa

21

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

V

REF

0V

LT1819

LTC2320-14

+

25Ω

+

–

0V

A

REFOUT1

IN1

10µF

1µF

REF

220pF

V

REF

0V

REF

+

–

0V

–

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

SDO1

CLKOUT

SCK

IN1

ONLY CHANNEL 1 SHOWN FOR CLARITY

232014 F10

Figure 10. Fully-Differential Application Circuit

ꢅꢋꢌ ꢌꢍꢋꢄ

ꢈ2ꢎꢏ ꢌꢍꢐꢑꢒꢄꢐꢄꢇꢓꢊ

1ꢗ3ꢕ3

ꢕ1ꢖ2

ꢅ

ꢆꢇ

ꢉ

ꢁ

ꢈꢅ

ꢁ ꢅ

ꢊ

ꢆꢇn

ꢁꢂ

ꢁꢂ ꢔ2

ꢃꢄꢀ

0

ꢂ

ꢃꢄꢀ

ꢔ2

ꢂ

ꢃꢄꢀ

ꢁꢕ1ꢖ2

ꢁ1ꢗ3ꢕ4

232014 ꢀ11

Figure 11. Fully-Differential Transfer Function

232014fa

22

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Input Filtering

ADC REFERENCE

The noise and distortion of the buffer amplifier and signal

source must be considered since they add to the ADC

noise and distortion. Noisy input signals should be filtered

prior to the buffer amplifier input with a low bandwidth

filter to minimize noise. The simple 1-pole RC lowpass fil-

ter shown in Figure 12 is sufficient for many applications.

Internal Reference

The LTC2320-14 has an on-chip, low noise, low

drift (20ppm/°C max), temperature compensated band-

gap reference. It is internally buffered and is available

at REF (Pin 8). The reference buffer gains the internal

reference voltage to 4.096V for supply voltages V = 5V

and to 2.048V for V = 3.3V. The REF pin also drives

the four internal reference buffers with a current limited

output (250μA) so it may be easily overdriven with an

external reference in the range of 1.25V to 5V. Bypass

REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor

to compensate the reference buffer and minimize noise.

The 1μF capacitor should be as close as possible to the

LTC2320-14 package to minimize wiring inductance. The

voltage on the REF pin must be externally buffered if used

for external circuitry.

DD

The sampling switch on-resistance (R ) and the sample

capacitor (C ) form a second lowpa^Os^Ns filter that limits

DD

IN

the input bandwidth to the ADC core to 110MHz. A buffer

amplifier with a low noise density must be selected to

minimize the degradation of the SNR over this bandwidth.

High quality capacitors and resistors should be used in

the RC filters since these components can add distor-

tion. NPO and silver mica type dielectric capacitors have

excellent linearity. Carbon surface mount resistors can

generate distortion from self heating and from damage

that may occur during soldering. Metal film surface mount

resistors are much less susceptible to both problems.

SINGLE-ENDED

INPUT SIGNAL

50Ω

+

IN

LTC2320

–

IN

3.3nF

SINGLE-ENDED

TO DIFFERENTIAL

232014 F12

DRIVER

BW = 1MHz

Figure 12. Input Signal Chain

Table 2. Reference Configurations and Ranges

REFOUT1,2,3,4

DIFFERENTIAL INPUT

RANGE PIN

REFERENCE CONFIGURATION

V

REFBUFEN

5V

REF PIN

4.096V

DD

Internal Reference with Internal Buffers

5V

3.3V

5V

4.096V

3.3V

5V

2.048V

Common External Reference with Internal Buffer (REF Pin

Externally Overdriven)

1.25V to 5V

4.096V

1.25V to 3.3V

1.25V to 5V

1.25V to 3.3V

1.25V to 5V

1.25V to 3.3V

1.25V to 5V

1.25V to 3.3V

3.3V

5V

3.3V

0V

External Reference with REF Buffers Disabled

3.3V

0V

2.048V

232014fa

23

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

External Reference

recommended when overdriving REFOUT. The LTC6655-5

offers the same small size, accuracy, drift and extended

temperature range as the LTC6655-4.096. By using a 5V

reference, a higher SNR can be achieved. We recommend

bypassing the LTC6655-5 with a 10μF ceramic capacitor

(X5R, 0805 size) close to each of the REFOUT1,2,3,4 pins.

If the REF pin voltage is used as a REFOUT reference when

REFBUFEN is connected to GND, it should be buffered

externally.

The internal REFOUT1,2,3,4 buffers can also be over-

driven from 1.25V to 5V with an external reference at

REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,

REFBUFEN must be grounded to disable the REF buffers.

A 55k internal resistance loads the REFOUT1,2,3,4 pins

when the REF buffers are disabled. To maximize the input

signal swing and corresponding SNR, the LTC6655-5 is

ꢀ

ꢈ

3ꢉ3ꢀ ꢃꢊ ꢋꢀ

ꢁꢁ

ꢐꢄꢈ

ꢌꢌ

ꢄꢈ ꢁꢉ

13ꢆ2ꢈ

ꢌꢍꢈꢏꢎꢈꢍꢇ

ꢌꢍꢈ

ꢑꢒꢋꢔꢓꢋꢒꢎ

ꢑꢒꢋ

ꢀꢁꢂꢃꢃꢄꢄꢅ4ꢆ0ꢇꢃ

ꢈ

ꢉꢓꢁꢘꢋ

ꢈ

ꢕꢎ

1ꢐꢈ

ꢖꢗꢌꢎ

ꢂꢃꢄ2320ꢅ14

ꢉꢓꢁꢘꢖ

ꢀꢁꢂ2320ꢅ14

10ꢊꢋ

0ꢆ1ꢊꢋ

ꢌꢍꢈꢊꢎꢃ1

ꢑꢒꢋꢉꢓꢁ1

ꢑꢒꢋꢉꢓꢁ2

ꢑꢒꢋꢉꢓꢁ3

ꢑꢒꢋꢉꢓꢁ4

10ꢐꢈ

ꢌꢍꢈꢊꢎꢃ2

10ꢐꢈ

10ꢊꢋ

ꢌꢍꢈꢊꢎꢃ3

10ꢐꢈ

10ꢊꢋ

ꢌꢍꢈꢊꢎꢃ4

10ꢐꢈ

10ꢊꢋ

ꢆꢇꢁ

ꢍꢎꢌ

232014 ꢈ13a

232014 ꢋ13ꢏ

(13a) LTC2320-14 Internal Reference Circuit

(13b) LTC2320-14 with a Shared External Reference Circuit

ꢁ

ꢎꢀꢁ

ꢇꢇ

ꢏꢐꢆꢒꢑꢆꢐꢌ

ꢏꢐꢆ

1ꢅꢆ

ꢀꢁ ꢂꢃ 13ꢄ2ꢁ

ꢈꢂꢉꢓꢓꢀꢀꢊ4ꢄ0ꢔꢓ

ꢁ

ꢕꢌ

ꢃꢑꢂꢘꢆ

ꢁ

ꢃꢑꢂꢘꢖ

ꢏꢐꢆꢃꢑꢂ1

ꢖꢗꢇꢌ

10ꢅꢆ

0ꢄ1ꢅꢆ

ꢈꢂꢉ2320ꢊ14

ꢈꢂꢉꢓꢓꢀꢀꢊ2ꢄ04ꢙ

ꢁ

ꢏꢐꢆꢃꢑꢂ2

ꢏꢐꢆꢃꢑꢂ3

ꢕꢌ

ꢃꢑꢂꢘꢆ

ꢁ

ꢃꢑꢂꢘꢖ

ꢖꢗꢇꢌ

ꢈꢂꢉꢓꢓꢀꢀꢊ2ꢄꢀ

ꢁ

ꢕꢌ

ꢃꢑꢂꢘꢆ

ꢖꢗꢇꢌ

ꢁ

ꢃꢑꢂꢘꢖ

ꢈꢂꢉꢓꢓꢀꢀꢊ3

ꢁ

ꢕꢌ

ꢃꢑꢂꢘꢆ

ꢁ

ꢃꢑꢂꢘꢖ

ꢏꢐꢆꢃꢑꢂ4

ꢖꢗꢇꢌ

ꢋꢌꢇ

232014 ꢆ13ꢍ

(13c) LTC2320-14 with Different External Reference Voltages

Figure 13. Reference Connections

232014fa

24

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Internal Reference Buffer Transient Response

The REFOUT1,2,3,4 pins of the LTC2320-14 draw charge

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2320-14 provides

guaranteed tested limits for both AC distortion and noise

measurements.

(Q

) from the external bypass capacitors during each

CONV

conversion cycle. If the internal reference buffer is over-

driven, the external reference must provide all of this charge

with a DC current equivalent to I_REF= Q_CONV/t_CYC

.

Thus, the DC current draw of I_{REFOUT1,2,3,4}depends

on the sampling rate and output code. In applications

where a burst of samples is taken after idling for long

periods, as shown in Figure 14 , I_REFBUFquickly goes from

approximately ~75µA to a maximum of 500µA for REFOUT

= 5V at 1.5Msps. This step in DC current draw triggers a

transient response in the external reference that must be

considered since any deviation in the voltage at REFOUT

will affect the accuracy of the output code. If an external

reference is used to overdrive REFOUT1,2,3,4, the fast

settling LTC6655 reference is recommended.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is bandlimited

to frequencies from above DC and below half the sampling

frequency. Figure 16 shows that the LTC2320-14 achieves

a typical SINAD of 80dB at a 1.5MHz sampling rate with

a 500kHz input.

CNV

Signal-to-Noise Ratio (SNR)

ꢁꢂꢃꢄ

ꢅꢄꢆꢁꢇꢂ

232014 ꢀ14

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 16 shows

that the LTC2320-14 achieves a typical SNR of 81dB at a

1.5MHz sampling rate with a 500kHz input.

Figure 14. CNV Waveform Showing Burst Sampling

1ꢀ3ꢁ4

122ꢀꢀ

0

ꢀꢁꢂ ꢃ ꢄ1ꢅ1ꢆꢇ

ꢀꢁꢂ ꢃ ꢄꢅ0ꢆ2ꢇꢈ

ꢀ20

ꢀ40

ꢀꢁꢂꢃꢄ ꢅ ꢆ0ꢇꢆꢈꢉ

ꢀꢁꢂꢃ ꢄ ꢅ4ꢆꢇꢈꢉ

ꢀ1ꢁ2

4ꢀ0ꢁꢂꢃ ꢄꢅꢆꢇꢈ

40ꢀꢁ

ꢀꢁ0

0

ꢂ

ꢀꢁ ꢃ 1ꢄꢅꢆꢇꢈ ꢉꢊꢋꢌꢍꢎ ꢏꢌꢐꢎ

ꢀ100

ꢀ120

ꢀ140

ꢂ

ꢀꢁ ꢃ 0ꢄ

ꢀ40ꢁꢂ

ꢀ20 ꢀ10

0

10 20 30 40 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0

ꢀꢁꢂꢂꢃꢄꢅꢆ ꢂꢄꢇꢁ ꢈꢉꢊꢋ

232014 ꢀ1ꢁ

0

0ꢀ1 0ꢀ2 0ꢀ3 0ꢀ4 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

Figure 15. Transient Response of the LTC2320-14

232014 ꢀ1ꢁ

Figure 16. 32k Point FFT of the LTC2320-14

232014fa

25

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Total Harmonic Distortion (THD)

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 10ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

Total harmonic distortion (THD) is the ratio of the

RMS sum of all harmonics of the input signal to the

fundamental itself. The out-of-band harmonics alias into

the frequency band between DC and half the sampling

frequency (f

/2). THD is expressed as:

SMPL

2

V2 + V3 + V4 + …+V

N

TIMING AND CONTROL

THD= 20log

V1

CNV Timing

where V1 is the RMS amplitude of the fundamental

The LTC2320-14 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

falling edge starts the conversion and readout process.

The conversion process is timed by the SCK input clock.

For optimum performance, CNV should be driven by a

clean low jitter signal. The Typical Application at the back

of the data sheet illustrates a recommended implemen-

tation to reduce the relatively large jitter from an FPGA

CNV pulse source. Note the low jitter input clock times

the falling edge of the CNV signal. The rising edge jitter

of CNV is much less critical to performance. The typical

pulse width of the CNV signal is 30ns with < 1.5ns rise

and fall times at a 1.5Msps conversion rate.

frequency and V2 through V are the amplitudes of the

N

second through Nth harmonics.

POWER CONSIDERATIONS

The LTC2320-14 requires two power supplies: the 3.3V

to 5V power supply (V_DD), and the digital input/output

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2320-14 to communicate with any digital

logic operating between 1.8V and 2.5V. When using LVDS

I/O, the OV supply must be set to 2.5V.

DD

Power Supply Sequencing

The LTC2320-14 does not have any specific power sup-

ply sequencing requirements. Care should be taken to

adhere to the maximum voltage relationships described in

the Absolute Maximum Ratings section. The LTC2320-14

has a power-on-reset (POR) circuit that will reset the

LTC2320-14 at initial power-up or whenever the power

SCK Serial Data Clock Input

In SDR mode (SDR/DDR Pin 23 = GND), the falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins. A 100MHz external clock must be applied at

the SCK pin to achieve 1.5Msps throughput using all eight

SDO outputs. In DDR mode (SDR/DDR Pin 23 = OV ),

DD

33

31

2ꢀ

each input edge of SCK shifts the conversion result MSB

first onto the SDO pins. A 50MHz external clock must be

applied at the SCK pin to achieve 1.5Msps throughput

using all eight SDO1 through SDO8 outputs.

ꢀ

ꢀ ꢁꢂ

ꢀꢀ

2ꢀ

23

21

1ꢀ

CLKOUT Serial Data Clock Output

ꢀ

ꢀ 3ꢁ3ꢂ

ꢀꢀ

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK to

capture the SDO output eases timing requirements at the

receiver. For low throughput speed applications, CLKOUT

0

0ꢀ3

0ꢀꢁ

1ꢀ2

1ꢀꢁ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈꢉꢅꢊꢋꢌ ꢍꢂꢎꢏꢎꢐ

232014 ꢀ1ꢁ

can be disabled by tying Pin 34 to OV .

Figure 17. Power Supply Current of the LTC2320-14

Versus Sampling Rate

DD

232014fa

26

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Nap/Sleep Modes

conversion result MSB first on the SDO pins. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver. The timing skew of the CLKOUT and SDO

outputs are matched. For high throughput applications,

using CLKOUT instead of SCK to capture the SDO output

eases timing requirements at the receiver. In CMOS mode,

use the SDO1 – SDO8, and CLKOUT pins as outputs. Use

Nap mode is a method to save power without sacrificing

power-up delays for subsequent conversions. Sleep mode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2320-14,

the SCK signal must be held high or low and a series

of two CNV pulses must be applied. This is the case for

both CMOS and LVDS modes. The second rising edge of

CNV initiates the nap state. The nap state will persist until

either a single rising edge of SCK is applied, or further

CNV pulses are applied. The SCK rising edge will put the

LTC2320-14 back into the operational (full-power) state.

When in nap mode, two additional pulses will put the

LTC2320-14 in sleep mode. When configured for CMOS

I/O operation, a single rising edge of SCK can return the

LTC2320-14 into operational mode. A 10ms delay is nec-

essary after exiting sleep mode to allow the reference buf-

fer to recharge the external filter capacitor. In LVDS mode,

exit sleep mode by supplying a fifth CNV pulse. The fifth

pulse will return the LTC2320-14 to operational mode,

and further SCK pulses will keep the part from re-entering

nap and sleep modes. The fifth SCK pulse also works in

CMOS mode as a method to exit sleep. In the absence of

SCK pulses, repetitive CNV pulses will cycle the LTC2320-

14 between operational, nap and sleep modes indefinitely.

+

the SCK pin as an input. In LVDS mode, use the SDOA /

–

+

–

+

–

SDOA through SDOD /SDOD and CLKOUT /CLKOUT

pins as differential outputs. Each LVDS lane yields two

channels worth of data: SDOA yields CH1 and CH2 data,

SDOB yields CH3 and CH4 data, SDOC yields CH5 and

CH6 data and SDOD yields CH7 and CH8 data. These pins

must be differentially terminated by an external 100Ω

+

–

resistor at the receiver (FPGA). The SCK /SCK pins are

differential inputs and must be terminated differentially by

an external 100Ω resistor at the receiver(ADC).

SDR/DDR Modes

The LTC2320-14 has an SDR (single data rate) and DDR

(double data rate) mode for reading conversion data from

the SDO pins. In both modes, CLKOUT is a delayed ver-

sion of SCK. In SDR mode, each negative edge of SCK

shifts the conversion data out the SDO pins. In DDR

mode, each edge of the SCK input shifts the conversion

data out. In DDR mode, the required SCK frequency is half

of what is required in SDR mode. Tie SDR/DDR to ground

RefertothetimingdiagramsinFigure18,Figure19,Figure20

and Figure 21 for more detailed timing information about

sleep and nap modes.

to configure for SDR mode and to OV for DDR mode.

DD

The CLKOUT signal is a delayed version of the SCK input

and is phase aligned with the SDO data. In SDR mode, the

SDO transitions on the falling edge of CLKOUT as illus-

trated in Figure 21. We recommend using the rising edge

of CLKOUT to latch the SDO data into the FPGA register

in SDR mode. In DDR mode, The SDO transitions on each

input edge of SCK. We recommend using the CLKOUT ris-

ing and falling edges to latch the SDO data into the FPGA

registers in DDR mode. Since CLKOUT and SDO data is

phase aligned, the SDO signals will need to be digitally

delayed in the FPGA to provide adequate setup and hold

timing margins in DDR mode.

DIGITAL INTERFACE

The LTC2320-14 features a serial digital interface that

is simple and straightforward to use. The flexible OV

DD

supply allows the LTC2320-14 to communicate with any

digital logic operating between 1.8V and 2.5V. In addi-

tion to a standard CMOS SPI interface, the LTC2320-14

provides an optional LVDS SPI interface to support low

noise digital design. The CMOS /LVDS pin is used to select

the digital interface mode. The SCK input clock shifts the

232014fa

27

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

CNV

1

2

ꢒꢏꢃ ꢈꢄꢉꢆ

ꢀꢁꢂꢂ ꢃꢄꢅꢆꢇ ꢈꢄꢉꢆ

ꢊꢋꢌ

ꢍꢄꢂꢉ ꢊꢎꢏꢎꢐꢋ ꢍꢐꢑꢍ ꢄꢇ ꢂꢄꢅ

ꢕ

ꢅꢏꢌꢆ ꢄꢒ 1ꢊꢎ ꢊꢋꢌ ꢆꢉꢑꢆ

ꢊꢉꢄ1 ꢓ ꢔ

ꢕ

232014 ꢀ1ꢔ

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

ꢇꢆꢀꢄꢁꢎ

ꢇꢆꢏꢄꢍꢆꢇꢐ

ꢇꢆꢀꢄꢁꢎ1 ꢑ 4

4ꢊ0ꢋꢌꢍ

ꢛ

ꢅꢕꢓꢆ

CNV

1

2

3

4

ꢘꢕꢃ ꢈꢄꢉꢆ

ꢒꢂꢆꢆꢃ ꢈꢄꢉꢆ

ꢀꢁꢂꢂ ꢃꢄꢅꢆꢇ ꢈꢄꢉꢆ

ꢒꢏꢓ

ꢔꢄꢂꢉ ꢒꢎꢕꢎꢖꢏ ꢔꢖꢗꢔ ꢄꢇ ꢂꢄꢅ

ꢅꢕꢓꢆ ꢄꢘ 1ꢒꢎ ꢒꢏꢓ ꢆꢉꢗꢆ

ꢒꢉꢄ1 ꢑ ꢙ

ꢚ

232014 ꢀ1ꢋ

Figure 19. CMOS Mode SLEEP and WAKE Using SCK

ꢅꢆꢇꢈꢉꢊ

ꢅꢆꢋꢈꢄꢆꢅꢌ

ꢅꢆꢇꢈꢉꢊ1 ꢛ 4

4ꢁ0ꢂꢃꢄ

ꢚ

ꢕꢒꢎꢆ

ꢕꢒꢎꢆ ꢈꢖ ꢀꢊꢏ

CNV ꢆꢑꢔꢆ

CNV

1

2

3

4

ꢀ

ꢖꢒꢗ ꢘꢈꢑꢆ

ꢍꢐꢆꢆꢗ ꢘꢈꢑꢆ

ꢇꢉꢐꢐ ꢗꢈꢕꢆꢅ ꢘꢈꢑꢆ

ꢍꢋꢎ

ꢏꢈꢐꢑ ꢍꢊꢒꢊꢓꢋ ꢏꢓꢔꢏ ꢈꢅ ꢐꢈꢕ

ꢍꢑꢈ1 ꢛ ꢜ

ꢙ

232014 ꢇ20

Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV

232014fa

28

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

SDR MODE TIMING

DDR MODE TIMING

ꢀ

ꢀꢁꢀ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀ

ꢀꢁꢂꢃꢂꢄꢅꢆ

ꢀ

ꢀꢁꢂꢃꢂꢄꢅꢆ

CNV

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

1

2

3

14

1ꢀ

1

2

3

14

1ꢀ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

1

2

3

14

1ꢀ

1

2

3

14

1ꢀ

ꢀ

ꢀꢁꢂꢃꢂꢄꢃꢅꢆꢇ

ꢀ

ꢀꢁꢂꢃꢂꢄꢃꢅꢆꢇ

ꢀ

ꢀꢁꢂꢃꢄꢀꢅꢃ

ꢀꢁꢂꢃꢄꢀꢅꢆ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢀꢅꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ1ꢁ

ꢀ14

ꢀ13

ꢀ2

ꢀ1

ꢀ0 ꢀ1ꢁ

ꢀꢁꢂ

ꢀ1ꢁ

ꢀ14

ꢀ13

ꢀ2

ꢀ1

ꢀ0 ꢀ1ꢁ

232014 21

Figure 21. LTC2320-14 Timing Diagram

232014fa

29

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

Multiple Data Lanes

a sequential circular manner. For example, the first conver-

sion result on SDO1 corresponds to analog input channel 1,

followed by the conversion results for channels 2 through

8. The data output on SDO1 then wraps back to channel

1 and this pattern repeats indefinitely. Other SDO lanes

follow a similar circular pattern except the first conversion

result presented on each lane corresponds to its associated

analog input channel.

The LTC2320-14 has up to eight SDO data lanes in CMOS

mode and four SDO lanes in LVDS mode. In CMOS mode,

the number of possible data lanes range from eight

(SDO1 – SDO8), four (SDO1, SDO3, SDO5 and SDO7), two

(SDO1 and SDO5) and one (SDO1). Generally, the more

data lanes used, the lower the required SCK frequency.

When using less than eight lanes in CMOS mode, there is a

limit on the maximum possible conversion frequency (see

Table 3). Each SDO pin will hold the MSB of the conversion

data. In DDR mode you can use a SCK frequency half of

SDR mode. See Table 3 for examples of various possibili-

ties and the resulting SCK frequency required.

Applications that cannot accommodate the full eight lanes

of serial data may employ fewer lanes without reconfigur-

ing the LTC2320-14. For example, capturing the first two

conversion results (32 SCK cycles total in SDR mode and

32 SCK edges in DDR mode) from SDO1, SDO3, SDO5, and

SDO7 provides data for analog input channels 1 and 2, 3

and 4, 5 and 6, and 7 and 8, respectively, using four output

lanes. Similarly, capturing the first four conversion results

(64 SCK cycles total in SDR mode and 64 SCK edges in

DDR mode) from SDO1 and SDO5 provides data for ana-

log input channels 1 to 4 and 5 to 8, respectively, using

two output lanes. If only one lane can be accommodated,

capturing the first eight conversion results (128 SCK cycles

total in SDR mode and 128 SCK edges in DDR mode)

from SDO1 provides data for all analog input channels.

Generally, the more data lanes used, the lower the required

SCK frequency. When using less than eight lanes in CMOS

mode, there is a limit on the maximum possible conversion

Multiple Data Lanes

The LTC2320-14 has up to eight serial data output data

lanes in CMOS mode and four serial data output lane pairs

in LVDS mode. The data on each lane consists of 14-bit

conversion results presented MSB first.

CMOS

In CMOS mode, the number of possible data lanes range

from eight (SDO1 – SDO8), four (SDO1, SDO3, SDO5 and

SDO7), two (SDO1 and SDO5) and one (SDO1). As sug-

gested in the CMOS Timing Diagrams, each SDO lane out-

puts the conversion results for all analog input channels in

2.5V

LTC2320-14

FPGA OR DSP

LTC2320-14

FPGA OR DSP

OV

DD

OV

DD

+

–

+

–

+

–

+

–

SCK

100Ω

+

–

+

–

+

–

SDOD

+

–

+

–

+

–

SDOC

100Ω

2.5V

CMOS/LVDS

+

–

+

–

+

–

+

–

CLKOUT

100Ω

+

–

+

–

+

–

SDOB

+

–

+

–

+

–

+

–

SDOA

RETIMING

FLIP-FLOP

RETIMING

FLIP-FLOP

CNV

232014 F22

232014 F23

Figure 22. LTC2320-14 Using the LVDS Interface

Figure 23. LTC2320-14 Using the LVDS Interface with One Lane

232014fa

30

For more information www.linear.com/LTC2320-14

LTC2320-14

APPLICATIONS INFORMATION

frequency. See Table 3 for examples of various possibilities

and the resulting SCK frequency required.

and 128 SCK edges in DDR mode) from SDOA provides

data for all analog input channels. Generally, the more

data lanes used, the lower the required SCK frequency.

When using less than four lanes in LVDS mode, there is

a limit on the maximum possible conversion frequency.

See Table 3 for examples of various possibilities and the

resulting SCK frequency required.

LVDS

In LVDS mode, the number of possible data lane pairs

range from four (SDOA – SDOD), two (SDOA and SDOC)

and one (SDOA). As suggested in the LVDS Timing

Diagrams, each SDO lane pair outputs the conversion

results for all analog input channels in a sequential cir-

cular manner. For example, the first conversion result on

SDOA corresponds to analog input channel pair 1 and 2,

followed by the conversion results for channels 3 through

8. The data output on SDOA then wraps back to channel

1 and this pattern repeats indefinitely. Other SDO lanes

follow a similar circular pattern except the first conversion

result presented on each lane corresponds to its associ-

ated analog input channel pairs (SDOA: analog inputs 1

and 2, SDOB: analog inputs 3 and 4, SDOC: analog inputs

5 and 6 and SDOD: analog inputs 7 and 8).

BOARD LAYOUT

To obtain the best performance from the LTC2320-14,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common

returns for these bypass capacitors are essential to the

low noise operation of the ADC. A single solid ground

plane is recommended for this purpose. When possible,

screen the analog input traces using ground.

Applications that cannot accommodate the full four lanes

of serial data may employ fewer lanes without reconfigur-

ing the LTC2320-14. For example, capturing the first four

conversion results (64 SCK cycles total in SDR mode

and 64 SCK edges in DDR mode) from SDOA and SDOC

provides data for analog input channels 1 through 4, and

5 through 8, respectively, using two output lanes. If only

one lane can be accommodated, capturing the first eight

conversion results (128 SCK cycles total in SDR mode

Recommended Layout

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2395A, the evaluation kit for the LTC2320-14.

Table 3. Conversion Frequency for Various I/O Modes

CONVERSION

FREQUENCY

(Msps/CH)

CMOS/

I/O MODE LVDS PIN

SDR/

DDR PIN

SDO1 – 8

LANES

SDOA – D

LANES

SCK FREQ

(MHz)

CLKOUT FREQ

(MHz)

SCK

CYCLES

OV

DD

GND (SDR) SDO1 – SDO8

OV (DDR) SDO1 – SDO8

DD

100

50

100

50

16

8

1.5

GND

CMOS

1.8V to 2.5V

2.5V

SDO1, SDO3,

SDO5, SDO7

SDO1

(CMOS)

OV (DDR)

50

16

1.25

DD

GND (SDR)

100

200

100

150

300

100

200

100

150

300

128

32

16

32

128

0.5

1.5

1.4

1.0

SDOA – SDOD

SDOA, SDOC

SDOA

OV (DDR)

OV

DD

LVDS

(LVDS)

OV (DDR)

DD

GND (SDR)

Notes: Conversion Period (SDR) = t

Conversion Period (DDR) = t

+ t

+ (128/(Lanes • f ))

+ (64/(Lanes • f ))

SCK

CNV_MIN

CONV_MAX SCK

CNV_MIN

CONV_MAX

Conversion Frequency = 1/Conversion Period

SCK Cycles (SDR) = 128/Lanes

SCK Cycles (DDR) = 64/Lanes

232014fa

31

For more information www.linear.com/LTC2320-14

LTC2320-14

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2320-14#packaging for the most recent package drawings.

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

ꢀꢁꢞ0 ±0ꢁ0ꢞ

ꢟꢁ10 ±0ꢁ0ꢞ

ꢞꢁꢞ0 ꢌꢆꢗ

ꢂ2 ꢃꢄꢅꢆꢃꢇ

0ꢁꢀ0 ±0ꢁ0ꢞ

ꢟꢁ4ꢞ ±0ꢁ0ꢞ

ꢟꢁꢞ0 ꢌꢆꢗ

ꢂ2 ꢃꢄꢅꢆꢃꢇ

ꢀꢁ10 ±0ꢁ0ꢞ ꢣꢁꢞ0 ±0ꢁ0ꢞ

ꢞꢁ41 ±0ꢁ0ꢞ

ꢒꢍꢑꢓꢍꢏꢆ ꢉꢔꢊꢕꢄꢈꢆ

0ꢁ2ꢞ ±0ꢁ0ꢞ

0ꢁꢞ0 ꢙꢃꢑ

ꢌꢆꢑꢉꢖꢖꢆꢈꢅꢆꢅ ꢃꢉꢕꢅꢆꢌ ꢒꢍꢅ ꢒꢄꢊꢑꢚ ꢍꢈꢅ ꢅꢄꢖꢆꢈꢃꢄꢉꢈꢃ

ꢍꢒꢒꢕꢝ ꢃꢉꢕꢅꢆꢌ ꢖꢍꢃꢓ ꢊꢉ ꢍꢌꢆꢍꢃ ꢊꢚꢍꢊ ꢍꢌꢆ ꢈꢉꢊ ꢃꢉꢕꢅꢆꢌꢆꢅ

ꢞꢁꢞ0 ꢌꢆꢗ

ꢂ2 ꢃꢄꢅꢆꢃꢇ

0ꢁꢀꢞ ±0ꢁ0ꢞ

ꢀꢁ00 ±0ꢁ10

ꢂ2 ꢃꢄꢅꢆꢃꢇ

ꢌ ꢠ 0ꢁ11ꢞ

ꢊꢝꢒ

0ꢁ00 ꢤ 0ꢁ0ꢞ

ꢞ1

ꢞ2

0ꢁ40 ±0ꢁ10

ꢒꢄꢈ 1 ꢊꢉꢒ ꢖꢍꢌꢓ

ꢂꢃꢆꢆ ꢈꢉꢊꢆ ꢟꢇ

1

2

ꢒꢄꢈ 1 ꢈꢉꢊꢑꢚ

ꢌ ꢠ 0ꢁ30 ꢊꢝꢒ ꢉꢌ

0ꢁ3ꢞ × 4ꢞ°ꢑ

ꢑꢚꢍꢖꢗꢆꢌ

ꢟꢁ4ꢞ ±0ꢁ10

ꢣꢁ00 ±0ꢁ10

ꢂ2 ꢃꢄꢅꢆꢃꢇ

ꢟꢁꢞ0 ꢌꢆꢗ

ꢂ2 ꢃꢄꢅꢆꢃꢇ

ꢞꢁ41 ±0ꢁ10

ꢂꢔꢓꢏꢞ2ꢇ ꢥꢗꢈ ꢌꢆꢡ

ꢦ 030ꢟ

ꢌ ꢠ 0ꢁ10

ꢊꢝꢒ

0ꢁ2ꢞ ±0ꢁ0ꢞ

0ꢁꢞ0 ꢙꢃꢑ

ꢊꢉꢒ ꢡꢄꢆꢎ

ꢃꢄꢅꢆ ꢡꢄꢆꢎ

0ꢁ200 ꢌꢆꢗ

0ꢁ00 ꢤ 0ꢁ0ꢞ

ꢙꢉꢊꢊꢉꢖ ꢡꢄꢆꢎꢢꢆꢘꢒꢉꢃꢆꢅ ꢒꢍꢅ

0ꢁꢀꢞ ±0ꢁ0ꢞ

232014fa

32

For more information www.linear.com/LTC2320-14

LTC2320-14

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

01/18 Corrected no latency operation.

18, 25

232014fa

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

33

For more information www.linear.com/LTC2320-14

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

LTC2320-14

TYPICAL APPLICATION

Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop

V

CC

NC7SVUO4P5X

0.1µF

1k

MASTER_CLOCK

V

CC

50Ω

1k

D

ꢁRꢂ

NC7SV74K8X

CONV

ꢃ

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

CꢀR

CONV ENABLE

CNV

LTC2320-14

SCK

10Ω

CLKOUT

GND

CMOS/LVDS

SDR/DDR

SDO1 – 8

232014 TA02

NC7SVU04P5X (× 9)

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC2320-16/LTC2320-12 16-/12-Bit, Octal 1.5Msps/CH, Simultaneous

Sampling ADCs

3.3V/5V Supply, 20mW/Ch, 20ppm°C Max Internal Reference, Flexible

Inputs, 7mm × 8mm QFN Package

LTC2310-16/LTC2310-14/ 16-/14-/12-Bit, Differential Input ADC with Wide

3.3V/5V Supply, Single-Channel, 35mW, 20ppm/°C Max Internal

Reference, Flexible Inputs, 16-Lead MSO Package

LTC2310-12

Input Common Mode

LTC2321-16/LTC2321-14/ Dual 16-/14-/12-Bit, 2Msps, Simultaneous

LTC2321-12 Sampling ADCs

3.3V/5V Supply, 33mW/Ch, 20ppm°C Max Internal Reference,

Flexible Inputs, 4mm × 5mm QFN-28 Package

LTC2324-16/LTC2324-14/ Quad 16-/14-/12-Bit, 2Msps/Channel, Simultaneous 3.3V/5V Supply, Single-Channel, 40mW, 20ppm/°C Max Internal

LTC2324-12

Sampling ADCs

Reference, Flexible Inputs, 52-Lead QFN Package

LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,

LTC2377-16/LTC2376-16 Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

DACs

LTC2632

Dual 12-/10-/8-Bit, SPI V

Reference

DACs with Internal

DACs with External

2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, 8-Pin ThinSOT™ Package

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit SPI V

Reference

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead

MSOP Package

OUT

References

LTC6655

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm

Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm

Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1818/LT1819

400MHz, 2500V/µs, 9mA Single/Dual Operational

Amplifiers

–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply

Current, Unity-Gain Stable

LT1806

LT6200

325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,

Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable

165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable

Low Noise, Op Amp Family

232014fa

LT 0118 REV A • PRINTED IN USA

www.linear.com/LTC2320-14

34

 ANALOG DEVICES, INC. 2018

For more information www.linear.com/LTC2320-14


型号：	LTC2320HUKG-14#PBF
厂家：	Linear
描述：	LTC2320-14 - Octal, 14-Bit + Sign, 1.5Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: -40°C to 125°C 转换器
文件：	总34页 (文件大小：2053K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2320HUKG-14#PBF [Linear]

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