LTC2324IUKG-14#PBF [Linear]
LTC2324-14 - Quad, 14-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C;型号: | LTC2324IUKG-14#PBF |
厂家: | Linear |
描述: | LTC2324-14 - Quad, 14-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C |
文件: | 总30页 (文件大小:1418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2324-14
Quad, 14-Bit + Sign,
2Msps/Ch Simultaneous Sampling ADC
FeaTures
DescripTion
The LTC®2324-14 is a low noise, high speed quad
n
2Msps/Ch Throughput Rate
n
Four Simultaneously Sampling Channels
Guaranteed 14-Bit, No Missing Codes
14-bit + sign successive approximation register (SAR)
ADCwithdifferentialinputsandwideinputcommonmode
range. Operating from a single 3.3V or 5V supply, the
n
n
8V Differential Inputs with Wide Input
P-P
Common Mode Range
LTC2324-14 has an 8V differential input range, making
P-P
n
n
n
n
n
81dB SNR (Typ) at f = 500kHz
it ideal for applications which require a wide dynamic
range with high common mode rejection. The LTC2324-
14 achieves 1LSꢀ INL typical, no missing codes at 14
bits and 81dꢀ SNR.
IN
IN
–90dB THD (Typ) at f = 500kHz
Guaranteed Operation to 125°C
Single 3.3V or 5V Supply
Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
TheLTC2324-14hasanonboardlowdrift(20ppm/°Cmax)
2.048V or 4.096V temperature-compensated reference.
The LTC2324-14 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
2Msps per channel throughput with no latency makes the
LTC2324-14 ideally suited for a wide variety of high speed
applications. The LTC2324-14 dissipates only 40mW per
channel and offers nap and sleep modes to reduce the
power consumption to 26μW for further power savings
during inactive periods.
n
n
n
n
1.8V to 2.5V I/O Voltages
CMOS or LVDS SPI-Compatible Serial I/O
Power Dissipation 40mW/Ch (Typ)
Small 52-Lead (7mm × 8mm) QFN Package
applicaTions
n
High Speed Data Acquisition Systems
n
Communications
n
Optical Networking
Multiphase Motor Control
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners.
n
Typical applicaTion
10µF
1µF
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
3.3V OR 5V
1.8V TO 2.5V
32k Point FFT fSMPL = 2Msps,
fIN = 500kHz
+
–
IN , IN
0
–20
V
GND
GND
O
V
DD
DD
SNR = 82.3dB
THD = –90.9dB
SINAD = 81.6dB
SFDR = 96.5dB
ARBITRARY
DIFFERENTIAL
14-BIT
+SIGN
SAR ADC
+
–
V
V
CMOS/LVDS
SDR/DDR
REFBUFEN
DD
0V
DD
0V
DD
0V
DD
0V
A
IN1
IN1
S/H
A
–40
14-BIT
+SIGN
SAR ADC
+
–
SDO1
SDO2
SDO3
SDO4
CLKOUT
SCK
A
A
IN2
IN2
S/H
–60
LTC2324-14
+
–
–80
14-BIT
+SIGN
SAR ADC
BIPOLAR
UNIPOLAR
A
A
IN3
IN3
V
V
S/H
–100
–120
–140
CNV
SAMPLE
CLOCK
14-BIT
+SIGN
SAR ADC
+
–
A
A
IN4
IN4
S/H
REF REFOUT1 REFOUT2 REFOUT3 REFOUT4
0
0.2
0.4
0.6
0.8
1
1µF
10µF
10µF
10µF
10µF
FOUR SIMULTANEOUS
SAMPLING CHANNELS
FREQUENCY (MHz)
232414 TA01b
232414 TA01a
232414f
1
For more information www.linear.com/LTC2324-14
LTC2324-14
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltage (V )..................................................6V
DD
Supply Voltage (OV )................................................3V
DD
Analog Input Voltage
52 51 50 49 48 47 46 45 44 43 42 41
–
+
–
A
, A (Note 3) ................... –0.3V to (V + 0.3V)
–
IN
IN DD
A
A
1
2
40 DNC/SDOD
IN4
+
+
+
REFOUT1,2,3,4........................ .–0.3V to (V + 0.3V)
39 SDO4/SDOD
DD
DD
IN4
GND
–
GND
OV
3
38
37
CNV........................................ –0.3V to (OV + 0.3V)
A
IN3
4
DD
Digital Input Voltage
+
–
A
IN3
5
36 DNC/SDOC
SDO3/SDOC
35
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
REFOUT3
GND
6
Digital Output Voltage
–
7
34 CLKOUTEN/CLKOUT
53
GND
+
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
REF
8
33 CLKOUT/CLKOUT
DD
REFOUT2
–
9
32 GND
Operating Temperature Range
A
A
10
11
31 OV
IN2
DD
LTC2324C ................................................ 0°C to 70°C
LTC2324I .............................................–40°C to 85°C
LTC2324H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
+
–
30 DNC/SDOB
IN2
+
+
GND 12
–
29 SDO2/SDOB
–
A
A
13
14
28 DNC/SDOA
IN1
+
27 SDO1/SDOA
IN1
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
T
= 150°C, θ = 31°C/W, θ = 2°C/W
JMAX
JA JC
EXPOSED PAD (PIN 53) IS GND, MUST ꢀE SOLDERED TO PCꢀ
http://www.linear.com/product/LTC2324-14#orderinfo
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC2324UKG-14
LTC2324UKG-14
LTC2324UKG-14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2324CUKG-14#PꢀF
LTC2324IUKG-14#PꢀF
LTC2324HUKG-14#PꢀF
LTC2324CUKG-14#TRPꢀF
LTC2324IUKG-14#TRPꢀF
LTC2324HUKG-14#TRPꢀF
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPꢀF suffix.
232414f
2
For more information www.linear.com/LTC2324-14
LTC2324-14
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
+
+
–
–
l
l
l
l
l
V
V
V
V
Absolute Input Range (A to A
)
)
(Note 5)
0
V
DD
V
DD
IN
IN
IN
IN
IN
IN
–
+
+
Absolute Input Range (A to A
(Note 5)
0
V
IN
–
+
–
– V
Input Differential Voltage Range
Common Mode Input Range
V
V
= V – V
–REFOUT1,2,3,4
REFOUT1,2,3,4
V
IN
IN
IN
IN
+
–
= (V – V )/2
0
V
DD
V
CM
CM
IN
IN
I
IN
Analog Input DC Leakage Current
Analog Input Capacitance
–1
1
μA
pF
dꢀ
V
C
IN
10
CMRR
Input Common Mode Rejection Ratio
CNV High Level Input Voltage
CNV Low Level Input Voltage
CNV Input Current
f
IN
= 500kHz
102
l
l
l
V
V
1.5
IHCNV
ILCNV
INCNV
0.5
10
V
I
–10
μA
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
14
TYP
MAX
UNITS
ꢀits
l
l
Resolution
No Missing Codes
14
ꢀits
Transition Noise
0.8
1
LSꢀ
RMS
l
l
l
INL
Integral Linearity Error
Differential Linearity Error
ꢀipolar Zero-Scale Error
ꢀipolar Zero-Scale Error Drift
ꢀipolar Full-Scale Error
ꢀipolar Full-Scale Error Drift
(Note 6)
(Note 7)
–2.5
–0.99
–1.5
2.5
0.99
1.5
LSꢀ
DNL
ꢀZE
0.4
0
LSꢀ
LSꢀ
0.01
0
LSꢀ/°C
LSꢀ
l
FSE
V
V
= 4.096V (REFꢀUFEN Grounded) (Note 7)
= 4.096V (REFꢀUFEN Grounded)
–2.5
2.5
REFOUT1,2,3,4
15
ppm/°C
REFOUT1,2,3,4
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
81
MAX
UNITS
dꢀ
l
l
l
l
SINAD
Signal-to-(Noise + Distortion) Ratio f = 500kHz, V
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
75
IN
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
81
dꢀ
SNR
Signal-to-Noise Ratio
76
78
82
dꢀ
82.5
–90
–91
93
dꢀ
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
–77.5
dꢀ
dꢀ
SFDR
dꢀ
93
dꢀ
–3dꢀ Input ꢀandwidth
Aperture Delay
55
MHz
ps
500
500
1
Aperture Delay Matching
Aperture Jitter
ps
ps
RMS
Transient Response
Full-Scale Step
3
ns
232414f
3
For more information www.linear.com/LTC2324-14
LTC2324-14
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Internal Reference Output Voltage
4.75V < V < 5.25V
4.078
2.034
4.096
2.048
4.115
2.064
V
V
REFOUT1,2,3,4
DD
3.13V < V < 3.47V
DD
l
V
Temperature Coefficient
(Note 14)
3
20
ppm/°C
Ω
REF
REFOUT1,2,3,4 Output Impedance
Line Regulation
0.25
0.3
V
4.75V < V < 5.25V
mV/V
REFOUT1,2,3,4
DD
I
External Reference Current
REFꢀUFEN = 0V
REFOUT1,2,3,4
REFOUT1,2,3,4 = 4.096V
REFOUT1,2,3,4 = 2.048V
(Notes 9, 10)
385
204
μA
μA
DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
CMOS/LVDS = GND
MIN
0.8 • OV
–10
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
IH
IL
DD
0.2 • OV
DD
I
V
IN
= 0V to OV
DD
10
μA
pF
IN
C
IN
Digital Input Capacitance
5
l
l
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500μA
OV – 0.2
V
V
OH
O
DD
I = 500μA
O
0.2
10
OL
l
I
I
I
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
μA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SINK
DD
LVDS Digital Inputs and Outputs
CMOS/LVDS = OV
DD
l
l
l
l
l
l
V
V
V
V
V
V
LVDS Differential Input Voltage
LVDS Common Mode Input Voltage
LVDS Differential Output Voltage
LVDS Common Mode Output Voltage
100Ω Differential Termination
DD
240
1
600
1.45
600
1.4
mV
V
ID
OV = 2.5V
100Ω Differential Termination
OV = 2.5V
DD
IS
100Ω Differential Termination
OV = 2.5V
DD
220
0.85
100
0.85
350
1.2
200
1.2
mV
V
OD
100Ω Differential Termination
OV = 2.5V
DD
OS
Low Power LVDS Differential Output Voltage 100Ω Differential Termination
350
1.4
mV
V
OD_LP
OS_LP
OV = 2.5V
DD
Low Power LVDS Common Mode Output Voltage 100Ω Differential Termination
OV = 2.5V
DD
232414f
4
For more information www.linear.com/LTC2324-14
LTC2324-14
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Supply Voltage
5V Operation
3.3V Operation
4.75
3.13
5.25
3.47
V
V
DD
+
–
l
IV
DD
Supply Current
2Msps Sample Rate (IN = IN = 0V)
31
39
mA
CMOS I/O Mode
CMOS/LVDS = GND
Supply Voltage
l
l
l
l
OV
1.71
2.63
8
V
mA
mA
µA
DD
OVDD
NAP
I
I
I
Supply Current
2Msps Sample Rate (C = 5pF)
4.4
5.3
20
L
Nap Mode Current
Sleep Mode Current
Power Dissipation
Conversion Done (I
)
6.4
90
VDD
Sleep Mode (I
+ I
)
OVDD
SLEEP
VDD
l
l
l
P
V
= 3.3V, 2Msps Sample Rate
DD
102
18
20
130
21.1
288
mW
mW
µW
D_3.3V
Nap Mode
Sleep Mode
l
l
l
P
D_5V
Power Dissipation
V
= 5V, 2Msps Sample Rate
162
27
30
203
32
424
mW
mW
µW
DD
Nap Mode
Sleep Mode
LVDS I/O Mode
CMOS/LVDS = OV , OV = 2.5V
DD DD
l
l
l
l
OV
Supply Voltage
Supply Current
2.37
2.63
33
V
mA
mA
µA
DD
OVDD
NAP
I
I
I
2Msps Sample Rate (C = 5pF, R = 100Ω)
26
5.3
20
L
L
Nap Mode Current
Sleep Mode Current
Power Dissipation
Conversion Done (I
)
6.4
90
VDD
Sleep Mode (I
+ I
)
OVDD
SLEEP
VDD
l
l
l
P
V
= 3.3V, 2Msps Sample Rate
DD
151
52
80
185
56
288
mW
mW
µW
D_3.3V
Nap Mode
Sleep Mode
l
l
l
P
D_5V
Power Dissipation
V
= 5V, 2Msps Sample Rate
214
52
30
265
69
424
mW
mW
µW
DD
Nap Mode
Sleep Mode
aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
2
UNITS
Msps
µs
l
l
l
l
f
t
t
t
t
t
Maximum Sampling Frequency
Time ꢀetween Conversions
Conversion Time
SMPL
(Note 11) t
= t
+ t
+ t
READOUT
0.5
220
30
1000
CYC
CYC
CNVH
CONV
ns
CONV
CNV High Time
ns
CNVH
Sampling Aperture
(Note 11) t
= t
– t
CONV
250
50
ns
ACQUISITION
WAKE
ACQUISITION
CYC
REFOUT1,2,3,4 Wake-Up Time
C
= 10µF
ms
REFOUT1,2,3,4
CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND
l
l
l
l
l
t
t
t
t
t
SCK Period
(Note 13)
9.1
4.1
4.1
0
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)
1.5
4.5
HSDO_SDR
DSCKCLKOUT
L
SCK to CLKOUT Delay
(Note 12)
2
232414f
5
For more information www.linear.com/LTC2324-14
LTC2324-14
aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
(Note 11)
(Note 11)
(Note 11)
MIN
TYP
MAX
UNITS
ns
l
l
l
t
t
t
ꢀus Relinquish Time After CNV↑
SDO Valid Delay from CNV↓
SCK Delay Time to CNV↑
3
3
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
ns
0
ns
CMOS I/O Mode, DDR CMOS/LVDS = GND, SDR/ DDR = OV
DD
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SCK Period
18.2
8.2
8.2
0
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)
1.5
4.5
3
HSDO_DDR
DSCKCLKOUT
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
L
SCK to CLKOUT Delay
(Note 12)
(Note 11)
(Note 11)
(Note 11)
2
ꢀus Relinquish Time After CNV↑
SDO Valid Delay from CNV↓
SCK Delay Time to CNV↑
3
0
LVDS I/O Mode, SDR CMOS/LVDS = OV , SDR/DDR = GND
DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
3.3
1.5
1.5
0
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)
1.5
4
HSDO_SDR
DSCKCLKOUT
DSCKHCNVH
L
SCK to CLKOUT Delay
(Note 12)
(Note 11)
2
SCK Delay Time to CNV↑
0
LVDS I/O Mode, DDR CMOS/LVDS = OV , SDR/DDR = OV = 2.5V
DD
DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
6.6
3
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCK Low Time
SCKH
3
SCKL
SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)
0
1.5
4
HSDO_DDR
DSCKCLKOUT
DSCKHCNVH
L
SCK to CLKOUT Delay
(Note 12)
(Note 11)
2
SCK Delay Time to CNV↑
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dꢀ are referred to a full-scale 4.096V input
with REF = 4.096V.
Note 2: All voltage values are with respect to ground.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
Note 3: When these pin voltages are taken below ground, or above V or
must be turned off by setting REFꢀUFEN = 0V.
DD
OV , they will be clamped by internal diodes. This product can handle input
DD
Note 10: f
= 2MHz, I
varies proportionally with sample rate.
SMPL
REFOUT1,2,3,4
currents up to 100mA below ground, or above V or OV , without latch-up.
DD
DD
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V.
Note 13: t
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OV
logic levels.
Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.096V, f = 2MHz.
SMPL
DD
DD
DD
DD
Note 5: Recommended operating conditions.
of 9.1ns allows a shift clock frequency up to 110MHz for
SCK
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: ꢀipolar zero error is the offset voltage measured from –0.5LSꢀ
when the output code flickers between 0000 0000 0000 000 and 1111
1111 1111 111. Full-scale bipolar error is the worst-case of –FS or +FS
DD
232414f
6
For more information www.linear.com/LTC2324-14
LTC2324-14
aDc TiMing characTerisTics
0.8 • OV
DD
t
WIDTH
0.2 • OV
DD
50%
50%
t
t
DELAY
DELAY
232414 F01
0.8 • OV
0.8 • OV
0.2 • OV
DD
DD
DD
DD
0.2 • OV
Figure 1. Voltage Levels for Timing Specifications
232414f
7
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LTC2324-14
Typical perForMance characTerisTics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
= 4.096V, fSMPL = 2Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
4
3
1.0
0.5
150000
σ = 0.75
135000
120000
105000
90000
2
1
Right Click In Graph Area for Menu
Double Click In Graph Area for Data Setup
0
0
75000
60000
45000
30000
15000
0
–1
–2
–3
–4
–0.5
–1.0
–16384
–8192
0
8192
16384
–16384
–8192
0
8192
16384
–8 –6.4–4.8–3.2–1.6 0.0 1.6 3.2 4.8 6.4
8
1
1
OUTPUT CODE
OUTPUT CODE
CODE
232414 G01
232414 G02
232414 G03
THD, Harmonics vs Input
Frequency (1kHz to 1MHz)
32k Point FFT, fSMPL = 2Msps,
fIN = 500kHz
SNR, SINAD vs Input Frequency
(1kHz to 1MHz)
0
–20
83.0
82.8
82.6
82.4
82.2
82.0
81.8
81.6
81.4
81.2
81.0
–80
–84
SNR = 82.3dB
THD = –90.9dB
SINAD = 81.6dB
SFDR = 96.5dB
–88
–40
–92
THD
–96
SNR
–60
–100
–104
–108
–112
–116
–120
HD3
–80
HD2
–100
–120
–140
SINAD
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
232414 G04
232414 G05
232414 G06
THD, Harmonics vs Input
Common Mode
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
32k Point FFT, IMD, fSMPL =2Msps,
AIN+ = 500kHz, AIN– = 1.3MHz
–85
–90
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
0
–20
f = 500kHz
THD = 84dB
f = 500kHz
V
= 800kHz, 4Vpp
CM
SNR
SINAD
–40
THD
–95
–60
HD3
–80
–100
–105
–110
HD2
–100
–120
–140
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.2
0.4
0.6
0.8
INPUT COMMON MODE (V)
V
(V)
REFOUT
FREQUENCY (MHz)
232414 G07
232414 G08
232414 G09
232414f
8
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LTC2324-14
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
Step Response
Typical perForMance characTerisTics
= 4.096V, fSMPL = 2Msps, unless otherwise noted.
CMRR vs Input Frequency
Crosstalk vs Input Frequency
(Large Signal Settling)
16384
120
112
104
96
–105
–107
–109
–111
–113
–115
–117
–119
–121
–123
–125
V
= 4Vpp
CM
12288
8192
4.096V RANGE
4096
0
88
IN+ = 2MHz SQUARE WAVE
IN– = 0V
–4096
80
–20 –10
0
10 20 30 40 50 60 70 80 90
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
SETTLING TIME (ns)
FREQUENCY (MHz)
FREQUENCY (MHz)
232414 G12
232414 G10
232414 G11
Step Response
(Fine Settling)
External Reference Supply
Current vs Sample Frequency
REF Output vs Temperature
125
100
75
400
300
200
100
0
1.00
0.50
REFBUFEN = 0V
(EXT REF BUF
V
= 3.3V
DD
OVERDRIVING REF BUF)
0
50
–0.50
–1.00
–1.50
–2.00
–2.50
–3.00
25
V
= 4.096V
REFOUT1,2,3,4
0
V
= 5V
DD
–25
–50
–75
–100
–125
4.096V RANGE
V
= 2.048V
REFOUT1,2,3,4
IN+ = 2.0MHz SQUARE WAVE
IN– = 0V
–20 –10
0
10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
–55 –35 –15
5
25 45 65 85 105 125
SETTLING TIME (ns)
SAMPLE FREQUENCY (Msps)
TEMPERATURE (°C)
232414 G13
232414 G14
232414 G15
Supply Current
vs Sample Frequency
OVDD Current vs SCK Frequency,
CLOAD = 10pF
Offset Error vs Temperature
1.0
0.5
5
4
3
2
1
0
32
30
28
26
24
22
20
18
16
14
12
35
30
25
20
15
Full Scale Sinusoidal Input
LVDS
CMOS(2.5V)
V
= 5V
DD
0
CMOS(1.8V)
V
DD
= 3.3V
–0.5
LOW POWER LVDS
–1.0
–55 –35 –15
5
25 45 65 85 105 12
0
22
44
66
88
110
0
0.4
0.8
1.2
1.6
2
TEMPERATURE (°C)
SCK FREQUENCY (MHz)
SAMPLE FREQUENCY (Msps)
232414 G16
232414 G18
232414 G17
232414f
9
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LTC2324-14
pin FuncTions
PINS THAT ARE THE SAME FOR ALL DIGITAL I/O MODES
REFOUT1(Pin22):ReferenceBuffer1Output.Anonboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
+
–
AIN4 , AIN4 (Pins 2, 1): Analog Differential Input Pins.
+
–
Full-scale range (AIN4 – AIN4 ) is REFOUT4 voltage.
These pins can be driven from V to GND.
DD
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.
These pins and exposed pad (Pin 53) must be tied directly
to a solid ground plane.
SDR/DDR (Pin 23): Double Data Rate Input. Controls the
frequency of SCK and CLKOUT. Tie to GND for the falling
edge of SCK to shift each serial data output (Single Data
+
–
AIN3 , AIN3 (Pins 5, 4): Analog Differential Input Pins.
+
–
Full-scale range (AIN3 – AIN3 ) is REFOUT3 voltage.
These pins can be driven from V to GND.
Rate, SDR). Tie to OV to shift serial data output on each
DD
DD
edge of SCK (Double Data Rate, DDR). CLKOUT will be a
REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
delayed version of SCK for both pin states.
CNV (Pin 24): Convert Input. This pin, when high, defines
the acquisition phase. When this pin is driven low, the
conversion phase is initiated and output data is clocked
out. This input must be driven at OV levels with a low
DD
jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
REF (Pin 8): Common 4.096V reference output. Decouple
to GND with a 1μF low ESR ceramic capacitor. May be
overdriven with a single external reference to establish a
common reference for ADC cores 1 through 4.
to enable CMOS mode, tie to OV to enable LVDS mode.
DD
Float this pin to enable low power LVDS mode.
OV (Pins 31, 37): I/O Interface Digital Power. The range
DD
of OV is 1.71V to 2.63V. This supply is nominally set
REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
DD
to the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OV to GND (Pins 32 and 38)
DD
with 0.1µF capacitors.
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
to V when using the internal reference. Tie to ground
DD
to disable the internal REFOUT1–4 buffers for use with
+
–
external voltage references. This pin has a 500k internal
AIN2 ,AIN2 (Pins11,10):AnalogDifferentialInputPins.
+
–
pull-up to V .
Full-scale range (AIN2 – AIN2 ) is REFOUT2 voltage.
These pins can be driven from V to GND.
DD
DD
REFOUT4 (Pin45):ReferenceBuffer4Output.Anonboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
+
–
AIN1 ,AIN1 (Pins14,13):AnalogDifferentialInputPins.
+
–
Full-scale range (AIN1 – AIN1 ) is REFOUT1 voltage.
These pins can be driven from V to GND.
DD
V
(Pins 15, 21, 44, 52): Power Supply. Bypass V to
DD
DD
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
capacitorclosetothepart. TheV pinsshouldbeshorted
together and driven from the same supply.
DD
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
232414f
10
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LTC2324-14
pin FuncTions
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR
FLOAT)
SDO1(Pin27):CMOSSerialDataOutputforADCChannel1.
The conversion result is shifted MSB first on each falling
edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from SDO1 in SDR mode, 16 SCK edges
in DDR mode.
+
–
SDOA , SDOA (Pins 27, 28): LVDS Serial Data Output
for ADC Channel 1. The conversion result is shifted CH1
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 14-bit conversion data to be read from SDOA in SDR
mode,16SCKedgesinDDRmode.Terminatewitha100Ω
resistor at the receiver (FPGA).
SDO2(Pin29):CMOSSerialDataOutputforADCChannel2.
The conversion result is shifted MSB first on each falling
edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from SDO2 in SDR mode, 16 SCK edges
in DDR mode.
+
–
SDOB , SDOB (Pins 29, 30): LVDS Serial Data Output
for ADC Channel 2. The conversion result is shifted CH2
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 14-bit conversion data to be read from SDOB in SDR
mode,16SCKedgesinDDRmode.Terminatewitha100Ω
resistor at the receiver (FPGA).
SDO3(Pin35):CMOSSerialDataOutputforADCChannel3.
The conversion result is shifted MSB first on each falling
edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from SDO3 in SDR mode, 16 SCK edges
in DDR mode.
+
–
CLKOUT ,CLKOUT (Pins33,34):SerialDataClockOutput.
CLKOUT provides a skew-matched clock to latch the SDO
outputatthereceiver.ThesepinsechotheinputatSCKwith
a small delay. These pins must be differentially terminated
by an external 100Ω resistor at the receiver (FPGA).
SDO4 (Pin 39): CMOS Serial Data Output for ADC Channel
4. The conversion result is shifted MSB first on each fall-
ing edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from SDO4 in SDR mode, 16 SCK edges
in DDR mode.
+
–
SDOC , SDOC (Pins 35, 36): LVDS Serial Data Output
for ADC channel 3. The conversion result is shifted CH3
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 14-bit conversion data to be read from SDOA in SDR
mode,16SCKedgesinDDRmode.Terminatewitha100Ω
resistor at the receiver (FPGA).
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver (FPGA). The logic level is determined by
+
–
OV . This pin echoes the input at SCK with a small delay.
SDOD , SDOD (Pins 39, 40): LVDS Serial Data Output
for ADC Channel 4. The conversion result is shifted CH4
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 14-bit conversion data to be read from SDOA in SDR
mode,16SCKedgesinDDRmode.Terminatewitha100Ω
resistor at the receiver (FPGA).
DD
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
Pin 34 to OV for a small power savings. If CLKOUT is
DD
used, ground this pin.
SCK (Pin 41): Serial Data Clock Input. The falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins in SDR mode (DDR = LOW). In DDR mode
(SDR/DDR = HIGH) each edge of this clock shifts the
conversion result MSB first onto the SDO pins. The logic
+
–
SCK , SCK (Pins 41, 42): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins in SDR mode (SDR/DDR = LOW).
In DDR mode (SDR/DDR = HIGH) each edge of this clock
shifts the conversion result MSB first onto the SDO pins.
Thesepinsmustbedifferentiallyterminatedbyanexternal
level is determined by OV .
DD
DNC (Pins 28, 30, 36, 40, 42): In CMOS mode, do not
connect this pin.
100Ω resistor at the receiver (ADC).
232414f
11
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LTC2324-14
FuncTional block DiagraM
CMOS IO Mode
V
GND
DD
24
CNV
(15, 21, 44, 52)
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
A
+
–
SDO1
DNC
IN1
+
–
27
28
14
13
14-BIT+SIGN
SAR ADC
CMOS
I/O
S/H
A
IN1
REFOUT1
×1
REF
22
A
A
+
–
IN2
SDO2
DNC
+
–
11
10
29
30
14-BIT+SIGN
SAR ADC
CMOS
I/O
S/H
IN2
REFOUT2
×1
REF
9
SCK
CLKOUT
41
42
33
34
CMOS
RECEIVERS
OUTPUT
CLOCK DRIVER
DNC
CLKOUTEN
SDR/DDR
23
A
A
+
–
IN3
SDO3
DNC
+
5
4
35
36
14-BIT+SIGN
SAR ADC
CMOS
I/O
S/H
–
IN3
REFOUT3
×1
REF
6
A
A
+
–
IN4
SDO4
DNC
+
2
1
39
40
14-BIT+SIGN
SAR ADC
CMOS
I/O
S/H
–
IN4
REFOUT4
×1
REF
45
250μA
OV (31, 37)
DD
REF
×1.7
×3.4
8
1.2V INT REF
REFBUFEN
43
25
CMOS/LVDS
232414 BDa
232414f
12
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LTC2324-14
FuncTional block DiagraM
LVDS IO Mode
V
GND
DD
24
CNV
(15, 21, 44, 52)
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
+
A
+
–
SDOA
SDOA
IN1
+
–
27
28
14
13
LVDS
I/O
14-BIT+SIGN
SAR ADC
–
S/H
A
IN1
REFOUT1
×1
REF
22
+
A
A
+
–
SDOB
IN2
+
–
11
10
29
30
LVDS
I/O
14-BIT+SIGN
SAR ADC
–
S/H
SDOB
IN2
REFOUT2
×1
REF
9
+
+
–
CLKOUT
SCK
SCK
41
42
33
34
LVDS
RECEIVERS
OUTPUT
CLOCK DRIVER
–
CLKOUT
SDR/DDR
23
+
A
+
SDOC
IN3
+
5
4
35
36
LVDS
I/O
14-BIT+SIGN
SAR ADC
–
S/H
–
A
–
SDOC
IN3
REFOUT3
×1
REF
6
+
A
A
+
–
SDOD
IN4
+
2
1
39
40
LVDS
I/O
14-BIT+SIGN
SAR ADC
–
S/H
–
SDOD
IN4
REFOUT4
×1
REF
45
250μA
OV (31, 37)
DD
REF
×1.7
×3.4
8
1.2V INT REF
REFBUFEN
43
25
CMOS/LVDS
232414 BDb
232414f
13
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LTC2324-14
TiMing DiagraM
SDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
SAMPLE N+1
CNV
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
Hi-Z
Hi-Z
CLKOUT
Hi-Z
Hi-Z
SDO1
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
Hi-Z
Hi-Z
SDO4
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 4
CONVERSION N
CHANNEL 1
CONVERSION N
232414 TD01
DDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
SAMPLE N+1
ACQUIRE
CNV
CONVERT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
Hi-Z
Hi-Z
CLKOUT
SDO1
Hi-Z
Hi-Z
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
Hi-Z
Hi-Z
SDO4
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
CHANNEL 4
CONVERSION N
232414 TD02
232414f
14
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LTC2324-14
TiMing DiagraM
SDR Mode, LVDS (Reading 1 Channel per SDO Pair)
SAMPLE N
SAMPLE N+1
CNV
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
CLKOUT
SDOA
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
SDOD
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 4
CONVERSION N
CHANNEL 1
CONVERSION N
232414 TD03
DDR Mode, LVDS (Reading 1 Channel per SDO Pair)
SAMPLE N
SAMPLE N+1
ACQUIRE
CNV
CONVERT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
CLKOUT
SDOA
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
SDOD
DONT CARE
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D14
CHANNEL 1
CONVERSION N
232414 TD04
CHANNEL 4
CONVERSION N
232414f
15
For more information www.linear.com/LTC2324-14
LTC2324-14
applicaTions inForMaTion
OVERVIEW
input with binary-weighted fractions of the reference volt-
age (e.g., V /2, V /4 … V /32768) using
adifferentialcomparator. Attheendofconversion, aCDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 14-bit digital output code
for serial transfer.
REFOUT
REFOUT
REFOUT
The LTC2324-14 is a low noise, high speed 15-bit succes-
sive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2324-14 has a
4V or 8V differential input range, making it ideal for
P-P
P-P
applications which require a wide dynamic range. The
LTC2324-14achieves 1LSBINLtypical,nomissingcodes
at 14 bits and 81dB SNR.
TRANSFER FUNCTION
The LTC2324-14 digitizes the full-scale voltage of 2 ×
15
REFOUT1,2,3,4 into 2 levels, resulting in an LSB size of
TheLTC2324-14hasanonboardreferencebufferandlow
drift(20ppm/°Cmax)4.096Vtemperature-compensated
reference. The LTC2324-14 also has a high speed SPI-
compatible serial interface that supports CMOS or LVDS.
The fast 2Msps per channel throughput with no-cycle
latency makes the LTC2324-14 ideally suited for a wide
variety of high speed applications. The LTC2324-14 dis-
sipates only 40mW per channel. Nap and sleep modes
are also provided to reduce the power consumption
of the LTC2324-14 during inactive periods for further
power savings.
250µV with REF = 4.096V. The ideal transfer function is
shown in Figure 2. The output data is in 2’s complement
format.
Analog Input
The differential inputs of the LTC2324-14 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2324-14 digitizes the
+
–
difference voltage between the A and A pins while
IN
IN
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between V and GND.
CONVERTER OPERATION
DD
The LTC2324-14 can also digitize more limited classes of
analog input signals such as pseudo-differential unipolar/
bipolarandfullydifferentialwithnoconfigurationrequired.
The LTC2324-14 operates in two phases. During the ac-
quisition phase, the sample capacitor is connected to the
+
–
analog input pins A and A to sample the differential
IN
IN
The analog inputs of the LTC2324-14 can be modeled
by the equivalent circuit shown in Figure 3. The back-
to-back diodes at the inputs form clamps that provide
analoginputvoltage,asshowninFigure3.Afallingedgeon
the CNV pin initiates a conversion. During the conversion
phase,the15-bitCDACissequencedthroughasuccessive
approximationalgorithmeffectivelycomparingthesampled
ESD protection. In the acquisition phase, 10pF (C )
IN
V
DD
C
011 1111 1111 1111
011 1111 1111 1110
IN
R
15Ω
ON
10pF
+
A
IN
000 0000 0000 0001
000 0000 0000 0000
111 1111 1111 1111
BIAS
VOLTAGE
V
DD
C
IN
R
15Ω
ON
10pF
1LSB = 2 • REFOUT
100 0000 0000 0001
–
232414 F03
A
IN
32768
100 0000 0000 0000
–REFOUT/2
–1
LSB
0
1
LSB
REFOUT/2
–1LSB
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2324-14
INPUT VOLTAGE (V)
232414 F02
Figure 2. LTC2324-14 Transfer Function
232414f
16
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from the sampling capacitor in series with approximately
mode input range relaxes the accuracy requirements of
anysignalconditioningcircuitspriortotheanaloginputs.
15Ω(R )fromtheon-resistanceofthesamplingswitch
ON
is connected to the input. Any unwanted signal that is
common to both inputs will be reduced by the common
mode rejection of the ADC sampler. The inputs of the
ADC core draw a small current spike while charging the
Pseudo-Differential Bipolar Input Range
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically
C capacitors during acquisition.
IN
V
/2, and applying a signal to the other A pin. In this
REF
IN
case the analog input swings symmetrically around the
fixedinputyieldingbipolartwo’scomplementoutputcodes
with an ADC span of half of full-scale. This configuration
is illustrated in Figure 4, and the corresponding transfer
function in Figure 5. The fixed analog input pin need not
Single-Ended Signals
Single-ended signals can be directly digitized by the
LTC2324-14. These signals should be sensed pseudo-
differentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
be set at V /2, but at some point within the V rails
REF
DD
the main analog signal to the other A pin, any noise or
allowingthealternateinputtoswingsymmetricallyaround
IN
+
–
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2324-14 flexibility
handles both pseudo-differential unipolar and bipolar
signals,withnoconfigurationrequired.Thewidecommon
thisvoltage.Iftheinputsignal(A –A )swingsbeyond
IN IN
REFOUT1,2,3,4/2, valid codes will be generated by the
ADC and must be clamped by the user, if necessary.
V
V
REF
REF
LT1819
LTC2324-14
+
25Ω
+
–
0V
0V
A
REFOUT1
IN1
10µF
1µF
V
REF
REF
220pF
10k
V
/2
REF
25Ω
+
–
V
/2
REF
–
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
A
IN1
SDO1
CLKOUT
SCK
10k
1µF
ONLY CHANNEL 1 SHOWN FOR CLARITY
232414 F04
Figure 4. Pseudo-Differential Bipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
A
IN
+
–
(A – A
)
IN
IN
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
DOTTED REGIONS AVAILABLE
–8192
–16384
232414 F05
Figure 5. Pseudo-Differential Bipolar Transfer Function
232414f
17
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Pseudo-Differential Unipolar Input Range
The LT®1819 high speed dual operational amplifier is
recommendedforperformingsingle-ended-to-differential
conversions, as shown in Figure 8. In this case, the first
amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high imped-
ance input of this amplifier.
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other A pin. In this case, the analog input
IN
swings between ground and V
yielding unipolar two’s
REF
complement output codes with an ADC span of half of
full-scale. This configuration is illustrated in Figure 6, and
the corresponding transfer function in Figure 7. If the input
V
REF
LT1819
V
REF
+
–
0V
+
–
signal (A – A ) swings negative, valid codes will be
IN
IN
0V
generated by the ADC and must be clamped by the user, if
necessary. A possible variant of this mode would be to tie
+
–
V
REF
V
REF
/2
+
–
A
IN
to ground and drive A between ground and V
IN REF
200Ω
0V
yieldingacodespanillustratedbythedottedlineinFigure7.
200Ω
V
REF
232414 F08
LT1818
LTC2324-14
+
V
REF
25Ω
+
–
0V
A
REFOUT1
IN1
0V
10µF
1µF
Figure 8. Single-Ended to Differential Driver
REF
220pF
Fully-Differential Inputs
25Ω
–
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
A
IN1
SDO1
CLKOUT
SCK
To achieve the best distortion performance of the
LTC2324-14, we recommend driving a fully-differential
signal through LT1819 amplifiers configured as two
unity-gain buffers, as shown in Figure 9. This circuit
achieves the full data sheet THD specification of –90dB at
input frequencies up to 500kHz. A fully-differential input
signal can span the maximum full-scale of the ADC, up to
REFOUT1,2,3,4. The common mode input voltage can
232414 F06
Figure 6. Pseudo-Differential Unipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
span the entire supply range up to V , limited by the
DD
input signal swing. The fully-differential configuration is
illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
A
IN
+
–
(A – A
IN IN
)
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
DOTTED REGIONS AVAILABLE
–8192
–16384
V
REF
0V
LT1819
232414 F07
V
REF
+
–
Figure 7. Pseudo-Differential Unipolar Transfer Function
0V
V
REF
0V
Single-Ended-to-Differential Conversion
V
REF
+
–
0V
Whilesingle-endedsignalscanbedirectlydigitizedaspre-
viously discussed, single-ended to differential conversion
circuits may also be used when higher dynamic range is
desired. By producing a differential signal at the inputs of
the LTC2324-14, the signal swing presented to the ADC is
maximized, thus increasing the achievable SNR.
232414 F09
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
232414f
18
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V
V
REF
REF
0V
LT1819
LTC2324-14
+
25Ω
25Ω
+
–
0V
A
A
REFOUT1
IN1
10µF
1µF
REF
220pF
V
V
REF
0V
REF
+
–
0V
–
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
SDO1
CLKOUT
SCK
IN1
ONLY CHANNEL 1 SHOWN FOR CLARITY
232414 F10
Figure 10. Fully-Differential Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8192
A
IN
+
–
(A
– A
)
INn
INn
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
–8192
–16384
232414 F11
Figure 11. Fully-Differential Transfer Function
INPUT DRIVE CIRCUITS
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs, which draw a small
current spike during acquisition.
A low impedance source can directly drive the high im-
pedance inputs of the LTC2324-14 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter
to minimize noise. The simple 1-pole RC lowpass filter
shown in Figure 12 is sufficient for many applications.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2324-14. The amplifier
provides low output impedance to minimize gain error
232414f
19
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SINGLE-ENDED
ADC REFERENCE
INPUT SIGNAL
+
50Ω
IN
IN
LTC2324
Internal Reference
–
3.3nF
The LTC2324-14 has an on-chip, low noise, low
drift (20ppm/°C max), temperature compensated band-
gap reference. It is internally buffered and is available
at REF (Pin 8). The reference buffer gains the internal
SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
232414 F12
BW = 1MHz
Figure 12. Input Signal Chain
reference voltage to 4.096V for supply voltages V = 5V
DD
and to 2.048V for V = 3.3V. The REF pin also drives
DD
The sampling switch on-resistance (R ) and the sample
ON
the four internal reference buffers with a current limited
output (250μA) so it may be easily overdriven with an
external reference in the range of 1.25V to 5V. Bypass
REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor
to compensate the reference buffer and minimize noise.
The 1μF capacitor should be as close as possible to the
LTC2324-14 package to minimize wiring inductance. The
REFBUFEN pin does not affect the internal REF buffer. The
voltage on the REF pin must be externally buffered if used
for external circuitry.
capacitor (C ) form a second lowpass filter that limits
IN
the input bandwidth to the ADC core to 110MHz. A buffer
amplifier with a low noise density must be selected to
minimize the degradation of the SNR over this bandwidth.
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
Table 1. Reference Configurations and Ranges
REFOUT1,2,3,4
PIN
DIFFERENTIAL INPUT
RANGE
REFERENCE CONFIGURATION
V
REFBUFEN
5V
REF PIN
4.096V
DD
Internal Reference with Internal Buffers
5V
3.3V
5V
4.096V
4.096V
3.3V
5V
2.048V
2.048V
2.048V
Common External Reference with Internal Buffer (REF Pin
Externally Overdriven)
1.25V to 5V
1.25V to 5V
4.096V
1.25V to 3.3V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
3.3V
5V
3.3V
0V
External Reference with REF Buffers Disabled
3.3V
0V
2.048V
232414f
20
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External Reference
recommendedwhenoverdrivingREFOUT. TheLTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. By using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a 10μF ceramic capacitor
(X5R, 0805 size) close to each of the REFOUT1,2,3,4
pins. If the REF pin voltage is used as a REFOUT refer-
ence when REFBUFEN is connected to GND, it should be
buffered externally.
The internal REFOUT1,2,3,4 buffers can also be over-
driven from 1.25V to 5V with an external reference at
REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,
REFBUFEN must be grounded to disable the REF buffers.
A 55k internal resistance loads the REFOUT1,2,3,4 pins
when the REF buffers are disabled. To maximize the input
signal swing and corresponding SNR, the LTC6655-5 is
V
3.3V TO 5V
DD
V
+5V
DD
5V TO
13.2V
REFBUFEN
REF
REFBUFEN
REF
LTC6655-4.096
V
V
IN
OUT_F
V
OUT_S
1µF
LTC2324-14
SHDN
LTC2324-14
10µF
10µF
REFOUT1
REFOUT2
REFOUT3
REFOUT4
0.1µF
REFOUT1
REFOUT2
REFOUT3
REFOUT4
10µF
10µF
10µF
10µF
10µF
10µF
GND
10µF
GND
232414 F13a
232414 F13b
(13a) LTC2324-14 Internal Reference Circuit
(13b) LTC2324-14 with a Shared External Reference Circuit
V
+5V
DD
REFBUFEN
REF
1µF
5V TO 13.2V
5V TO 13.2V
5V TO 13.2V
5V TO 13.2V
LTC6655-4.096
V
V
IN
OUT_F
V
OUT_S
REFOUT1
SHDN
10µF
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
LTC2324-14
LTC6655-2.048
V
V
REFOUT2
REFOUT3
IN
OUT_F
V
OUT_S
SHDN
LTC6655-2.5
V
V
IN
OUT_F
SHDN
V
OUT_S
LTC6655-3
V
V
IN
OUT_F
V
OUT_S
REFOUT4
SHDN
GND
232414 F13c
(13c) LTC2324-14 with Different External Reference Voltages
Figure 13. Reference Connections
232414f
21
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Internal Reference Buffer Transient Response
The REFOUT1,2,3,4 pins of the LTC2324-14 draw charge
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2324-14 provides
guaranteed tested limits for both AC distortion and noise
measurements. The typical large signal transient pulse
response of the ADC is illustrated in Figure 15.
(Q
) from the external bypass capacitors during each
CONV
conversion cycle. If the internal reference buffer is over-
driven,theexternalreferencemustprovideallofthischarge
with a DC current equivalent to I
= Q
/t
.
REF
CONV CYC
Thus, the DC current draw of I
depends
REFOUT1,2,3,4
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
periods, as shown in Figure 14 , I
quickly goes from
REFBUF
approximately~75µAtoamaximumof500µAforREFOUT
= 5V at 2Msps. This step in DC current draw triggers a
transient response in the external reference that must be
considered since any deviation in the voltage at REFOUT
will affect the accuracy of the output code. If an external
reference is used to overdrive REFOUT1,2,3,4, the fast
settling LTC6655 reference is recommended.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure16showsthattheLTC2324-14achieves
a typical SINAD of 81dB at a 2MHz sampling rate with a
500kHz input.
CNV
IDLE
PERIOD
232414 F14
Signal-to-Noise Ratio (SNR)
Figure 14. CNV Waveform Showing Burst Sampling
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2324-14 achieves a typical SNR of 81dB at a
2MHz sampling rate with a 500kHz input.
16384
12288
8192
4.096V RANGE
4096
0
SNR = 82.3dB
THD = –90.9dB
–20
–40
SINAD = 81.6dB
SFDR = 96.5dB
0
IN+ = 2MHz SQUARE WAVE
IN– = 0V
–4096
–60
–20 –10
0
10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
232414 F15
–80
Figure 15. Transient Response of the LTC2324-14
–100
–120
–140
0
0.2
0.4
0.6
0.8
1
FREQUENCY (MHz)
232414 F16
Figure 16. 32k Point FFT of the LTC2324-14
232414f
22
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Total Harmonic Distortion (THD)
allows the LTC2324-14 to communicate with any digital
logic operating between 1.8V and 2.5V. When using LVDS
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
I/O, the OV supply must be set to 2.5V.
DD
Power Supply Sequencing
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
The LTC2324-14 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2324-14
has a power-on-reset (POR) circuit that will reset the
LTC2324-14 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
2
V22 +V32 +V42 +… +VN
THD=20log
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through V are the amplitudes of the
N
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2324-14 requires two power supplies: the 3.3V
to 5V power supply (V ), and the digital input/output
DD
interface power supply (OV ). The flexible OV supply
DD
DD
35
30
25
20
15
V
= 5V
DD
V
DD
= 3.3V
0
0.4
0.8
1.2
1.6
2
SAMPLE FREQUENCY (Msps)
232414 F17
Figure 17. Power Supply Current of the LTC2324-14 Versus Sampling Rate
232414f
23
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TIMING AND CONTROL
capture the SDO output eases timing requirements at the
receiver. For low throughput speed applications, CLKOUT
CNV Timing
can be disabled by tying Pin 34 to OV .
DD
The LTC2324-14 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
fallingedgestartstheconversionandreadoutprocess.The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling
edge of the CNV signal. The rising edge jitter of CNV is
much less critical to performance. The typical pulse width
of the CNV signal is 30ns with < 1.5ns rise and fall times
at a 2Msps conversion rate.
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-updelaysforsubsequentconversions. Sleepmode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2324-14,
the SCK signal must be held high or low and a series of
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
asinglerisingedgeofSCKisapplied,orfurtherCNVpulses
are applied. The SCK rising edge will put the LTC2324-14
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2324-14 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2324-14 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2324-14 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2324-14 between
operational, nap and sleep modes indefinitely.
SCK Serial Data Clock Input
In SDR mode (SDR/DDR Pin 23 = GND), the falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins. A 110MHz external clock must be applied
at the SCK pin to achieve 2Msps throughput using all four
SDO outputs. In DDR mode (SDR/DDR Pin 23 = OV ),
DD
each input edge of SCK shifts the conversion result MSB
first onto the SDO pins. A 55MHz external clock must be
applied at the SCK pin to achieve 2Msps throughput using
all four SDO1 through SDO4 outputs.
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK to
RefertothetimingdiagramsinFigure18,Figure19,Figure20
and Figure 21 for more detailed timing information about
sleep and nap modes.
CNV
1
2
NAP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
Z
WAKE ON 1ST SCK EDGE
SDO1 – 4
Z
232414 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
232414f
24
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REFOUT
RECOVERY
REFOUT1 – 4
4.096V
4.096V
t
WAKE
CNV
1
2
3
4
NAP MODE
SLEEP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 4
Z
Z
Z
Z
232414 F19
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
REFOUT
RECOVERY
REFOUT1 – 4
4.096V
4.096V
t
WAKE
WAKE ON 5TH
CNV EDGE
CNV
1
2
3
4
5
NAP MODE
SLEEP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
SDO1 – 4
Z
Z
Z
Z
Z
232414 F20
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
SDR MODE TIMING
DDR MODE TIMING
t
t
CYC
CYC
t
t
t
READOUT
CNVH
CONV
t
t
t
CNVH
CONV
READOUT
t
DSCKCNVH
t
DSCKCNVH
CNV
CNV
t
t
SCKH
t
SCK
SCKH
t
SCK
SCK
SCK
1
2
3
14
15
16
1
2
3
14
15
16
t
SCKL
t
SCKL
CLKOUT
CLKOUT
1
2
3
14
15
16
1
2
3
14
15
16
t
DSCKCLKOUT
t
DSCKCLKOUT
t
t
t
t
DCNVSDOV
DCNVSDOZ
DCNVSDOZ
t
t
HSDO
DCNVSDOV
HSDO
HI-Z
HI-Z
HI-Z
HI-Z
SDO
D14
D13
D12
D1
D0
X
D14
SDO
D14
D13
D12
D1
D0
X
D14
232414 F21
Figure 21. LTC2324-14 Timing Diagram
232414f
25
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DIGITAL INTERFACE
outputs are matched. For high throughput applications,
using CLKOUT instead of SCK to capture the SDO output
eases timing requirements at the receiver. In CMOS mode,
use the SDO1 – SDO4, and CLKOUT pins as outputs. Use
The LTC2324-14 features a serial digital interface that
is simple and straightforward to use. The flexible OV
DD
supply allows the LTC2324-14 to communicate with any
digital logic operating between 1.8V and 2.5V. In addi-
tion to a standard CMOS SPI interface, the LTC2324-14
provides an optional LVDS SPI interface to support low
noise digital design. The CMOS /LVDS pin is used to select
the digital interface mode. The SCK input clock shifts the
conversion result MSB first on the SDO pins. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver. The timing skew of the CLKOUT and SDO
+
the SCK pin as an input. In LVDS mode, use the SDOA /
–
+
–
+
–
SDOA through SDOD /SDOD and CLKOUT /CLKOUT
pinsasdifferentialoutputs.Thesepinsmustbedifferentially
terminated by an external 100Ω resistor at the receiver
+
–
(FPGA). The SCK /SCK pins are differential inputs and
must be terminated differentially by an external 100Ω
resistor at the receiver(ADC).
2.5V
2.5V
LTC2324-14
FPGA OR DSP
LTC2324-14
FPGA OR DSP
OV
DD
OV
DD
+
–
+
–
+
–
+
–
SCK
SCK
SCK
SCK
100Ω
100Ω
100Ω
+
–
+
–
+
–
SDOD
SDOD
SDOD
SDOD
+
–
+
–
+
–
SDOC
SDOC
SDOC
SDOC
100Ω
100Ω
100Ω
100Ω
2.5V
2.5V
CMOS/LVDS
CMOS/LVDS
+
–
+
–
+
–
+
–
CLKOUT
CLKOUT
CLKOUT
CLKOUT
100Ω
100Ω
+
–
+
–
+
–
SDOB
SDOB
SDOB
SDOB
+
–
+
–
+
–
+
–
SDOA
SDOA
SDOA
SDOA
RETIMING
FLIP-FLOP
RETIMING
FLIP-FLOP
CNV
CNV
232414 F22
232414 F23
Figure 22. LTC2324-14 Using the LVDS Interface
Figure 23. LTC2324-14 Using the LVDS Interface with One Lane
232414f
26
For more information www.linear.com/LTC2324-14
LTC2324-14
applicaTions inForMaTion
SDR/DDR Modes
Multiple Data Lanes
The LTC2324-14 has an SDR (single data rate) and DDR
(double data rate) mode for reading conversion data from
theSDOpins.Inbothmodes,CLKOUTisadelayedversion
of SCK. In SDR mode, each negative edge of SCK shifts
the conversion data out the SDO pins. In DDR mode,
each edge of the SCK input shifts the conversion data
out. In DDR mode, the required SCK frequency is half of
what is required in SDR mode. Tie SDR/DDR to ground to
The LTC2324-14 has up to four SDO data lanes in CMOS
mode and four SDO lanes in LVDS mode. In CMOS mode,
thenumberofpossibledatalanesrangefrom four(SDO1,
SDO2, SDO3 and SDO4), two (SDO1 and SDO3) and one
(SDO1). Generally, themoredatalanesused, thelowerthe
required SCK frequency. When using less than four lanes
in CMOS mode, there is a limit on the maximum possible
conversionfrequency(seeTable2).EachSDOpinwillhold
the MSB of the conversion data. In DDR mode you can
use a SCK frequency half of SDR mode. See Table 2 for
examples of various possibilities and the resulting SCK
frequency required.
configure for SDR mode and to OV for DDR mode. The
DD
CLKOUTsignalisadelayedversionoftheSCKinputandis
phase aligned with the SDO data. In SDR mode, the SDO
transitions on the falling edge of CLKOUT as illustrated
in Figure 21. We recommend using the rising edge of
CLKOUT to latch the SDO data into the FPGA register in
SDR mode. In DDR mode, the SDO transitions on each
input edge of SCK. We recommend using the CLKOUT ris-
ing and falling edges to latch the SDO data into the FPGA
registers in DDR mode. Since the CLKOUT and SDO data
are phase aligned, we recommend digitally delaying the
SDO data in the FPGA to provide adequate setup and hold
timing margins in DDR mode.
CMOS
In CMOS mode, the number of possible data lanes range
from four (SDO1, SDO2, SDO3 and SDO4), two (SDO1
and SDO3) and one (SDO1). As suggested in the CMOS
Timing Diagrams, each SDO lane outputs the conversion
results for all analog input channels in a sequential cir-
cular manner. For example, the first conversion result on
SDO1 corresponds to analog input channel 1, followed
by the conversion results for channels 2 through 4. The
Table 2. Conversion Frequency for Various I/O Modes
CONVERSION
FREQUENCY
(Msps/CH)
CMOS/
I/O MODE LVDS PIN
SDR/
DDR PIN
SDO1 – 4
LANES
SDOA – D
LANES
SCK FREQ
(MHz)
CLKOUT FREQ
(MHz)
SCK
CYCLES
OV
DD
GND (SDR) SDO1 – SDO4
OV (DDR) SDO1 – SDO4
110
55
110
55
16
8
2.0
2.0
1.5
1.0
2.0
2.0
2.0
2.0
DD
GND
CMOS
1.8V to 2.5V
2.5V
(CMOS)
OV (DDR)
SDO1, SDO3
SDO1
55
55
32
64
16
8
DD
GND (SDR)
GND (SDR)
110
300
110
150
300
110
300
110
150
300
SDOA – SDOD
SDOA – SDOD
SDOA, SDOC
SDOA
OV (DDR)
DD
OV
DD
LVDS
(LVDS)
OV (DDR)
DD
16
64
GND (SDR)
Notes: Conversion Period (SDR) = t
Conversion Period (DDR) = t
+ t
+ t
+ (64/(Lanes • f ))
+ (32/(Lanes • f ))
SCK
CNV_MIN
CONV_MAX SCK
CNV_MIN
CONV_MAX
Conversion Frequency = 1/Conversion Period
SCK Cycles (SDR) = 64/Lanes
SCK Cycles (DDR) = 32/Lanes
232414f
27
For more information www.linear.com/LTC2324-14
LTC2324-14
applicaTions inForMaTion
data output on SDO1 then wraps back to channel 1 and
this pattern repeats indefinitely. Other SDO lanes follow a
similar circular pattern except the first conversion result
presented on each lane corresponds to its associated
analog input channel.
Applications that cannot accommodate the full four lanes
of serial data may employ fewer lanes without reconfigur-
ing the LTC2324-14. For example, capturing the first two
conversion results (32 SCK cycles total in SDR mode
and 32 SCK edges in DDR mode) from SDOA and SDOC
provides data for analog input channels 1 through 4,
respectively, using two output lanes. If only one lane can
be accommodated, capturing the first four conversion
results (64 SCK cycles total in SDR mode and 64 SCK
edges in DDR mode) from SDOA provides data for all
analog input channels. Generally, the more data lanes
used, the lower the required SCK frequency. When using
less than four lanes in LVDS mode, there is a limit on the
maximum possible conversion frequency. See Table 2 for
examples of various possibilities and the resulting SCK
frequency required.
Applicationsthatcannotaccommodatethefullfourlanes
of serial data may employ fewer lanes without reconfig-
uring the LTC2324-14. For example, capturing the first
two conversion results (32 SCK cycles total in SDR mode
and 32 SCK edges in DDR mode) from SDO1 and SDO3
provides data for analog input channels 1 and 2, 3 and 4,
respectively, using two output lanes. Similarly, capturing
the first four conversion results (64 SCK cycles total in
SDR mode and 64 SCK edges in DDR mode) from SDO1
provides data for analog input channels 1 to 4, using
one output lane. Generally, the more data lanes used,
the lower the required SCK frequency. When using less
than four lanes in CMOS mode, there is a limit on the
maximum possible conversion frequency. See Table 2
for examples of various possibilities and the resulting
SCK frequency required.
BOARD LAYOUT
To obtain the best performance from the LTC2324-14,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
LVDS
InLVDSmode,thenumberofpossibledatalanepairsrange
from four (SDOA – SDOD), two (SDOA and SDOC) and
one (SDOA). As suggested in the LVDS Timing Diagrams,
each SDO lane pair outputs the conversion results for all
analog input channels in a sequential circular manner. For
example, thefirstconversionresultonSDOAcorresponds
to analog input channel 1, followed by the conversion re-
sults for channels 2 through 4. The data output on SDOA
then wraps back to channel 1 and this pattern repeats
indefinitely. Other SDO lanes follow a similar circular pat-
tern except the first conversion result presented on each
lane corresponds to its associated analog input channel
pairs (SDOA: analog input 1, SDOB: analog input 2, SDOC:
analog input 3 and SDOD: analog input 4).
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Recommended Layout
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2395A, the evaluation kit for the LTC2324-14.
232414f
28
For more information www.linear.com/LTC2324-14
LTC2324-14
package DescripTion
Please refer to http://www.linear.com/product/LTC2324-14#packaging for the most recent package drawings.
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF
(2 SIDES)
7.10 ±0.05 8.50 ±0.05
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 ±0.05
7.00 ±0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
6.45 ±0.10
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 ±0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 ±0.05
0.50 BSC
TOP VIEW
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
232414f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
29
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2324-14
Typical applicaTion
Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop
V
CC
NC7SVUO4P5X
0.1µF
1k
MASTER_CLOCK
V
CC
50Ω
1k
D
PRE
NL17SZ740S8
CONV
Q
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
CLR
CONV ENABLE
CNV
LTC2324-14
SCK
10Ω
10Ω
CLKOUT
GND
GND
CMOS/LVDS
SDR/DDR
SDO1 – 8
232414 TA02
NC7SVU04P5X (× 5)
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2311-16/LTC2311-14/ 16-/14-/12-Bit, 5Msps Differential Input ADC
LTC2311-12
3.3V Supply, 1-Channel 40mW, 20ppm/°C Internal Reference, Flexible
Inputs, 16-Lead MSOP Package
LTC2320-16/LTC2320-14/ 16-/14-/12-Bit, Octal 1.5Msps/Channel
3.3V/5V Supply, 20mW/Channel, 20ppm/°C Internal Reference, Flexible
Inputs, 7mm × 8mm QFN-52 Package
LTC2320-12
Simultaneous Sampling ADC
LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, Dual 2Msps, Simultaneous
LTC2321-12 Sampling ADCs
3.3V/5V Supply, 40mW/Ch, 20ppm°C Max Internal Reference,
Flexible Inputs, 4mm × 5mm QFN-28 Package
LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
LTC2367-16/LTC2364-16 Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range,
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
LTC2377-16/LTC2376-16 Low Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACs
LTC2632
Dual 12-/10-/8-Bit, SPI V
Reference
DACs with Internal
DACs with External
2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, 8-Pin ThinSOT™ Package
OUT
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit SPI V
Reference
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead
MSOP Package
OUT
References
LTC6655
Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm
Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm
Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT1818/LT1819
400MHz, 2500V/µs, 9mA Single/Dual Operational
Amplifiers
–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply
Current, Unity-Gain Stable
LT1806
LT6200
325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,
Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable
165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable
Low Noise, Op Amp Family
232414f
LT 0717 • PRINTED IN USA
www.linear.com/LTC2324-14
30
LINEAR TECHNOLOGY CORPORATION 2017
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