LTC2376CMS-18#PBF_技术文档

LTC2376-18

18-Bit, 250ksps, Low Power

SAR ADC with 102dB SNR

FeaTures

DescripTion

The LTC^®2376-18 is a low noise, low power, high speed

18-bit successive approximation register (SAR) ADC. Op-

n

250ksps Throughput Rate

n

±±1.5ꢀSꢁ INꢀ ꢂ(aꢃx

n

Guaranteed ±8-ꢁit No (issing Codes

erating from a 2.5V supply, the LTC2376-18 has a V

fully differential input range with V ranging from 2.5V

to 5.1V. The LTC2376-18 consumes only 3.4mW and

achieves 1.75LSꢀ INL maximum, no missing codes at

18 bits with 102dꢀ SNR.

REF

n

ꢀow Power: 314mW at 250ksps, 314µW at 250sps

REF

n

±02dꢁ SNR ꢂTypx at f = 2kHz

IN

n

–±26dꢁ THD ꢂTypx at f = 2kHz

n

Digital Gain Compression ꢂDGCx

n

Guaranteed Operation to 125°C

The LTC2376-18 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 250ksps

throughput with no cycle latency makes the LTC2376-18

ideally suited for a wide variety of high speed applications.

Aninternaloscillatorsetstheconversiontime,easingexter-

nal timing considerations. The LTC2376-18 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

n

2.5V Supply

n

Fully Differential Input Range V

REF

n

V

Input Range from 2.5V to 5.1V

REF

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

The LTC2376-18 features a unique digital gain compres-

sion(DGC)function,whicheliminatesthedriveramplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

applicaTions

n

Medical Imaging

n

High Speed Data Acquisition

n

Portable or Compact Instrumentation

Industrial Process Control

Low Power ꢀattery-Operated Instrumentation

ATE

function that maps zero-scale code from 0V to 0.1 • V

REF

n

and full-scale code from V

to 0.9 • V . For a typical

REF

n

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Typical applicaTion

32k Point FFT f_S= 250ksps, f_IN= 2kHz

2.5V 1.8V TO 5V

0

SNR = 102.3dB

–20

–40

THD = –126dB

SINAD = 102.2dB

SFDR = 127dB

10µF

0.1µF

V

OV

DD

CHAIN

RDL/SDI

SDO

DD

6800pF

3300pF

6800pF

V

REF

20Ω

–60

+

–

IN

+

–

–80

0V

LTC2376-18

SCK

REF

BUSY

CNV

REF/DGC

–100

–120

–140

–160

–180

IN

SAMPLE CLOCK

0V

V

REF

GND

REF

237618 TA01

2.5V TO 5.1V

47µF

(X5R, 0805 SIZE)

0

25

50

75

100

125

FREQUENCY (kHz)

237618 TA02

237618fa

1

For more information www.linear.com/LTC2376-18

LTC2376-18

absoluTe MaxiMuM raTings

ꢂNotes ±, 2x

Supply Voltage (V )...............................................2.8V

Digital Output Voltage

DD

Supply Voltage (OV )................................................6V

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

Reference Input (REF).................................................6V

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC2376C................................................ 0°C to 70°C

LTC2376I .............................................–40°C to 85°C

LTC2376H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Analog Input Voltage (Note 3)

+

–

IN , IN ......................... (GND –0.3V) to (REF + 0.3V)

REF/DGC Input (Note 3).... (GND –0.3V) to (REF + 0.3V)

Digital Input Voltage

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

pin conFiguraTion

TOP VIEW

CHAIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

OV

TOP VIEW

V

DD

CHAIN 1

16 GND

GND

SDO

V

2

15 OV

DD

+

GND 3

14 SDO

13 SCK

17

GND

IN

SCK

+

–

IN

4

5

–

IN

RDL/SDI

BUSY

GND

12 RDL/SDI

11 BUSY

10 GND

GND

REF

GND 6

REF 7

REF/DGC 8

9

CNV

REF/DGC

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

DE PACKAGE

T

= 150°C, θ = 110°C/W

16-LEAD (4mm × 3mm) PLASTIC DFN

JMAX

JA

T

= 150°C, θ = 40°C/W

JMAX

JA

EXPOSED PAD (PIN 17) IS GND, MUST ꢀE SOLDERED TO PCꢀ

orDer inForMaTion ^{http://www1linear1com/product/ꢀTC23.6-±8#orderinfo}

ꢀEAD FREE FINISH

TAPE AND REEꢀ

PART (ARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TE(PERATURE RANGE

0°C to 70°C

LTC2376CMS-18#PꢀF

LTC2376IMS-18#PꢀF

LTC2376HMS-18#PꢀF

LTC2376CDE-18#PꢀF

LTC2376IDE-18#PꢀF

LTC2376CMS-18#TRPꢀF 237618

LTC2376IMS-18#TRPꢀF 237618

LTC2376HMS-18#TRPꢀF 237618

LTC2376CDE-18#TRPꢀF 23768

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

16-Lead (4mm × 3mm) Plastic DFN

LTC2376IDE-18#TRPꢀF

23768

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPꢀF suffix.

237618fa

2

For more information www.linear.com/LTC2376-18

LTC2376-18

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ

V +

PARA(ETER

CONDITIONS

(Note 5)

(IN

–0.05

TYP

(AX

UNITS

+

l

Absolute Input Range (IN )

V

+ 0.05

V

IN

REF

–

V –

IN

Absolute Input Range (IN )

(Note 5)

+ 0.05

V + – V – Input Differential Voltage Range

V

IN

= V + – V –

–V

+V

REF

IN

REF

V

CM

Common-Mode Input Range

V

/2–

V /2

REF

V

/2+

REF

0.1

l

I

Analog Input Leakage Current

Analog Input Capacitance

1

µA

IN

C

Sample Mode

Hold Mode

45

5

pF

IN

CMRR

Input Common Mode Rejection Ratio

f

IN

= 125kHz

86

dꢀ

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ PARA(ETER

CONDITIONS

(IN

18

TYP

(AX

UNITS

ꢀits

l

Resolution

No Missing Codes

18

ꢀits

Transition Noise

0.7

0.5

0.1

0

LSꢀ

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

ꢀipolar Zero-Scale Error

ꢀipolar Zero-Scale Error Drift

ꢀipolar Full-Scale Error

ꢀipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–1.75

–0.5

–8

1.75

0.5

8

LSꢀ

DNL

ꢀZE

LSꢀ

3

mLSꢀ/°C

LSꢀ

l

FSE

–40

7

40

0.05

ppm/°C

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –±dꢁFS1 ꢂNotes 4, 8x

SY(ꢁOꢀ PARA(ETER

CONDITIONS

(IN

98.5

98

TYP

102

(AX

UNITS

dꢀ

l

SINAD

SNR

Signal-to-(Noise + Distortion) Ratio

f

IN

f

IN

= 2kHz, V = 5V

REF

= 2kHz, V = 5V, (H-Grade)

dꢀ

REF

l

Signal-to-Noise Ratio

f

IN

f

IN

f

IN

= 2kHz, V = 5V

99.3

97.5

94.1

102

100

97

dꢀ

REF

= 2kHz, V = 5V, REF/DGC = GND

REF

= 2kHz, V = 2.5V

REF

l

f

IN

f

IN

f

IN

= 2kHz, V = 5V, (H-Grade)

98.8

97.1

93.6

102

100

97

dꢀ

REF

= 2kHz, V = 5V, REF/DGC = GND, (H-Grade)

REF

= 2kHz, V = 2.5V, (H-Grade)

REF

l

THD

Total Harmonic Distortion

f

IN

f

IN

f

IN

= 2kHz, V = 5V

–126

–127

–124

–106

–103

–106

dꢀ

REF

= 2kHz, V = 5V, REF/DGC = GND

REF

= 2kHz, V = 2.5V

REF

l

f

IN

f

IN

f

IN

= 2kHz, V = 5V, (H-Grade)

–126

–127

–124

–104

–100

–104

dꢀ

REF

= 2kHz, V = 5V, REF/DGC = GND, (H-Grade)

REF

= 2kHz, V = 2.5V, (H-Grade)

REF

l

SFDR

Spurious Free Dynamic Range

–3dꢀ Input ꢀandwidth

Aperture Delay

f

= 2kHz, V = 5V

105

127

34

dꢀ

MHz

ps

IN

REF

500

4

Aperture Jitter

ps

Transient Response

Full-Scale Step

3.460

µs

237618fa

3

For more information www.linear.com/LTC2376-18

LTC2376-18

reFerence inpuT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ

PARA(ETER

CONDITIONS

(Note 5)

(IN

TYP

(AX

5.1

UNITS

l

V

Reference Voltage

2.5

V

mA

V

REF

I

Reference Input Current

High Level Input Voltage REF/DGC Pin

Low Level Input Voltage REF/DGC Pin

(Note 9)

0.16

0.2

V

IHDGC

V

ILDGC

0.8V

REF

0.2V

V

REF

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ PARA(ETER

CONDITIONS

(IN

TYP

(AX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OV

IH

IL

DD

0.2 • OV

V

DD

I

V

= 0V to OV

DD

–10

10

µA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –500µA

O

OV – 0.2

DD

V

OH

OL

I = 500µA

O

0.2

10

V

I

V

= 0V to OV

DD

–10

µA

mA

OZ

OUT

= 0V

= OV

–10

10

SOURCE

SINK

DD

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ

PARA(ETER

Supply Voltage

CONDITIONS

(IN

2.375

1.71

TYP

(AX

2.625

5.25

1.7

UNITS

l

V

DD

2.5

V

OV

DD

I

Supply Current

Power Down Mode

250ksps Sample Rate

1.36

0.05

0.9

mA

µA

VDD

OVDD

PD

250ksps Sample Rate (C = 20pF)

L

+ I

l

Conversion Done (I

+ I )

REF

90

140

VDD

OVDD

REF

+ I , H-Grade)

0.9

µA

PD

P

Power Dissipation

Power Down Mode

250ksps Sample Rate

3.4

2.25

4.25

225

315

mW

µW

D

Conversion Done (I

+ I

+ I )

REF

VDD

OVDD

+ I , H-Grade)

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ

PARA(ETER

CONDITIONS

(IN

TYP

(AX

250

3

UNITS

ksps

µs

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

1.9

Acquisition Time

t

= t

– t (Note 10)

HOLD

3.460

µs

ACQ

CYC

Maximum Time ꢀetween Acquisitions

Time ꢀetween Conversions

CNV High Time

540

13

ns

HOLD

CYC

4

µs

20

ns

CNVH

ꢀUSYLH

CNVL

QUIET

CNV to ꢀUSY Delay

C = 20pF

L

ns

Minimum Low Time for CNV

SCK Quiet Time from CNV

(Note 11)

(Note 10)

20

ns

237618fa

4

For more information www.linear.com/LTC2376-18

LTC2376-18

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C1 ꢂNote 4x

SY(ꢁOꢀ

PARA(ETER

CONDITIONS

(IN

10

4

TYP

(AX

UNITS

ns

l

t

SCK Period

(Notes 11, 12)

SCK

SCK High Time

ns

SCKH

SCK Low Time

4

ns

SCKL

SDI Setup Time From SCK

SDI Hold Time From SCK

SCK Period in Chain Mode

SDO Data Valid Delay from SCK

SDO Data Remains Valid Delay from SCK

SDO Data Valid Delay from ꢀUSY

ꢀus Enable Time After RDL

ꢀus Relinquish Time After RDL

(Note 11)

4

ns

SSDISCK

HSDISCK

SCKCH

DSDO

HSDO

DSDOꢀUSYL

EN

1

ns

t

= t

+ t (Note 11)

DSDO

13.5

ns

SCKCH

SSDISCK

C = 20pF (Note 11)

L

9.5

ns

C = 20pF (Note 10)

L

1

ns

C = 20pF (Note 10)

L

5

ns

(Note 11)

16

13

ns

DIS

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may effect device

reliability and lifetime.

Note .: ꢀipolar zero-scale error is the offset voltage measured from

–0.5LSꢀ when the output code flickers between 00 0000 0000 0000 0000

and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of

–FS or +FS untrimmed deviation from ideal first and last code transitions

and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 8: All specifications in dꢀ are referred to a full-scale 5V input with a

5V reference voltage.

Note 3: When these pin voltages are taken below ground or above REFor

OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 100mA below ground or above REFor OV without

latch-up.

Note 9: f

= 250kHz, I varies proportionately with sample rate.

SMPL REF

DD

Note ±0: Guaranteed by design, not subject to test.

Note ±±: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

Note 4: V = 2.5V, OV = 2.5V, REF = 5V, V = 2.5V, f

= 250kHz,

DD

CM

SMPL

DD

REF/DGC = V

.

REF

and OV = 5.25V.

DD

Note 5: Recommended operating conditions.

Note ±2: t

of 10ns maximum allows a shift clock frequency up to

SCK

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

100MHz for rising capture.

0.8*OV

DD

t

WIDTH

0.2*OV

DD

50%

t

DELAY

237618 F01

0.8*OV

0.2*OV

DD

0.2*OV

DD

Figure ±1 Voltage ꢀevels for Timing Specifications

237618fa

5

For more information www.linear.com/LTC2376-18

LTC2376-18

Typical perForMance characTerisTics ^T_A^{= 25°C, V}_DD= 215V, OV_DD= 215V, V_C(= 215V,

REF = 5V, f_S(Pꢀ= 250ksps, unless otherwise noted1

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

1.5

1.0

0.5

0.4

80000

70000

60000

50000

40000

30000

20000

10000

0

σ = 0.7

0.3

0.2

0.5

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–131072 –65536

0

65536

131072

–131072 –65536

0

65536

131072

–2

–1

0

1

2

3

OUTPUT CODE

CODE

237618 G02

237618 G01

237618 G03

THD, Harmonics

32k Point FFT f_S= 250ksps,

f_IN= 2kHz

vs Input Frequency

SNR, SINAD vs Input Frequency

0

–20

103

102

101

100

99

–80

–90

SNR = 102.3dB

THD

2ND

3RD

SNR

THD = –126dB

SINAD = 102.2dB

SFDR = 127dB

–40

SINAD

–60

–100

–110

–120

–130

–140

–80

98

–100

–120

–140

–160

–180

97

96

95

94

93

0

25

50

75

100

125

0

25

50

75

100

125

0

25

50

75

100

125

FREQUENCY (kHz)

237618 G05

237618 G06

237618 TA02

SNR, SINAD vs Input level,

f_IN= 2kHz

SNR, SINAD vs Reference

Voltage, f_IN= 2kHz

THD, Harmonics vs Reference

Voltage, f_IN= 2kHz

103

102

101

100

99

103.0

102.5

102.0

101.5

101.0

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

SNR

THD

2ND

SINAD

3RD

98

97

2.5

3.0

3.5

4.0

4.5

5.0

–40

–30

–20

–10

0

2.5

3.0

3.5

4.0

4.5

5.0

REFERENCE VOLTAGE (V)

INPUT LEVEL (dB)

REFERENCE VOLTAGE (V)

237618 G08

237618 G07

237618 G09

237618fa

6

For more information www.linear.com/LTC2376-18

LTC2376-18

Typical perForMance characTerisTics ^T_A^{= 25°C, V}_DD= 215V, OV_DD= 215V, V_C(= 215V,

REF = 5V, f_S(Pꢀ= 250ksps, unless otherwise noted1

SNR, SINAD vs Temperature,

f_IN= 2kHz

THD, Harmonics vs Temperature,

f_IN= 2kHz

INꢀ/DNꢀ vs Temperature

105.0

104.5

104.0

103.5

103.0

102.5

102.0

101.5

101.0

100.5

100.0

–115

–120

–125

–130

–135

–140

1.0

0.5

SNR

MAX INL

THD

MAX DNL

MIN DNL

SINAD

3RD

0

2ND

MIN INL

–0.5

–1.0

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

237618 G10

237618 G11

237618 G12

Supply Current vs Temperature

Full-Scale Error vs Temperature

Offset Error vs Temperature

2.0

1.5

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

8

6

I

VDD

–FS

1.0

4

0.5

2

0

–0.5

–1.0

–1.5

–2.0

–2

–4

–6

–8

I

REF

+FS

I

OVDD

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

237618 G14

237618 G15

237618 G13

Reference Current

vs Reference Voltage

Shutdown Current vs Temperature

C(RR vs Input Frequency

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

0.18

0.16

0.14

0.12

0.1

I

+ I

VDD OVDD REF

0.08

0.06

0.04

0.02

0

2.5

3.0

3.5

4.0

4.5

5.0

0

20

40

60

80

100

120

–55 –35 –15

5

25 45 65 85 105 125

REFERENCE VOLTAGE (V)

FREQUENCY (kHz)

TEMPERATURE (°C)

237618 G16

237618 G17

237618 G18

237618fa

7

For more information www.linear.com/LTC2376-18

LTC2376-18

pin FuncTions

CHAIN ꢂPin ±x: Chain Mode Selector Pin. When low, the

LTC2376-18 operates in normal mode and the RDL/SDI

input pin functions to enable or disable SDO. When high,

the LTC2376-18 operates in chain mode and the RDL/SDI

pin functions as SDI, the daisy-chain serial data input.

ꢁUSY ꢂPin ±±x: ꢀUSY Indicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished. Logic levels are determined by 0V .

DD

RDꢀ/SDI ꢂPin ±2x: When CHAIN is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

Logic levels are determined by 0V .

DD

V

ꢂPin 2x: 2.5V Power Supply. The range of V is

DD

2.375Vto2.625V. ꢀypassV toGNDwitha10µFceramic

DD

capacitor.

determined by 0V .

DD

GND ꢂPins 3, 6, ±0 and ±6x: Ground.

SCKꢂPin±3x:SerialDataClockInput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSꢀ

+

–

IN , IN ꢂPins 4, 5x: Positive and Negative Differential

Analog Inputs.

first. Logic levels are determined by 0V .

DD

REF ꢂPin .x: Reference Input. The range of REF is 2.5V

to 5.1V. This pin is referred to the GND pin and should be

decoupledcloselytothepinwitha 47µFceramiccapacitor

(X5R, 0805 size).

SDOꢂPin±4x:SerialDataOutput. Theconversionresultor

daisy-chain data is output on this pin on each rising edge

of SCK MSꢀ first. The output data is in 2’s complement

format. Logic levels are determined by 0V .

DD

REF/DGCꢂPin8x:WhentiedtoREF,digitalgaincompression

is disabled and the LTC2376-18 defines full-scale accord-

OV ꢂPin ±5x: I/O Interface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

ing to the V

analog input range. When tied to GND,

REF

the same supply as the host interface (1.8V, 2.5V, 3.3V,

digital gain compression is enabled and the LTC2376-18

or 5V). ꢀypass OV to GND with a 0.1µF capacitor.

DD

defines full-scale with inputs that swing between 10% and

90% of the V analog input range.

GND ꢂEꢃposed Pad Pin ±. – DFN Package Onlyx: Ground.

Exposedpadmustbesoldereddirectlytothegroundplane.

REF

CNV ꢂPin 9x: Convert Input. A rising edge on this input

powers up the part and initiates a new conversion. Logic

levels are determined by 0V .

DD

FuncTional block DiagraM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 5V

LTC2376-18

CHAIN

SDO

RDL/SDI

SCK

+

IN

SPI

PORT

18-BIT SAMPLING ADC

–

IN

CNV

BUSY

REF/DGC

CONTROL LOGIC

GND

237618 BD01

237618fa

8

For more information www.linear.com/LTC2376-18

LTC2376-18

TiMing DiagraM

Conversion Timing Using the Serial Interface

CHAIN, RDL/SDI = 0

CNV

CONVERT

POWER-DOWN

BUSY

SCK

HOLD

ACQUIRE

D17 D16 D15 D2 D1 D0

SDO

237618 TD01

237618fa

9

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

OVERVIEW

TRANSFER FUNCTION

TheLTC2376-18isalownoise,lowpower,highspeed18-bit

successive approximation register (SAR) ADC. Operating

from a single 2.5V supply, the LTC2376-18 supports a

The LTC2376-18 digitizes the full-scale voltage of 2 × REF

18

into 2 levels, resulting in an LSꢀ size of 38µV with

REF = 5V. The ideal transfer function is shown in Figure 2.

The output data is in 2’s complement format.

large and flexible V fully differential input range with

REF

V

ranging from 2.5V to 5.1V, making it ideal for high

REF

performance applications which require a wide dynamic

range. The LTC2376-18 achieves 1.75LSꢀ INL max, no

missing codes at 18 bits and 102dꢀ SNR.

011...111

BIPOLAR

011...110

ZERO

000...001

000...000

111...111

111...110

Fast 250ksps throughput with no cycle latency makes

the LTC2376-18 ideally suited for a wide variety of high

speed applications. An internal oscillator sets the con-

version time, easing external timing considerations. The

LTC2376-18 dissipates only 3.4mW at 250ksps, while an

auto power-down feature is provided to further reduce

power dissipation during inactive periods.

100...001

FSR = +FS – –FS

1LSB = FSR/262144

100...000

–1 0V

LSB

INPUT VOLTAGE (V)

1

–FSR/2

FSR/2 – 1LSB

LSB

237618 F02

The LTC2376-18 features a unique digital gain compres-

sion(DGC)function,whicheliminatesthedriveramplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

Figure 21 ꢀTC23.6-±8 Transfer Function

ANAꢀOG INPUT

function that maps zero-scale code from 0V to 0.1 • V

The analog inputs of the LTC2376-18 are fully differential

in order to maximize the signal swing that can be digitized.

Theanaloginputscanbemodeledbytheequivalentcircuit

shown in Figure 3. The diodes at the input provide ESD

protection. In the acquisition phase, each input sees ap-

REF

and full-scale code from V

to 0.9 • V . For a typical

REF

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

proximately 45pF (C ) from the sampling CDAC in series

IN

with 40Ω (R ) from the on-resistance of the sampling

ON

CONVERTER OPERATION

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw a current spike while charging

The LTC2376-18 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

+

–

the C capacitors during acquisition. During conversion,

the analog inputs draw only a small leakage current.

converter (CDAC) is connected to the IN and IN pins to

sample the differential analog input voltage. A rising edge

ontheCNVpininitiatesaconversion.Duringtheconversion

phase, the 18-bit CDAC is sequenced through a succes-

sive approximation algorithm, effectively comparing the

sampled input with binary-weighted fractions of the refer-

IN

REF

C

45pF

IN

R

40Ω

ON

+

IN

ence voltage (e.g. V /2, V /4 … V /262144) using

REF

BIAS

VOLTAGE

the differential comparator. At the end of conversion, the

CDAC output approximates the sampled analog input. The

ADC control logic then prepares the 18-bit digital output

code for serial transfer.

REF

C

45pF

IN

R

40Ω

ON

–

237618 F03

Figure 31 The Equivalent Circuit for the

Differential Analog Input of the ꢀTC23.6-±8

237618fa

10

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LTC2376-18

applicaTions inForMaTion

INPUT DRIVE CIRCUITS

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

A low impedance source can directly drive the high im-

pedance inputs of the LTC2376-18 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC inputs

draw a current spike when entering acquisition.

Single-Ended-to-Differential Conversion

For best performance, a buffer amplifier should be used

to drive the analog inputs of the LTC2376-18. The ampli-

fier provides low output impedance, which produces fast

settling of the analog signal during the acquisition phase.

It also provides isolation between the signal source and

the current spike the ADC inputs draw.

Forsingle-endedinputsignals,asingle-endedtodifferential

conversion circuit must be used to produce a differential

signal at the inputs of the LTC2376-18. The LT6350 ADC

driver is recommended for performing single-ended-to-

differential conversions. The LT6350 is flexible and may

be configured to convert single-ended signals of various

amplitudes to the 5V differential input range of the

LTC2376-18. The LT6350 is also available in H-grade to

complement the extended temperature operation of the

LTC2376-18 up to 125°C.

Input Filtering

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

Figure 5a shows the LT6350 being used to convert a 0V

to 5V single-ended input signal. In this case, the first

amplifierisconfiguredasaunitygainbufferandthesingle-

ended input signal directly drives the high-impedance

input of the amplifier. As shown in the FFT of Figure 5b,

the LT6350 drives the LTC2376-18 to near full data sheet

performance.

LPF2

6800pF

SINGLE-ENDED-

20Ω

LPF1

INPUT SIGNAL

+

–

IN

500Ω

3300pF

The LT6350 can also be used to buffer and convert large

true bipolar signals which swing below ground to the 5V

differential input range of the LTC2376-18 in order to

maximize the signal swing that can be digitized. Figure 6a

shows the LT6350 being used to convert a 10V true bi-

polar signal for use by the LTC2376-18. In this case, the

first amplifier in the LT6350 is configured as an inverting

amplifier stage, which acts to attenuate and level shift the

inputsignaltothe0Vto5VinputrangeoftheLTC2376-18.

In the inverting amplifier configuration, the single-ended

input signal source no longer directly drives a high imped-

ance input of the first amplifier. The input impedance is

LTC2376-18

6600pF

IN

20Ω

237618 F04

SINGLE-ENDED- 6800pF

TO-DIFFERENTIAL

DRIVER

BW = 48kHz

BW = 600kHz

Figure 41 Input Signal Chain

Another filter network consisting of LPF2 should be used

between the buffer and ADC input to both minimize the

noisecontributionofthebufferandtohelpminimizedistur-

bances reflected into the buffer from sampling transients.

Long RC time constants at the analog inputs will slow

down the settling of the analog inputs. Therefore, LPF2

requires a wider bandwidth than LPF1. A buffer amplifier

with a low noise density must be selected to minimize

degradation of the SNR.

instead set by resistor R . R must be chosen carefully

IN IN

based on the source impedance of the signal source.

Higher values of R tend to degrade both the noise and

IN

distortion of the LT6350 and LTC2376-18 as a system.

237618fa

11

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

V

CM

LT6350

5V

0V

OUT1

4

5V

0V

R2 = 499Ω

R

INT

200pF

8

1

+

–

LT6350

5V

0V

OUT1

OUT2

4

5

5V

0V

–

+

R

INT

R

INT

8

+

–

OUT2

5

10µF

R4 = 402Ω

R3 = 2k

2

5V

0V

–

+

–

V

= V /2

REF

CM

1

2

237618 F05a

10V

0V

–10V

R

= 2k

R1 = 499Ω

IN

+

–

V

= V /2

REF

CM

Figure 5a1 ꢀT6350 Converting a 0V-5V Single-Ended

Signal to a ±5V Differential Input Signal

220pF

237618 F06a

Figure 6a1 ꢀT6350 Converting a ±±0V Single-Ended Signal

to a ±5V Differential Input Signal

0

SNR = 101dB

–20

–40

THD = –108.1dB

SINAD = 100.4dB

SFDR = 108.5dB

0

SNR = 100.8dB

–20

–40

THD = –100.1dB

SINAD = 97.9dB

SFDR = 102.3dB

–60

–80

–60

–100

–120

–140

–160

–180

–80

–100

–120

–140

–160

–180

0

25

50

75

100

125

FREQUENCY (kHz)

237618 F05b

0

25

50

75

100

125

Figure 5b1 32k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure 5a

FREQUENCY (kHz)

237618 F06b

Figure 6b1 32k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure 6a

R1, R2, R3 and R4 must be selected in relation to R to

IN

achievethedesiredattenuationandtomaintainabalanced

input impedance in the first amplifier. Table 1 shows the

5V

LT6203

5V

0V

3

2

+

–

resulting SNR and THD for several values of R , R1, R2,

IN

1

7

0V

R3 and R4 in this configuration. Figure 6b shows the re-

sulting FFT when using the LT6350 as shown in Figure 6a.

5V

0V

5V

0V

5

6

+

–

Table ±1 SNR, THD vs R_INfor ±±0V Single-Ended Input Signal1

R

R±

ꢂΩx

R2

ꢂΩx

R3

ꢂΩx

R4

ꢂΩx

SNR

ꢂdꢁx

THD

ꢂdꢁx

IN

ꢂΩx

237618 F07

2k

499

2k

402

2k

100.8

100.5

100.2

–100

–92

Figure .1 ꢀT6203 ꢁuffering a Fully Differential Signal Source

10k

100k

2.49k

24.9k

2.49k

24.9k

10k

100k

20k

–98

Digital Gain Compression

The LTC2376-18 offers a digital gain compression (DGC)

feature which defines the full-scale input swing to be be-

Fully Differential Inputs

tween 10% and 90% of the V analog input range. To

REF

To achieve the full distortion performance of the

LTC2376-18,alowdistortionfullydifferentialsignalsource

driven through the LT6203 configured as two unity gain

buffers as shown in Figure 7 can be used to get the full

data sheet THD specification of –126dꢀ.

enable digital gain compression, bring the REF/DGC pin

low. This feature allows the LT6350 to be powered off of

a single +5.5V supply since each input swings between

0.5V and 4.5V as shown in Figure 8. Needing only one

237618fa

12

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

5V

many applications. With its small size, low power and

highaccuracy,theLTC6655-5isparticularlywellsuitedfor

use with the LTC2376-18. The LTC6655-5 offers 0.025%

(max) initial accuracy and 2ppm/°C (max) temperature

coefficientforhighprecisionapplications.TheLTC6655-5

is fully specified over the H-grade temperature range and

complements the extended temperature operation of the

LTC2376-18 up to 125°C. We recommend bypassing the

LTC6655-5 with a 47µF ceramic capacitor (X5R, 0805

size) close to the REF pin.

4.5V

0.5V

0V

237618 F08

Figure 81 Input Swing of the ꢀTC23.6 with Gain

Compression Enabled

positive supply to power the LT6350 results in additional

power savings for the entire system.

TheREFpinoftheLTC2376-18drawscharge(Q

)from

CONV

Figure 9a shows how to configure the LT6350 to accept a

10V true bipolar input signal and attenuate and level shift

the signal to the reduced input range of the LTC2376-18

when digital gain compression is enabled. Figure 9b

shows an FFT plot with the LTC2376-18 being driven by

the LT6350 with digital gain compression enabled.

the 47µF bypass capacitor during each conversion cycle.

The reference replenishes this charge with a DC current,

I

= Q

/t . The DC current draw of the REF pin,

REF

CONV CYC

, depends on the sampling rate and output code. If

the LTC2376-18 is used to continuously sample a signal

at a constant rate, the LTC6655-5 will keep the deviation

of the reference voltage over the entire code span to less

than 0.5LSꢀs.

ADC REFERENCE

The LTC2376-18 requires an external reference to define

its input range. A low noise, low temperature drift refer-

enceiscriticaltoachievingthefulldatasheetperformance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

When idling, the REF pin on the LTC2376-18 draws only

a small leakage current (< 1µA). In applications where a

burst of samples is taken after idling for long periods as

shown in Figure 10, I quickly goes from approximately

REF

5.5V

V

LTC6655-5

IN

0

–20

OUT_F

OUT_S

SNR = 98.4dB

THD = –96.9dB

SINAD = 95.2dB

SFDR = 99.2dB

5V

1k

–40

47µF

V

CM

–60

4.5V

0.5V

2.5V

1k

10µF

3

+

–80

V

6800pF

LT6350

OUT1

OUT2

6.04k

4.32k

REF

V

4

DD

LTC2376-18

REF/DGC

–100

–120

–140

–160

–180

+

–

20Ω

IN

R

INT

8

+

–

INT

10µF

R

3300pF

20Ω

–

+

5

6

1

4.5V

2

–

237618 F09a

V

6800pF

10V

0V

–10V

= 15k

3.01k

IN

0

25

50

75

100

125

0.5V

V

CM

FREQUENCY (kHz)

237618 F09b

Figure 9a1 ꢀT6350 Configured to Accept a ±±0V Input Signal While Running Off of a

Single 515V Supply When Digital Gain Compression Is Enabled in the ꢀTC23.6-±8

Figure 9b1 32k Point FFT Plot

with f_IN= 2kHz for Circuit Shown

in Figure 9a

CNV

IDLE

PERIOD

IDLE

PERIOD

237618 F10

Figure ±01 CNV Waveform Showing ꢁurst Sampling

237618fa

13

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

0µA to a maximum of 0.2mA at 250ksps. This step in DC

currentdrawtriggersatransientresponseinthereference

that must be considered since any deviation in the refer-

ence output voltage will affect the accuracy of the output

code. In applications where the transient response of the

reference is important, the fast settling LTC6655-5 refer-

ence is also recommended.

Signal-to-Noise Ratio ꢂSNRx

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 11 shows

that the LTC2376-18 achieves a typical SNR of 102dꢀ at

a 250kHz sampling rate with a 2kHz input.

DYNA(IC PERFOR(ANCE

Total Harmonic Distortion ꢂTHDx

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2376-18 provides

guaranteed tested limits for both AC distortion and noise

measurements.

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

V2²+ V3²+ V4²+…+ V_N²

THD=20log

V1

Signal-to-Noise and Distortion Ratio ꢂSINADx

where V1 is the RMS amplitude of the fundamental fre-

quencyandV2throughV aretheamplitudesofthesecond

N

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure11showsthattheLTC2376-18achieves

a typical SINAD of 102dꢀ at a 250kHz sampling rate with

a 2kHz input.

through Nth harmonics.

POWER CONSIDERATIONS

The LTC2376-18 provides two power supply pins: the

2.5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2376-18 to communicate with any digital

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems.

0

SNR = 102.3dB

–20

–40

THD = –126dB

SINAD = 102.2dB

SFDR = 127dB

Power Supply Sequencing

–60

The LTC2376-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2376-18

has a power-on-reset (POR) circuit that will reset the

LTC2376-18 at initial power-up or whenever the power

supply voltage drops below 1V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 20µs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

–80

–100

–120

–140

–160

–180

0

25

50

75

100

125

FREQUENCY (kHz)

237618 F11

Figure ±±1 32k Point FFT with f_IN= 2kHz of the ꢀTC23.6-±8

time will produce invalid results.

237618fa

14

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

TI(ING AND CONTROꢀ

DIGITAꢀ INTERFACE

The LTC2376-18 has a serial digital interface. The flexible

CNV Timing

OV supplyallowstheLTC2376-18tocommunicatewith

DD

The LTC2376-18 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

the LTC2376-18. Once a conversion has been initiated,

it cannot be restarted until the conversion is complete.

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

ꢀUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within 40ns from the start of the conversion or after the

conversion has been completed. Once the conversion has

completed, the LTC2376-18 powers down and begins

acquiring the input signal.

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

20MHz, a 250ksps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D17 remains valid till the first rising edge of SCK.

The serial interface on the LTC2376-18 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2376-18. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy chained.

Acquisition

AproprietarysamplingarchitectureallowstheLTC2376-18

to begin acquiring the input signal for the next conver-

sion 527ns after the start of the current conversion. This

extends the acquisition time to 3.460µs, easing settling

requirementsandallowingtheuseofextremelylowpower

ADC drivers. (Refer to the Timing Diagram.)

1.6

1.4

1.2

I

VDD

1.0

0.8

0.6

0.4

0.2

0

Internal Conversion Clock

The LTC2376-18 has an internal clock that is trimmed to

achieve a maximum conversion time of 3µs.

I

REF

Auto Power-Down

I

OVDD

0

50

100

150

200

250

The LTC2376-18 automatically powers down after a

conversion has been completed and powers up once a

new conversion is initiated on the rising edge of CNV.

During power down, data from the last conversion can

be clocked out. To minimize power dissipation during

power down, disable SDO and turn off SCK. The auto

power-down feature will reduce the power dissipation of

the LTC2376-18 as the sampling frequency is reduced.

Since power is consumed only during a conversion, the

LTC2376-18remainspowered-downforalargerfractionof

SAMPLING RATE (kHz)

237618 F12

Figure ±21 Power Supply Current of the ꢀTC23.6-±8

Versus Sampling Rate

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 12.

237618fa

15

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LTC2376-18

applicaTions inForMaTion

Normal (ode, Single Device

Figure 13 shows a single LTC2376-18 operated in normal

mode with CHAIN and RDL/SDI tied to ground. With RDL/

SDI grounded, SDO is enabled and the MSꢀ(D17) of the

new conversion data is available at the falling edge of

ꢀUSY.ThisisthesimplestwaytooperatetheLTC2376-18.

When CHAIN = 0, the LTC2376-18 operates in normal

mode. In normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

high impedance. If RDL/SDI is low, SDO is driven.

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

LTC2376-18

SCK

RDL/SDI

SDO

DATA IN

CLK

237618 F13a

POWER-DOWN

ACQUIRE

CONVERT

POWER-DOWN

ACQUIRE

CONVERT

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

HOLD

ACQ

t

= t

– t

ACQ CYC HOLD

t

CONV

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

16

17

18

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D17

D16

D15

D1

D0

237618 F13

Figure ±31 Using a Single ꢀTC23.6-±8 in Normal (ode

237618fa

16

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

Normal (ode, (ultiple Devices

Since SDO is shared, the RDL/SDI input of each ADC must

be used to allow only one LTC2376-18 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure14,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSꢀ of the selected

device is output onto SDO.

Figure 14 shows multiple LTC2376-18 devices operating

in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.

ꢀy sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2376-18

B

LTC2376-18

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

237618 F14a

POWER-DOWN

ACQUIRE

CONVERT

POWER-DOWN

ACQUIRE

CONVERT

CHAIN = 0

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

SCK

SDO

1

2

3

14

15

16

17

18

19

30

31

32

t

SCKL

HSDO

t

DIS

DSDO

t

EN

Hi-Z

D15

D14

D13

D1

A

D0

A

D15

D14

D13

D1

B

D0

B

A

B

237618 F14

Figure ±41 Normal (ode With (ultiple Devices Sharing CNV, SCK and SDO

237618fa

17

For more information www.linear.com/LTC2376-18

LTC2376-18

applicaTions inForMaTion

Chain (ode, (ultiple Devices

This is useful for applications where hardware constraints

may limit the numberoflines needed to interface toa large

number of converters. Figure 15 shows an example with

two daisy-chained devices. The MSꢀ of converter A will

appear at SDO of converter ꢀ after 18 SCK cycles. The

MSꢀ of converter A is clocked in at the SDI/RDL pin of

converter ꢀ on the rising edge of the first SCK.

When CHAIN = OV , the LTC2376-18 operates in chain

DD

mode.Inchainmode,SDOisalwaysenabledandRDL/SDI

serves as the serial data input pin (SDI) where daisy-chain

data output from another ADC can be input.

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2376-18

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

237618 F15a

POWER-DOWN

ACQUIRE

CONVERT

POWER-DOWN

ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

SCK

t

SCKCH

t

QUIET

SCKH

1

2

3

16

17

18

19

20

34

35

36

t

SCKL

t

HSDO

SSDISCK

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D17

D16

D15

D1

D0

A

t

DSDOBUSYL

D17

D16

D15

D1

B

D17

D16

D1

A

D0

A

SDO

B

A

B

237618 F15

Figure ±51 Chain (ode Timing Diagram

237618fa

18

For more information www.linear.com/LTC2376-18

LTC2376-18

boarD layouT

To obtain the best performance from the LTC2376-18

a printed circuit board is recommended. Layout for the

printed circuit board (PCꢀ) should ensure the digital and

analog signal lines are separated as much as possible. In

particular,careshouldbetakennottorunanydigitalclocks

orsignalsalongsideanalogsignalsorunderneaththeADC.

Recommended ꢀayout

ThefollowingisanexampleofarecommendedPCꢀlayout.

A single solid ground plane is used. ꢀypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1783A, the

evaluation kit for the LTC2376-18.

Partial Top Silkscreen

237618fa

19

For more information www.linear.com/LTC2376-18

LTC2376-18

boarD layouT

Partial ꢀayer ± Component Side

Partial ꢀayer 2 Ground Plane

237618fa

20

For more information www.linear.com/LTC2376-18

LTC2376-18

boarD layouT

Partial ꢀayer 3 PWR Plane

Partial ꢀayer 4 ꢁottom ꢀayer

237618fa

21

For more information www.linear.com/LTC2376-18

LTC2376-18

boarD layouT

Partial Schematic of Demoboard

D G C R E F /

R E F

8

7

1 5

2

1

G N D

D D

V

G N D 1 6

O V

G N D

1 0

G N D

6

3

2

1

3

2

1

237618fa

22

For more information www.linear.com/LTC2376-18

LTC2376-18

package DescripTion

Please refer to http://www1linear1com/product/ꢀTC23.6-±8#packaging for the most recent package drawings1

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)

0.70 0.05

3.30 0.05

ꢀ.70 0.05

3.60 0.05

2.20 0.05

PACKAGE

OUTLINE

0.25 0.05

0.45 BSC

3.ꢀ5 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.ꢀꢀ5

TYP

0.40 0.ꢀ0

4.00 0.ꢀ0

(2 SIDES)

9

ꢀ6

R = 0.05

TYP

3.30 0.ꢀ0

3.00 0.ꢀ0

(2 SIDES)

ꢀ.70 0.ꢀ0

PIN ꢀ NOTCH

R = 0.20 OR

0.35 × 45°

PIN ꢀ

TOP MARK

(SEE NOTE 6)

CHAMFER

(DEꢀ6) DFN 0806 REV Ø

8

ꢀ

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

3.ꢀ5 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

237618fa

23

For more information www.linear.com/LTC2376-18

LTC2376-18

package DescripTion

Please refer to http://www1linear1com/product/ꢀTC23.6-±8#packaging for the most recent package drawings1

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

237618fa

24

For more information www.linear.com/LTC2376-18

LTC2376-18

revision hisTory

REV

DATE

DESCRIPTION

PAGE NU(ꢁER

A

08/16 Updated graphs G01, G02, and G03

6

237618fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

For more information www.linear.com/LTC2376-18

LTC2376-18

Typical applicaTion

ꢀT6350 Configured to Accept a ±±0V Input Signal While Running Off of a Single 515V Supply When

Digital Gain Compression Is Enabled in the ꢀTC23.6-±8

5.5V

V

LTC6655-5

IN

OUT_F

OUT_S

5V

1k

47µF

V

CM

4.5V

0.5V

2.5V

10µF

3

+

V

6800pF

LT6350

OUT1

OUT2

6.04k

4.32k

REF

V

4

DD

LTC2376-18

REF/DGC

+

–

20Ω

IN

R

INT

8

+

–

INT

10µF

R

3300pF

20Ω

–

+

5

6

1

4.5V

2

–

237618 TA03

V

10V

0V

= 15k

3.01k

IN

0.5V

V

CM

–10V

relaTeD parTs

PART NU(ꢁER

DESCRIPTION

CO((ENTS

ADCs

LTC2379-18

18-ꢀit, 1.6Msps Serial, Low Power ADC

16-ꢀit, 2Msps Serial, Low Power ADC

2.5V Supply, Differential Input, 101.2dꢀ SNR, 5V Input Range,

DGC, MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16

2.5V Supply, Differential Input, 96.2dꢀ SNR, 5V Input Range, DGC,

MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2383-16/LTC2382-16/ 16-ꢀit, 1Msps/500ksps/250ksps Serial, Low Power ADC 2.5V Supply, Differential Input, 92dꢀ SNR, 2.5V Input Range, Pin

LTC2381-16

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2393-16/LTC2392-16/ 16-ꢀit, 1Msps/500ksps/250ksps Parallel/Serial ADC

LTC2391-16

5V Supply, Differential Input, 94dꢀ SNR, 4.096V Input Range, Pin

Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages

LTC1865/LTC1865L

LTC2361

16-ꢀit, 250ksps/150ksps 2-Channel µPower ADC

12-ꢀit, 250ksps, Serial ADC

5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-10 Package

2.35V to 3.6V, 3.3mW, 6- and 8-Lead TSOT-23 Packages

DACS

LTC2757

18-ꢀit, Single Parallel I

SoftSpan™ DAC

1LSꢀ INL/DNL, Software-Selectable Ranges, 7mm × 7mm

LQFP-48 Package

OUT

LTC2641

16-ꢀit/14-ꢀit/12-ꢀit Single Serial V

DAC

1LSꢀ INL/DNL, MSOP-8 Package, 0V to 5V Output

OUT

LTC2630

12-ꢀit/10-ꢀit/8-ꢀit Single V

DACs

SC70 6-Pin Package, Internal Reference, 1LSꢀ INL (12 ꢀits)

OUT

REFERENCES

LTC6655

Precision Low Drift Low Noise ꢀuffered Reference

5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

A(PꢀIFIERS

LT6350

Low Noise Single-Ended-to-Differential ADC Driver

Rail-to-Rail Input and Outputs, 240ns, 0.01% Settling Time

LT6200/LT6200-5/

LT6200-10

165MHz/800MHz/1.6GHz Op Amp with

Unity Gain/AV = 5/AV = 10

Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dꢀ at

1MHz, TSOT23-6 Package

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low 1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢀandwidth

Power Amplifiers

LTC1992

Low Power, Fully Differential Input/Output Amplifier/

Driver Family

1mA Supply Current

237618fa

LT 0816 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

26

For more information www.linear.com/LTC2376-18

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2376-18

●

LINEAR TECHNOLOGY CORPORATION 2011


型号：	LTC2376CMS-18#PBF
厂家：	Linear
描述：	LTC2376-18 - 18-Bit, 250ksps, Low Power SAR ADC with 102dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总26页 (文件大小：1461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2376CMS-18#PBF [Linear]

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