LTC2380CDE-24#PBF [Linear]
LTC2380-24 - 24-Bit, 1.5Msps/2Msps, Low Power SAR ADC with Integrated Digital Filter; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C;型号: | LTC2380CDE-24#PBF |
厂家: | Linear |
描述: | LTC2380-24 - 24-Bit, 1.5Msps/2Msps, Low Power SAR ADC with Integrated Digital Filter; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C |
文件: | 总32页 (文件大小:1296K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2380-24
24-Bit, 1.5Msps/2Msps,
Low Power SAR ADC with
Integrated Digital Filter
FEATURES
DESCRIPTION
The LTC®2380-24 is a low noise, low power, high speed
24-bit successive approximation register (SAR) ADC with
anintegrateddigitalaveragingfilter.Operatingfroma2.5V
n
Guaranteed 24-Bits No Missing Codes
n
±±0.ppꢀ INꢁ ꢂ(yp)
n
Integrated Digital Filter with Real-(iꢀe Averaging
n
ꢁow Power: 28ꢀW at 2Msps
1±±dB SNR ꢂ(yp) at 10.Msps
14.dB Dynaꢀic Range ꢂ(yp) at 3±0.sps
–117dB (HD ꢂ(yp) at f = 2kHz
.±Hz/6±Hz Rejection
Digital Gain Coꢀpression ꢂDGC)
Guaranteed Operation to 85°C
Single 2.5V Supply
supply, theLTC2380-24hasa V fullydifferentialinput
REF
n
range with V ranging from 2.5V to 5.1V. The LTC2380-
REF
n
24 consumes only 28mW and achieves 3.5ppm INL
n
maximum and no missing codes at 24 bits.
IN
n
n
n
n
n
n
The LTC2380-24 has an easy to use integrated digital
averaging filter that can average 1 to 65536 conversion
results real-time, dramatically improving dynamic range
from 101dB at 1.5Msps to 145dB at 30.5sps. No separate
programminginterfaceorconfigurationregisterisrequired.
Fully Differential Input Range Up to 5V
1.8V to 5V SPI-Compatible Serial I/O with Daisy-
Chain Mode
The high speed SPI-compatible serial interface supports
1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-
chain mode. The LTC2380-24 automatically powers down
betweenconversions,reducingpowerdissipationatlower
sampling rates.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673,
8810443 and Patents pending.
n
16-Lead MSOP and 4mm × 3mm DFN Packages
APPLICATIONS
n
Seismology
n
Energy Exploration
n
Medical Imaging
n
High Speed Data Acquisition
n
Industrial Process Control
n
ATE
TYPICAL APPLICATION
Integral Nonlinearity vs Output Code
3.0
2.5V 1.8V TO 5V
10µF
2.0
0.1µF
1.0
0
V
OV
DD
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
REF/DGC
DD
6800pF
3300pF
6800pF
V
V
REF
10Ω
10Ω
+
–
+
–
IN
0V
LTC2380-24
REF
IN
–1.0
–2.0
–3.0
SAMPLE CLOCK
0V
V
REF
GND
REF
238024 TA01
2.5V TO 5.1V
47µF
(X7R, 1210 SIZE)
–8388608 –4194304 0 4194304 8388607
OUTPUT CODE
238024 TA01b
238024fa
1
For more information www.linear.com/LTC2380-24
LTC2380-24
ABSOLUTE MAXIMUM RATINGS ꢂNotes 1, 2)
Supply Voltage (V )...............................................2.8V
Digital Output Voltage
DD
Supply Voltage (OV )................................................6V
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
DD
Reference Input (REF).................................................6V
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC2380C................................................ 0°C to 70°C
LTC2380I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Analog Input Voltage (Note 3)
+
–
IN , IN .............................(GND – 0.3V) to (REF + 0.3V)
REF/DGC Input (Note 3) ....(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
PIN CONFIGURATION
TOP VIEW
CHAIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OV
TOP VIEW
V
DD
DD
CHAIN 1
16 GND
GND
SDO
V
2
15 OV
DD
DD
+
GND 3
14 SDO
13 SCK
IN
SCK
17
+
–
IN
IN
4
5
–
GND
IN
RDL/SDI
BUSY
GND
12 RDL/SDI
11 BUSY
10 GND
GND
REF
GND 6
REF 7
REF/DGC 8
9
CNV
REF/DGC
CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
DE PACKAGE
T
JMAX
= 150°C, θ = 110°C/W
16-LEAD (4mm × 3mm) PLASTIC DFN
JA
T
= 150°C, θ = 40°C/W
JMAX
JA
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
ꢂhttp://www0linear0coꢀ/product/ꢁ(C238±-24#orderinfo)
ꢁEAD FREE FINISH
(APE AND REEꢁ
PAR( MARKING*
238024
PACKAGE DESCRIP(ION
16-Lead Plastic MSOP
16-Lead Plastic MSOP
(EMPERA(URE RANGE
0°C to 70°C
LTC2380CMS-24#PBF
LTC2380IMS-24#PBF
LTC2380CDE-24#PBF
LTC2380IDE-24#PBF
LTC2380CMS-24#TRPBF
LTC2380IMS-24#TRPBF
LTC2380CDE-24#TRPBF
LTC2380IDE-24#TRPBF
238024
–40°C to 85°C
0°C to 70°C
23804
16-Lead (4mm × 3mm) Plastic DFN
16-Lead (4mm × 3mm) Plastic DFN
23804
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
238024fa
2
For more information www.linear.com/LTC2380-24
LTC2380-24
ELECTRICAL CHARACTERISTICS (he l denotes the specifications which apply over the full operating
teꢀperature range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ
PARAME(ER
CONDI(IONS
MIN
−0.1
−0.1
(YP
MAX
UNI(S
+
+
l
l
l
l
V
V
V
V
Absolute Input Range (IN )
(Note 5)
V
V
+ 0.1
V
V
IN
IN
IN
REF
REF
–
+
–
Absolute Input Range (IN )
(Note 5)
+ 0.1
–
+
–
– V
Input Differential Voltage Range
Common Mode Input Range
Analog Input Leakage Current
Analog Input Capacitance
V
IN
= V – V
−V
REF
V
REF
V
IN
IN
IN
−V /2 – 0.1
REF
V /2
REF
V /2 + 0.1
REF
V
CM
I
0.01
μA
IN
C
IN
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
f
IN
= 1MHz
86
dB
CONVERTER CHARACTERISTICS (he l denotes the specifications which apply over the full operating
teꢀperature range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ PARAME(ER
CONDI(IONS
MIN
24
24
1
(YP
MAX
UNI(S
Bits
l
l
l
Resolution
No Missing Codes
Bits
N
Number of Averages
Transition Noise
65536
N = 1, f
= 1.5Msps
SMPL
SMPL
55.7
13.6
1.75
0.55
LSB
SMPL
RMS
RMS
RMS
RMS
N = 16, f
= 2Msps
LSB
LSB
LSB
N = 1024, f
N = 16384, f
= 2Msps
= 2Msps
SMPL
l
l
l
INL
Integral Linearity Error
N = 1, f
N = 1, f
N = 4, f
= 1.5Msps (Note 6)
= 1.5Msps REF/DGC = GND (Note 6)
= 2Msps (Note 6)
–3.5
–3.5
–3.5
0.5
0.5
0.5
3.5
3.5
3.5
ppm
ppm
ppm
SMPL
SMPL
SMPL
l
l
DNL
ZSE
Differential Linearity Error
Zero-Scale Error
(Note 7)
(Note 8)
–0.5
−10
0.2
0
0.5
10
LSB
ppm
Zero-Scale Error Drift
Full-Scale Error
7
ppb/°C
ppm
l
FSE
(Note 8)
−100
10
0.05
100
Full-Scale Error Drift
ppm/°C
DYNAMIC ACCURACY (he l denotes the specifications which apply over the full operating teꢀperature range,
otherwise specifications are at (A = 2.°C and AIN = –1dBFS0 ꢂNotes 4, 9)
SYMBOꢁ PARAME(ER
CONDI(IONS
MIN
(YP
MAX UNI(S
+
+
+
+
–
–
–
–
DR
Dynamic Range
IN = IN = V , V = 5V, N = 1, f
= 1.5Msps
101
113
131
141
145
dB
dB
dB
dB
dB
CM REF
SMPL
IN = IN = V , V = 5V, N = 16, f
= 2Msps
CM REF
CM REF
CM REF
CM REF
SMPL
SMPL
IN = IN = V , V = 5V, N = 1024, f
= 2Msps
IN = IN = V , V = 5V, N = 16384, f
= 2Msps
= 2Msps
SMPL
SMPL
+
–
IN = IN = V , V = 5V, N = 65536, f
l
SINAD
SNR
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
= 2kHz, V = 5V
97.5
100
dB
IN
REF
l
l
l
f
f
f
f
f
= 2kHz, V = 5V, N = 1, f = 1.5Msps
SMPL
97.5
95.5
92.5
100
98
dB
dB
dB
dB
dB
IN
IN
IN
IN
IN
REF
= 2kHz, V = 5V, REF/DGC = GND, N = 1, f
= 1.5Msps
= 2Msps
REF
SMPL
= 2kHz, V = 2.5V, N = 1, f
= 1.5Msps
95
REF
SMPL
IN
= 2kHz, V = 5V, N = 16, A = –20dBFS, f
112
130
REF
SMPL
= 100Hz, V = 5V, N = 1024, A = –20dBFS, f
= 2Msps
REF
IN
SMPL
l
l
l
THD
Total Harmonic Distortion
f
IN
f
IN
f
IN
f
IN
f
IN
= 2kHz, V = 5V, N = 1, f = 1.5Msps
SMPL
–117
–119
–117
–120
–120
–114
–114
–113
dB
dB
dB
dB
dB
REF
= 2kHz, V = 5V, REF/DGC = GND, N = 1, f
= 1.5Msps
= 2Msps
REF
REF
SMPL
= 2kHz, V = 2.5V, N = 1, f
= 1.5Msps
SMPL
IN
= 2kHz, V = 5V, N = 16, A = –20dBFS, f
REF
SMPL
= 100Hz, V = 5V, N = 1024, A = –20dBFS, f = 2Msps
SMPL
REF
IN
238024fa
3
For more information www.linear.com/LTC2380-24
LTC2380-24
DYNAMIC ACCURACY (he l denotes the specifications which apply over the full operating teꢀperature range,
otherwise specifications are at (A = 2.°C and AIN = –1dBFS0 ꢂNotes 4, 9)
SYMBOꢁ PARAME(ER
SFDR Spurious Free Dynamic Range
CONDI(IONS
= 2kHz, V = 5V
MIN
(YP
120
34
MAX UNI(S
l
f
114
dB
MHz
ps
IN
REF
–3dB Input Linear Bandwidth
Aperture Delay
500
4
Aperture Jitter
ps
RMS
Transient Response
Full–Scale Step
95
ns
REFERENCE INPUT (he l denotes the specifications which apply over the full operating teꢀperature range, otherwise
specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ PARAME(ER
CONDI(IONS
(Note 5)
MIN
(YP
MAX
5.1
UNI(S
l
l
l
l
V
Reference Voltage
2.5
V
mA
V
REF
REF
I
Reference Input Current
(Note 10)
1.9
2.1
V
V
High Level Input Voltage REF/DGC Pin
Low Level Input Voltage REF/DGC Pin
0.8V
REF
IHDGC
0.2V
V
ILDGC
REF
DIGITAL INPUTS AND DIGITAL OUTPUTS (he l denotes the specifications which apply over the
full operating teꢀperature range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ PARAME(ER
CONDI(IONS
MIN
(YP
MAX
UNI(S
V
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
0.8 • OV
IH
IL
DD
0.2 • OV
10
V
DD
I
V
IN
= 0V to OV
DD
–10
μA
pF
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I = –500µA
O
OV – 0.2
DD
V
OH
OL
I = 500µA
O
0.2
10
V
I
I
I
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
µA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SINK
DD
POWER REQUIREMENTS (he l denotes the specifications which apply over the full operating teꢀperature
range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ PARAME(ER
CONDI(IONS
MIN
2.375
1.71
(YP
MAX
2.625
5.25
13
UNI(S
l
l
l
V
Supply Voltage
Supply Voltage
2.5
V
V
DD
OV
DD
I
I
I
Supply Current
Supply Current
Power Down Mode
N = 4, f
N = 4, f
= 2Msps
11.2
0.4
1
mA
mA
μA
VDD
OVDD
PD
SMPL
SMPL
= 2Msps (C = 20pF)
L
l
Conversion Done (I
+ I
+ I
)
)
90
VDD
OVDD
REF
P
D
Power Dissipation
Power Down Mode
N = 4, f
= 2Msps
28
2.5
32.5
225
mW
μW
SMPL
Conversion Done (I
+ I
+ I
VDD
OVDD
REF
ADC TIMING CHARACTERISTICS (he l denotes the specifications which apply over the full operating
teꢀperature range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ
PARAME(ER
CONDI(IONS
MIN
(YP
MAX
2
UNI(S
l
l
f
f
Maximum Sampling Frequency
Output Data Rate
N ≥ 4
Msps
SMPL
ODR
1.5
Msps
238024fa
4
For more information www.linear.com/LTC2380-24
LTC2380-24
ADC TIMING CHARACTERISTICS(he l denotes the specifications which apply over the full operating
teꢀperature range, otherwise specifications are at (A = 2.°C0 ꢂNote 4)
SYMBOꢁ
PARAME(ER
CONDI(IONS
MIN
343
95
(YP
MAX
UNI(S
ns
l
l
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Conversion Time
392
CONV
ACQ
Acquisition Time
t
= t
– t
– t (Note 7)
BUSYLH
ns
ACQ
CYC
CONV
Time Between Conversions
CNV High Time
500
20
ns
CYC
ns
CNVH
CNVL
Minimum Low Time for CNV
CNV↑ to BUSY↑ Delay
SCK Quiet Time from CNV↑
SCK Period
(Note 11)
20
ns
C = 20pF
L
13
ns
BUSYLH
QUIET
SCK
(Note 7)
10
10
4
ns
(Notes 11, 12)
ns
SCK High Time
ns
SCKH
SCKL
SCK Low Time
4
ns
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
(Note 11)
(Note 11)
4
ns
SSDISCK
HSDISCK
SCKCH
DSDO
1
ns
t
= t
+ t (Note 11)
DSDO
13.5
ns
SCKCH
SSDISCK
l
l
l
C = 20pF, OV = 5.25V
7.5
8
9.5
ns
ns
ns
L
DD
DD
DD
C = 20pF, OV = 2.5V
L
C = 20pF, OV = 1.71V
L
l
l
l
l
t
t
t
t
SDO Data Remains Valid Delay from SCK↑ C = 20pF (Note 7)
1
ns
ns
ns
ns
HSDO
DSDOBUSYL
EN
L
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
C = 20pF (Note 7)
5
L
(Note 11)
(Note 11)
16
13
Bus Relinquish Time After RDL↑
DIS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
Note 7: Guaranteed by design, not subject to test.
Note 8: Bipolar zero-scale error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 0000 0000
and 1111 1111 1111 1111 1111 1111. Full-scale bipolar error is the
worst-case of –FS or +FS untrimmed deviation from ideal first and last code
transitions and includes the effect of offset error.
OV , they will be clamped by internal diodes. This product can handle
Note 9: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
DD
input currents up to 100mA below ground or above REF or OV without
DD
latchup.
Note 1±: f
= 2MHz, I varies proportionally with sample rate.
REF
SMPL
Note 4: V = 2.5V, OV = 2.5V, REF = 5V, V = 2.5V, f = 1.5MHz,
SMPL
DD
DD
CM
Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
DD
DD
REF/DGC = V , N = 1.
REF
and OV = 5.25V.
DD
Note .: Recommended operating conditions.
Note 12: t
of 10ns maximum allows a shift clock frequency up to
SCK
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
100MHz for rising edge capture.
0.8 • OV
t
DD
t
WIDTH
0.2 • OV
DD
50%
50%
t
DELAY
DELAY
238024 F01
0.8 • OV
0.8 • OV
0.2 • OV
DD
DD
DD
DD
0.2 • OV
Figure 10 Voltage ꢁevels for (iꢀing Specifications
238024fa
5
For more information www.linear.com/LTC2380-24
LTC2380-24
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
DC Histogram, N = 1
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.5Msps, N = 1, unless otherwise noted.
Integral Nonlinearity vs Output
Code
Differential Nonlinearity vs
Output Code
3.0
2.0
1.0
0.8
10000
σ = 55.7
0.6
8000
6000
4000
2000
0
0.4
1.0
0.2
0
–0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–300 –200 –100
0
100
200
300
–8388608 –4194304 0 4194304 8388607
–8388608 –4194304 0 4194304 8388607
OUTPUT CODE
OUTPUT CODE
CODE
238024 G01
238024 G02
238024 G03
DC Histogram, N = 16,
fSMPL = 2Msps
DC Histogram, N = 10 24,
fSMPL = 2Msps
DC Histogram, N = 16384,
fSMPL = 2Msps
10000
8000
6000
4000
2000
0
10000
8000
6000
4000
2000
0
10000
8000
6000
4000
2000
0
σ = 13.6
σ = 1.75
σ = 0.55
–300 –200 –100
0
100
200
300
–8 –6 –4 –2
0
2
4
6
8
–8 –6 –4 –2
0
2
4
6
8
CODE
CODE
CODE
238024 G04
238024 G05
238024 G06
DC Histogram, N = 65536,
fSMPL = 2Msps
128k Point FFT fSMPL = 1.5Msps,
fIN = 2kHz
128k Point FFT fSMPL = 2Msps,
fIN = 2kHz, N = 16
10000
8000
6000
4000
2000
0
0
–20
0
–20
SNR = 112.4dB
SNR = 100.3dB
THD = –117.3dB
SINAD = 100.2dB
SFDR = 117.4dB
σ = 0.33
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
–8 –6 –4 –2
0
2
4
6
8
0
150
300
450
600
750
0
12.5
25
37.5
50
62.5
CODE
FREQUENCY (kHz)
FREQUENCY (kHz)
238024 G07
238024 G08
238024 G09
238024fa
6
For more information www.linear.com/LTC2380-24
LTC2380-24
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.5Msps, N = 1, unless otherwise noted.
128k Point FFT fSMPL = 2Msps,
fIN = 10 0 Hz, N = 10 24
32k Point FFT fSMPL = 2Msps,
fIN = 10 Hz, N = 16384
8k Point FFT fSMPL = 2Msps,
IN+ = IN– = VCM, N = 65536
0
–20
0
–20
0
SNR = 130.2dB
DR = 145dB
SNR = 138.3dB
–20
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
244
488
732
976
0
15.3
30.5
45.8
61
0
3
6
9
12
15
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
238024 G10
238024 G11
238024 G12
Dynamic Range, Transition Noise
vs Number of Averages (N)
THD, Harmonics vs Input
Frequency
SNR, SINAD vs Input Frequency
150
140
130
120
110
100
100
101
100
99
98
97
96
95
94
93
92
–90
–100
–110
–120
–130
–140
TRANSITION NOISE
SNR
THD
10
1
3RD
SINAD
2ND
DYNAMIC RANGE
0.1
1
10
100
1k
10k
70k
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
NUMBER OF AVERAGES (N)
FREQUENCY (kHz)
FREQUENCY (kHz)
238024 G13
238024 G14
238024 G15
SNR, SINAD vs Input level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
101.5
101.0
100.5
100.0
99.5
101
100
99
–115.0
–120.0
–125.0
–130.0
–135.0
–140.0
–145.0
THD
SNR
3RD
SINAD
SNR
98
2ND
98
SINAD
97
96
99.0
95
–40
–30
–20
–10
0
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
INPUT LEVEL (dB)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
238024 G16
238024 G17
238024 G18
238024fa
7
For more information www.linear.com/LTC2380-24
LTC2380-24
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.5Msps, N = 1, unless otherwise noted.
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
INL vs Temperature
101.0
100.5
100.0
99.5
–110
–115
–120
–125
–130
–135
–140
4.0
3.0
THD
SNR
2.0
MAX INL
3RD
SINAD
1.0
0
–1.0
–2.0
–3.0
–4.0
MIN INL
2ND
99.0
98.5
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
85
5
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
238024 G19
238024 G20
238024 G21
Full-Scale Error vs Temperature
Zero-Scale Error vs Temperature
Supply Current vs Temperature
10
5
5
4
12
10
8
3
2
–FS
1
I
I
I
I
I
I
– f
= 2Msps, N = 4
= 1.5Msps, N = 1
= 2Msps, N = 4
= 1.5Msps, N = 1
= 2Msps, N = 4
= 1.5Msps, N = 1
VDD
VDD
SMPL
– f
SMPL
0
0
6
– f
OVDD SMPL
– f
OVDD SMPL
–1
–2
–3
–4
–5
+FS
– f
– f
REF
REF
SMPL
SMPL
4
–5
2
–10
0
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
238024 G22
238024 G23
238024 G24
Power-Down Current vs
Temperature
Reference Current vs Reference
Voltage
CMRR vs Input Frequency
10
8
100
95
90
85
80
75
70
2.0
1.5
1.0
0.5
I
+I
+I
VDD OVDD REF
f
= 2Msps
SMPL
6
4
f
= 1.5Msps
SMPL
2
0
–40
–15
10
35
60
85
0.001
0.01
0.1
1
10
2.5
3
3.5
4
4.5
TEMPERATURE (°C)
FREQUENCY (MHz)
REFERENCE VOLTAGE (V)
238024 G25
238024 G26
238024 G27
238024fa
8
For more information www.linear.com/LTC2380-24
LTC2380-24
PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2380-24 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2380-24 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OV .
DD
RDL/SDI (Pin 12): Bus Enabling Input/Serial Data Input
Pin. This pin serves two functions depending on whether
the part is operating in normal mode (CHAIN pin low) or
chain mode(CHAIN pin high). In normal mode, RDL/SDI
is a bus enabling input for the serial data I/O bus. When
RDL/SDI is low in normal mode, data is read out of the
ADC on the SDO pin. When RDL/SDI is high in normal
mode, SDO becomes Hi-Z and SCK is disabled. In chain
mode, RDL/SDI acts as a serial data input pin where data
from another ADC in the daisy chain is input. Logic levels
Logic levels are determined by OV .
DD
V
(Pin 2): 2.5V Power Supply. The range of V is
DD
DD
2.375V to 2.625V. Bypass V to GND with a 10µF ce-
DD
ramic capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
+
–
IN , IN (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
are determined by OV .
DD
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupledcloselytothepinwitha47µFceramiccapacitor
(X7R, 1210 size, 10V rating).
SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OV .
DD
REF/DGC (Pin 8): When tied to REF, digital gain compres-
sion is disabled and the LTC2380-24 defines full-scale ac-
SDO(Pin14):SerialDataOutput. Theconversionresultor
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
cordingtothe V analoginputrange.WhentiedtoGND,
REF
digital gain compression is enabled and the LTC2380-24
defines full-scale with inputs that swing between 10% and
format. Logic levels are determined by OV .
DD
90% of the V analog input range.
REF
OV (Pin 15): I/O Interface Digital Power. The range of
DD
CNV (Pin 9): Convert Input. A rising edge on this input
OV is 1.71V to 5.25V. This supply is nominally set to
DD
powers up the part and initiates a new conversion. Logic
the same supply as the host interface (1.8V, 2.5V, 3.3V,
levels are determined by OV .
or 5V). Bypass OV to GND with a 0.1µF capacitor.
DD
DD
GND (Exposed Pad Pin 17 –DFN Package Only): Ground.
Exposedpadmustbesoldereddirectlytothegroundplane.
238024fa
9
For more information www.linear.com/LTC2380-24
LTC2380-24
FUNCTIONAL BLOCK DIAGRAM
V
= 2.5V
DD
OV = 1.8V to 5V
DD
REF = 5V
CHAIN
+
–
IN
IN
+
SDO
24-BIT
SAMPLING ADC
DIGITAL
FILTER
SPI
PORT
RDL/SDI
SCK
–
CNV
BUSY
CONTROL LOGIC
REF/DGC
GND
238024 BD
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
CNV
POWER-DOWN AND ACQUIRE
BUSY
CONVERT
SCK
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
SDO
238024 TD01
DATA FROM CONVERSION
NUMBER OF SAMPLES
AVERAGED FOR DATA
238024fa
10
For more information www.linear.com/LTC2380-24
LTC2380-24
APPLICATIONS INFORMATION
OVERVIEW
011...111
011...110
BIPOLAR
ZERO
The LTC2380-24 is a low noise, low power, high speed
24-bit successive approximation register (SAR) ADC with
anintegrateddigitalaveragingfilter.Operatingfroma2.5V
000...001
000...000
111...111
111...110
supply, theLTC2380-24hasa V fullydifferentialinput
REF
range with V ranging from 2.5V to 5.1V. The LTC2380-
REF
100...001
100...000
24 consumes only 28mW and achieves 3.5ppm INL
FSR = +FS – –FS
1LSB = FSR/16777216
maximum and no missing codes at 24 bits.
–1 0V
1
–FSR/2
FSR/2 – 1LSB
LSB
LSB
The LTC2380-24 has an easy to use integrated digital
averaging filter that can average 1 to 65536 conversion
results real-time, dramatically improving dynamic range
from 101dB at 1.5Msps to 145dB at 30.5sps. No separate
programminginterfaceorconfigurationregisterisrequired.
INPUT VOLTAGE (V)
238024 F02
Figure 2. LTC2380 -24 Transfer Function
ANALOG INPUT
The analog inputs of the LTC2380-24 are fully differential
in order to maximize the signal swing that can be digitized.
Theanaloginputscanbemodeledbytheequivalentcircuit
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees ap-
The high speed SPI-compatible serial interface supports
1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-
chain mode. The LTC2380-24 automatically powers down
betweenconversions,reducingpowerdissipationatlower
sampling rates.
proximately 45pF (C ) from the sampling CDAC in series
IN
with 40Ω (R ) from the on-resistance of the sampling
ON
CONVERTER OPERATION
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
The LTC2380-24 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
+
–
the C capacitors during acquisition. During conversion,
converter (CDAC) is connected to the IN and IN pins
to sample the differential analog input voltage. A rising
edge on the CNV pin initiates a conversion. During the
conversionphase,the24-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
IN
the analog inputs draw only a small leakage current.
REF
C
45pF
IN
R
40Ω
ON
+
–
IN
IN
reference voltage (e.g. V /2, V /4 … V /16777216)
REF
REF
REF
BIAS
VOLTAGE
usingthedifferentialcomparator.Attheendofconversion,
the CDAC output approximates the sampled analog input.
TheADCcontrollogicthenpassesthe24-bitdigitaloutput
code to the digital filter for further processing.
REF
C
45pF
IN
R
40Ω
ON
238024 F03
TRANSFER FUNCTION
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2380 -24
The LTC2380-24 digitizes the full-scale voltage of 2 ×
24
REF into 2 levels, resulting in an LSB size of 0.6µV with
INPUT DRIVE CIRCUITS
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
Alowimpedancesourcecandirectlydrivethehighimped-
ance inputs of the LTC2380-24 without gain error. A high
238024fa
11
For more information www.linear.com/LTC2380-24
LTC2380-24
APPLICATIONS INFORMATION
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For
best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2380-24. The amplifier
provides low output impedance, which produces fast set-
tling of the analog signal during the acquisition phase. It
also provides isolation between the signal source and the
ADC input currents.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2380-24 is in dealing with current spikes drawn
by the ADC inputs at the start of each acquisition phase.
The ADC inputs may be modeled as a switched capacitor
load of the drive circuit. A drive circuit may rely partially
on attenuating switched-capacitor current spikes with
small filter capacitors C
placed directly at the ADC
FILT
inputs, and partially on the driver amplifier having suffi-
cient bandwidth to recover from the residual disturbance.
Amplifiers optimized for DC performance may not have
sufficientbandwidthtofullyrecoverattheADC’smaximum
conversionrate, whichcanproducenonlinearityandother
errors. Coupling filter circuits may be classified in three
broad categories:
Noise and Distortion
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)
shown in Figure 4 is sufficient for many applications.
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is consider-
ably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2380-24),thedisturbancewillnotcontributeanyerror.
LPF2
6800pF
SINGLE-ENDED-
10Ω
LPF1
INPUT SIGNAL
+
–
IN
500Ω
3300pF
LTC2380-24
6600pF
IN
10Ω
238024 F04
SINGLE-ENDED- 6800pF
TO-DIFFERENTIAL
DRIVER
BW = 48kHz
BW = 1.2MHz
PartiallySettled–Inthiscase, thebeginningofacquisition
causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
Figure 4. Input Signal Chain
A coupling filter network (LPF2) should be used between
thebufferandADCinputtominimizedisturbancesreflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
of the analog inputs. Therefore, LPF2 typically requires a
widerbandwidththanLPF1. Thisfilteralsohelpsminimize
the noise contribution from the buffer. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion. NP0
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
Fully Averaged – If the coupling filter capacitors (C ) at
FILT
the ADC inputs are much larger than the ADC’s sample
capacitors (45pF), then the sampling glitch is greatly at-
tenuated. The driving amplifier effectively only sees the
238024fa
12
For more information www.linear.com/LTC2380-24
LTC2380-24
APPLICATIONS INFORMATION
average sampling current, which is quite small. At 2Msps,
the equivalent input resistance is approximately 11k (as
shown in Figure 5), a benign resistive load for most pre-
cision amplifiers. However, resistive voltage division will
occur between the coupling filter’s DC resistance and the
ADC’s equivalent (switched-capacitor) input resistance,
thus producing a gain error.
Let R and R be the source impedances of the dif-
S1 S2
ferential input drive circuit shown in Figure 7, and let I
L1
and I be the leakage currents flowing out of the ADC’s
analog inputs. The voltage error, V , due to the leakage
L2
E
currents can be expressed as:
RS1+R
IL1+IL2
V =
S2 • I –I + R –R
•
S2
(
)
(
)
E
L1 L2
S1
2
2
+
LTC2380-24
IN
The common mode input leakage current, (I + I )/2, is
R
EQ
L1
L2
typicallyextremelysmall(Figure6)overtheentireoperating
temperaturerangeandcommonmodeinputvoltagerange.
Thus, any reasonable mismatch (below 5%) of the source
C
C
FILT >> 45pF
BIAS
VOLTAGE
–
IN
R
EQ
FILT >> 45pF
impedancesR andR willcauseonlyanegligibleerror.
S1
S2
238024 F05
Thedifferentialinputleakagecurrent, (I –I ), increases
L1 L2
1
REQ
=
with temperature as shown in Figure 6 and is maximum
fSMPL •45pF
when V = V . The differential leakage current is also
IN
REF
Figure 5. Equivalent Circuit for the Differential
Analog Input of the LTC2380 -24 at 2Msps
typically very small, and its nonlinear component is even
smaller. Only the nonlinear component will impact the
ADC’s linearity.
The input leakage currents of the LTC2380-24 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currentstoanaddedinputvoltageerror. Theinputleakage
currents,bothcommonmodeanddifferential,aretypically
extremely small over the entire operating temperature
range. Figure 6 shows input leakage currents over tem-
perature for a typical part.
I
L1
+
R
S1
+
IN
IN
LTC2380-24
V
E
–
–
R
S2
I
L2
238024 F07
Figure 7. Source Impedances of a Driver and
Input Leakage Currents of the LTC2380 -24
10
V
= V
REF
IN
For optimal performance, it is recommended that the
source impedances, R and R , be between 5Ω and
S1
S2
5
0
DIFFERENTIAL
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
R
S1
and R are usually not critical. The guaranteed AC
S2
and DC specifications are tested with 10Ω source imped-
ances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling
of the inputs.
COMMON
–5
–40
–15
10
35
60
85
TEMPERATURE (°C)
238024 F06
Fully Differential Inputs
Figure 6. Common Mode and Differential
Input Leakage Current over Temperature
A low distortion fully differential signal source driven
through the LT6203 configured as two unity gain buffers
as shown in Figure 8 can be used to get the full data sheet
distortion performance of –117dB.
238024fa
13
For more information www.linear.com/LTC2380-24
LTC2380-24
APPLICATIONS INFORMATION
499Ω
499Ω
5V
LT6203
5V
3
2
+
–
1
0V
LT6203
0V
5V
0V
6
5
–
+
OUT2
OUT1
7
1
5V
0V
5V
0V
3
2
+
–
5V
5
6
+
–
7
0V
5V
0V
238024 F08
Figure 8. LT620 3 Buffering a Fully Differential Signal Source
249Ω
Single-Ended-to-Differential Conversion
+
–
V
= REF/2
10µF
CM
For single-ended input signals, a single-ended-to-
differential conversion circuit must be used to produce
a differential signal at the inputs of the LTC2380-24.
The LT6203 ADC driver is recommended for performing
single-ended-to-differential conversions. The LT6203 is
flexible and may be configured to convert single-ended
signals of various amplitudes to the 5V differential input
range of the LTC2380-24.
238024 F09a
Figure 9a. LT620 3 Converting a 0 V to 5V Single-Ended
Signal to a ±5V Differential Input Signal
0
SNR = 100.2dB
–20
–40
THD = –112.5dB
SINAD = 100dB
SFDR = 116.7dB
–60
–80
Figure 9a shows the LT6203 being used to convert a 0V to
5Vsingle-endedinputsignal.Inthiscase,thefirstamplifier
is configured as a unity gain buffer and the single-ended
inputsignaldirectlydrivesthehigh-impedanceinputofthe
amplifier. As shown in the FFT of Figure 9b, the LT6203
drivestheLTC2380-24tonearfulldatasheetperformance.
–100
–120
–140
–160
–180
0
150
300
450
600
750
FREQUENCY (kHz)
238024 F09b
Digital Gain Compression
Figure 9b. 128k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 9a
The LTC2380-24 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be
tween 10% and 90% of the V analog input range. To
5V
4.5V
REF
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the SAR ADC driver to be powered
off of a single positive supply since each input swings
between 0.5V and 4.5V as shown in Figure 10. Needing
only one positive supply to power the SAR ADC driver
results in additional power savings for the entire system.
0.5V
0V
238024 F10
Figure 10 . Input Swing of the LTC2380 -24 with
Gain Compression Enabled
With DGC enabled, the LTC2380-24 can be driven by the
low power LTC6362 differential driver which is powered
fromasingle5Vsupply.Figure11ashowshowtoconfigure
the LTC6362 to accept a 3.28V true bipolar single-ended
input signal and level shift the signal to the reduced input
range of the LTC2380-24 when digital gain compression
is enabled. When paired with the LTC6655-4.096 for the
reference, the entire signal chain solution can be powered
from a single 5V supply, minimizing power consump-
tion and reducing complexity. As shown in the FFT of
Figure 11b, the single 5V supply solution can achieve up
to 96dB of SNR.
238024fa
14
For more information www.linear.com/LTC2380-24
LTC2380-24
APPLICATIONS INFORMATION
5V
V
V
V
LTC6655-4.096
0
–20
IN
SNR = 98.2dB
THD = –107.7dB
SINAD = 97.7dB
SFDR = 111dB
OUT_F
OUT_S
4.096V
–40
1k
47µF
–60
1k
V
CM
3.69V
0.41V
2.5V
1k
10µF
–80
3
4
+
V
6800pF
–100
–120
–140
–160
–180
REF
V
1k
DD
LTC2380-24
REF/DGC
+
–
8
1
35.7Ω
3300pF
35.7Ω
IN
IN
+
LTC6362
3.28V
0V
–3.28V
1k
–
5
6
3.69V
2
V
CM
–
238024 F11a
V
6800pF
0
150
300
450
600
750
0.41V
FREQUENCY (kHz)
1k
238024 F11b
Figure 11a. LTC6362 Configured to Accept a ±3.28V Input Signal While Running from
a Single 5V Supply When Digital Gain Compression Is Enabled in the LTC2380 -24
Figure 11b. 128k Point FFT Plot
with fIN = 2kHz for Circuit Shown
in Figure 11a
DC Accuracy
require substantial headroom to the power supply rails for
best performance. Inverting amplifier circuits configured
to minimize swing at the amplifier input terminals may
perform better with less headroom than unity-gain buffer
amplifiers. The linearity and thermal properties of an in-
vertingamplifier’sfeedbacknetworkshouldbeconsidered
carefully to ensure DC accuracy.
Many driver circuits presented in this data sheet em-
phasize AC performance (Distortion and Signal to Noise
Ratio), and the amplifiers are chosen accordingly. The
very low level of distortion is a direct consequence of the
excellent INL of the LTC2380-24, and this property can
be exploited in DC applications as well. Note that while
the LTC6362 and LT6203 are characterized by excellent
AC specifications, their DC specifications do not match
those of the LTC2380-24. The offset of these amplifiers,
forexample, ismorethan500μVundercertainconditions.
In contrast, the LTC2380-24 has a guaranteed maximum
offset error of 130µV (typical drift 0.007ppm/°C), and a
guaranteed maximum full-scale error of 100ppm (typical
drift 0.05ppm/°C). Low drift is important to maintain ac-
curacyoverwidetemperaturerangesinacalibratedsystem.
ADC REFERENCE
The LTC2380-24 requires an external reference to define
its input range. A low noise, low temperature drift refer-
enceiscriticaltoachievingthefulldatasheetperformance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
manyapplications. Withitssmallsize, lowpowerandhigh
accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2380-24. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
Amplifiers have to be selected very carefully to provide a
24-bit accurate DC signal chain. A large-signal open-loop
gain of at least 126dB may be required to ensure 1ppm
linearity for amplifiers configured for a gain of negative
1. However, less gain is sufficient if the amplifier’s gain
characteristic is known to be (mostly) linear. An ampli-
fier’s offset versus signal level must be considered for
amplifiers configured as unity gain buffers. For example,
1ppm linearity may require that the offset is known to
vary less than 5μV for a 5V swing. However, greater offset
variations may be acceptable if the relationship is known
to be (mostly) linear. Unity-gain buffer amplifiers typically
WhenchoosingabypasscapacitorfortheLTC6655-5, the
capacitor’s voltage rating, temperature rating, and pack-
age size should be carefully considered. Physically larger
capacitorswithhighervoltageandtemperatureratingstend
to provide a larger effective capacitance, better filtering
the noise of the LTC6655-5, and consequently producing
a higher SNR. Therefore, we recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
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LTC2380-24
APPLICATIONS INFORMATION
TheREFpinoftheLTC2380-24drawscharge(Q
)from
improvement of the SNR as N increases, because any
noiseontheREFpinwillmodulatearoundthefundamental
frequency of the input signal. Therefore, it is critical to
use a low-noise reference, especially if the input signal
amplitude approaches full-scale. For small input signals,
the dynamic range will improve as described earlier in
this section.
CONV
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
I
I
= Q
/t . The DC current draw of the REF pin,
REF
CONV CYC
, depends on the sampling rate and output code. If
REF
the LTC2380-24 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5ppm.
DYNAMIC PERFORMANCE
When idling, the REF pin on the LTC2380-24 draws only a
smallleakagecurrent(<1µA).Inapplicationswhereaburst
of samples is taken after idling for long periods as shown
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2380-24 provides
guaranteed tested limits for both AC distortion and noise
measurements.
in Figure 12, I
quickly goes from approximately 0µA
REF
to a maximum of 2mA at 2Msps. This step in DC current
draw triggers a transient response in the reference that
must be considered since any deviation in the reference
output voltage will affect the accuracy of the output code.
In applications where the transient response of the refer-
ence is important, the fast settling LTC6655-5 reference
is also recommended.
Dynamic Range
The dynamic range is the ratio of the RMS value of a full
scaleinputtothetotalRMSnoisemeasuredwiththeinputs
In applications where power management is critical, the
external reference may be powered down such that the
voltageontheREFpincangobelow2V. Insuchscenarios,
it is recommended that after the voltage on the REF pin
recoverstoabove2V,theADC’sinternaldigitalI/Oregisters
beclearedbeforetheinitiationofthenextconversion. This
can be achieved by providing at least 20 rising edges on
the SCK pin before the first CNV rising edge.
shorted to V /2. The dynamic range of the LTC2380-24
REF
without averaging (N = 1) is 101dB which improves by
3dB for every 2× increase in the number of conversion
results averaged (N) per measurement.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
componentsattheADCoutput. Theoutputisband-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure13showsthattheLTC2380-24achieves
a typical SINAD of 100dB at a 1.5MHz sampling rate with
a 2kHz input.
Reference Noise
The dynamic range of the ADC will increase approximately
3dB for every 2× increase in the number of conversion
results averaged (N). The SNR should also improve as a
function of N in the same manner. For large input signals
near full-scale, however, any reference noise will limit the
CNV
IDLE
PERIOD
IDLE
PERIOD
238024 F12
Figure 12. CNV Waveform Showing Burst Sampling
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LTC2380-24
APPLICATIONS INFORMATION
0
interface power supply (OV ). The flexible OV supply
DD
DD
SNR = 100.3dB
THD = –117.3dB
SINAD = 100.2dB
SFDR = 117.4dB
–20
–40
allows the LTC2380-24 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
–60
–80
Power Supply Sequencing
–100
–120
–140
–160
–180
The LTC2380-24 does not have any specific power sup-
ply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described
in the Absolute Maximum Ratings section. The LTC2380-
24 has a power-on-reset (POR) circuit that will reset the
LTC2380-24 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 200µs after a POR event to ensure the re-initialization
period has ended. Any conversions initiated before this
time will produce invalid results. In addition, after a POR
event, it is recommended that the ADC’s internal digital
I/O registers be cleared before the initiation of the next
conversion. This can be achieved by providing at least 20
risingedgesontheSCKpinbeforethefirstCNVrisingedge.
0
150
300
450
600
750
FREQUENCY (kHz)
238024 F13
Figure 13. 128k Point FFT Plot of the LTC2380 -24
with fIN = 2kHz and fSMPL = 1.5MHz
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 13 shows
that the LTC2380-24 achieves a typical SNR of 100dB at
a 1.5MHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
TIMING AND CONTROL
CNV Timing
TotalHarmonicDistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
The LTC2380-24 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up
the LTC2380-24. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2380-24 powers down and begins
acquiring the input signal.
/2).
SMPL
V22 + V32 + V42 +…+ VN2
THD=20log
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through V are the amplitudes of the
N
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2380-24 provides two power supply pins: the
2.5V power supply (V ), and the digital input/output
DD
238024fa
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LTC2380-24
APPLICATIONS INFORMATION
Internal Conversion Clock
DIGITAL INTERFACE
The LTC2380-24 features a simple and easy to use se-
rial digital interface that supports output data rates up
to 1.5Msps. The interface controls a digital averaging
filter, which can be used to increase the dynamic range
The LTC2380-24 has an internal clock that is trimmed
to achieve a maximum conversion time of 392ns. With a
minimum acquisition time of 95ns, a maximum sample
rate of 2Msps is guaranteed without any external adjust-
ments. Note that the serial I/O data transfer time limits the
of measurements. The flexible OV supply allows the
DD
LTC2380-24tocommunicatewithanydigitallogicoperat-
ingbetween1.8Vand5V,including2.5Vand3.3Vsystems.
The digital interface of the LTC2380-24 is backwards
compatible with the LTC2378-20 family.
outputdatarate(f )to1.5Msps(SeeConventionalSAR
ODR
Operation section). A sample rate of 2Msps is achievable
when averaging 4 or more conversion results while using
a distributed read (See Distributed Read section).
1
Digital Averaging Filter (SINC Decimation Filter)
Auto Power-Down
Many SAR ADC applications use digital averaging tech-
niques to reduce the uncertainty of measurements due
to noise. An FPGA or DSP is typically needed to compute
the average of multiple A/D conversion results. The
LTC2380-24 features an integrated digital averaging
filter that can provide the function without any additional
hardware, thus simplifying the application solution and
providing a number of unique advantages. The digital
averaging filter can be used to average blocks of as few
as N = 1 or as many as N = 65536 conversion results.
The LTC2380-24 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CNV. During
power-down,datafromthelastconversioncanbeclocked
out. To minimize power dissipation during power-down,
disableSDOandturnoffSCK.Theautopower-downfeature
willreducethepowerdissipationoftheLTC2380-24asthe
sampling rate is reduced. Since power is consumed only
during a conversion, the LTC2380-24 remains powered-
down for a larger fraction of the conversion cycle (t ) at
CYC
The digital averaging filter described in this section is also
lower sample rates, thereby reducing the average power
dissipation which scales with the sampling rate as shown
in Figure 14.
1
1
known as a SINC digital decimation filter. A SINC digital
decimation filter is an FIR filter with N equal-valued taps.
12
Block Diagram
I
,
N = 4
VDD
I
I
I
I
, N = 4
OVDD
REF
VDD
OVDD
10
8
Figure15illustratesablockdiagramofthedigitalaveraging
filter, including a Conversion Result Register, the Digital
Signal Processing (DSP) block, and an I/O Register.
,
N = 1
, N = 1
6
TheConversionResultRegisterholdsthe24-bitconversion
resultfromthemostrecentsampletakenattherisingedge
4
2
DIGITAL AVERAGING FILTER
0
CONVERSION
RESULT
REGISTER
DIGITAL
SIGNAL
PROCESSING
24-BIT
SAMPLING ADC
I/O
REGISTER
0
0.5
1
1.5
2
SDO
SAMPLING RATE (Msps)
238024 F14
Figure 14. Power Supply Current of the LTC2380 -24
Versus Sampling Rate
CNV
SCK
238024 F15
Figure 15. Block Diagram with Digital Averaging Filter
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LTC2380-24
APPLICATIONS INFORMATION
of CNV. The DSP block provides an averaging operation,
loading average values of conversion results into the I/O
Register for the user to read through the serial interface.
Reducing Measurement Noise Using the Digital
Averaging Filter
Digital averaging techniques are often employed to re-
duce the uncertainty of measurements due to noise. The
LTC2380-24 features a digital averaging filter, making it
easy to perform an averaging operation without providing
any additional hardware and software.
Conventional SAR Operation
The LTC2380-24 may be operated like a conventional no-
latencySARasshowninFigure16. Eachconversionresult
is read out via the serial interface before the next conver-
sion is initiated. Note how the contents of the I/O Register
track the contents of the Conversion Result Register and
that both registers contain a result corresponding to a
single conversion. The digital averaging filter is transpar-
ent to the user when the LTC2380-24 is operated in this
way. No programming is required. Simply read out each
Averaging 4 Conversion Results
Figure 17 shows a case where an output result is read
out once for every 4 conversions initiated. As shown, the
output result read out from the I/O Register is the average
of the 4 previous conversion results. The digital averaging
filter will automatically average conversion results until an
output result is read out. When an output result is read
out, thedigitalaveragingfilterisresetandanewaveraging
operation starts with the next conversion result.
conversion result in each cycle. R represents the 24-bit
i
conversion result corresponding to conversion number i.
As few as 20 SCKs may be given in each conversion cycle
(instead of the 24 shown in Figure 16) to obtain a 20-bit
accurate result, making the LTC2380-24 backwards com-
patible with the LTC2378-20. A maximum sampling rate
of 1.5Msps can be used when operating the LTC2380-24
like a conventional SAR.
Inthisexample,outputresultsarereadoutafterconversion
numbers0,4and8.Thedigitalaveragingfilterisresetafter
CONVERSION
0
1
2
3
4
5
6
7
8
NUMBER
CNV
BUSY
CONVERSION
RESULT
R0
R1
R2
R3
R4
R5
R6
R7
R8
REGISTER
I/O
REGISTER
R0
24
R1
24
R2
24
R3
24
R4
24
R5
24
R6
24
R7
24
R8
24
1
1
1
1
1
1
1
1
1
SCK
238024 F16
Figure 16. Conventional SAR Operation Timing
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LTC2380-24
APPLICATIONS INFORMATION
CONVERSION
0
1
2
3
4
5
6
7
8
NUMBER
CNV
BUSY
CONVERSION
RESULT
REGISTER
R0
R1
R1
R2
R3
R4
R5
R5
R6
R7
R8
I/O
REGISTER
R(–3)+R(–2)+R(–1)+R0
4
R1 + R2
2
R1 + R2 + R3
4
R1 + R2 + R3 + R4
4
R5 + R6
2
R5 + R6 + R7
4
R5 + R6 + R7 + R8
4
1
24
1
24
1
24
SCK
238024 F17
Figure 17. Averaging 4 Conversion Results
conversionnumber0andstartsanewaveragingoperation
beginning with conversion number 1. The output result
(R1 + R2 + R3 + R4)/4 is read out after conversion number
4, which resets the digital averaging filter again. Since the
digital averaging filter automatically averages conversion
results for each new conversion performed, an arbitrary
number of conversion results, up to the upper limit of
65536, may be averaged with no programming required.
average of N conversion results. In each case, the result
is read out between two consecutive A/D conversion
(BUSY) periods, limiting the sampling rate to 1.5Msps
with a 100MHz clock (see Timing Diagrams).
Distributed Read
Sampling rates greater than 1.5Msps are achievable when
using a distributed read. Distributed reads require that
multiple conversion results be averaged. A minimum of 4
conversion results must be averaged to run the LTC2380-
24 at its maximum sampling rate of 2Msps.
Averaging 3 Conversion Results
The output result, when averaging N conversion results
for values of N that are not a power of 2, will be scaled by
N/M, where M is a weighting factor that is the next power
of 2 greater than N (described later in the Weighting Fac-
tor section). Figure 18 shows an example where only 3
conversion results are averaged. The output result read
out is scaled by N/M = ¾.
If at least 1 but less than 20 SCK pulses(0 < SCKs < 20)
are given in a conversion cycle between 2 BUSY falling
edges (See Figure 19), the I/O Register is not updated
with the output of the digital averaging filter, preserving
its contents. This allows an output result to be read from
the I/O Register over multiple conversion cycles, easing
the speed requirements of the serial interface.
Using the Digital Averaging Filter with Reduced
Data Rate
A read is initiated by a rising edge of a first SCK pulse and
it must be terminated before a next read can be initiated.
The digital averaging filter is reset upon the initiation of a
read wherein a new averaging operation begins. Conver-
The examples given in Figures 16, 17 and 18 illustrate
some of the most common ways to use the LTC2380-24.
Simply read each individual conversion result, or read an
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LTC2380-24
APPLICATIONS INFORMATION
CONVERSION
0
1
2
3
4
5
6
7
8
NUMBER
CNV
BUSY
CONVERSION
RESULT
REGISTER
R0
R1
R1
R2
R3
R4
R4
R5
R6
R7
R7
R8
I/O
REGISTER
R(–2) + R(–1) + R0
4
R1 + R2
2
R1 + R2 + R3
4
R4 + R5
2
R4 + R5 + R6
4
R7 + R8
2
1
24
1
24
1
24
SCK
238024 F18
Figure 18. Averaging 3 Conversion Results
sions completed after the digital averaging filter is reset
will automatically be averaged until a new read is initiated.
Thus, the digital averaging filter will calculate averages of
conversion results from conversions completed between
a time when one read is initiated to when a next read is
initiated.
is terminated at the completion of conversion number
5. A second read is initiated after conversion number 5,
whichresultsin(R2+ R3+ R4+ R5)/4beingreadoutfrom
the I/O Register since conversion numbers 2, 3, 4 and 5
completed between the initiation of the two reads shown.
Averaging 25 Conversions Using a Distributed Read
A read is terminated by providing either 0 or greater
than 19 SCK pulses (rising edges) in a conversion cycle
between 2 BUSY falling edges, allowing the I/O Register
to be updated with new averages from the output of the
digital averaging filter.
Figure20showsanexamplewhereareadisinitiatedevery
25conversioncycles,usingasingleSCKpulseperconver-
sion cycle to read the output result from the I/O Register.
The first rising SCK edge initiates a read where a single
bit is then read out over the next 23 conversion cycles. No
SCK pulses are provided between the BUSY falling edges
of conversion numbers 25 and 26, whereby the read is
terminated at the completion of conversion number 26. A
2nd read is initiated after conversion number 26, resulting
in (R2 + R3 +…+ R25 + R26)/32 being read out from the
I/O Register. Since 0 < SCKs < 20 pulses are given each
conversion period during the read, the contents of the I/O
Register are not updated, allowing the distributed read to
occur without interruption.
Averaging 4 Conversions Using a Distributed Read
Figure 19 shows an example where reads are initiated
every 4 conversion cycles, and the I/O register is read
over 3 conversion cycles. This allows the serial interface
to run at 1/3 of the speed that it would otherwise have to
run. The first rising SCK edge initiates a 1st read, and 3
groups of 8-bits are read out over 3 conversion cycles.
No SCK pulses are provided between the BUSY falling
edges of conversion numbers 4 and 5, whereby the read
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APPLICATIONS INFORMATION
CONVERSION
0
1
2
3
4
5
6
7
8
NUMBER
CNV
CONVERSIONS COMPLETED BETWEEN
INITIATION OF READS
BUSY
CONVERSION
RESULT
R0
R1
R2
R3
R4
R5
R6
R7
R8
REGISTER
BLOCK OF CONVERSION RESULTS AVERAGED FOR 1 MEASUREMENT
I/O R(–6) +R(–5) +R(–4)+R(–3)
REGISTER
R(–2) + R(–1) + R0 + R1
4
R2 + R3 + R4 + R5
4
4
1
8
9
16
17
24
1
8
9
16
17
24
SCK
0 SCKs
0 <SCKs<20
0 <SCKs<20
0<SCKs <20
0 SCKs
0<SCKs <20
0<SCKs <20
0<SCKs <20
0 SCKs
1ST READ
2ND READ
238024 F19
READ READ
TERMINATED INITIATED
DIGITAL AVERAGING
FILTER RESETS
READ READ
TERMINATED INITIATED
DIGITAL AVERAGING
FILTER RESETS
Figure 19. Averaging 4 Conversion Results and Reading Out Data with a Distributed Read
CONVERSION
NUMBER
0
1
2
3
4
23
24
25
26
27
CNV
CONVERSIONS COMPLETED BETWEEN
INITIATION OF READS
BUSY
CONVERSION
RESULT
R0
R1
R2
R3
R23
R24
R25
R26
REGISTER
I/O
REGISTER
R(–23) + R(–22) +…+ R0 + R1
32
(REPEATING READ PATTERN – AVERAGE OF 25 CONVERSION
RESULTS FROM 25 CONVERSIONS PRECEDING INITIATION OF READ)
R2 + R3 +…+ R25 + R26
32
1
2
3
4
23
24
1
SCK
0 SCKs
0 <SCKs<20
0 <SCKs<20
0<SCKs <20
1 SCK/CNV
READ
0<SCKs <20
0<SCKs <20
0 SCKs
0 <SCKs <20
238024 F20
Figure 20 . Averaging 25 Conversion Results and Reading Out Data with a Distributed Read
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APPLICATIONS INFORMATION
Minimum Shift Clock Frequency
Table 1. Weighting Factors and Throughput for Various Values of N
N
M
OUTPUT DATA RATE
= 1.5Msps
Requiring at least 1 SCK pulse per conversion cycle while
performing a read sets a lower limit on the SCK frequency
f
SMPL
1
2
3
1
2
4
1.5Msps
750ksps
500ksps
that can be used which is: f
= f
.
SCK
SMPL
Noise vs Averaging
f
= 2Msps
SMPL
The noise of the ADC is un-correlated from one sample to
the next. As a result, the ADC noise for a measurement will
decrease by √N where N is the number of A/D conversion
results averaged for a given measurement. Other noise
sources, such as noise from the input buffer amplifier and
referencenoisemaybecorrelatedfromsample-to-sample
and may be reduced by averaging, but to a lesser extent.
4
4
500ksps
5 - 8
8
400ksps - 250ksps
222.2ksps - 125ksps
117.6ksps - 62.5ksps
60.6ksps - 31.3ksps
30.8ksps - 15.6ksps
15.5ksps - 7.8ksps
7.8ksps - 3.9ksps
3.9ksps - 2ksps
9 - 16
16
17 - 32
32
33 - 64
64
65 - 128
128
129 - 256
257 - 512
513 - 1024
1025 - 2048
2049 - 4096
4097 - 8192
8193 - 16384
16385 - 32768
32769 - 65536
256
512
Weighting Factor
1024
2048
4096
8192
16384
32768
65536
When conversion results are averaged, the resulting
output code represents an equally weighted average of
the previous N samples if N is a power of 2. If N is not a
power of 2, a weighting factor, M, is chosen according to
2ksps - 1ksps
976sps - 488sps
488sps - 244sps
244sps - 122sps
122sps - 61sps
Table 1. Specifically, if R represents the 24-bit conversion
i
th
result of the i analog sample, then the output code, D,
representing N averaged conversion results is defined as:
61sps - 30.5sps
N R
i=1M
In cases where N/M < 1, achieving a full-scale output
result would require driving the analog inputs beyond
the specified guaranteed input differential voltage range.
Doing so is strongly discouraged since operation of the
LTC2380-24 beyond guaranteed specifications could
result in undesired behavior, possibly corrupting results.
For proper operation, it is recommended that the analog
i
D=
∑
Table 1 illustrates weighting factors for any number of
averages, N, between 1 and 65536 and the resulting
data throughputs. Note that M reaches a maximum value
of 65536 when N = 65536. For N > 65536, the digital
averaging filter will continue to accumulate conversion
results such that N/M > 1. In such a case, if the ADC core
produces conversion results that have a non-zero mean,
the output result will eventually saturate at positive or
negative full-scale.
input differential voltage not exceed the V specifica-
REF
tion. Note that the output results do not saturate at N/M
when N/M < 1.
50 Hz and 60 Hz Rejection
Particular input frequencies may be rejected by selecting
the appropriate number of averages, N, based on the
sampling rate, f
, and the desired frequency to be
SMPL
. If,
rejected, f
REJECT
1
fSMPL
1
T
=
•N=
AVG
fREJECT
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APPLICATIONS INFORMATION
then, D is an average value for a full sine wave cycle of
0
–20
–40
–60
f
, resulting in zero gain for that particular frequency
REJECT
and integer multiples thereof up to f
Figure 21). Solving for N gives:
– f
(See
SMPL
REJECT
fSMPL
N=
fREJECT
Using this expression, we can find N for rejecting 50Hz
and 60Hz as well as other frequencies. Note that N and
0
250 500 750 1000 1250 1500 1750 2000
FREQUENCY (kHz)
238024 F21
f
may be traded off to achieve rejection of particular
SMPL
Figure 21. SINC1 Filter with fSMPL = 2Msps and N = 8
frequencies as shown below.
To reject 50Hz with f = 2Msps:
Count
SMPL
2,000,000sps
50Hz
= 40,000
In addition to the 24-bit output code, a 16-bit WORD,
C[15:0], is appended to produce a total output WORD
of 40 bits, as shown in Figure 22. C[15:0] is the straight
binaryrepresentation(MSBfirst)ofthenumberofsamples
averaged to produce the output result minus one. For
instance, if N samples are averaged to produce the output
result, C[15:0] will equal N – 1. Thus, if N is 1 which is
the case with no averaging, C[15:0] will always be 0. If
N is 16384, then C[15:0] will equal 16383, and so on. If
more than 65536 samples are averaged, then C[15:0]
saturates at 65535.
N=
To reject both 50Hz and 60Hz (each being a multiple of
10Hz), with N = 1024:
f
= 1024 • 10Hz
= 10.24ksps
SMPL
1
Figure 21 shows an example of a SINC filter where
= 2Msps and N = 8, resulting in f = 250kHz.
f
SMPL
REJECT
Note that input frequencies above DC other than f
REJECT
ormultiplesthereofarealsoattenuatedtovaryingdegrees
due to the averaging operation.
CHAIN, RDL/SDI = 0
CNV
POWER-DOWN AND ACQUIRE
BUSY
CONVERT
SCK
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
SDO
238024 F22
DATA FROM CONVERSION
NUMBER OF SAMPLES
AVERAGED FOR DATA
Figure 22. Serial Output Code Parsing
238024fa
24
For more information www.linear.com/LTC2380-24
LTC2380-24
TIMING DIAGRAMS
Normal Mode, Single Device
SDO is driven. Figure 23 shows a single LTC2380-24
operated in normal mode with CHAIN and RDL/SDI tied
to ground. With RDL/SDI grounded, SDO is enabled and
When CHAIN = 0, the LTC2380-24 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance and SCK is ignored. If RDL/SDI is low,
the MSB(D23) of the output result is available t
DSDOBUSYL
after the falling edge of BUSY. The count information is
shifted out after the output result.
CONVERT
DIGITAL HOST
CNV
CHAIN
BUSY
IRQ
LTC2380-24
RDL/SDI
SCK
SDO
DATA IN
CLK
238024 F23a
POWER-DOWN
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
AND ACQUIRE
CHAIN = 0
RDL/SDI = 0
t
CYC
t
CNVH
t
CNVL
CNV
t
= t
– t
– t
ACQ CYC CONV BUSYLH
t
BUSY
t
CONV
ACQ
t
BUSYLH
t
t
QUIET
SCK
t
SCKH
22
1
2
3
23
24
SCK
SDO
t
SCKL
t
HSDO
t
t
DSDO
DSDOBUSYL
C15
D23
D22
D21
D1
D0
C15
238024 F23b
Figure 23. Using a Single LTC2380 -24 in Normal Mode
238024fa
25
For more information www.linear.com/LTC2380-24
LTC2380-24
TIMING DIAGRAMS
Normal Mode, Multiple Devices
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2380-24 to drive SDO at a
timeinordertoavoidbusconflicts. AsshowninFigure24,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
deviceisoutputontoSDO.Thecountinformationisshifted
out after the output result.
Figure 24 shows multiple LTC2380-24 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
RDL
RDL
B
A
CONVERT
DIGITAL HOST
CNV
CNV
CHAIN
CHAIN
BUSY
SDO
IRQ
LTC2380-24
LTC2380-24
A
SDO
B
RDL/SDI
SCK
RDL/SDI
DATA IN
SCK
CLK
238024 F24a
CONVERT
POWER-DOWN
AND ACQUIRE
POWER-DOWN AND ACQUIRE
CONVERT
CHAIN = 0
t
CNVL
CNV
BUSY
t
CONV
t
BUSYLH
RDL/SDI
RDL/SDI
A
B
t
SCK
t
t
QUIET
SCKH
22
1
2
3
23
24
25
26
27
46
47
48
SCK
SDO
t
SCKL
t
HSDO
t
EN
t
t
DSDO
DIS
Hi-Z
Hi-Z
Hi-Z
D23A
D22A
D21A
D1A
D0A
D23B D22B
D21B
D1B
D0B
238024 F24b
Figure 24. Normal Mode with Multiple Devices Sharing CNV, SCK and SDO
238024fa
26
For more information www.linear.com/LTC2380-24
LTC2380-24
TIMING DIAGRAMS
Chain Mode, Multiple Devices
number of converters. Figure 25 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 40 SCK cycles. The
MSB of converter A is clocked in at the RDL/SDI pin of
converter B on the rising edge of the first SCK pulse. The
functionality of the digital averaging filter is preserved
when in chain mode.
When CHAIN = OV , the LTC2380-24 operates in chain
DD
mode. In chain mode, SDO is always enabled and RDL/
SDI serves as the serial data pin (SDI) where daisy-chain
data output from another ADC can be input.
This is useful for applications where hardware constraints
maylimitthenumberoflines needed tointerface to a large
CONVERT
OV
OV
DD
DD
DIGITAL HOST
CNV
CNV
CHAIN
CHAIN
BUSY
IRQ
LTC2380-24
A
LTC2380-24
B
SDO
RDL/SDI
RDL/SDI
SDO
DATA IN
SCK
SCK
CLK
238024 F25a
CONVERT
POWER-DOWN
AND ACQUIRE
POWER-DOWN AND ACQUIRE
CONVERT
CHAIN = OV
DD
RDL/SDI = 0
A
t
CNVL
CNV
BUSY
t
CONV
t
BUSYLH
t
SCKCH
t
t
QUIET
SCKH
42
1
2
3
38
39
40
41
43
78
79
80
SCK
t
SCKL
t
SSDISCK
t
HSDO
t
t
DSDO
HSDISCK
D23A
D23B
D22A
D22B
D21A
C1A
C1B
C0A
C0B
SDO = RDL/SDI
A
B
B
t
DSDOBUSYL
D21B
D23A
D22A
D21A
C1A
C0A
SDO
238024 F25b
Figure 25. Chain Mode Timing Diagram
238024fa
27
For more information www.linear.com/LTC2380-24
LTC2380-24
BOARD LAYOUT
To obtain the best performance from the LTC2380-24
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2289A, the evaluation kit for the LTC2380-24.
238024fa
28
For more information www.linear.com/LTC2380-24
LTC2380-24
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2380 -24#packaging for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)
0.70 0.05
3.30 0.05
ꢀ.70 0.05
3.60 0.05
2.20 0.05
PACKAGE
OUTLINE
0.25 0.05
0.45 BSC
3.ꢀ5 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.ꢀꢀ5
TYP
0.40 0.ꢀ0
4.00 0.ꢀ0
(2 SIDES)
9
ꢀ6
R = 0.05
TYP
3.30 0.ꢀ0
3.00 0.ꢀ0
(2 SIDES)
ꢀ.70 0.ꢀ0
PIN ꢀ NOTCH
R = 0.20 OR
PIN ꢀ
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DEꢀ6) DFN 0806 REV Ø
8
ꢀ
0.23 0.05
0.45 BSC
0.75 0.05
0.200 REF
3.ꢀ5 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
238024fa
29
For more information www.linear.com/LTC2380-24
LTC2380-24
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2380 -24#packaging for the most recent package drawings.
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
0.889 ±0.127
(.035 ±.005)
5.10
3.20 – 3.45
(.201)
(.126 – .136)
MIN
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.50
(.0197)
BSC
0.305 ±0.038
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
REF
16151413121110
9
RECOMMENDED SOLDER PAD LAYOUT
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
DETAIL “A”
0.254
4.90 ±0.152
(.193 ±.006)
(.010)
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS16) 0213 REV A
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
238024fa
30
For more information www.linear.com/LTC2380-24
LTC2380-24
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
07/16 Updated the Integral Nonlinearity vs Output Code graph
Deleted Dots denoting full operating temperature for Transition Noise
Updated THD specifications
1, 6
3
3
Updated the Transient Response specification
Updated the Acquisition Time specification
4
5, 18
6
Updated the Differential Nonlinearity vs Output Code graph
Updated the Board Layout section
28
238024fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2380-24
TYPICAL APPLICATION
LTC6362 Configured to Accept a ±10 V Input Signal While Running from a Single 5V
Supply with Digital Gain Compression Enabled in the LTC2380 -24
5V
V
IN
LTC6655-4.096
V
V
OUT_F
4.096V
OUT_S
1k
1k
47µF
333Ω
V
CM
3.69V
2.5V
10µF
3
5
+
V
6800pF
0.41V
REF
V
DD
1k
+
–
8
1
35.7Ω
3300pF
35.7Ω
IN
IN
+
LTC6362
LTC2380-24
REF/DGC
10V
0V
–10V
1k
–
4
6
3.69V
2
V
CM
–
238024 TA02
V
6800pF
0.41V
333Ω
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps, 0.5ppm 2.5V Supply, 5V Fully Differential Input, 104dB SNR, MSOP-16 and
LTC2376-20
INL Serial, Low Power ADC
4mm × 3mm DFN-16 Packages
LTC2379-18/LTC2378-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps
LTC2377-18/LTC2376-18 Serial, Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps
LTC2377-16/LTC2376-16 Serial, Low Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2369-18/LTC2368-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps
LTC2367-18/LTC2364-18 Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps
LTC2367-16/LTC2364-16 Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACs
LTC2757
18-Bit, Single Parallel I
SoftSpan™ DAC
1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
1LSB INL /DNL, MSOP-8 Package, 0V to 5V Output
OUT
LTC2641
16-Bit/14-Bit/12-Bit Single Serial V
DAC
OUT
LTC2630
12-Bit/10-Bit/8-Bit Single V
DACs
SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)
OUT
REFERENCES
LTC6655
Precision Low Drift Low Noise Buffered
Reference
5V/4.906V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise,
MSOP-8 Package
LTC6652
Precision Low Drift Low Noise Buffered
Reference
5V/4.906V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise,
MSOP-8 Package
AMPLIFIERS
LT6237
Dual Rail-to-Rail Output ADC Driver
215MHz GBW, 1.1nV/√Hz, 3.5mA Supply Current
LT6203
Dual 100MHz Rail-to-Rail Input/Output Low 1.9nV/√Hz, 3mA Maximum Supply Current, 100MHz Gain Bandwidth
Noise Power Amplifier
LTC6362
Low Power, Fully Differential Input/Output
Amplifier/Driver
Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and 3mm × 3mm
DFN-8 Packages
238024fa
LT 0716 Rev A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2380-24
●
●
LINEAR TECHNOLOGY CORPORATION 2015
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