LTC2380CMS-16#PBF [Linear]
LTC2380-16 - 16-Bit, 2Msps, Low Power SAR ADC with 96dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC2380CMS-16#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2380-16 - 16-Bit, 2Msps, Low Power SAR ADC with 96dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C |
| 文件： | 总24页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LTC2380-16
16-Bit, 2Msps, Low Power
SAR ADC with 96dB SNR
FEATURES
DESCRIPTION
The LTC®2380-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2380-16 has a
n
2Msps Throughput Rate
n
±±0.6Sꢀ IN6 ꢁMaꢂx
n
Guaranteed 1.-ꢀit No Missing Codes
n
6ow Power: 19mW at 2Msps, 19μW at 2ksps
V
REF
fully differential input range with V ranging from
REF
n
9.dꢀ SNR ꢁtypx at f = 2kHz
2.5V to 5.1V. The LTC2380-16 consumes only 19mW and
achieves 0.6LSꢀ ꢁIL maximum, no missing codes at
16-bits with 96dꢀ SIR.
IN
n
–117dꢀ THD ꢁtypx at f = 2kHz
IN
n
Digital Gain Compression ꢁDGCx
n
Guaranteed Operation to 125°C
The LTC2380-16 has a high speed SPꢁ-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic while
alsofeaturingadaisychainmode.Thefast2Mspsthrough-
put with no cycle latency makes the LTC2380-16 ideally
suited for a wide variety of high speed applications. An
internaloscillatorsetstheconversiontime,easingexternal
timingconsiderations.TheLTC2380-16automaticallypow-
ers down between conversions, leading to reduced power
dissipation that scales with the sampling rate.
n
2.5V Supply
n
Fully Differential ꢁnput Range V
REF
n
n
n
n
n
n
V
ꢁnput Range from 2.5V to 5.1V
REF
Io Pipeline Delay, Io Cycle Latency
1.8V to 5V ꢁ/O Voltages
SPꢁ-Compatible Serial ꢁ/O with Daisy-Chain Mode
ꢁnternal Conversion Clock
16-pin MSOP and 4mm × 3mm DFI Packages
The LTC2380-16 features a unique digital gain compres-
sion(DGC)function,whicheliminatesthedriveramplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
APPLICATIONS
n
Medical ꢁmaging
n
High Speed Data Acquisition
n
Portable or Compact ꢁnstrumentation
ꢁndustrial Process Control
function that maps zero-scale code from 0V to 0.1 • V
REF
n
and full-scale code from V
to 0.9 • V . For a typical
REF
REF
n
Low Power ꢀattery-Operated ꢁnstrumentation
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
n
ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
32k Point FFT fS = 2Msps, fIN = 2kHz
0
2.5V 1.8V TO 5V
10μF
SIR = 96.4dꢀ
–20
–40
THD = –119dꢀ
SꢁIAD = 96.3dꢀ
SFDR = 122dꢀ
0.1μF
–60
V
OV
DD
CHAꢁI
RDL/SDꢁ
SDO
SCK
ꢀUSY
CIV
DD
3300pF
3300pF
3300pF
V
V
REF
20Ω
20Ω
+
–
–80
ꢁI
0V
–100
–120
–140
–160
–180
LTC2380-16
REF
ꢁI
SAMPLE CLOCK
0V
V
REF/DGC
REF
GID
REF
238016 TA01
2.5V TO 5.1V
47μF
(X5R, 0805 SꢁZE)
0
100 200 300 400 500 600 700 800 900 1000
FREQUEICY (kHz)
238016 TA02
238016p
1
LTC2380-16
ABSOLUTE MAXIMUM RATINGS
ꢁNotes 1, 2x
Supply Voltage (V )...............................................2.8V
Digital Output Voltage
DD
Supply Voltage (OV )................................................6V
(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)
DD
DD
Reference ꢁnput (REF).................................................6V
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC2380C................................................ 0°C to 70°C
LTC2380ꢁ .............................................–40°C to 85°C
LTC2380H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Analog ꢁnput Voltage (Iote 3)
+
–
ꢁI , ꢁI ......................... (GID –0.3V) to (REF + 0.3V)
REF/DGC ꢁnput (Iote 3).... (GID –0.3V) to (REF + 0.3V)
Digital ꢁnput Voltage
(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)
DD
PIN CONFIGURATION
TOP VꢁEW
CHAꢁI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GID
OV
TOP VꢁEW
V
DD
DD
CHAꢁI 1
16 GID
GID
SDO
V
2
15 OV
DD
DD
+
GID 3
14 SDO
13 SCK
17
GID
ꢁI
SCK
+
–
ꢁI
ꢁI
4
5
–
ꢁI
RDL/SDꢁ
ꢀUSY
GID
12 RDL/SDꢁ
11 ꢀUSY
10 GID
GID
REF
GID 6
REF 7
REF/DGC 8
9
CIV
REF/DGC
CIV
MS PACKAGE
16-LEAD PLASTꢁC MSOP
DE PACKAGE
T
= 150°C, θ = 110°C/W
16-LEAD (4mm × 3mm) PLASTꢁC DFI
JMAX
JA
T
= 150°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PꢁI 17) ꢁS GID, MUST ꢀE SOLDERED TO PCꢀ
ORDER INFORMATION
6EAD FREE FINISH
LTC2380CMS-16#PꢀF
LTC2380ꢁMS-16#PꢀF
LTC2380HMS-16#PꢀF
LTC2380CDE-16#PꢀF
LTC2380ꢁDE-16#PꢀF
TAPE AND REE6
PART MARKING*
PACKAGE DESCRIPTION
16-Lead Plastic MSOP
16-Lead Plastic MSOP
16-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
LTC2380CMS-16#TRPꢀF 238016
LTC2380ꢁMS-16#TRPꢀF 238016
LTC2380HMS-16#TRPꢀF 238016
LTC2380CDE-16#TRPꢀF 23806
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
16-Lead (4mm × 3mm) Plastic DFI
16-Lead (4mm × 3mm) Plastic DFI
LTC2380ꢁDE-16#TRPꢀF
23806
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
238016p
2
LTC2380-16
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6
V +
PARAMETER
CONDITIONS
(Iote 5)
MIN
TYP
MAX
UNITS
+
l
l
l
l
Absolute ꢁnput Range (ꢁI )
–0.05
–0.05
V
V
+ 0.05
V
V
V
V
ꢁI
REF
REF
–
V
–
Absolute ꢁnput Range (ꢁI )
(Iote 5)
+ 0.05
ꢁI
V + – V – ꢁnput Differential Voltage Range
V
ꢁI
= V + – V –
–V
+V
REF
ꢁI
ꢁI
ꢁI
ꢁI
REF
V
CM
Common-Mode ꢁnput Range
V
/2–
V
/2
REF
V
/2+
REF
0.05
REF
0.05
l
ꢁ
Analog ꢁnput Leakage Current
Analog ꢁnput Capacitance
1
μA
ꢁI
C
Sample Mode
Hold Mode
45
5
pF
pF
ꢁI
CMRR
ꢁnput Common Mode Rejection Ratio
f
ꢁI
= 1MHz
83
dꢀ
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6 PARAMETER
CONDITIONS
MIN
16
TYP
MAX
UNITS
ꢀits
l
l
Resolution
Io Missing Codes
16
ꢀits
Transition Ioise
0.15
0.25
0.1
0
LSꢀ
RMS
l
l
l
ꢁIL
ꢁntegral Linearity Error
Differential Linearity Error
ꢀipolar Zero-Scale Error
ꢀipolar Zero-Scale Error Drift
ꢀipolar Full-Scale Error
ꢀipolar Full-Scale Error Drift
(Iote 6)
(Iote 7)
(Iote 7)
–0.6
–0.5
–2
0.6
0.5
2
LSꢀ
DIL
ꢀZE
LSꢀ
LSꢀ
1
mLSꢀ/°C
LSꢀ
l
FSE
–10
2
10
0.1
ppm/°C
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dꢀFS0 ꢁNotes 4, 8x
SYMꢀO6 PARAMETER
CONDITIONS
MIN
94
TYP
MAX
UNITS
l
l
SꢁIAD
SIR
Signal-to-(Ioise + Distortion) Ratio
f
ꢁI
= 2kHz
96
dꢀ
Signal-to-Ioise Ratio
f
ꢁI
f
ꢁI
f
ꢁI
= 2kHz, V = 5V
94
96.1
95.3
93.4
dꢀ
dꢀ
dꢀ
REF
= 2kHz, V = 5V, REF/DGC = GID
REF
= 2kHz, V = 2.5V
REF
l
THD
Total Harmonic Distortion
f
ꢁI
f
ꢁI
f
ꢁI
= 2kHz, V = 5V
–109
–117
–114
–103
dꢀ
dꢀ
dꢀ
REF
= 2kHz, V = 5V, REF/DGC = GID
REF
= 2kHz, V = 2.5V
REF
SFDR
Spurious Free Dynamic Range
–3dꢀ ꢁnput ꢀandwidth
Aperture Delay
f
ꢁI
= 2kHz
118
34
dꢀ
MHz
ps
500
4
Aperture Jitter
ps
Transient Response
Full-Scale Step
175
ns
238016p
3
LTC2380-16
REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6
PARAMETER
CONDITIONS
(Iote 5)
MIN
TYP
MAX
5.1
UNITS
l
l
l
l
V
Reference Voltage
2.5
V
mA
V
REF
REF
ꢁ
Reference ꢁnput Current
High Level ꢁnput Voltage REF/DGC Pin
Low Level ꢁnput Voltage REF/DGC Pin
(Iote 9)
1.2
1.5
V
V
0.8V
REF
ꢁHDGC
0.2V
V
ꢁLDGC
REF
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6 PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
V
High Level ꢁnput Voltage
Low Level ꢁnput Voltage
Digital ꢁnput Current
0.8 • OV
ꢁH
ꢁL
DD
V
0.2 • OV
10
V
DD
ꢁ
ꢁI
V
ꢁI
= 0V to OV
DD
–10
μA
pF
C
V
V
Digital ꢁnput Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
ꢁI
l
l
l
ꢁ = –500 μA
O
OV – 0.2
DD
V
OH
OL
ꢁ = 500 μA
O
0.2
10
V
ꢁ
ꢁ
ꢁ
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
μA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SꢁIK
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6
PARAMETER
Supply Voltage
Supply Voltage
CONDITIONS
MIN
2.375
1.71
TYP
MAX
2.625
5.25
8.5
UNITS
l
l
l
V
2.5
V
V
DD
OV
DD
ꢁ
ꢁ
ꢁ
ꢁ
Supply Current
Supply Current
Power Down Mode
Power Down Mode
2Msps Sample Rate
7.5
1.1
0.9
0.9
mA
mA
μA
VDD
OVDD
PD
2Msps Sample Rate (C = 20pF)
L
l
l
Conversion Done (ꢁ
Conversion Done (ꢁ
+ ꢁ
+ ꢁ
)
40
110
VDD
VDD
OVDD
OVDD
, H-Grade)
μA
PD
P
Power Dissipation
Power Down Mode
Power Down Mode
2Msps Sample Rate
19
2.25
2.25
21
100
275
mW
μW
μW
D
Conversion Done (ꢁ
Conversion Done (ꢁ
+ ꢁ
+ ꢁ
)
VDD
VDD
OVDD
OVDD
, H-Grade)
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6
PARAMETER
CONDITIONS
MIN
TYP
MAX
2
UNITS
Msps
ns
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
SMPL
COIV
ACQ
290
175
500
20
310
Acquisition Time
t
= t
–t
– t (Iote 10)
ꢀUSYLH
ns
ACQ
CYC COIV
Time ꢀetween Conversions
CIV High Time
ns
CYC
ns
CIVH
ꢀUSYLH
CIVL
QUꢁET
SCK
C = 20pF (Iote 11)
L
15
ns
CIV ↑ to ꢀUSY Delay
Minimum Low Time for CIV
SCK Quiet Time from CIV ↑
SCK Period
(Iote 11)
20
10
10
4
ns
(Iote 10)
ns
(Iotes 11, 12)
ns
SCK High Time
ns
SCKH
238016p
4
LTC2380-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C0 ꢁNote 4x
SYMꢀO6
PARAMETER
CONDITIONS
MIN
4
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
SCK Low Time
SCKL
(Iote 11)
(Iote 11)
4
ns
SDꢁ Setup Time From SCK ↑
SDꢁ Hold Time From SCK ↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK ↑
SDO Data Remains Valid Delay from SCK ↑
SDO Data Valid Delay from ꢀUSY↓
ꢀus Enable Time After RDL ↓
ꢀus Relinquish Time After RDL↑
SSDꢁSCK
HSDꢁSCK
SCKCH
DSDO
1
ns
t
= t
+ t (Iote 11)
DSDO
13.5
ns
SCKCH
SSDꢁSCK
C = 20pF (Iote 11)
L
9.5
ns
C = 20pF (Iote 10)
L
1
ns
HSDO
C = 20pF (Iote 10)
L
5
ns
DSDOꢀUSYL
EI
(Iote 11)
(Iote 11)
16
13
ns
ns
DꢁS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REFor
The deviation is measured from the center of the quantization band.
Note 7: ꢀipolar zero-scale error is the offset voltage measured from
–0.5LSꢀ when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
OV , they will be clamped by internal diodes. This product can handle
Note 8: All specifications in dꢀ are referred to a full-scale 5V input with a
5V reference voltage.
DD
input currents up to 100mA below ground or above REFor OV without
DD
latch-up.
Note 9: f
= 2MHz, ꢁ varies proportionately with sample rate.
REF
SMPL
Note 4: V = 2.5V, OV = 2.5V, REF = 5V, f
= 2MHz,
DD
DD
SMPL
Note 1±: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
REF/DGC = V
.
REF
DD
DD
Note 5: Recommended operating conditions.
and OV = 5.25V.
DD
Note .: ꢁntegral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Note 12: t
100MHz for rising capture.
of 10ns maximum allows a shift clock frequency up to
SCK
0.8*OV
DD
t
WꢁDTH
0.2*OV
DD
50%
50%
t
t
DELAY
DELAY
238016 F01
0.8*OV
0.8*OV
0.2*OV
DD
DD
DD
0.2*OV
DD
Figure 10 Voltage 6evels for Timing Specifications
238016p
5
LTC2380-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 205V, OVDD = 205V, REF = 5V,
fSMP6 = 2Msps, unless otherwise noted0
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
1.0
0.8
0.5
0.4
140000
120000
100000
80000
60000
40000
20000
0
σ = 0.15
0.6
0.3
0.4
0.2
0.2
0.1
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16384
32768
49152
65536
0
16384
32768
49152
65536
32676 32677 32678 32679 32680
OUTPUT CODE
OUTPUT CODE
CODE
238016 G01
238016 G02
238016 G03
THD, Harmonics
32k Point FFT fS = 2Msps,
fIN = 2kHz
vs Input Frequency
SNR, SINAD vs Input Frequency
0
–20
98
96
94
92
90
88
86
84
82
80
–80
–85
SIR = 96.4dꢀ
THD = –119dꢀ
SꢁIAD = 96.3dꢀ
SFDR = 122dꢀ
SIR
–90
–40
3RD
–95
–60
–100
–105
–110
–115
–120
–125
–130
THD
–80
SꢁIAD
–100
–120
–140
–160
–180
2ID
0
100 200 300 400 500 600 700 800 900 1000
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
FREQUEICY (kHz)
FREQUEICY (kHz)
FREQUEICY (kHz)
238016 G05
238016 G06
238016 G04
SNR, SINAD vs Input level,
IN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
f
96.5
96.0
95.5
95.0
94.5
94.0
93.5
93.0
97.0
96.5
96.0
95.5
95.0
–100
–105
–110
–115
–120
–125
–130
–135
–140
SIR
SIR
SꢁIAD
THD
3RD
SꢁIAD
2ID
2.5
3.0
3.5
4.0
4.5
5.0
–40
–30
–20
–10
0
2.5
3.0
3.5
4.0
4.5
5.0
REFEREICE VOLTAGE (V)
ꢁIPUT LEVEL (dꢀ)
REFEREICE VOLTAGE (V)
238016 G16
238016 G07
238016 G17
238016p
6
LTC2380-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 205V, OVDD = 205V, REF = 5V,
fSMP6 = 2Msps, unless otherwise noted0
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
IN6/DN6 vs Temperature
98.0
97.5
97.0
96.5
96.0
95.5
95.0
94.5
94.0
–105
–110
–115
–120
–125
–130
–135
0.50
0.25
0
MAX ꢁIL
THD
SIR
MAX DIL
SꢁIAD
3RD
MꢁI DIL
MꢁI ꢁIL
–0.25
–0.50
2ID
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
238016 G08
238016 G09
238016 G10
Full-Scale Error vs Temperature
Offset Error vs Temperature
Supply Current vs Temperature
1.00
0.75
0.50
0.25
0
8
7
6
5
4
3
2
1
0
2.0
1.5
ꢁ
VDD
–FS
1.0
0.5
0
–0.25
–0.50
–0.75
–1.00
–0.5
–1.0
–1.5
–2.0
ꢁ
OVDD
+FS
ꢁ
REF
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
238016 G12
238016 G13
238016 G11
Reference Current vs
Reference Voltage
Shutdown Current vs Temperature
CMRR vs Input Frequency
45
40
35
30
25
20
15
10
5
100
95
90
85
80
75
70
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
ꢁ
+ ꢁ
VDD OVDD
0
2.5
3.0
3.5
4.0
4.5
5.0
0
200
400
600
800
1000
–55 –35 –15
5
25 45 65 85 105 125
REFEREICE VOLTAGE (V)
FREQUEICY (kHz)
TEMPERATURE (°C)
238016 G14
238016 G15
238016 G18
238016p
7
LTC2380-16
PIN FUNCTIONS
CHAIN ꢁPin 1x: Chain Mode Selector Pin. When low, the
LTC2380-16 operates in Iormal Mode and the RDL/SDꢁ
input pin functions to enable or disable SDO. When high,
the LTC2380-16 operates in Chain Mode and the RDL/
SDꢁ pin functions as SDꢁ, the daisychain serial data input.
ꢀUSY ꢁPin 11x: ꢀUSY indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0V .
DD
RD6/SDI ꢁPin 12x: When CHAꢁI is low, the part is in Ior-
mal Mode and the pin is treated as a bus enabling input.
When CHAꢁI is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisychain is input. Logic levels are
Logic levels are determined by 0V .
DD
V
ꢁPin 2x: 2.5V Power Supply. The range of V is
DD
DD
2.375Vto2.625V. ꢀypassV toGIDwitha10μFceramic
DD
capacitor.
determined by 0V .
DD
GND ꢁPins 3, ., 1± and 1.x: Ground.
SCKꢁPin13x:SerialDataClockꢁnput.WhenSDOisenabled,
theconversionresultordaisychaindatafromanotherADC
is shifted out on the rising edges of this clock MSꢀ first.
+
–
IN , IN ꢁPins 4, 5x: Positive and Iegative Differential
Analog ꢁnputs.
Logic levels are determined by 0V .
DD
REF ꢁPin 7x: Reference ꢁnput. The range of REF is 2.5V
to 5.1V. This pin is referred to the GID pin and should be
decoupledcloselytothepinwitha47μFceramiccapacitor
(X5R, 0805 size).
SDOꢁPin14x:SerialDataOutput. Theconversionresultor
daisychain data is output on this pin on each rising edge
of SCK MSꢀ first. The output data is in 2’s complement
format. Logic levels are determined by 0V .
DD
REF/DGCꢁPin8x:WhentiedtoREF,digitalgaincompression
OV ꢁPin 15x: ꢁ/O ꢁnterface Digital Power. The range of
DD
isdisabledandtheLTC2380-16definesfull-scaleaccording
OV is 1.71V to 5.25V. This supply is nominally set to
DD
to the V analog input range. When tied to GID, digital
REF
the same supply as the host interface (1.8V, 2.5V, 3.3V,
gain compression is enabled and the LTC2380-16 defines
or 5V). ꢀypass OV to GID with a 0.1μF capacitor.
DD
full-scale with inputs that swing between 10% and 90%
of the V analog input range.
GND ꢁEꢂposed Pad Pin 17 – DFN Package Onlyx: Ground.
Exposedpadmustbesoldereddirectlytothegroundplane.
REF
CNV ꢁPin 9x: Convert ꢁnput. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0V .
DD
FUNCTIONAL BLOCK DIAGRAM
V
= 2.5V
DD
OV = 1.8V to 5V
DD
REF = 5V
LTC2380-16
CHAꢁI
SDO
RDL/SDꢁ
SCK
+
+
ꢁI
SPꢁ
PORT
16-ꢀꢁT SAMPLꢁIG ADC
–
–
ꢁI
CIV
ꢀUSY
REF/DGC
COITROL LOGꢁC
GID
238016 ꢀD01
238016p
8
LTC2380-16
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAꢁI, RDL/SDꢁ = 0
CIV
POWER-DOWI AID ACQUꢁRE
COIVERT
ꢀUSY
SCK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
238016 TD02
238016p
9
LTC2380-16
APPLICATIONS INFORMATION
OVERVIEW
TRANSFER FUNCTION
TheLTC2380-16isalownoise,lowpower,highspeed16-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2380-16 supports a
The LTC2380-16 digitizes the full-scale voltage of 2 × REF
16
into 2 levels, resulting in an LSꢀ size of 152μV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
large and flexible V fully differential input range with
REF
V
ranging from 2.5V to 5.1V, making it ideal for high
REF
performance applications which require a wide dynamic
range. The LTC2380-16 achieves 0.6LSꢀ ꢁIL max, no
missing codes at 16-bits and 96dꢀ SIR.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
Fast 2Msps throughput with no cycle latency makes the
LTC2380-16 ideally suited for a wide variety of high speed
applications.Aninternaloscillatorsetstheconversiontime,
easing external timing considerations. The LTC2380-16
dissipatesonly19mWat2Msps,whileanautopower-down
feature is provided to further reduce power dissipation
during inactive periods.
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
–1 0V
LSB
1
–FSR/2
FSR/2 – 1LSB
LSB
INPUT VOLTAGE (V)
The LTC2380-16 features a unique digital gain compres-
sion(DGC)function,whicheliminatesthedriveramplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
238016 F02
Figure 20 6TC238±-1. Transfer Function
ANA6OG INPUT
function that maps zero-scale code from 0V to 0.1 • V
REF
The analog inputs of the LTC2380-16 are fully differential
in order to maximize the signal swing that can be digitized.
Theanaloginputscanbemodeledbytheequivalentcircuit
shown in Figure 3. The diodes at the input provide ESD
protection. ꢁn the acquisition phase, each input sees ap-
and full-scale code from V
to 0.9 • V . For a typical
REF
REF
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
proximately 45pF (C ) from the sampling CDAC in series
ꢁI
with 40ꢂ (R ) from the on-resistance of the sampling
CONVERTER OPERATION
OI
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
The LTC2380-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
+
–
converter (CDAC) is connected to the ꢁI and ꢁI pins
to sample the differential analog input voltage. A rising
edge on the CIV pin initiates a conversion. During the
conversionphase,the16-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
the C capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
ꢁI
REF
C
45pF
ꢁI
R
OI
40Ω
+
ꢁI
ꢁI
referencevoltage(e.g.V /2,V /4…V /65536)using
REF
REF
REF
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 16-bit digital output
code for serial transfer.
ꢀꢁAS
VOLTAGE
REF
C
45pF
ꢁI
R
OI
40Ω
–
238016 F03
Figure 30 The Equivalent Circuit for the
Differential Analog Input of the 6TC238±-1.
238016p
10
LTC2380-16
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.IPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
A low impedance source can directly drive the high im-
pedance inputs of the LTC2380-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
Single-Ended-to-Differential Conversion
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2380-16. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
ꢁt also provides isolation between the signal source and
the current spike the ADC inputs draw.
Forsingle-endedinputsignals,asingle-endedtodifferential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2380-16. The LT6350 ADC
driver is recommended for performing single-ended-to-
differential conversions. The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the 5V differential input range of the
LTC2380-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2380-16 up to 125°C.
Input Filtering
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Ioisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)
shown in Figure 4 is sufficient for many applications.
Figure 5a shows the LT6350 being used to convert a 0V
to 5V single-ended input signal. ꢁn this case, the first
amplifierisconfiguredasaunitygainbufferandthesingle-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5b,
the LT6350 drives the LTC2380-16 to near full datasheet
performance.
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noisecontributionofthebufferandtohelpminimizedistur-
bances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SIR.
The LT6350 can also be used to buffer and convert large
true bipolar signals which swing below ground to the
5V differential input range of the LTC2380-16 in order
to maximize the signal swing that can be digitized. Fig-
ure 6a shows the LT6350 being used to convert a 10V
true bipolar signal for use by the LTC2380-16. ꢁn this
case, the first amplifier in the LT6350 is configured as
an inverting amplifier stage, which acts to attenuate and
level shift the input signal to the 0V to 5V input range of
the LTC2380-16. ꢁn the inverting amplifier configuration,
the single-ended input signal source no longer directly
drives a high impedance input of the first amplifier. The
LPF2
3300pF
SꢁIGLE-EIDED-
20Ω
LPF1
ꢁIPUT SꢁGIAL
+
–
ꢁI
500Ω
3300pF
LTC2380-16
6600pF
ꢁI
20Ω
238016 F04
SꢁIGLE-EIDED- 3300pF
TO-DꢁFFEREITꢁAL
DRꢁVER
input impedance is instead set by resistor R . R must
ꢁI ꢁI
ꢀW = 48kHz
be chosen carefully based on the source impedance of the
ꢀW = 800kHz
signal source. Higher values of R tend to degrade both
ꢁI
Figure 40 Input Signal Chain
the noise and distortion of the LT6350 and LTC2380-16
as a system.
238016p
11
LTC2380-16
APPLICATIONS INFORMATION
V
CM
LT6350
5V
0V
OUT1
4
5V
0V
R2 = 499
R
R
ꢁIT
ꢁIT
200pF
8
1
+
–
LT6350
5V
0V
OUT1
OUT2
4
5
5V
0V
–
+
R
R
ꢁIT
8
+
–
ꢁIT
OUT2
5
10μF
R4 = 402
R3 = 2k
2
5V
0V
–
+
+
–
V
= V /2
REF
CM
1
2
238016 F05a
10V
0V
–10V
R
= 2k
R1 = 499
ꢁI
+
–
V
= V /2
REF
CM
Figure 5a0 6T.35± Converting a ±V-5V Single-Ended
Signal to a ±5V Differential Input Signal
220pF
238016 F06a
Figure .a0 6T.35± Converting a ±1±V Single-Ended Signal to
a ±5V Differential Input Signal
0
SIR = 96.1dꢀ
–20
–40
THD = –104.7dꢀ
SꢁIAD = 95.5dꢀ
SFDR = 108dꢀ
0
SIR = 96dꢀ
–60
–20
–40
THD = –93dꢀ
SꢁIAD = 91.2dꢀ
SFDR = 94.3dꢀ
–80
–100
–120
–140
–160
–180
–60
–80
–100
–120
–140
–160
–180
0
100 200 300 400 500 600 700 800 9001000
FREQUEICY (kHz)
238016 F05b
0
100 200 300 400 500 600 700 800 9001000
Figure 5b0 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
FREQUEICY (kHz)
238016 F06b
Figure .b0 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure .a
R1, R2, R3 and R4 must be selected in relation to R to
ꢁI
achievethedesiredattenuationandtomaintainabalanced
input impedance in the first amplifier. Table 1 shows the
5V
0V
LT6203
5V
0V
3
2
+
–
resulting SIR and THD for several values of R , R1, R2,
ꢁI
1
7
R3 and R4 in this configuration. Figure 6b shows the re-
sulting FFT when using the LT6350 as shown in Figure 6a.
5V
0V
5V
0V
5
6
+
–
Table 10 SNR, THD vs RIN for ±1±V Single-Ended Input Signal0
R
R1
ꢁΩx
R2
ꢁΩx
R3
ꢁΩx
R4
ꢁΩx
SNR
ꢁdꢀx
THD
ꢁdꢀx
IN
ꢁΩx
238016 F07
2k
499
499
2k
402
2k
96
96
93
–93
–96
–97
Figure 70 6T.2±3 ꢀuffering a Fully Differential Signal Source
10k
100k
2.49k
24.9k
2.49k
24.9k
10k
100k
20k
Digital Gain Compression
The LTC2380-16 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be-
Fully Differential Inputs
To achieve the full distortion performance of the
LTC2380-16,alowdistortionfullydifferentialsignalsource
driven through the LT6203 configured as two unity gain
buffers as shown in Figure 7 can be used to get the full
data sheet THD specification of –117dꢀ.
tween 10% and 90% of the V analog input range. To
REF
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the LT6350 to be powered off of
a single +5.5V supply since each input swings between
0.5V and 4.5V as shown in Figure 8. Ieeding only one
238016p
12
LTC2380-16
APPLICATIONS INFORMATION
5V
many applications. With its small size, low power and
highaccuracy, theLTC6655-5isparticularlywellsuitedfor
use with the LTC2380-16. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2380-16 up to 125°C. We recommend bypassing the
LTC6655-5witha47μFceramiccapacitor(X5R,0805size)
close to the REF pin.
4.5V
0.5V
0V
238016 F08
Figure 80 Input Swing of the 6TC238± with Gain
Compression Enabled
positive supply to power the LT6350 results in additional
power savings for the entire system.
TheREFpinoftheLTC2380-16drawscharge(Q
)from
COIV
Figure 9a shows how to configure the LT6350 to accept a
10V true bipolar input signal and attenuate and level shift
the signal to the reduced input range of the LTC2380-16
whendigitalgaincompressionisenabled.Figure9bshows
anFFTplotwiththeLTC2380-16beingdrivenbytheLT6350
with digital gain compression enabled.
the 47μF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
ꢁ
ꢁ
= Q
/t . The DC current draw of the REF pin,
REF
REF
COIV CYC
, depends on the sampling rate and output code. ꢁf
the LTC2380-16 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSꢀs.
ADC REFERENCE
The LTC2380-16 requires an external reference to define
its input range. A low noise, low temperature drift refer-
ence is critical to achieving the full datasheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
When idling, the REF pin on the LTC2380-16 draws only
a small leakage current (< 1μA). ꢁn applications where a
burst of samples is taken after idling for long periods as
shown in Figure 10, ꢁ quickly goes from approximately
REF
5.5V
V
V
V
LTC6655-5
ꢁI
0
–20
OUT_F
OUT_S
SIR = 94.6dꢀ
THD = –94.6dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 95.9dꢀ
5V
1k
–40
47μF
V
CM
–60
4.5V
0.5V
2.5V
1k
10μF
3
+
–80
V
3300pF
LT6350
OUT1
OUT2
6.04k
4.32k
REF
V
4
DD
LTC2380-16
REF/DGC
–100
–120
–140
–160
–180
+
–
20Ω
ꢁI
ꢁI
R
R
ꢁIT
8
+
–
ꢁIT
10μF
R
3300pF
20Ω
–
+
5
6
1
4.5V
2
–
238016 F09a
V
3300pF
10V
0V
–10V
= 15k
3.01k
ꢁI
0
100 200 300 400 500 600 700 800 9001000
0.5V
V
CM
FREQUEICY (kHz)
238016 F09b
Figure 9a0 6T.35± Configured to Accept a ±1±V Input Signal While Running Off of a
Single 505V Supply When Digital Gain Compression Is Enabled in the 6TC238±-1.
Figure 9b0 32k Point FFT Plot with
fIN = 2kHz for Circuit Shown in
Figure 9a
CIV
ꢁDLE
PERꢁOD
ꢁDLE
PERꢁOD
238016 F10
Figure 1±0 CNV Waveform Showing ꢀurst Sampling
238016p
13
LTC2380-16
APPLICATIONS INFORMATION
0μA to a maximum of 1.5mA at 2Msps. This step in DC
currentdrawtriggersatransientresponseinthereference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
code. ꢁn applications where the transient response of the
reference is important, the fast settling LTC6655-5 refer-
ence is also recommended.
Signal-to-Noise Ratio ꢁSNRx
The signal-to-noise ratio (SIR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 11 shows
that the LTC2380-16 achieves a typical SIR of 96dꢀ at a
2MHz sampling rate with a 2kHz input.
DYNAMIC PERFORMANCE
Total Harmonic Distortion ꢁTHDx
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. ꢀy applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2380-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
TotalHarmonicDistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
V22 + V32 + V42 +…+ VI2
THD=20log
V1
Signal-to-Noise and Distortion Ratio ꢁSINADx
where V1 is the RMS amplitude of the fundamental fre-
quencyandV2throughV aretheamplitudesofthesecond
I
The signal-to-noise and distortion ratio (SꢁIAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 11 shows that the LTC2380-16 achieves
a typical SꢁIAD of 96dꢀ at a 2MHz sampling rate with a
2kHz input.
through Ith harmonics.
POWER CONSIDERATIONS
The LTC2380-16 provides two power supply pins: the
2.5V power supply (V ), and the digital input/output
DD
interface power supply (OV ). The flexible OV supply
DD
DD
allows the LTC2380-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
0
SIR = 96.4dꢀ
–20
–40
THD = –119dꢀ
SꢁIAD = 96.3dꢀ
SFDR = 122dꢀ
Power Supply Sequencing
–60
The LTC2380-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2380-16
has a power-on-reset (POR) circuit that will reset the
LTC2380-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
–80
–100
–120
–140
–160
–180
0
100 200 300 400 500 600 700 800 900 1000
FREQUEICY (kHz)
238016 F11
Figure 110 32k Point FFT with fIN = 2kHz of the 6TC238±-1.
238016p
14
LTC2380-16
APPLICATIONS INFORMATION
reinitialize the ADC. Io conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
powered-downforalargerfractionoftheconversioncycle
CYC
power dissipation which scales with the sampling rate as
shown in Figure 12.
(t ) at lower sample rates, thereby reducing the average
TIMING AND CONTRO6
CNV Timing
DIGITA6 INTERFACE
The LTC2380-16 has a serial digital interface. The flexible
OV supply allows the LTC2380-16 to communicate with
DD
The LTC2380-16 conversion is controlled by CIV. A ris-
ing edge on CIV will start a conversion and power up the
LTC2380-16.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CIV should be driven by a clean low jitter
signal. Converter status is indicated by the ꢀUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CIV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2380-16 powers down and begins acquiring the
input signal.
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
100MHz, a 2Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2380-16 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2380-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPꢁ bus or are daisy-chained.
Internal Conversion Clock
The LTC2380-16 has an internal clock that is trimmed to
achieveamaximumconversiontimeof310ns.Withamin-
imum acquisition time of 175ns, throughput performance
of 2Msps is guaranteed without any external adjustments.
8
7
6
ꢁ
VDD
5
4
3
2
1
0
Auto Power-Down
The LTC2380-16 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CIV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disableSDOandturnoffSCK.Theautopower-downfeature
will reduce the power dissipation of the LTC2380-16 as
the sampling frequency is reduced. Since power is con-
sumedonlyduringaconversion, theLTC2380-16remains
ꢁ
OVDD
ꢁ
REF
0
400
800
1200
1600
2000
SAMPLꢁIG RATE (kHz)
238016 F12
Figure 120 Power Supply Current of the 6TC238±-1.
Versus Sampling Rate
238016p
15
LTC2380-16
TIMING DIAGRAM
Normal Mode, Single Device
Figure 13 shows a single LTC2380-16 operated in Iormal
Mode with CHAꢁI and RDL/SDꢁ tied to ground. With RDL/
SDꢁ grounded, SDO is enabled and the MSꢀ(D15) of the
new conversion data is available at the falling edge of
ꢀUSY. ThisisthesimplestwaytooperatetheLTC2380-16.
When CHAꢁI = 0, the LTC2380-16 operates in Iormal
mode. ꢁn Iormal mode, RDL/SDꢁ enables or disables the
serial data output pin SDO. ꢁf RDL/SDꢁ is high, SDO is in
high-impedance. ꢁf RDL/SDꢁ is low, SDO is driven.
COIVERT
DꢁGꢁTAL HOST
ꢁRQ
CIV
CHAꢁI
ꢀUSY
LTC2380-16
SCK
RDL/SDꢁ
SDO
DATA ꢁI
CLK
238016 F13a
POWER-DOWI
AID ACQUꢁRE
COIVERT
POWER-DOWI AID ACQUꢁRE
COIVERT
CHAꢁI = 0
RDL/SDꢁ = 0
t
CYC
t
CIVH
t
CIVL
CIV
t
= t
– t
– t
ACQ CYC COIV ꢀUSYLH
t
t
COIV
ACQ
ꢀUSY
t
SCK
t
ꢀUSYLH
t
t
QUꢁET
SCKH
1
2
3
14
15
16
SCK
SDO
t
t
SCKL
HSDO
t
t
DSDO
DSDOꢀUSYL
D15
D14
D13
D1
D0
238016 F13
Figure 130 Using a Single 6TC238±-1. in Normal Mode
238016p
16
LTC2380-16
TIMING DIAGRAM
Normal Mode, Multiple Devices
Since SDO is shared, the RDL/SDꢁ input of each ADC must
be used to allow only one LTC2380-16 to drive SDO at a
timeinordertoavoidbusconflicts. AsshowninFigure14,
the RDL/SDꢁ inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDꢁ is brought low, the MSꢀ of the selected
device is output onto SDO.
Figure 14 shows multiple LTC2380-16 devices operating
in Iormal Mode(CHAꢁI = 0) sharing CIV, SCK and SDO.
ꢀy sharing CIV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
RDL
RDL
ꢀ
A
COIVERT
CIV
CIV
CHAꢁI
ꢀUSY
SDO
ꢁRQ
CHAꢁI
LTC2380-16
ꢀ
LTC2380-16
A
DꢁGꢁTAL HOST
SDO
RDL/SDꢁ
RDL/SDꢁ
SCK
SCK
DATA ꢁI
CLK
238016 F15
POWER-DOWI
AID ACQUꢁRE
COIVERT
COIVERT
POWER-DOWI AID ACQUꢁRE
CHAꢁI = 0
t
CIVL
CIV
t
COIV
ꢀUSY
t
ꢀUSYLH
RDL/SDꢁ
A
ꢀ
RDL/SDꢁ
t
SCK
t
t
QUꢁET
SCKH
17
SCK
SDO
1
2
3
14
15
16
18
19
30
31
32
t
t
SCKL
HSDO
t
t
DSDO
DꢁS
t
EI
Hi-Z
Hi-Z
Hi-Z
D15
A
D14
D13
D1
A
D0
D15
D14
D13
D1
ꢀ
D0
ꢀ
A
A
A
ꢀ
ꢀ
ꢀ
238016 F14
Figure 140 Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
238016p
17
LTC2380-16
TIMING DIAGRAM
When CHAꢁI = OV , the LTC2380-16 operates in Chain
This is useful for applications where hardware constraints
maylimitthenumberoflinesneededtointerfacetoalarge
number of converters. Figure 15 shows an example with
two daisy chained devices. The MSꢀ of converter A will
appear at SDO of converter ꢀ after 16 SCK cycles. The
MSꢀ of converter A is clocked in at the SDꢁ/RDL pin of
converter ꢀ on the rising edge of the first SCK.
DD
Mode. ꢁnChainMode,SDOisalwaysenabledandRDL/SDꢁ
serves as the serial data input pin (SDꢁ) where daisychain
data output from another ADC can be input.
COIVERT
OV
OV
DD
DD
CIV
CIV
CHAꢁI
CHAꢁI
DꢁGꢁTAL HOST
LTC2380-16
LTC2380-16
RDL/SDꢁ
SDO
RDL/SDꢁ
ꢀUSY
SDO
ꢁRQ
A
ꢀ
DATA ꢁI
SCK
SCK
CLK
238016 F15a
POWER-DOWI
AID ACQUꢁRE
COIVERT
POWER-DOWI AID ACQUꢁRE
COIVERT
CHAꢁI = OV
DD
RDL/SDꢁ = 0
A
t
CYC
t
CIVL
CIV
ꢀUSY
t
COIV
t
ꢀUSYLH
SCK
t
SCKCH
t
t
QUꢁET
SCKH
1
2
3
14
15
16
17
18
30
31
32
t
SCKL
t
t
HSDO
SSDꢁSCK
t
t
DSDO
HSDꢁSCK
SDO = RDL/SDꢁ
A
ꢀ
D15
D14
D14
D13
D1
D0
D0
A
A
A
A
A
t
DSDOꢀUSYL
D15
D13
D1
ꢀ
D15
D14
D1
A
D0
A
SDO
ꢀ
ꢀ
ꢀ
ꢀ
A
A
ꢀ
238016 F15
Figure 150 Chain Mode Timing Diagram
238016p
18
LTC2380-16
BOARD LAYOUT
To obtain the best performance from the LTC2380-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCꢀ) should ensure the digital and
analog signal lines are separated as much as possible. ꢁn
particular,careshouldbetakennottorunanydigitalclocks
orsignalsalongsideanalogsignalsorunderneaththeADC.
Recommended 6ayout
ThefollowingisanexampleofarecommendedPCꢀlayout.
A single solid ground plane is used. ꢀypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1783A, the
evaluation kit for the LTC2380-16.
Partial Top Silkscreen
238016p
19
LTC2380-16
BOARD LAYOUT
Partial 6ayer 1 Component Side
Partial 6ayer 2 Ground Plane
238016p
20
LTC2380-16
BOARD LAYOUT
Partial 6ayer 3 PWR Plane
Partial 6ayer 4 ꢀottom 6ayer
238016p
21
LTC2380-16
BOARD LAYOUT
Partial Schematic of Demoboard
D G C R E F /
R E F
8
7
1 5
2
1
G I D
D D
D D
V
G I D 1 6
O V
G I D
1 0
G I D
6
3
3
2
1
3
2
1
238016p
22
LTC2380-16
PACKAGE DESCRIPTION
DE Package
1.-6ead Plastic DFN ꢁ4mm × 3mmx
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.115
0.40 0.10
4.00 0.10
(2 SꢁDES)
TYP
16
9
0.70 0.05
R = 0.05
TYP
3.30 0.05
1.70 0.05
3.30 0.10
3.60 0.05
2.20 0.05
3.00 0.10
(2 SꢁDES)
PACKAGE
OUTLꢁIE
1.70 0.10
PꢁI 1 IOTCH
R = 0.20 OR
0.35 s 45°
PꢁI 1
TOP MARK
(SEE IOTE 6)
CHAMFER
(DE16) DFI 0806 REV Ø
8
1
0.23 0.05
0.45 ꢀSC
0.75 0.05
0.200 REF
0.25 0.05
0.45 ꢀSC
3.15 REF
ꢀOTTOM VꢁEW—EXPOSED PAD
3.15 REF
0.00 – 0.05
RECOMMEIDED SOLDER PAD PꢁTCH AID DꢁMEISꢁOIS
APPLY SOLDER MASK TO AREAS THAT ARE IOT SOLDERED
IOTE:
1. DRAWꢁIG PROPOSED TO ꢀE MADE VARꢁATꢁOI OF VERSꢁOI (WGED-3) ꢁI JEDEC
PACKAGE OUTLꢁIE MO-229
2. DRAWꢁIG IOT TO SCALE
3. ALL DꢁMEISꢁOIS ARE ꢁI MꢁLLꢁMETERS
4. DꢁMEISꢁOIS OF EXPOSED PAD OI ꢀOTTOM OF PACKAGE DO IOT ꢁICLUDE
MOLD FLASH. MOLD FLASH, ꢁF PRESEIT, SHALL IOT EXCEED 0.15mm OI AIY SꢁDE
5. EXPOSED PAD SHALL ꢀE SOLDER PLATED
6. SHADED AREA ꢁS OILY A REFEREICE FOR PꢁI 1 LOCATꢁOI OI THE
TOP AID ꢀOTTOM OF PACKAGE
MS Package
1.-6ead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
4.039 p 0.102
(.159 p .004)
(IOTE 3)
0.889 p 0.127
(.035 p .005)
0.280 p 0.076
(.011 p .003)
REF
16151413121110
9
3.00 p 0.102
(.118 p .004)
(IOTE 4)
DETAꢁL “A”
0o – 6o TYP
5.23
4.90 p 0.152
(.193 p .006)
3.20 – 3.45
(.206)
0.254
(.010)
(.126 – .136)
MꢁI
GAUGE PLAIE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6 7 8
0.50
(.0197)
ꢀSC
0.305 p 0.038
(.0120 p .0015)
TYP
0.86
(.034)
REF
1.10
(.043)
MAX
DETAꢁL “A”
0.18
(.007)
RECOMMEIDED SOLDER PAD LAYOUT
SEATꢁIG
PLAIE
IOTE:
0.17 – 0.27
(.007 – .011)
TYP
1. DꢁMEISꢁOIS ꢁI MꢁLLꢁMETER/(ꢁICH)
2. DRAWꢁIG IOT TO SCALE
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
0.50
(.0197)
ꢀSC
3. DꢁMEISꢁOI DOES IOT ꢁICLUDE MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS.
MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE
4. DꢁMEISꢁOI DOES IOT ꢁICLUDE ꢁITERLEAD FLASH OR PROTRUSꢁOIS.
ꢁITERLEAD FLASH OR PROTRUSꢁOIS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE
5. LEAD COPLAIARꢁTY (ꢀOTTOM OF LEADS AFTER FORMꢁIG) SHALL ꢀE 0.102mm (.004") MAX
238016p
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2380-16
TYPICAL APPLICATION
6T.35± Configured to Accept a ±1±V Input Signal While Running Off of a Single 505V Supply When
Digital Gain Compression Is Enabled in the 6TC238±-1.
5.5V
V
V
V
LTC6655-5
ꢁI
OUT_F
OUT_S
5V
1k
1k
47μF
V
CM
4.5V
2.5V
10μF
3
+
V
3300pF
LT6350
OUT1
OUT2
0.5V
6.04k
4.32k
REF
V
DD
4
+
–
20Ω
ꢁI
ꢁI
R
ꢁIT
R
ꢁIT
8
+
–
LTC2380-16
REF/DGC
10μF
R
3300pF
20Ω
–
+
5
6
1
4.5V
2
–
238016 TA03
V
3300pF
10V
0V
= 15k
3.01k
ꢁI
0.5V
V
CM
–10V
RELATED PARTS
PART NUMꢀER
DESCRIPTION
COMMENTS
ADCs
LTC2393-16/LTC2392-16/ 16-ꢀit, 1Msps/500ksps/250ksps Parallel/Serial
LTC2391-16 ADC
5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, Pin
Compatible Family in 7mm × 7mm LQFP-48 and QFI package
LTC2383-16/LTC2382-16/ 16-ꢀit, 1Msps/500ksps/250ksps Serial, Low
2.5V Supply, Differential ꢁnput, 92dꢀ SIR, 2.5V ꢁnput Range, Pin
Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 package
LTC2381-16
Power ADC
LTC1864/LTC1864L
LTC1865/LTC1865L
LTC2302/LTC2306
16-bit, 250ksps/150ksps 1-Channel μPower ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
16-bit, 250ksps/150ksps 2-Channel μPower ADC 5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-8 Package
12-ꢀit, 500ksps, 1-/2-Channel, Low Ioise, ADC
5V Supply, 14mW at 500ksps, 10-Pin DFI Package
LTC2355-14/LTC2356-14 14-ꢀit, 3.5Msps Serial ADC
3.3V Supply, 1-Channel, Unipolar/ꢀipolar, 18mW, MSOP-10 Package
DACs
LTC2757
18-ꢀit Single Parallel ꢁ
SoftSpan DAC
OUT
1LSꢀ ꢁIL/DIL, Software-Selectable Ranges, 7mm × 7mm LQFP-48
Package
LTC2641-16
LTC2630
16-ꢀit Single Serial V
DACs
DACs
1LSꢀ ꢁIL, 1LSꢀ DIL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, ꢁnternal Reference, 1LSꢀ ꢁIL (12ꢀits)
OUT
12-/10-/8-ꢀit Single V
OUT
REFERENCES
LTC6652
Precision Low Drift Low Ioise ꢀuffered Reference 5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Ioise, MSOP-8 Package
Precision Low Drift Low Ioise ꢀuffered Reference 5V/2.5V, 2ppm/°C, 0.25ppm Peak-to-Peak Ioise, MSOP-8 Package
LTC6655
AMP6IFIERS
LT6350
Low Ioise Single-Ended-To-Differential ADC
Driver
Rail-to-Rail ꢁnput and Outputs, 240ns 0.01% Settling Time, DFI-8 or
MSOP-8 Packages
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with Unity
Gain/AV = 5/AV = 10
Low Ioise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dꢀ at 1MHz,
TSOT23-6 Package
LT6202/LT6203
Single/Dual 100MHz Rail-to-Rail ꢁnput/Output
Ioise Low Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢀandwidth
LTC1992
Low Power, Fully Differential ꢁnput/Output
Amplifier/Driver Family
1mA Supply Current
238016p
LT 0211 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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