LTC2381CDE-16PBF [Linear]
16-Bit, 250ksps, Low Power SAR ADC with Serial Interface; 16位， 250ksps的，低功耗SAR ADC ，具有串行接口
| 型号： | LTC2381CDE-16PBF |
| 厂家： | 
Linear |
| 描述： | 16-Bit, 250ksps, Low Power SAR ADC with Serial Interface |
| 文件： | 总24页 (文件大小：1106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2381-16
16-Bit, 250ksps, Low Power
SAR ADC with Serial Interface
FEATURES
DESCRIPTION
The LTC®2381-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2381-16 has a
2.5V fully differential input range. The LTC2381-16
consumes only 3.25mW and achieves 2LSꢀ ꢁIL max,
no missing codes at 16-bits and 92dꢀ SIR.
n
250ksps Throughput Rate
n
2ꢀSꢁ INꢀ ꢂ(aꢃx
n
Guaranteed 16-ꢁit No (issing Codes
n
ꢀow Power: 3.25mW at 250ksps, 13μW at 1ksps
n
92dꢁ SNR ꢂtypx at f = 20kHz
IN
n
Eꢃtended Acquisition Time of 3.25μs Allows Use of
ꢀower Power Drivers
The LTC2381-16 has a high speed SPꢁ-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisychain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2381-16
ideally suited for a wide variety of high speed applica-
tions. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2381-16
automatically powers down between conversions, lead-
ing to reduced power dissipation that scales with the
sampling rate.
n
Guaranteed Operation to 125°C
n
2.5V Supply
n
Fully Differential ꢁnput Range 2.5V
n
External 2.5V Reference ꢁnput
n
Io Pipeline Delay, Io Cycle Latency
n
1.8V to 5V ꢁ/O Voltages
n
SPꢁ-Compatible Serial ꢁ/O with Daisy-Chain Mode
n
ꢁnternal Conversion Clock
n
16-pin MSOP and 4mm × 3mm DFI Packages
APPLICATIONS
The LTC2381-16 features a proprietary sampling
architecture that enables the ADC to begin acquiring the
next sample during the current conversion. The resulting
extended acquisition time of 3.25μs allows the use of
extremely low power ADC drivers.
n
Medical ꢁmaging
n
High Speed Data Acquisition
n
Portable or Compact ꢁnstrumentation
ꢁndustrial Process Control
Low Power ꢀattery-Operated ꢁnstrumentation
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
n
ATE
TYPICAL APPLICATION
32k Point FFT fS = 250ksps, fIN = 20kHz
0
2.5V 1.8V TO 5V
SIR = 91.8dꢀ
–20
–40
THD = –106dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 107dꢀ
10μF
0.1μF
AIALOG ꢁIPUT
0V TO 2.5V
–60
V
OV
DD
50Ω
50Ω
100Ω
3300pF
100Ω
CHAꢁI
RDL/SDꢁ
SDO
SCK
ꢀUSY
CIV
DD
+
–
ꢁI
–80
LT6350
LTC2381-16
–100
–120
–140
–160
–180
ꢁI
SAMPLE CLOCK
REF
GID
238116 TA01
2.5V
SꢁIGLE-EIDED-
TO-DꢁFFEREITꢁAL
DRꢁVER
47μF
(X5R, 0805 SꢁZE)
0
25
50
75
100
125
FREQUEICY (kHz)
238116 TA02a
238116f
1
LTC2381-16
ABSOLUTE MAXIMUM RATINGS
ꢂNotes 1, 2x
Digital Output Voltage
Supply Voltage (V )...............................................2.8V
DD
(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)
DD
Supply Voltage (OV )................................................6V
DD
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC2381C ................................................ 0°C to 70°C
LTC2381ꢁ .............................................–40°C to 85°C
LTC2381H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Reference ꢁnput (REF)..............................................2.8V
Analog ꢁnput Voltage (Iote 3)
+
–
ꢁI , ꢁI ......................... (GID –0.3V) to (REF + 0.3V)
Digital ꢁnput Voltage
(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)
DD
PIN CONFIGURATION
TOP VꢁEW
CHAꢁI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GID
OV
TOP VꢁEW
V
DD
DD
CHAꢁI 1
16 GID
GID
SDO
V
2
15 OV
DD
DD
+
GID 3
14 SDO
13 SCK
17
GID
ꢁI
SCK
+
–
ꢁI
ꢁI
4
5
–
ꢁI
RDL/SDꢁ
ꢀUSY
GID
12 RDL/SDꢁ
11 ꢀUSY
10 GID
GID
REF
REF
GID 6
REF 7
REF 8
9
CIV
CIV
MS PACKAGE
16-LEAD (4mm s 5mm) PLASTꢁC MSOP
DE PACKAGE
16-LEAD (4mm s 3mm) PLASTꢁC DFI
T
= 150°C, θ = 110°C/W
JA
JMAX
T
= 150°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PꢁI 17) ꢁS GID, MUST ꢀE SOLDERED TO PCꢀ
ORDER INFORMATION
ꢀEAD FREE FINISH
LTC2381CMS-16#PꢀF
LTC2381ꢁMS-16#PꢀF
LTC2381HMS-16#PꢀF
LTC2381CDE-16#PꢀF
LTC2381ꢁDE-16#PꢀF
TAPE AND REEꢀ
PART (ARKING
PACKAGE DESCRIPTION
16-Lead Plastic MSOP
16-Lead Plastic MSOP
16-Lead Plastic MSOP
TE(PERATURE RANGE
0°C to 70°C
LTC2381CMS-16#TRPꢀF 238116
LTC2381ꢁMS-16#TRPꢀF 238116
LTC2381HMS-16#TRPꢀF 238116
LTC2381CDE-16#TRPꢀF 23816
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
16-Lead (4mm × 3mm) Plastic DFI
16-Lead (4mm × 3mm) Plastic DFI
LTC2381ꢁDE-16#TRPꢀF
23816
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
238116f
2
LTC2381-16
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ
V +
PARA(ETER
CONDITIONS
(Iote 5)
(IN
–0.05
–0.05
TYP
(AX
UNITS
+
l
l
l
l
Absolute ꢁnput Range (ꢁI )
V
V
V
V
V
V
ꢁI
REF
REF
–
V –
ꢁI
Absolute ꢁnput Range (ꢁI )
(Iote 5)
V + – V – ꢁnput Differential Voltage range
V
= V + – V –
–V
+V
REF
ꢁI
ꢁI
ꢁI
ꢁI
ꢁI
REF
V
CM
Common-Mode ꢁnput Range
V
/2–
V /2
REF
V
/2+
REF
0.05
REF
0.05
l
ꢁ
Analog ꢁnput Leakage Current
Analog ꢁnput Capacitance
1
μA
ꢁI
C
Sample Mode
Hold Mode
45
5
pF
pF
ꢁI
CMRR
ꢁnput Common Mode Rejection Ratio
70
dꢀ
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ PARA(ETER
CONDITIONS
(IN
16
TYP
(AX
UNITS
ꢀits
l
l
Resolution
Io Missing Codes
16
ꢀits
Transition Ioise
0.6
0.9
0.5
0.25
3
LSꢀ
RMS
l
l
l
ꢁIL
ꢁntegral Linearity Error
Differential Linearity Error
ꢀipolar Zero-Scale Error
ꢀipolar Zero-Scale Error Drift
ꢀipolar Full-Scale Error
ꢀipolar Full-Scale Error Drift
(Iote 6)
(Iote 7)
(Iote 7)
–2
–1
–6
2
1
6
LSꢀ
DIL
ꢀZE
LSꢀ
LSꢀ
mLSꢀ/°C
LSꢀ
l
FSE
–14
3
14
0.1
ppm/°C
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dꢁFS. ꢂNotes 4, 8x
SY(ꢁOꢀ PARA(ETER
CONDITIONS
(IN
88.5
89
TYP
92
(AX
UNITS
dꢀ
l
l
l
SꢁIAD
SIR
Signal-to-(Ioise + Distortion) Ratio
f
ꢁI
f
ꢁI
f
ꢁI
f
ꢁI
= 20kHz
Signal-to-Ioise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
–3dꢀ ꢁnput ꢀandwidth
Aperture Delay
= 20kHz
92
dꢀ
THD
= 20kHz, First 5 Harmonics
= 20kHz
–106
107
30
–99
dꢀ
SFDR
dꢀ
MHz
ns
2
Aperture Jitter
30
ps
Transient Response
Full-Scale Step
250
ns
238116f
3
LTC2381-16
REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ
PARA(ETER
CONDITIONS
(Iote 5)
(IN
TYP
(AX
2.6
UNITS
V
l
l
V
Reference Voltage
Load Current
2.4
REF
REF
ꢁ
(Iote 9)
285
μA
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ PARA(ETER
CONDITIONS
(IN
TYP
(AX
UNITS
V
l
l
l
V
V
High Level ꢁnput Voltage
Low Level ꢁnput Voltage
Digital ꢁnput Current
0.8 • OV
ꢁH
ꢁL
DD
0.2 • OV
10
V
DD
ꢁ
V
ꢁI
= 0V to OV
DD
–10
μA
pF
ꢁI
C
V
V
Digital ꢁnput Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
ꢁI
l
l
l
ꢁ = –500 μA
O
OV – 0.2
DD
V
OH
OL
ꢁ = 500 μA
O
0.2
10
V
ꢁ
ꢁ
ꢁ
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
μA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SꢁIK
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ
PARA(ETER
Supply Voltage
Supply Voltage
CONDITIONS
(IN
2.375
1.71
TYP
(AX
2.625
5.25
UNITS
l
V
2.5
V
V
DD
OV
DD
l
l
l
ꢁ
Supply Current
Power Down Mode
Power Down Mode
250ksps Sample Rate
Conversion Done
Conversion Done (H-Grade)
1.3
0.5
0.5
1.7
40
110
mA
μA
μA
DD
P
Power Dissipation
Power Down Mode
Power Down Mode
250ksps Sample Rate
Conversion Done
Conversion Done (H-Grade)
3.25
1.25
1.25
4.25
100
275
mW
μW
μW
D
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ
PARA(ETER
CONDITIONS
(IN
TYP
(AX
250
3
UNITS
ksps
μs
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
SMPL
COIV
ACQ
2
Acquisition Time
t
= t
– t (Iote 10)
HOLD
3.25
μs
ACQ
CYC
Maximum Time ꢀetween Acquisitions
Time ꢀetween Conversions
CIV High Time
750
20
ns
HOLD
CYC
4
us
20
ns
CIVH
ꢀUSYLH
CIVL
SCK
C = 20pF (Iote 11)
L
ns
CIV ↑ to ꢀUSY Delay
Minimum Low Time for CIV
SCK Period
(Iote 11)
200
10
ns
(Iotes 11, 12)
ns
238116f
4
LTC2381-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ꢂNote 4x
SY(ꢁOꢀ
PARA(ETER
CONDITIONS
(IN
4
TYP
(AX
UNITS
ns
l
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
t
SCK High Time
SCKH
SCK Low Time
4
ns
SCKL
(Iote 11)
(Iote 11)
4
ns
SDꢁ Setup Time From SCK ↑
SDꢁ Hold Time From SCK ↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK ↑
SDO Data Remains Valid Delay from SCK ↑
SDO Data Valid Delay from ꢀUSY ↓
ꢀus Enable Time After RDL ↓
ꢀus Relinquish Time After RDL ↑
SCK Setup Time from RDL/SDꢁ ↓
SCK Hold Time from RDL/SDꢁ ↓
SSDꢁSCK
HSDꢁSCK
SCKCH
DSDO
1
ns
t
= t
+ t (Iote 11)
DSDO
13.5
ns
SCKCH
SSDꢁSCK
C = 20pF (Iote 11)
L
9.5
ns
C = 20pF (Iote 10)
L
1
ns
HSDO
C = 20pF (Iote 10)
L
5
ns
DSDOꢀUSYL
EI
(Iote 11)
(Iote 11)
(Iote 10)
(Iote 10)
16
13
ns
ns
DꢁS
1
ns
SSCKRDL
HSCKRDL
16
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: ꢀipolar zero-scale error is the offset voltage measured from
–0.5LSꢀ when the output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 2: All voltage values are with respect to ground.
Note 8: All specifications in dꢀ are referred to a full-scale 2.5V input with
a 2.5V reference voltage.
Note 3: When these pin voltages are taken below ground or above REF
or OV , they will be clamped by internal diodes. This product can handle
DD
input currents up to 100mA below ground or above REFor OV without
Note 9: f
= 250kHz, ꢁ varies proportionately with sample rate.
SMPL REF
DD
latch-up.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
Note 4: V = 2.5V, OV = 2.5V, REF = 2.5V, f = 250kHz.
SMPL
DD
DD
DD
DD
Note 5: Recommended operating conditions.
and OV = 5.25V.
DD
Note 6: ꢁntegral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 12: t
100MHz for rising capture.
of 10ns maximum allows a shift clock frequency up to
SCK
0.8*OV
DD
t
WꢁDTH
0.2*OV
DD
t
t
50%
50%
DELAY
DELAY
238216 F01
0.8*OV
0.2*OV
0.8*OV
0.2*OV
DD
DD
DD
DD
Figure 1. Voltage ꢀevels for Timing Specifications
238116f
5
LTC2381-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
fS(Pꢀ = 250ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
2.0
1.5
1.0
0.5
0.0
1600000
1400000
1200000
1000000
1.0
0.5
0.0
800000
600000
400000
200000
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
0
16384
32768
49152
65536
0
16384
32768
49152
65536
32764
32765
32767
CODE
32768
32769
OUTPUT CODE
OUTPUT CODE
238116 G01
238116 G02
238116 G03
32k Point FFT fS = 250Ksps,
fIN = 20kHz
THD, Harmonics
SNR, SINAD vs Input Frequency
vs Input Frequency
0
–20
93
92.5
92
–90
–95
SIR = 91.8dꢀ
THD = –106dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 107dꢀ
–40
–100
–105
–110
–115
–120
–125
–130
–60
SIR
3RD
2ID
THD
–80
91.5
91
–100
–120
–140
–160
–180
SꢁIAD
90.5
90
0
25
50
75
100
125
0
25
50
75
100
0
25
50
FREQUEICY (kHz)
75
100
FREQUEICY (kHz)
FREQUEICY (kHz)
238116 G05
238116 G06
238116 G04
SNR, SINAD vs Input level,
fIN = 20kHz
SNR, SINAD vs Temperature
THD, Harmonics vs Temperature
93.0
92.5
92.0
91.5
91.0
93.00
92.50
92.00
91.50
91.00
–100
–105
–110
–115
–120
SIR
SꢁIAD
SIR
THD
2ID
SꢁIAD
3RD
–55 –35 –15
5
25 45 65 85 105 125
–40
–30
–20
–10
0
–55 –35 –15
5
25 45 65 85 105 125
ꢁIPUT LEVEL (dꢀ)
TEMPERATURE (ºC)
TEMPERATURE (°C)
238116 G07
238116 G08
238116f
6
LTC2381-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
fS(Pꢀ = 250ksps, unless otherwise noted.
INꢀ/DNꢀ vs Temperature
Full-Scale Error vs Temperature
Offset Error vs Temperature
1
0.5
0
0
–0.5
–1
0
–0.25
–0.5
–0.75
–1
–FS
MAX ꢁIL
MAX DIL
MꢁI DIL
MꢁI ꢁIL
+FS
–0.5
–1.5
–1
–2
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
238116 G10
238116 G11
238116 G12
Supply Current vs Temperature
Shutdown Current vs Temperature
Supply Current vs Sampling Rate
1.5
1
1.4
1.2
1
30
25
20
15
10
5
ꢁ
+ ꢁ
+ ꢁ
VDD OVDD REF
ꢁ
VDD
0.8
0.6
0.4
0.2
0
0.5
0
ꢁ
REF
ꢁ
OVDD
0
0
50
100
150
200
250
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
SAMPLꢁIG RATE (kHz)
TEMPERATURE (°C)
238116 G13
238116 G14
238116 G15
238116f
7
LTC2381-16
PIN FUNCTIONS
CHAIN ꢂPin 1x: Chain Mode Selector Pin. When low, the
LTC2381-16 operates in Iormal Mode and the RDL/SDꢁ
input pin functions to enable or disable SDO. When high,
the LTC2381-16 operates in Chain Mode and the RDL/SDꢁ
pin functions as SDꢁ, the daisychain serial data input.
RDꢀ/SDIꢂPin12x:WhenCHAꢁIislow,thepartisinIormal
Mode and the pin is treated as a bus enabling input. When
CHAꢁI is high, the part is in chain mode and the pin is
treated as a serial data input pin where data from another
ADC in the daisychain is input.
V
ꢂPin 2x: 2.5V Digital Power Supply. The range of
SCKꢂPin13x:SerialDataClockꢁnput.WhenSDOisenabled,
theconversionresultordaisychaindatafromanotherADC
is shifted out on the rising edges of this clock MSꢀ first.
DD
DD
V
is 2.375V to 2.625V. ꢀypass V to GID with a 10μF
DD
ceramic capacitor.
GND ꢂPins 3, 6, 10 and 16x: Ground.
SDOꢂPin14x:SerialDataOutput. Theconversionresultor
daisychain data is output on this pin on each rising edge
of SCK MSꢀ first. The output data is in 2’s complement
format.
+
–
IN , IN ꢂPins 4, 5x: Positive and Iegative Differential
Analog ꢁnputs.
REF ꢂPins 7, 8x: Reference ꢁnput. The range of REF is 2.4V
to 2.6V. This pin is referred to the GID pin and should be
decoupledcloselytothepinwitha47μFceramiccapacitor
(X5R, 0805 size).
OV ꢂPin 15x: ꢁ/O ꢁnterface Digital Power. The range of
DD
OV is 1.71V to 5.25V. This supply is nominally set to
DD
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). ꢀypass OV to GID with a 0.1μF capacitor.
DD
CNV ꢂPin 9x: Convert ꢁnput. A rising edge on this input
initiates a new conversion. When the conversion is done,
the part powers down as long as CIV is held high. When
CIV is returned low, the part powers up in preparation
for the next conversion.
GND ꢂEꢃposed Pad Pin 17 – DFN Package Onlyx: Ground.
Exposed pad must be soldered directly to the ground
plane.
ꢁUSY ꢂPin 11x: ꢀUSY indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished.
FUNCTIONAL BLOCK DIAGRAM
V
= 2.5V
DD
OV = 1.8V to 5V
DD
REF = 2.5V
LTC2381-16
+
CHAꢁI
SDO
RDL/SDꢁ
SCK
+
–
ꢁI
SPꢁ
PORT
16-ꢀꢁT SAMPLꢁIG ADC
–
ꢁI
CIV
COITROL LOGꢁC
ꢀUSY
GID
238116 ꢀD01
238116f
8
LTC2381-16
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAꢁI, RDL/SDꢁ = 0
CIV
POWER-UP
POWER-DOWI
COIVERT
ꢀUSY
HOLD
ACQUꢁRE
SCK
SDO
D15 D14 D13 D2 D1 D0
238116 TD01
APPLICATIONS INFORMATION
OVERVIEW
CONVERTER OPERATION
TheLTC2381-16isalownoise,lowpower,highspeed16-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2381-16 supports a
large 2.5V fully differential input range, making it ideal
for high performance applications which require a wide
dynamicrange.TheLTC2381-16achieves 2LSꢀꢁILmax,
no missing codes at 16-bits and 92dꢀ SIR.
A rising edge on the CIV pin initiates a conversion. During
the conversion phase, the 16-bit CDAC is sequenced
throughasuccessiveapproximationalgorithm,effectively
comparing the sampled input with binary-weighted
fractions of the reference voltage (e.g. V /2, V /4 …
REF
REF
V
REF
/65536) using the differential comparator. At the end
ofconversion,theCDACoutputapproximatesthesampled
analog input. The ADC control logic then prepares the
16-bit digital output code for serial transfer.
Fast 250ksps throughput with no cycle latency makes the
LTC2381-16 ideally suited for a wide variety of high speed
applications.Aninternaloscillatorsetstheconversiontime,
easing external timing considerations. The LTC2381-16
dissipates only 3.25mW at 250ksps, while an auto
power-down feature is provided to further reduce power
dissipation during inactive periods.
TRANSFER FUNCTION
The LTC2381-16 digitizes the full-scale voltage of 2 × REF
16
into 2 levels, resulting in an LSꢀ size of 76μV with
REF=2.5V.TheidealtransferfunctionisshowninFigure2.
The output data is in 2’s complement format.
The LTC2381-16 features a proprietary sampling
architecture that enables the ADC to begin acquiring the
next sample during the current conversion. The resulting
extended acquisition time of 3.25μs allows the use of
extremely low power ADC drivers.
ANAꢀOG INPUT
The analog inputs of the LTC2381-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent
238116f
9
LTC2381-16
APPLICATIONS INFORMATION
circuit shown in Figure 3. The diodes at the input provide
time is important even for DC inputs, because the ADC
inputs draw a current spike when entering acquisition.
ESD protection. ꢁn the acquisition phase, each input sees
approximately45pF(C )fromthesamplingCDACinseries
ꢁI
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2381-16. The amplifier
provides low output impedance which produces fast
settling of the analog signal during the acquisition phase.
ꢁt also provides isolation between the signal source and
the current spike the ADC inputs draw.
with 40ꢂ (R ) from the on-resistance of the sampling
OI
switch.Anyunwantedsignalthatiscommontobothinputs
will be reduced by the common mode rejection of the
ADC. The inputs draw a current spike while charging the
C capacitors during acquisition. When the LTC2381-16
ꢁI
is not acquiring the input, the analog inputs draw only a
small leakage current.
Input Filtering
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Ioisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)
shown in Figure 4 is sufficient for many applications.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
Another filter network consisting of LPF2 and the 100Ω
series input resistors should be used between the buffer
and ADC inputs to both minimize the noise contribution
of the buffer and to help minimize disturbances reflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
of the analog inputs. Therefore, LPF2 requires a wider
bandwidth than LPF1. A buffer amplifier with a low noise
density must be selected to minimize degradation of the
SIR. With the 482kHz lowpass filter shown in Figure 4,
the LT6350 provides the full data sheet performance of
the LTC2381-16.
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
–1 0V
LSB
1
LSB
–FSR/2
FSR/2 – 1LSB
INPUT VOLTAGE (V)
238116 F02
Figure 2. ꢀTC2381-16 Transfer Function
REF
C
ꢁI
R
R
OI
+
ꢁI
ꢁI
ꢀꢁAS
VOLTAGE
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.IPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
REF
C
ꢁI
OI
–
238116 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the ꢀTC2381-16
LPF2
50Ω
SꢁIGLE-EIDED-
ꢁIPUT SꢁGIAL
100Ω
LPF1
+
ꢁI
ꢁI
INPUT DRIVE CIRCUITS
500Ω
3300pF
LTC2381-16
LT6350
A low impedance source can directly drive the high
impedance inputs of the LTC2381-16 without gain error.
A high impedance source should be buffered to minimize
settling time during acquisition and to optimize the
distortion performance of the ADC. Minimizing settling
–
6600pF
50Ω
100Ω
ꢀW = 482kHz
238116 F04
SꢁIGLE-EIDED-
TO-DꢁFFEREITꢁAL
DRꢁVER
ꢀW = 48kHz
Figure 4. Input Signal Chain
238116f
10
LTC2381-16
APPLICATIONS INFORMATION
Single-Ended-to-Differential Conversion
The LT6350 can also be used to buffer and convert large,
truebipolarsignalswhichswingbelowgroundtothe 2.5V
differential input range of the LTC2381-16. Figure 7 shows
theLT6350beingusedtoconverta 10Vtruebipolarsignal
for use by the LTC2381-16. The input impedance is again
Forsingle-endedinputsignals,asingle-endedtodifferential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2381-16. The LT6350 ADC
driver is recommended for performing single-ended-to-
differential conversions.The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the 2.5V differential input range of the
LTC2381-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2381-16 up to 125°C.
set by resistor R . Table 2 shows the resulting SIR and
ꢁI
THDforseveralvaluesofR .Figure7ashowstheresulting
ꢁI
FFT when using the LT6350 as shown in Figure 7.
LT6350
OUT1
OUT2
0V to
2.5V
4
5
R
R
ꢁIT
8
1
+
–
ꢁIT
0V to 2.5V
Figure 5 shows the LT6350 being used to convert a 0V
to 2.5V single-ended input signal. ꢁn this case, the first
amplifierisconfiguredasaunitygainbufferandthesingle-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5a,
the LT6350 drives the LTC2381-16 to full datasheet
performance without degrading the SIR or THD .
–
+
2.5V to
0V
2
+
–
V
= V /2
REF
CM
238116 F05
Figure 5. ꢀT6350 Converting a 0V-2.5V Single-Ended Signal
to a 2.5V Differential Input Signal
The LT6350 can also be used to buffer and convert
single-ended signals larger than the input range of the
LTC2381-16 in order to maximize the signal swing that
can be digitized. Figure 6 shows the LT6350 converting a
0V-5V single-ended input signal to the 2.5V differential
input range of the LTC2381-16. ꢁn this case, the first
amplifier in the LT6350 is configured as an inverting
amplifier stage, which acts to attenuate the input signal
down to the 0V-2.5V input range of the LTC2381-16. ꢁn the
inverting amplifier configuration, the single-ended input
signal source no longer directly drives a high impedance
input of the first amplifier. The input impedance is instead
0
SIR = 91.8dꢀ
–20
–40
THD = –106dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 107dꢀ
–60
–80
–100
–120
–140
–160
–180
0
25
50
75
100
125
FREQUEICY (kHz)
set by resistor R . R must be chosen carefully based on
ꢁI ꢁI
238116 F05a
the source impedance of the signal source. Higher values
Figure 5a. 32k Point FFT Plot for Circuit Shown in Figure 5
of R tend to degrade both the noise and distortion of
ꢁI
the LT6350 and LTC2381-16 as a system. R1, R2 and R3
must be selected in relation to R to achieve the desired
ꢁI
attenuation and to maintain a balanced input impedance
in the first amplifier. Table 1 shows the resulting SIR
and THD for several values of R , R1, R2 and R3 in this
ꢁI
configuration. Figure 6a shows the resulting FFT when
using the LT6350 as shown in Figure 6.
238116f
11
LTC2381-16
APPLICATIONS INFORMATION
V
V
REF
CM
R2 = 1.24k
200pF
R2 = 1k
150pF
LT6350
LT6350
OUT1
OUT2
2.5V to
0V
4
5
OUT1
OUT2
2.5V to
0V
4
5
R
R
V
8
+
–
ꢁIT
ꢁIT
R
R
ꢁIT
8
+
–
ꢁIT
10μF
R4 = 1.1k
R3 = 10k
10μF
R4 = 680Ω
R3 = 2k
–
+
–
+
0V to
2.5V
0V to
2.5V
1
2
1
2
R
= 2k
R1 = 1k
R = 10k
ꢁI
ꢁI
R1 = 1.24k
+
–
+
–
V
= V /2
REF
= V /2
REF
CM
CM
75pF
0V to 5V
10V
238116 F06
220pF
238116 F07
Figure 6. ꢀT6350 Converting a 0V-5V Single-Ended Signal to
a 2.5V Differential Input Signal
Figure 7. ꢀT6350 Converting a 10V Single-Ended Signal to
a 2.5V Differential Input Signal
0
0
SIR = 91.7dꢀ
SIR = 91.8dꢀ
–20
–40
THD = –100dꢀ
SꢁIAD = 91.2dꢀ
SFDR = 103.5dꢀ
–20
–40
THD = –95.5dꢀ
SꢁIAD = 91.4dꢀ
SFDR = 96.9dꢀ
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
25
50
75
100
125
0
25
50
75
100
125
FREQUEICY (kHz)
FREQUEICY (kHz)
238116 F06a
238116 F07a
Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6
Table 1. SNR, THD vs RIN for 0-5V Single-Ended Input Signal
Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7
Table 2. SNR, THD vs RIN for 10V Single-Ended Input Signal
R
R1
ꢂΩx
R2
ꢂΩx
R3
ꢂΩx
R4
ꢂΩx
SNR
ꢂdꢁx
THD
ꢂdꢁx
R
R1
ꢂΩx
R2
ꢂΩx
R3
ꢂΩx
R4
ꢂΩx
SNR
ꢂdꢁx
THD
ꢂdꢁx
IN
IN
ꢂΩx
ꢂΩx
2k
1k
5k
1k
5k
2k
680
3.3k
16k
92
91
91
–100
–100
–97
10k
1.24k
6.19k
12.4k
1.24k
6.19k
12.4k
10k
50k
1.1k
5.49k
11k
92
91
91
–96
–96
–97
10k
50k
10k
50k
50k
25k
25k
100k
100k
ADC REFERENCE
use with the LTC2381-16. The LTC6652-2.5 offers 0.05%
(max) initial accuracy and 5ppm/°C (max) temperature
coefficientforhighprecisionapplications.TheLTC6652-2.5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2381-16 up to 125°C. We recommend bypassing the
LTC6652-2.5 with a 47μF ceramic capacitor (X5R, 0805
size) close to the REF pin. All performance curves shown
TheLTC2381-16requiresanexternalreferencetodefineits
input range. A low noise, low temperature drift reference
is critical to achieving the full datasheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
manyapplications. Withitssmallsize, lowpowerandhigh
accuracy, the LTC6652-2.5 is particularly well suited for
in this datasheet were obtained using the LTC6652-2.5.
238116f
12
LTC2381-16
APPLICATIONS INFORMATION
TheREFpinoftheLTC2381-16drawscharge(Q
)from
COIV
V
OUT_S
LTC6655-2.5
the 47μF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
V
OUT_F
1Ω
47μF
ꢁ
ꢁ
= Q
/t . The DC current draw of the REF pin,
REF
REF
COIV CYC
REF
, depends on the sampling rate and output code. ꢁf
the LTC2381-16 is used to continuously sample a signal
at a constant rate, the LTC6652-2.5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSꢀs.
LTC2381-16
238116 F09
Figure 9. ꢀTC6655-2.5 Driving REF of ꢀTC2381-16
When idling, the REF pin on the LTC2381-16 draws only a
smallleakagecurrent(<1μA).ꢁnapplicationswhereaburst
of samples is taken after idling for long periods as shown
0
SIR = 91.8dꢀ
in Figure 8, ꢁ quickly goes from approximately 0μA to
–20
–40
THD = –106dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 107dꢀ
REF
a maximum of 285μA at 250ksps. This step in DC current
draw triggers a transient response in the reference that
must be considered since any deviation in the reference
outputvoltagewillaffecttheaccuracyoftheoutputcode.ꢁn
applications where the transient response of the reference
is important, the fast settling LTC6655-2.5 reference
is recommended. ꢁnserting a 1Ω resistor between the
47μF bypass capacitor and reference output as shown in
Figure 9 helps to improve the transient settling time and
minimize the reference voltage deviation.
–60
–80
–100
–120
–140
–160
–180
0
25
50
75
100
125
FREQUEICY (kHz)
238116 F10
Figure 10. 32k Point FFT of the ꢀTC2381-16
DYNA(IC PERFOR(ANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. ꢀy applying a low distortion sine wave
andanalyzingthedigitaloutputusinganFFTalgorithm,the
ADC’s spectral content can be examined for frequencies
outside the fundamental. The LTC2381-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio ꢂSINADx
The signal-to-noise and distortion ratio (SꢁIAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 10 shows that the LTC2381-16 achieves
a typical SꢁIAD of 92dꢀ at a 250kHz sampling rate with
a 20kHz input.
CIV
ꢁDLE
PERꢁOD
ꢁDLE
PERꢁOD
238116 F08
Figure 8. CNV Waveform Showing ꢁurst Sampling
238116f
13
LTC2381-16
APPLICATIONS INFORMATION
Signal-to-Noise Ratio ꢂSNRx
TI(ING AND CONTROꢀ
CNV Timing
The signal-to-noise ratio (SIR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2381-16 achieves a typical SIR of 92dꢀ at a
250kHz sampling rate with a 20kHz input.
The LTC2381-16 conversion is controlled by CIV. A rising
edgeonCIVwillstartaconversion.Onceaconversionhas
been initiated, it cannot be restarted until the conversion
is complete. For optimum performance, CIV should be
driven by a clean low jitter signal. Converter status is
indicatedbytheꢀUSYoutputwhichremainshighwhilethe
conversion is in progress. To ensure that no errors occur
in the digitized results, any additional transitions on CIV
should occur within 40ns from the start of the conversion
or after the conversion has been completed.
Total Harmonic Distortion ꢂTHDx
TotalHarmonicDistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
ACQUISITION
2
V22 + V32 + V42 +…+ VI
AproprietarysamplingarchitectureallowstheLTC2381-16
to begin acquiring the input signal for the next conversion
750nsafterthestartofthecurrentconversion.Thisextends
theacquisitiontimeto3.25μs,easingsettlingrequirements
and allowing the use of extremely low power ADC drivers.
(Refer to the Timing Diagram.)
THD=20log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through V are the amplitudes of the
I
second through Ith harmonics.
1.4
1.2
1
POWER CONSIDERATIONS
The LTC2381-16 provides two power supply pins: the 2.5V
power supply (V ), and the digital input/output interface
DD
0.8
0.6
0.4
0.2
0
power supply (OV ). The flexible OV supply allows the
DD
DD
LTC2381-16tocommunicatewithanydigitallogicoperating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2381-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2381-16
has a power-on-reset (POR) circuit that will reset the
LTC2381-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
reinitialize the ADC. Io conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
0
50
100
150
200
250
SAMPLꢁIG RATE (kHz)
238116 F11
Figure 11. Power Supply Current of the ꢀTC2381-16
Versus Sampling Rate
Internal Conversion Clock
The LTC2381-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 2.5μs.
238116f
14
LTC2381-16
APPLICATIONS INFORMATION
Auto Power-Down
DIGITAꢀ INTERFACE
The LTC2381-16 automatically powers down after a
conversion has been completed as long as CIV remains
high.Duringpower-down,thedatafromthelastconversion
can be clocked out. To minimize power dissipation during
power-down, disable SDO and turn off SCK. To power up
The LTC2381-16 has a serial digital interface. The flexible
OV supply allows the LTC2381-16 to communicate with
DD
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin
when an external clock is applied to the SCK pin if SDO
is enabled. Clocking out the data after the conversion will
yield the best performance. With a shift clock frequency
of at least 15MHz, a 250ksps throughput is still achieved.
The serial output data changes state on the rising edge
of SCK and can be captured on the falling edge or next
rising edge of SCK. D15 remains valid till the first rising
edge of SCK.
the part, bring CIV low at least 200ns (t
) before the
COIVL
initiation of the next conversion. The auto power-down
feature will reduce the power dissipation of the LTC2381-
16 as the sampling frequency is reduced. Since the time
required to power up the part does not change at lower
sample rates, the LTC2381-16 can remain powered-down
for a larger fraction of the conversion cycle (t ), thereby
CYC
reducing the average power dissipation which scales
linearly with sampling rate as shown in Figure 11.
The serial interface on the LTC2381-16 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2381-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPꢁ bus or are daisy-chained.
238116f
15
LTC2381-16
TIMING DIAGRAM
Normal (ode, Single Device
Figure 12 shows a single LTC2381-16 operated in Iormal
Mode with CHAꢁI and RDL/SDꢁ tied to ground. With RDL/
SDꢁ grounded, SDO is enabled and the MSꢀ(D15) of the
newconversiondataisavailableatthefallingedgeofꢀUSY.
This is the simplest way to operate the LTC2381-16.
When CHAꢁI = 0, the LTC2381-16 operates in Iormal
mode. ꢁn Iormal mode, RDL/SDꢁ enables or disables the
serial data output pin SDO. ꢁf RDL/SDꢁ is high, SDO is in
high-impedance. ꢁf RDL/SDꢁ is low, SDO is driven.
COIVERT
DꢁGꢁTAL HOST
ꢁRQ
CIV
CHAꢁI
ꢀUSY
LTC2381-16
SCK
RDL/SDꢁ
SDO
DATA ꢁI
CLK
238116 F10
COIVERT
POWER-DOWI
POWER-UP
COIVERT
ACQUꢁRE
CHAꢁI = 0
ACQUꢁRE
t
CYC
t
CIVH
t
CIV
CIVL
t
t
ACQ
HOLD
t
= t
– t
ACQ CYC HOLD
ꢀUSY
SCK
t
COIV
t
SCK
t
ꢀUSYLH
t
SCKH
1
2
3
14
15
16
t
SCKL
t
HSDO
t
DSDOꢀUSYL
t
DSDO
SDO
D15
D14
D13
D1
D0
238116 F10a
(RDL/SDꢁ = 0)
Figure 12. Using a Single ꢀTC2381-16 in Normal (ode
238116f
16
LTC2381-16
TIMING DIAGRAM
Normal (ode, (ultiple Devices
timeinordertoavoidbusconflicts. AsshowninFigure13,
the RDL/SDꢁ inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDꢁ is brought low, the MSꢀ of the selected
device is output onto SDO. To ensure the MSꢀ is properly
output and captured, SCK must be held low at least 1ns
before and 16ns after bringing RDL/SDꢁ low.
Figure 13 shows multiple LTC2381-16 devices operating
in Iormal Mode(CHAꢁI = 0) sharing CIV, SCK and SDO.
ꢀy sharing CIV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDꢁ input of each ADC must
be used to allow only one LTC2381-16 to drive SDO at a
RDL2
RDL1
COIVERT
CIV
CIV
CHAꢁI
ꢀUSY
SDO
ꢁRQ
CHAꢁI
LTC2381-16
ꢀ
LTC2381-16
A
DꢁGꢁTAL HOST
SDO
RDL/SDꢁ
RDL/SDꢁ
SCK
SCK
DATA ꢁI
CLK
238116 F11
COIVERT
POWER-DOWI
COIVERT
POWER-UP
ACQUꢁRE
CHAꢁI = 0
CIV
ACQUꢁRE
t
CIVL
t
HOLD
ꢀUSY
t
COIV
t
ꢀUSYLH
RDL/SDꢁ
A
RDL/SDꢁ
ꢀ
t
SCK
t
t
SCKH
HSCKRDL
SCK
SDO
1
2
3
14
15
16
17
18
19
30
31
32
t
t
t
SCKL
SSCKRDL
HSDO
t
DꢁS
t
DSDO
t
EI
Hi-Z
Hi-Z
Hi-Z
D15
D14
D13
D1
D0
D15
D14
D13
D1
D0
ꢀ
A
A
A
A
A
ꢀ
ꢀ
ꢀ
ꢀ
238116 F11a
Figure 13. Normal (ode with (ultiple Devices Sharing CNV, SCK and SDO
238116f
17
LTC2381-16
TIMING DIAGRAM
When CHAꢁI = OV , the LTC2381-16 operates in Chain
This is useful for applications where hardware constraints
maylimitthenumberoflinesneededtointerfacetoalarge
number of converters. Figure 14 shows an example with
two daisy chained devices. The MSꢀ of converter A will
appear at SDO of converter ꢀ after 16 SCK cycles. The
MSꢀ of converter A is clocked in at the SDꢁ/RDL pin of
converter ꢀ on the rising edge of the first SCK.
DD
Mode. ꢁnChainMode,SDOisalwaysenabledandRDL/SDꢁ
serves as the serial data input pin (SDꢁ) where daisychain
data output from another ADC can be input.
COIVERT
OV
OV
DD
DD
CIV
CIV
CHAꢁI
CHAꢁI
DꢁGꢁTAL HOST
LTC2381-16
LTC2381-16
RDL/SDꢁ
SDO
RDL/SDꢁ
ꢀUSY
SDO
ꢁRQ
A
ꢀ
DATA ꢁI
SCK
SCK
CLK
238116 F12
COIVERT
POWER-DOWI
POWER-UP
COIVERT
ACQUꢁRE
ACQUꢁRE
CHAꢁI = OV
DD
RDL/SDꢁ = 0
A
t
CYC
t
CIVL
CIV
t
HOLD
ꢀUSY
t
COIV
t
ꢀUSYLH
t
SCKCH
t
SCKH
SCK
1
2
3
14
15
16
17
18
30
31
32
t
t
SSDꢁSCK
SCKL
t
HSDO
t
HSDꢁSCK
t
DSDO
SDO = RDL/SDꢁ
A
ꢀ
D15
D14
D13
D1
D0
D0
A
A
A
A
A
t
DSDOꢀUSYL
D15
D14
D13
D1
D15
D14
D1
A
D0
A
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
A
A
SDO
ꢀ
238116 F14
Figure 14. Chain (ode Timing Diagram
238116f
18
LTC2381-16
BOARD LAYOUT
To obtain the best performance from the LTC2381-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCꢀ) should ensure the digital and
analog signal lines are separated as much as possible.
ꢁn particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended ꢀayout
ThefollowingisanexampleofarecommendedPCꢀlayout.
A single solid ground plane is used. ꢀypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1571A, the
evaluation kit for the LTC2381-16.
Partial Top Silkscreen
238116 F13
238116f
19
LTC2381-16
BOARD LAYOUT
Partial ꢀayer 1 Component Side
238116 ꢀL01
Partial ꢀayer 2 Ground Plane
238116 ꢀL02
238116f
20
LTC2381-16
BOARD LAYOUT
Partial ꢀayer 3 PWR Plane
238116 ꢀL03
Partial ꢀayer 4 ꢁottom ꢀayer
238116 ꢀL04
238116f
21
LTC2381-16
BOARD LAYOUT
Partial Schematic of Demoboard
R E F 1
8
R E F
1
G I D
7
D D
G I D 1 6
O V
1 5
G I D
1 0
D D
V
2
G I D
6
3
3
2
1
3
2
1
238116f
22
LTC2381-16
PACKAGE DESCRIPTION
DE Package
16-ꢀead Plastic DFN ꢂ4mm × 3mmx
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.115
0.40 0.10
4.00 0.10
(2 SꢁDES)
TYP
16
9
0.70 0.05
R = 0.05
TYP
3.30 0.05
1.70 0.05
3.30 0.10
3.60 0.05
2.20 0.05
3.00 0.10
(2 SꢁDES)
PACKAGE
OUTLꢁIE
1.70 0.10
PꢁI 1 IOTCH
R = 0.20 OR
0.35 s 45°
PꢁI 1
TOP MARK
(SEE IOTE 6)
CHAMFER
(DE16) DFI 0806 REV Ø
8
1
0.23 0.05
0.45 ꢀSC
0.75 0.05
0.200 REF
0.25 0.05
0.45 ꢀSC
3.15 REF
ꢀOTTOM VꢁEW—EXPOSED PAD
3.15 REF
0.00 – 0.05
RECOMMEIDED SOLDER PAD PꢁTCH AID DꢁMEISꢁOIS
APPLY SOLDER MASK TO AREAS THAT ARE IOT SOLDERED
IOTE:
1. DRAWꢁIG PROPOSED TO ꢀE MADE VARꢁATꢁOI OF VERSꢁOI (WGED-3) ꢁI JEDEC
PACKAGE OUTLꢁIE MO-229
2. DRAWꢁIG IOT TO SCALE
3. ALL DꢁMEISꢁOIS ARE ꢁI MꢁLLꢁMETERS
4. DꢁMEISꢁOIS OF EXPOSED PAD OI ꢀOTTOM OF PACKAGE DO IOT ꢁICLUDE
MOLD FLASH. MOLD FLASH, ꢁF PRESEIT, SHALL IOT EXCEED 0.15mm OI AIY SꢁDE
5. EXPOSED PAD SHALL ꢀE SOLDER PLATED
6. SHADED AREA ꢁS OILY A REFEREICE FOR PꢁI 1 LOCATꢁOI OI THE
TOP AID ꢀOTTOM OF PACKAGE
(S Package
16-ꢀead Plastic (SOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
4.039 p 0.102
(.159 p .004)
(IOTE 3)
0.889 p 0.127
(.035 p .005)
0.280 p 0.076
(.011 p .003)
REF
16151413121110
9
3.00 p 0.102
(.118 p .004)
(IOTE 4)
DETAꢁL “A”
0o – 6o TYP
5.23
4.90 p 0.152
(.193 p .006)
3.20 – 3.45
(.206)
0.254
(.010)
(.126 – .136)
MꢁI
GAUGE PLAIE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6 7 8
0.50
(.0197)
ꢀSC
0.305 p 0.038
(.0120 p .0015)
TYP
0.86
(.034)
REF
1.10
(.043)
MAX
DETAꢁL “A”
0.18
(.007)
RECOMMEIDED SOLDER PAD LAYOUT
SEATꢁIG
PLAIE
IOTE:
0.17 – 0.27
(.007 – .011)
TYP
1. DꢁMEISꢁOIS ꢁI MꢁLLꢁMETER/(ꢁICH)
2. DRAWꢁIG IOT TO SCALE
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
0.50
(.0197)
ꢀSC
3. DꢁMEISꢁOI DOES IOT ꢁICLUDE MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS.
MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE
4. DꢁMEISꢁOI DOES IOT ꢁICLUDE ꢁITERLEAD FLASH OR PROTRUSꢁOIS.
ꢁITERLEAD FLASH OR PROTRUSꢁOIS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE
5. LEAD COPLAIARꢁTY (ꢀOTTOM OF LEADS AFTER FORMꢁIG) SHALL ꢀE 0.102mm (.004") MAX
238116f
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2381-16
TYPICAL APPLICATION
ADC Driver: Single-Ended Input to Differential Output with Filter
0
–20
SIR = 91.8dꢀ
THD = –106dꢀ
SꢁIAD = 91.6dꢀ
SFDR = 107dꢀ
LPF2
50Ω
SꢁIGLE-EIDED
ꢁIPUT SꢁGIAL
–40
LT6350
LPF1
500Ω
100Ω
100Ω
+
–
4
5
ꢁI
–60
R
R
ꢁIT
3300pF
8
1
+
–
ꢁIT
LTC2381-16
–80
6600pF
ꢁI
–100
–120
–140
–160
–180
50Ω
ꢀW = 482kHz
+
–
238116 TA03
2
ꢀW = 48kHz
+
–
V
= V /2
REF
CM
0
25
50
75
100
125
FREQUEICY (kHz)
238116 TA04
RELATED PARTS
PART NU(ꢁER
DESCRIPTION
CO((ENTS
ADCs
LT2383/LTC2382
16-ꢀit, 1Msps/500ksps Serial ADC
16-ꢀit, 1Msps Parallel/Serial ADC
16-ꢀit, 500Ksps Parallel/Serial ADC
16-ꢀit, 250Ksps Parallel/Serial ADC
2.5V Supply, Differential ꢁnput, 92dꢀ SIR, 2.5V ꢁnput Range,16-Pin MSOP
and 4mmx3mm16-Pin DFI Packages,Pin Compatible with the LTC2382-16
LTC2393-16
LTC2392-16
LTC2391-16
5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2392-16, LTC2391-16
5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2393-16, LTC2391-16
5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2393-16, LTC2392-16
LTC1864/LTC1864L
LTC1865/LTC1865L
LTC2302/LTC2306
16-bit, 250ksps/150ksps 1-channel μPower, ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
16-bit, 250ksps 2-channel μPower ADC
5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
5V Supply, 14mW at 500ksps, 10-Pin DFI Package
12-ꢀit, 500ksps, 1-/2-Channel, Low Ioise, ADC
LTC2355-14/LTC2356-14 14-ꢀit, 3.5Msps Serial ADC
3.3V Supply, 1-Channel, Unipolar/ꢀipolar, 18mW, MSOP-10 Package
DACs
LTC2641
16-ꢀit Single Serial V
DACs
DACs
1LSꢀ ꢁIL, 1LSꢀ DIL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, ꢁnternal Reference, 1LSꢀ ꢁIL (12ꢀits)
OUT
LTC2630
12-/10-/8-ꢀit Single V
OUT
REFERENCES
LTC6652
Precision Low Drift Low Ioise ꢀuffered Reference 2.5V, 5ppm/°C Max Tempco, 2.1ppm Peak-to-Peak Ioise, MSOP-8 Package
Precision Low Drift Low Ioise ꢀuffered Reference 2.5V, 5ppm/°C Max Tempco, 0.25ppm Peak-to-Peak Ioise, MSOP-8 Package
LTC6655
A(PꢀIFIERS
LT6350
Low Ioise Single-Ended-To-Differential ADC Driver Rai-to-Rail ꢁnput and Outputs, 240ns 0.01% Settling Time, DFI-8 or
MSOP-8 Packages
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with Unity
Gain/AV = 5/AV = 10
Low Ioise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dꢀ at 1MHz,
TSOT23-6 Package
LT6202/LT6203
Single/Dual 100MHz Rail-to-Rail ꢁnput/Output
Ioise Low Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢀandwidth
LTC1992
Low Power, Fully Differential ꢁnput/Output
Amplifier/Driver Family
1mA Supply Current
238116f
LT 0810 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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