LTC2387IUH-16#PBF_技术文档

LTC2387-16

16-Bit, 15Msps SAR ADC

FEATURES

DESCRIPTION

TheLTC^®2387-16isalownoise,highspeed,16-bit15Msps

successive approximation register (SAR) ADC ideally

suited for a wide range of applications. The combination

of excellent linearity and wide dynamic range makes the

LTC2387-16 ideal for high speed imaging and instru-

mentation applications. No-latency operation provides a

unique solution for high speed control loop applications.

The very low distortion at high input frequencies enables

communications applications requiring wide dynamic

range and significant signal bandwidth.

n

15Msps Throughput Rate

n

No Pipeline Delay, No Cycle Latency

n

93.8dB SNR (Typ) at f = 1MHz

102dB SFDR (Typ) at f = 1MHz

IN

n

Nyquist Sampling Up to 7.5MHz Input

Guaranteed 16-Bit, No Missing Codes

±±.8LSB ꢀNL (Max)

8.192V Differential ꢀnputs

P-P

5V and 2.5V Supplies

ꢀnternal 2±ppm/°C (Max) Reference

Serial LVDS ꢀnterface

To support high speed operation while minimizing the

number of data lines, the LTC2387-16 features a serial

LVDS digital interface. The LVDS interface has one-lane

and two-lane output modes, allowing the user to optimize

the interface data rate for each application.

125mW Power Dissipation

32-Pin (5mm × 5mm) QFN Package

APPLICATIONS

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 77±5765, 82329±5, 881±443. Other patents are pending.

n

High Speed Data Acquisition

n

ꢀmaging

n

Communications

n

Control Loops

n

ꢀnstrumentation

n

ATE

TYPICAL APPLICATION

FFT, f_SMPL= 15Msps, f_IN= 2kHz

0

5V

2.5V

SNR = 94.0dB

–20

–40

THD = –117dB

SINAD = 93.9dB

SFDR = 119dB

0.1µF

–60

V

OV

DD

CLK

DCO

DA

DD

DDL

24.9Ω

+

LVDS

INTERFACE

IN

4.096V

–80

82pF

+

DB

0V

4.096V

–100

–120

–140

–160

LTC2387-16

TWOLANES

TESTPAT

PD

–

82pF

24.9Ω

0V

–

IN

V

CM

SAMPLE

CLOCK

CNV

GND

0.1µF

REFBUF REFGND REFIN

0

2.5

5

7.5

0.1µF

FREQUENCY (MHz)

238716 TA1b

238716 TA01a

10µF

238716f

1

For more information www.linear.com/LTC2387-16

LTC2387-16

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage (V )..................................................6V

DD

Supply Voltage (V , OV )...................................2.8V

DDL

DD

Analog ꢀnput Voltage (Note 3)

+

–

32 31 30 29 28 27 26 25

ꢀN , ꢀN .........................(GND – ±.3V) to (V + ±.3V)

DD

+

–

GND

1

2

3

4

5

6

7

8

24 CLK

23 CLK

REFBUF.........................(GND – ±.3V) to (V + ±.3V)

DD

+

IN

REFꢀN (Note 4)...........................(GND – ±.3V) to 2.8V

–

IN

OV

DD

22

21

Digital ꢀnput Voltage (Note 3)

GND

REFGND

REFBUF

GND

33

GND

+

PD, TESTPAT ............. (GND – ±.3V) to (OV + ±.3V)

20 DCO

DD

+

–

CLK , CLK ................ (GND – ±.3V) to (OV + ±.3V)

DCO

+

19

+

18 DA

17 DA

TWOLANES, CNV ,

CNV ...........................(GND – ±.3V) to (V

–

+ ±.3V)

DDL

9

10 11 12 13 14 15 16

Power Dissipation.............................................. 5±±mW

Operating Temperature Range

LTC2387C................................................ ±°C to 7±°C

LTC2387ꢀ .............................................–4±°C to 85°C

Storage Temperature Range .................. –65°C to 15±°C

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

= 125°C, θ = 34°C/W

T

JMAX

JA

EXPOSED PAD (PꢀN 33) ꢀS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC2387CUH-16#PBF

LTC2387ꢀUH-16#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

32-Lead (5mm × 5mm) Plastic QFN

TEMPERATURE RANGE

±°C to 7±°C

–4±°C to 85°C

LTC2387CUH-16#TRPBF 238716

LTC2387ꢀUH-16#TRPBF 238716

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 5±± unit reels through

designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 6)

MIN

–±.1

TYP

MAX

UNITS

+

l

V

Absolute ꢀnput Range (ꢀN )

V

+ ±.1

V

ꢀN

REFBUF

–

+

–

Absolute ꢀnput Range (ꢀN )

(Note 6)

+ ±.1

–

+

–

– V

ꢀnput Differential Voltage Range

Common Mode ꢀnput Range

Analog ꢀnput DC Leakage Current

Analog ꢀnput Capacitance

V

– V

–V

V

REFBUF

V

ꢀN

REFBUF

+

(V + V )/2

V

/2 – ±.1

REFBUF

V

/2

V /2 + ±.1

REFBUF

V

ꢀNCM

ꢀN

REFBUF

ꢀ

–1

1

μA

ꢀN

C

Sample Mode

Hold Mode

2±

2

pF

ꢀN

CMRR

ꢀnput Common Mode Rejection Ratio

f

= 1MHz

75

dB

ꢀN

238716f

2

For more information www.linear.com/LTC2387-16

LTC2387-16

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

16

Bits

Transition Noise

±.35

±±.15

±±.±6

±±.4

LSB

RMS

l

ꢀNL

ꢀntegral Linearity Error

Differential Linearity Error

Zero-Scale Error

REFBUF = 4.±96V (Notes 7, 9)

(Note 8)

–±.8

–4

±.8

4

LSB

DNL

ZSE

LSB

Zero-Scale Error Drift

Full-Scale Error

±.±±5

LSB/°C

l

FSE

REFBUF = 4.±96V (REFBUF Overdriven) (Notes 8, 9)

REFꢀN = 2.±48V (REFꢀN Overdriven) (Note 8)

–6.5

–4±

±1.3

±7

6.5

4±

LSB

Full-Scale Error Drift

REFBUF = 4.±96V (REFBUF Overdriven) (Note 9)

REFꢀN = 2.±48V (REFꢀN Overdriven)

±±.1

±1.5

ppm/°C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS. (Notes 5, 10)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

SꢀNAD

Signal-to-(Noise + Distortion) Ratio

f

ꢀN

f

ꢀN

f

ꢀN

= 2kHz

= 1MHz

= 5MHz

91

93.9

93.2

82.6

dB

l

SNR

THD

Signal-to-Noise Ratio

f

= 2kHz

= 1MHz

= 5MHz

91.2

94

dB

ꢀN

93.8

93.1

l

Total Harmonic Distortion

(First Five Harmonics)

f

ꢀN

f

ꢀN

f

ꢀN

= 2kHz

= 1MHz

= 5MHz

–117

–1±1

–83

–1±1

–96

dB

l

SFDR

Spurious Free Dynamic Range

–3dB ꢀnput Bandwidth

f

ꢀN

f

ꢀN

f

ꢀN

= 2kHz

= 1MHz

= 5MHz

1±±

97

119

1±2

84

dB

2±±

MHz

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

= ±μA

MIN

TYP

2.±48

±5

MAX

2.±53

±2±

UNITS

V

REFꢀN

ꢀnternal Reference Output Voltage

ꢀ

2.±43

OUT

l

V

REFꢀN

Temperature Coefficient

(Note 11)

ppm/°C

kΩ

REFꢀN Output ꢀmpedance

Line Regulation

15

V

REFꢀN

V

= 4.75V to 5.25V

DD

±.3

mV/V

V

REFꢀN ꢀnput Voltage Range

(REFꢀN Overdriven) (Note 6)

2.±±8

2.±48

2.±88

238716f

3

For more information www.linear.com/LTC2387-16

LTC2387-16

REFERENCE BUFFER CHARACTERISTICS ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

= 2.±48V

MIN

4.±9±

4.±16

TYP

MAX

4.1±2

4.176

1.8

UNITS

l

V

Reference Buffer Output Voltage

REFBUF ꢀnput Voltage Range

REFBUF Load Current

V

4.±96

V

REFBUF

REFꢀN

(REFBUF Overdriven) (Notes 6, 9)

ꢀ

V

= 4.±96V (REFBUF Overdriven) (Notes 9, 12)

= 4.±96V, Sleep Mode (REFBUF Overdriven) (Note 9)

1.6

±.5

mA

REFBUF

l

V

Common Mode Output

V

= 4.±96V, ꢀ = ±μA

OUT

2.±28

2.±48

15

2.±68

V

CM

REFBUF

V

Output ꢀmpedance

–1mA < ꢀ

< 1mA

OUT

Ω

CM

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PD, TESTPAT, TWOLANES

l

V

High Level ꢀnput Voltage

Low Level ꢀnput Voltage

Digital ꢀnput Current

V

= OV = 2.5V

1.7

V

ꢀH

ꢀL

DDL

DD

= OV = 2.5V

±.6

1±

DD

ꢀ

ꢀN

= ±V to 2.5V

–1±

μA

pF

ꢀN

C

Digital ꢀnput Capacitance

3

2

ꢀN

+

–

CNV , Single-Ended Convert Start Mode (CNV Tied to GND)

l

V

ꢀH

V

ꢀL

C

ꢀN

High Level ꢀnput Voltage

Low Level ꢀnput Voltage

Digital ꢀnput Capacitance

V

= 2.5V

1.7

V

DDL

±.6

pF

+

–

CNV /CNV , Differential Convert Start Mode

l

V

Differential ꢀnput Voltage

(Note 13)

175

±.8

35±

65±

1.7

mV

V

ꢀD

Common Mode ꢀnput Voltage

1.25

ꢀCM

+

–

CLK /CLK (LVDS Clock Input)

l

V

Differential ꢀnput Voltage

175

±.8

35±

65±

1.7

mV

V

ꢀD

Common Mode ꢀnput Voltage

1.25

ꢀCM

+

–

+

–

+

–

DCO /DCO , DA /DA , DB /DB (LVDS Outputs)

l

V

OD

V

OS

Differential Output Voltage

1±±Ω Differential Load

247

35±

454

mV

V

Common Mode Output Voltage

1.125

1.25

1.375

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 6)

MIN

4.75

TYP

5

MAX

5.25

UNITS

l

V

Supply Voltage

V

DD

(Note 6)

2.375

2.5

2.625

DDL

OV

(Note 6)

DD

l

ꢀ

Supply Current

15Msps Sample Rate

Power-Down Mode (ꢀ

5

31.4

8.8

1

6

mA

μA

VDD

VDDL

OVDD

POWERDOWN

Supply Current

35

Supply Current

Power-Down Mode Current

1±.3

2±

25±

)

VDD

VDDL

+ ꢀ

OVDD

)

2

μA

l

P

Power Dissipation

Power-Down Mode

15Msps Sample Rate

Power-Down Mode (ꢀ

125

1±

144

725

mW

μW

D

+ ꢀ

)

OVDD

VDD

VDDL

ꢀ

ꢀncrease in ꢀ

with Differential CNV Mode Enabled (No ꢀncrease During Power-Down)

with Two-Lane Mode Enabled (No ꢀncrease During Power-Down)

2.1

3.6

mA

DꢀFFCNV

VDDL

OVDD

mA

TWOLANE

238716f

4

For more information www.linear.com/LTC2387-16

LTC2387-16

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

±.±2

54

TYP

MAX

15

UNITS

Msps

ns

l

f

t

Sampling Frequency

SMPL

CONV

ACQ

CNV↑ to Output Data Ready

Acquisition Time

58

63

t

– 39

ns

CYC

l

Time Between Conversions

CNV High Time

66.6

5

5±,±±±

49

ns

CYC

(Note 13)

ns

CNVH

CNVL

CNV Low Time

8

ns

CNV↑ to First CLK↑ from the Same Conversion

65

ns

FꢀRSTCLK

LASTCLK

CNV↑ to Last CLK↓ from the Previous

Conversion

ns

l

t

CLK High Time

1.25

±.7

ns

ps

ns

CLKH

CLKL

CLK Low Time

CLK to DCO Delay

CLK to DA/DB Delay

DCO to DA/DB skew

Sampling Delay Time

Sampling Delay Jitter

(Note 13)

1.3

±

2.3

2±±

CLKDCO

CLKD

SKEW

AP

±.7

t

– t

(Note 13)

CLKDCO

–2±±

CLKD

(Note 13)

±

±.25

ps

RMS

JꢀTTER

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: ꢀntegral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Zero-scale error is the offset voltage measured from –±.5LSB

when the output code flickers between ±±±± ±±±± ±±±± ±±±± and

1111 1111 1111 1111. Full-scale error is the worst-case deviation of the

first and last code transitions from ideal and includes the effect of offset

error.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above V

,

DD

V

or OV , they will be clamped by internal diodes. This product can

DDL

DD

handle input currents up to 1±±mA below ground or above V , V

or

DD DDL

OV without latchup.

Note 4: When this pin voltage is taken below ground, it will be clamped by

Note 9: When REFBUF is overdriven, the internal reference buffer must be

turned off by setting REFꢀN = ±V.

DD

an internal diode. When this pin voltage is taken above V , it is clamped

by a diode in series with a 2k resistor. This product can handle input

currents up to 1±±mA below ground without latchup.

Note 10: All specifications in dB are referred to a full-scale ±V

differential input.

Note 11: Temperature coefficient is calculated by dividing the maximum

DDL

REFBUF

Note 5: V = 5V, V

= 2.5V, OV = 2.5V, f = 15MHz,

change in output voltage by the specified temperature range.

DD

DDL

DD

SMPL

REFꢀN = 2.±48V, single-ended CNV, one-lane output mode unless

otherwise noted.

Note 6: Recommended operating conditions.

Note 12: f

= 15MHz, ꢀ

varies linearly with sample rate.

SMPL

REFBUF

Note 13: Guaranteed by design, not subject to test.

238716f

5

For more information www.linear.com/LTC2387-16

LTC2387-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 5V, V_DDL= 2.5V, OV_DD= 2.5V,

REFIN = 2.048V, f_SMPL= 15Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code (ppm)

Differential Nonlinearity vs

Output Code

Integral Nonlinearity vs

Output Code (LSB)

0.5

0.4

0.5

0.4

6.0

4.5

0.3

3.0

0.2

1.5

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–1.5

–3.0

–4.5

–6.0

0

16384

32768

49152

65536

0

16384

32768

49152

65536

0

16384

32768

49152

65536

OUTPUT CODE

238716 G01a

238716 G02

238716 G01b

32k Point FFT f_SMPL= 15Msps,

f_IN= 2kHz

32k Point FFT f_SMPL= 15Msps,

f_IN= 200kHz

DC Histogram

225000

200000

175000

150000

125000

100000

75000

50000

25000

0

–20

0

–20

σ = 0.35

SNR = 94.0dB

THD = –117dB

THD = –109dB

SINAD = 93.8dB

SFDR = 109dB

SINAD = 93.9dB

–40

SFDR = 119dB

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

N–3

N–2

N–1

N

N+1

N+2

N+3

0

2.5

5

7.5

0

2.5

5

7.5

OUTPUT CODE

FREQUENCY (MHz)

238716 G03

238716 G04

238716 G05

32k Point FFT f_SMPL= 15Msps,

f_IN= 1MHz

32k Point FFT f_SMPL= 15Msps,

f_IN= 5MHz

SNR, SINAD vs Input Frequency

96

94

92

90

88

86

84

82

80

78

0

–20

0

–20

SNR

SNR = 93.1dB

THD = –83dB

SINAD = 82.6dB

SFDR = 84dB

SNR = 93.8dB

THD = –102dB

SINAD = 93.2dB

SFDR = 103dB

–40

SINAD

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0.01

0.1

1

10

0

2.5

5

7.5

0

2.5

5

7.5

FREQUENCY (MHz)

238716 G08

238716 G07

238716 G06

238716f

6

For more information www.linear.com/LTC2387-16

LTC2387-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 5V, V_DDL= 2.5V, OV_DD= 2.5V,

REFIN = 2.048V, f_SMPL= 15Msps, unless otherwise noted.

THD vs Input Frequency

and Amplitude

SFDR vs Input Level, f_IN= 2kHz

SFDR vs Input Level, f_IN= 1MHz

150

140

130

120

110

100

90

–70

–80

150

140

130

120

110

100

90

–1dBFS

–3dBFS

–6dBFS

–10dBFS

dBFS

–90

–100

–110

–120

–130

–140

dBc

80

70

60

50

–70 –60 –50 –40 –30 –20 –10

0

–70 –60 –50 –40 –30 –20 –10

0

0.01

0.1

1

10

INPUT LEVEL (dBFS)

FREQUENCY (MHz)

238716 G11

238716 G10

238716 G09

SNR, SINAD vs Temperature,

THD, Harmonics vs Temperature,

f_IN= 2kHz, –1dBFS

INL/DNL vs Temperature

0.40

0.30

95

94

93

92

91

–105

–110

–115

–120

–125

SNR

SINAD

MAX INL

MAX DNL

MIN DNL

MIN INL

THD

2ND

3RD

0.20

0.10

–0.00

–0.10

–0.20

–0.30

–0.40

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

238716 G14

238716 G13

TEMPERATURE (°C)

238716 G12

Full-Scale Error vs Temperature,

REFBUF = 4.096V

Zero-Scale Error vs Temperature

Supply Current vs Temperature

35

30

25

20

15

10

5

1.5

1.0

1.5

1.0

0.5

+ FS

I

VDDL

VDD

OVDD

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

– FS

0

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

238716 G15

238716 G16

238716 G17

238716f

7

For more information www.linear.com/LTC2387-16

LTC2387-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 5V, V_DDL= 2.5V, OV_DD= 2.5V,

REFIN = 2.048V, f_SMPL= 15Msps, unless otherwise noted.

Analog Input Current

vs Differential Input Voltage

Internal Reference Output

vs Temperature

Supply Current vs Sample Rate

35

30

25

20

15

10

5

1.00

0.75

0.50

0.25

0

2.050

2.049

2.048

2.047

f

= 15Msps

SMPL

THREE TYPICAL UNITS

–

IN

I

VDDL

VDD

OVDD

–0.25

–0.50

–0.75

–1.00

+

IN

0

5

10

15

–4.096

–2.048

0

2.048

4.096

–40

–20

0

20

40

60

80

SAMPLE RATE (MHz)

DIFFERENTIAL INPUT (V)

TEMPERATURE (°C)

238716 G18

238716 G19

238716 G20

PIN FUNCTIONS

GND (Pins 1, 4, 10, 21, 26, 29 ): Ground. Connect to a

can be applied to REFIN if a more accurate reference is

required.Forincreasedfilteringofreferencenoise,bypass

this pin to GND using a 0.1µF or larger ceramic capacitor.

If the internal reference buffer is not used, tie REFIN to

GND to power down the buffer and connect an external

buffered reference to REFBUF.

solid ground plane in the PCB underneath the ADC.

+

–

IN , IN (Pins 2, 3): Positive and Negative Differential

Analog Inputs. The inputs must be driven differentially

and 180° out of phase, with a common mode voltage of

2.048V.Thedifferentialinputrangeis±4.0ꢀ 6V(eachinput

pin swings from 0V to 4.0ꢀ 6V.)

V

(Pins 11, 12): 5V Analog Power Supply. The range

DD

together and bypassed to GND with 0.1μF and 10μF ce-

ramic capacitors.

DD

of V is 4.75V to 5.25V. The two pins should be shorted

REFGND (Pins 5, 6): Reference Ground. The two pins

should be shorted together and connected to the refer-

ence bypass capacitor with a short, wide trace. In ad-

dition, connect the pins to the exposed pad (Pin 33). A

suggested layout is shown in the ADC Reference section

of the data sheet.

PD (Pin 13): Digital input that enables power-down mode.

When PD is low, the LTC2387 enters power-down mode,

and all circuitry (including the LVDS interface) is shut

down. When PD is high, the part operates normally. Logic

REFBUF (Pins 7, 8): Internal Reference Buffer Output.

The output voltage of the internal 2× gain reference buffer,

nominally 4.0ꢀ 6V, is provided on this pin. The two pins

should be shorted together and bypassed to REFGND with

a 10µF (X7R, 0805 size) ceramic capacitor. If the internal

buffer is not required, tie REFIN to GND to power down

the buffer and connect an external 4.0ꢀ 6V reference to

REFBUF.

levels are determined by OV .

DD

TESTPAT (Pin 14): Digital input that forces the LVDS data

outputs to be a test pattern. When TESTPAT is high, the

digital outputs are a test pattern. When TESTPAT is low,

the digital outputs are the ADC conversion result. Logic

levels are determined by OV .

DD

–

+

–

+

DB /DB , DA /DA (Pins 15/16, 17/18): Serial LVDS

–

+

REFIN(Pin9):InternalReferenceOutput/ReferenceBuffer

Input. The output voltage of the internal reference, nomi-

nally 2.048V, is output on this pin. An external reference

Data Outputs. In one-lane output mode, DB /DB are not

used and their LVDS driver is disabled to reduce power

consumption.

238716f

8

For more information www.linear.com/LTC2387-16

LTC2387-16

PIN FUNCTIONS

DCO /DCO (Pins 19/20): LVDS Data Clock Output. This

is an echoed version of CLK /CLK that can be used to

latch the data outputs.

–

+

into the hold mode and starts a conversion cycle. CNV

–

+

–

can also be driven with a 2.5V CMOS signal if CNV is

tied to GND.

OV (Pin 22): 2.5V Output Power Supply. The range of

V

(Pins 30, 31): 2.5V Analog Power Supply. The

DD

DDL

range of V

OV is 2.375V to 2.625V. Bypass to GND with a 0.1μF

is 2.375V to 2.625V. The two pins should

DD

DDL

ceramic capacitor.

be shorted together and bypassed to GND with 0.1μF and

10μF ceramic capacitors.

–

+

CLK /CLK (Pins 23/24): LVDS Clock Input. This is an

externally applied clock that serially shifts out the conver-

sion result.

V

CM

(Pin 32): Common Mode Output. V , nominally

CM

2.048V, can be used to set the common mode of the ana-

log inputs. Bypass to GND with a 0.1μF ceramic capacitor

TWOLANES (Pin 25): Digital input that enables two-lane

close to the pin. If V is not used, the bypass capacitor

CM

output mode. When TWOLANES is high (two-lane output

is not necessary as long as the parasitic capacitance on

–

+

mode), the ADC outputs two bits at a time on DA /DA

the V pin is under 10pF.

–

+

CM

and DB /DB . When TWOLANES is low (one-lane output

–

+

mode), the ADC outputs one bit at a time on DA /DA , and

Exposed Pad (Pin 33): The exposed pad on the bottom

of the package. Connect to the ground plane of the PCB

using multiple vias.

–

+

DB /DB aredisabled.LogiclevelsaredeterminedbyV

.

DDL

–

+

CNV /CNV (Pins 27/28): Conversion Start LVDS Input.

+

A rising edge on CNV puts the internal sample-and-hold

FUNCTIONAL BLOCK DIAGRAM

V

DDL

OV

DD

CNV

TWOLANES

CONTROL

TESTPAT

LOGIC

PD

CLK

+

–

IN

+

DCO

SERIAL

LVDS

INTERFACE

16-BIT, 15Msps ADC

DA

DB

–

V

CM

0.5

15k

2.048V

REFERENCE

2

GND

REFGND

REFBUF

REFIN

238716 BD

238716f

9

For more information www.linear.com/LTC2387-16

LTC2387-16

TIMING DIAGRAM

238716f

10

For more information www.linear.com/LTC2387-16

LTC2387-16

TIMING DIAGRAM

238716f

11

For more information www.linear.com/LTC2387-16

LTC2387-16

TIMING DIAGRAM

Data Output Timing

t

CLKL

CLKH

–

+

CLK

t

CLKDCO

–

+

DCO

t

CLKD

–

DA

+

–

DA

DB

+

DB

238716 TD03

APPLICATIONS INFORMATION

OVERVIEW

CONVERTER OPERATION

TheLTC2387-16isalownoise,highspeed,16-bitsucces-

siveapproximationregister(SAR)ADC.Operatingfrom5V

and 2.5V supplies, the LTC2387-16 has a fully differential

±4.0ꢀ 6V input range, making it ideal for applications that

require a wide dynamic range. The LTC2387-16 achieves

±0.8 LSB INL (maximum), no missing codes at 16-bits

and ꢀ 4dB SNR (typical).

The LTC2387-16 operates in two phases. During the ac-

quisition phase, the sample capacitors are connected to

the analog input pins IN and IN to sample the differential

analog input voltage. A rising edge on the CNV pin initiates

a conversion. During the conversion phase, the ADC is

sequencedthroughasuccessiveapproximationalgorithm,

comparing the sampled input with binary-weighted frac-

+

–

tions of the reference voltage (e.g. V

/2, V

/4

REFBUF

The LTC2387-16 includes a precision internal 2.048V

reference, with a guaranteed 0.25% initial accuracy and

a ±20ppm/°C (maximum) temperature coefficient, as well

as an internal reference buffer. The LTC2387-16 also has

a high speed serial LVDS interface that can output one or

two bits at a time. The fast 15Msps throughput with no

pipeline latency makes the LTC2387-16 ideally suited for

awidevarietyofhighspeedapplications.TheLTC2387-16

dissipates only 125mW at 15Msps and has a power-down

mode to reduce the power consumption to 10μW during

inactive periods.

… V

/65536) using a differential comparator. At the

REFBUF

end of conversion, control logic prepares the 16-bit digital

output code for serial transfer.

TRANSFER FUNCTION

The LTC2387-16 digitizes the full-scale voltage of 2×

16

REFBUF into 2 levels, resulting in an LSB size of 125μV

withREFBUF=4.0ꢀ 6V.Theoutputdataisintwo’scomple-

ment format. The ideal transfer function is shown in

Figure 1. The ideal offset binary transfer function can be

obtained from the two’s complement transfer function by

invertingthemostsignificantbit(MSB)ofeachoutputcode.

238716f

12

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

The inputs draw a small current spike while charging the

SAMPLE

consistentanddoesnotdependonthepreviouslysampled

input voltage. During conversion and power-down, the

analog inputs draw only a small leakage current.

011...111

C

capacitorsduringacquisition.Thiscurrentspikeis

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

Input Drive Circuits

A low impedance source can directly drive the high im-

pedance inputs of the LTC2387-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC signals because the ADC inputs

draw a current spike when entering acquisition.

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/65536

–1 0V

1

LSB

–FSR/2

FSR/2 – 1LSB

LSB

INPUT VOLTAGE (V)

238716 F01

Figure 1. LTC2387-16 Transfer Function

ANALOG INPUTS

The LTC2387-16 has a fully differential ±4.0ꢀ 6V input

range. The IN and IN pins should be driven 180 degrees

out-of-phase with respect to each other, centered around

a common mode voltage (IN + IN )/2 that is restricted

For best performance, a buffer amplifier should be used

to drive the analog inputs of the LTC2387-16. The ampli-

fier provides low output impedance enabling fast settling

of the analog signal during the acquisition phase. It also

providesisolationbetweenthesignalsourceandthecurrent

spike drawn by the ADC inputs when entering acquisition.

+

–

+

–

to (V

/2 ± 0.1V). The ADC samples and digitizes the

REFBUF

+

voltage difference between the two analog input pins (IN

–

The LTC2387-16 is optimized for pulsed inputs that are

fully settled when sampled, or dynamic signals up to the

Nyquist frequency (7.5MHz). Input signals that change

faster than 300mV/ns when they are sampled are not

− IN ), and any unwanted signal that is common to both

inputs is reduced by the common mode rejection ratio

(CMRR) of the ADC. The analog inputs can be modeled

by the equivalent circuit shown in Figure 2. The diodes

and 10Ω resistors at the input provide ESD and overdrive

protection. In the acquisition phase, each input sees ap-

recommended. This is equivalent to an 8V sine wave

P-P

at 12MHz.

proximately 18pF (C

) from the sampling capacitor

SAMPLE

Input Filtering

in series with 28Ω (R ) from the on-resistance of the

ON

sampling switch. C

is a lumped capacitance on the

The noise and distortion of the buffer amplifier and other

supporting circuitry must be considered since they add

to the ADC noise and distortion. A buffer amplifier with

low noise density must be selected to minimize SNR

degradation. A filter network should be placed between

the buffer output and ADC input to both minimize the

noise contribution of the buffer and reduce disturbances

reflected into the buffer from ADC sampling transients. A

simple one-pole lowpass RC filter is sufficient for many

applications. It is important that the RC time constant of

this filter be small enough to allow the analog inputs to

PAR

order of 2pF formed primarily of diode junctions.

V

DD

C

SAMPLE

18pF

10Ω

28Ω

+

IN

C

PAR

2pF

BIAS

VOLTAGE

V

DD

SAMPLE

18pF

10Ω

C

–

IN

settlewithintheADCacquisitiontime(t ),asinsufficient

PAR

ACQ

2pF

settling can limit INL and THD performance.

238716 F02

High quality capacitors and resistors should be used in

Figure 2. Equivalent Circuit for the Differential Analog

Inputs of the LTC2387-16

the RC filters since these components can add distortion.

238716f

13

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

NPO type dielectric capacitors have excellent linearity.

Carbon surface mount resistors can generate distortion

from self-heating and from damage that may occur during

soldering. Metal film surface mount resistors are much

less susceptible to both problems.

Input Currents

One of the biggest challenges in coupling an amplifier to

the LTC2387-16 is in dealing with current spikes drawn

by analog inputs at the start of each acquisition phase.

Theanaloginputsmaybemodeledasaswitchedcapacitor

loadonthedrivecircuit.Adrivecircuitmayrelypartiallyon

attenuating switched-capacitor current spikes with small

filter capacitors placed directly at the ADC inputs and par-

tially on the driver amplifier having sufficient bandwidth to

recoverfromtheresidualdisturbance.Amplifiersoptimized

for DC performance may not have sufficient bandwidth

to fully recover at the ADC’s maximum conversion rate,

whichcanproducenonlinearityandothererrors.Coupling

filter circuits may be classified in two broad categories:

Figure 3 shows a typical input drive circuit with an RC

filter. The optimal values for R and C are application spe-

cific and may require experimentation. Setting R = 24.9Ω

gives good performance over a wide range of conditions.

4.096V

24.9Ω

0V

+

C

FILT

IN

LTC2387-16

–

4.096V

IN

C

FILT

Fully Settled – This case is characterized by filter time

constants and an overall settling time that are consider-

ably shorter than the sample period. When acquisition

begins, the coupling filter is disturbed. For a typical first

order RC filter, the disturbance will look like an initial step

with an exponential decay. The amplifier will have its own

response to the disturbance, which may include ringing. If

the input settles completely (to within the accuracy of the

LTC2387-16),thedisturbancewillnotcontributeanyerror.

0V

238716 F03

24.9Ω

Figure 3. Typical Input Drive Circuit

The value for C

involves a trade off: larger values give

FILT

betternoise,andsmallervaluesgivebetterfull-scaleerror.

Figure 4 shows a range of capacitor values to consider as

a starting point based on the sample rate.

PartiallySettled–Inthiscase, thebeginningofacquisition

causes a disturbance of the coupling filter, which then

begins to settle out towards the nominal input voltage.

However, acquisition ends (and the conversion begins)

before the input settles to its final value. This generally

produces a gain error, but as long as the settling is linear,

no distortion is produced. The coupling filter’s response

is affected by the amplifier’s output impedance and other

parameters. A linear settling response to fast switched-

capacitor current spikes can NOT always be assumed for

precision, low bandwidth amplifiers. The coupling filter

serves to attenuate the current spikes’ high-frequency

energy before it reaches the amplifier.

400

350

MAX VALUE (LOWER NOISE)

300

250

200

150

100

50

MIN VALUE

(LOWER FULL–SCALE ERROR)

9

10

11

12

13

14

15

SAMPLE RATE (Msps)

238716 F04

Figure 4. Suggested Range of C_FILTValues vs Sample Rate

238716f

14

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

ADC REFERENCE

REFIN

0.1µF

10µF

TheinternalreferencecircuitryoftheLTC2387-16isshown

in Figure 5. There is a low noise, low drift (20ppm/°C),

bandgapreferenceconnectedtoREFIN(Pin9).Aninternal

reference buffer gains the REFIN voltage by 2× to 4.096V

at REFBUF (Pins 7, 8). The voltage difference between

REFBUFandREFGNDdeterminesthefull-scaleinputrange

of the ADC. The reference and reference buffer can also

be externally driven if desired.

LTC2387-16

REFBUF

REFGND

238716 F06

Figure 6. Configuration for Using the Internal Reference

Figure 7 shows a suggested layout for the REFBUF capaci-

tor. The capacitor should be connected to REFBUF and

REFGND through short, wide traces. REFGND should also

be connected with a wide trace to the grounded exposed

pad (Pin 33).

LTC2387-16

15k

REFIN

2.048V

9

REFERENCE

REFBUF

8

7

6

5

2×

1

2

3

4

5

6

7

8

ADC

CORE

8k

REFGND

238716 F05

Figure 5. LTC2387-16 Internal Reference Circuitry

9

10 11 12

Internal Reference with Internal Reference Buffer

To use the internal reference and internal reference buf-

fer, bypass REFIN to GND with a 0.1μF ceramic capacitor

(Figure 6). Bypass REFBUF to REFGND with a single 10μF

(X7R,0805size)ceramiccapacitor.TheREFBUFcapacitor

shouldbeascloseaspossibletotheLTC2387-16package

to minimize wiring inductance. Do not place this capaci-

tor on the opposite side of the board. Adding a second,

smaller capacitor in parallel with the 10μF may degrade

performance and is not recommended.

238716 F07

Figure 7. Suggested REFBUF Bypass Capacitor Layout

238716f

15

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

External Reference with Internal Reference Buffer

REFIN

If more accuracy and/or lower drift is desired, REFIN can

be directly overdriven by an external 2.048V reference as

shown in Figure 8. Linear Technology offers a portfolio of

high performance references designed to meet the needs

of many applications. With its small size, low power, and

high accuracy, the LTC6655-2.048 is well suited for use

with the LTC2387-16 when overdriving the internal ref-

erence. The LTC6655-2.048 offers 0.025% (max) initial

accuracy and 2ppm/°C (max) temperature coefficient for

highprecisionapplications.BypassingtheLTC6655-2.048

with a 2.7μF to 10μF ceramic capacitor close to the REFIN

pin is recommended.

LTC2387-16

LTC6655-4.096

5V

V

REFBUF

IN

OUT_F

SHDN

V

OUT_S

GND

10µF

0.1µF

REFGND

238716 F09

Figure 9. Overdriving REFBUF Using the LTC6655-4.096

Common Mode Output

TheV pinisanoutputthatprovidesone-halfthevoltage

CM

present on the REFBUF pin. This voltage can be used to

setthecommonmodeofadifferentialamplifierdrivingthe

LTC6655-2.048

analog inputs. Bypass V to GND with a 0.1μF ceramic

CM

5V

V

REFIN

IN

SHDN

OUT_F

capacitor. If V is not used it can be left floating, but the

CM

OUT_S

LTC2387-16

2.7µF

10µF

GND

0.1µF

parasitic capacitance on the pin needs to be under 10pF.

REFBUF

TheV outputhas1/fnoisewhichformostdrivercircuits

CM

will be removed by the ADC common mode rejection ratio.

REFGND

V

is not recommended for single-ended to differential

CM

238716 F08

circuits that pass the V noise to only one ADC input.

CM

Figure 8. Using the LTC6655-2.048 as an External Reference

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2387-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

External Reference Buffer

The internal reference buffer can also be overdriven with

an external 4.096V reference at REFBUF as shown in

Figure 9. To do so, REFIN must be grounded to disable

the reference buffer. The external reference must have a

fast transient response and be able to drive the 0.5mA

to 1.6mA load at the REFBUF pin. The LTC6655-4.096 is

recommended when overdriving REFBUF.

238716f

16

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

Signal-to-Noise and Distortion Ratio (SINAD)

0

–20

SNR = 94.0dB

THD = –117dB

SINAD = 93.9dB

SFDR = 119dB

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure10showsthattheLTC2387-16achieves

a typical SINAD of 93.9dB at a 15MHz sampling rate with

a 2kHz input.

–40

–60

–80

–100

–120

–140

–160

0

2.5

5

7.5

Signal-to-Noise Ratio (SNR)

FREQUENCY (MHz)

238716 F10

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 10 shows

that the LTC2387-16 achieves a typical SNR of 94dB at a

15MHz sampling rate with a 2kHz input.

Figure 10. 32k Point FFT of the

LTC2387-16, f_SMPL= 15Msps, f_IN= 2kHz

POWER CONSIDERATIONS

The LTC2387-16 requires three power supplies: V (5V),

DD

V

DDL

(2.5V), and OV (2.5V). Bypass V to GND with

DD DD

a 0.1μF ceramic capacitor close to the pair of pins and a

10μF ceramic capacitor in parallel. Bypass V to GND

Total Harmonic Distortion (THD)

DDL

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

with a 0.1μF ceramic capacitor close to the pair of pins

and a 10μF ceramic capacitor in parallel. OV can come

DD

from the same source as V

but it should be isolated

by a ferrite bead and have its own 0.1μF bypass capacitor.

DDL

/2).

SMPL

Power Supply Sequencing

2

V2²+V3²+V4²+…+ V_n

THD=20log

The LTC2387-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2387-16

has a power-on-reset (POR) circuit that will reset the

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through V are the amplitudes of the

second through nth harmonics. Figure 10 shows that the

LTC2387-16achievesatypicalTHDof–117dBata15MHz

sampling rate with a 2kHz input.

n

LTC2387-16 at initial power-up or whenever V or V

DD

DDL

drops well below their minimum values. Once the supply

voltage re-enters the nominal supply voltage range, the

POR will reinitialize the ADC.

238716f

17

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

Power-Down Mode

+

edge of CNV should be driven by a clean low jitter signal.

Note that the ADC is less sensitive to jitter on the falling

When PD is pulled low, LTC2387-16 enters power-down

mode. In this state, all internal functions, including the

referenceandLVDSoutputs,areturnedoffandsubsequent

conversionrequestsareignored. Thepowerconsumption

drops to a typical value of 10µW. This mode can be used

if the LTC2387-16 is inactive for a long period of time and

the user wants to minimize power dissipation.

+

edge of CNV .

In applications that are insensitive to jitter, CNV can be

driven directly from an FPGA.

Internal Conversion Clock

The LTC2387-16 has an internal clock that is trimmed

to achieve a maximum conversion time of 63ns. With a

typical acquisition time of 27.7ns, throughput perfor-

mance of 15Msps is guaranteed.

The amount of time required to recover from power-down

modedependsonhowREFBUFisconfigured. Whenusing

the internal reference buffer with a 10µF bypass capacitor,

the ADC will stabilize after 20ms. If REFBUF is externally

driven, the recovery time can be significantly less.

DIGITAL INTERFACE

The LTC2387-16 has a serial LVDS digital interface that

is easy to connect to an FPGA. Three LVDS pairs are re-

quired: CLK , DCO , and DA . A fourth LVDS pair, DB ,

is optional (Figure 11).

TIMING AND CONTROL

CNV Timing

±

+

TheLTC2387-16conversioniscontrolledbytheCNV and

–

+

–

CNV inputs. CNV /CNV can be driven directly with an

LTC2387-16

FPGA

+

–

CLK

+

–

LVDS signal. Alternatively, CNV can be driven with a 0V

100Ω

to 2.5V CMOS signal when CNV is tied to GND. A rising

–

+

CLK

+

edge on CNV will sample the analog inputs and start a

DCO

+

–

conversion. The pulse width of CNV should meet the

100Ω

t

and t

specifications in the timing table.

–

+

CNVH

CNVL

DCO

DA

AftertheLTC2387-16ispoweredon, orexitspower-down

mode, conversion data is invalid for the first two conver-

sion cycles. Subsequent results are accurate as long as

+

–

100Ω

–

+

DA

DB

+

–

thetimebetweenconversionsmeetsthet specification.

CYC

OPTIONAL

DB

–

If the analog input signal has not completely settled when

it is sampled, the ADC noise performance will be affected

by jitter on the rising edge of CNV . In this case the rising

238716 F11

+

Figure 11. Digital Output Interface to an FPGA

238716f

18

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

The LVDS signals should be routed on the PC board as

100Ω differential transmission lines and terminated at the

receiver with 100Ω resistors.

Data must be clocked out after the current conversion is

complete,andbeforethenextconversionfinishes.Thevalid

time window for clocking out data is shown in Figure 13.

Note that it is allowed to be still clocking out data when

the next conversion begins.

+

A conversion is started by the rising edge of CNV . When

the conversion is complete, the most-significant data bit

±

is output on DA . Data is then ready to be shifted out by

Two-Lane Output Mode

±

applying a burst of eight clock pulses to the CLK input.

±

At high sample rates the required LVDS interface data rate

can reach >400Mbps. Most FPGAs can support this, but

if a lower data rate is desired, the two-lane output mode

can be used. When the TWOLANES input pin is tied high,

The data on DA is updated by every edge of CLK . An

±

echoed version of CLK is output on DCO . The edges of

±

DA and DCO are aligned, so DCO can be used to latch

±

DA in the FPGA. The timing of a single conversion is

shown in Figure 12.

CNV

1

2

3

4

5

6

7

8

CLK

DCO

t

CONV

D15

14 13 12

11 10 D9

D8 D7

D6 D5 D4

D3 D2

D1 D0

LSB

DA

238716 F12

MSB

Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode

CONVERSION N

CONVERSION N+1

CNV

CLK

t

FIRSTCLK

LASTCLK

1

2

3

4

5

6

7

8

238716 F13

TIME WINDOW FOR CLOCKING OUT CONVERSION N

Figure 13. Valid Time Window for Clocking Out Data

238716f

19

For more information www.linear.com/LTC2387-16

LTC2387-16

APPLICATIONS INFORMATION

±

the optional LVDS output DB is enabled, and data is out-

(except for REFBUF). The traces connecting the pins and

bypass capacitors must be kept short and should be made

as wide as possible.

±

put two bits at a time on DA and DB . Enabling the DB

output increases the supply current from OV by about

DD

3.6mA. In two-lane mode, four clock pulses are required

Of particular importance is the capacitor between REFBUF

and REFGND, which should be a 10μF (X7R, 0805 size)

ceramic capacitor. This capacitor should be on the same

side of the circuit board as the ADC, and as close to the

device as possible. Adding a second, smaller capacitor in

parallel with the 10μF may degrade performance and is

not recommended.

±

for CLK (see Timing Diagrams).

Output Test Patterns

To allow in-circuit testing of the digital interface to the

ADC, there is a test mode that forces the ADC data outputs

to known values:

One-Lane Mode: 1010 0000 0111 1111

Two-Lane Mode: 1100 1100 0011 1111

Theanaloginputs,convertstart,anddigitaloutputsshould

not be routed next to each other. Ground fill and grounded

vias should be used as barriers to isolate these signals

from each other.

The test pattern is enabled when the TESTPAT pin is

brought high.

Exposed Package Pad

BOARD LAYOUT

For good electrical and thermal performance, the exposed

pad on the bottom of the package must be soldered to a

large grounded pad on the PC board. This pad should be

connectedtotheinternalgroundplanesbyanarrayofvias.

The LTC2387-16 requires a printed circuit board with a

clean unbroken ground plane. A multilayer board with an

internal ground plane in the first layer beneath the ADC is

recommended. Layoutfortheprinted circuitboardshould

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

Mechanical Stress Shift

The mechanical stress of mounting a part to a board can

cause subtle changes to the SNR and internal voltage

reference. The best soldering method is to use IR reflow

or convection soldering with a controlled temperature

profile. Hand soldering with a heat gun or a soldering iron

is not recommended.

High quality ceramic bypass capacitors should be used

at the V , V , OV , V , REFIN, and REFBUF pins.

DD DDL

DD CM

Bypass capacitors must be located as close to the pins as

possible. Size 0402 ceramic capacitors are recommended

238716f

20

For more information www.linear.com/LTC2387-16

LTC2387-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2387-16#packaging for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

3.50 REF

(4 SIDES)

3.45 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ±0.05

5.00 ±0.10

(4 SIDES)

31 32

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ±0.10

3.50 REF

(4-SIDES)

3.45 ±0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ±0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

238716f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

21

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2387-16

LTC2387-16

TYPICAL APPLICATION

Input Drive Circuit with Low Distortion up to 1MHz

0

–20

5V

0.1µF

2.5V 2.5V

SNR = 93dB

THD = –115dB

SINAD = 93dB

SFDR = 115dB

0.1µF

–40

4.096V

24.9Ω

0V

–60

V

OV

DD

DDL

CLK

DCO

DA

LVDS

+

–80

82pF

IN

INTERFACE

1/2 LT6201

f

IN

< 1MHz

DB

LTC2387-16

–100

–120

–140

–160

TWOLANES

TESTPAT

PD

–

4.096V

IN

82pF

0V

REFBUF REFGND

REFIN

CNV

15MHz

SAMPLE

CLOCK

24.9Ω

238716 TA02

1/2 LT6201

0.1µF

0

2.5

5

7.5

10µF

FREQUENCY (MHz)

238716 TA02b

128k Point FFT, f_SMPL= 15Msps,

f_IN= 50kHz

Low Power, Low Noise Input Drive Circuit for Signals up to 8kHz

0

+7.5V

SNR = 94.0dB

4.096V

–20

THD = –114dB

1/2 LT6237

5.1Ω

SINAD = 94.0dB

SFDR = 116dB

0V

24.9Ω

–40

10nF

20Ω

f

< 8kHz

C1

–60

–80

+

IN

27nF

68pF

4.096V

LTC2387-16

1/2 LT6237

5.1Ω

–

–100

–120

–140

–160

0V

C2

27nF

IN

68pF

24.9Ω

10nF

20Ω

238716 TA03

-2.5V

C1, C2: GRM3195C1H273JA01D OR OTHER NP0 CAPACITOR

0

50

100

150

200

FREQUENCY (kHz)

238716 TA03b

128k Point FFT, f_SMPL= 15Msps,

f_IN= 8kHz (Zoomed View)

RELATED PARTS

PART NUMBER DESCRIPTION

ADCs

COMMENTS

LTC2378-20

LTC2387-18

LTC2271

20-Bit, 1Msps, Low Power SAR ADC

104dB SNR, –125dB THD, 21mW at 1Msps

18-Bit, 15Msps SAR ADC

95.7dB SNR, 102dB SFDR, ±3LSB INL (Max)

84.1dB SNR, 99dB SFDR, 92mW per Channel

16-Bit, 20Msps Serial Dual ADC

References

LTC6655

Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Amplifiers

LT6200

Low Noise Op-Amp

0.95nV/√Hz, Up to 1.6GHz GBW

238716f

LT 1015 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

22

For more information www.linear.com/LTC2387-16

●

 LINEAR TECHNOLOGY CORPORATION 2015

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2387-16


型号：	LTC2387IUH-16#PBF
厂家：	Linear
描述：	LTC2387-16 - 16-Bit, 15Msps SAR ADC; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 转换器
文件：	总22页 (文件大小：1149K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2387IUH-16#PBF [Linear]

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