LTC2401_技术文档

Final Electrical Specifications

LTC2401/LTC2402

1-/2-Channel 24-Bit µPower

No Latency ∆Σ^TMADC in MSOP-10

January 2000

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FEATURES

DESCRIPTIO

■

24-Bit ADC in Tiny MSOP-10 Package

The LTC^®2401/LTC2402 are 1- and 2-channel 2.7V to

5.5Vmicropower24-bitanalog-to-digitalconverterswith

an integrated oscillator, 4ppm INL and 0.6ppm RMS

noise. These ultrasmall devices use delta-sigma technol-

ogy and a new digital filter architecture that settles in a

single cycle. This eliminates the latency found in conven-

tional ∆Σ converters and simplifies multiplexed applica-

tions.

■

1- or 2-Channel Inputs

■

Automatic Channel Selection (Ping-Pong) (LTC2402)

Zero Scale and Full Scale Set for Reference

and Ground Sensing

4ppm INL, No Missing Codes

4ppm Full-Scale Error

0.5ppm Offset

0.6ppm Noise

Internal Oscillator—No External Components Required

110dB Min, 50Hz/60Hz Notch Filter

Single Conversion Settling Time for

Multiplexed Applications

Reference Input Voltage: 0.1V to V_CC

Live Zero—Extended Input Range Accommodates

12.5% Overrange and Underrange

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200µA) and Auto Shutdown

■

Through a single pin, the LTC2401/LTC2402 can be

configured for better than 110dB rejection at 50Hz or

60Hz ±2%, or can be driven by an external oscillator for

a user defined rejection frequency in the range 1Hz to

120Hz. The internal oscillator requires no external fre-

quency setting components.

■

These converters accept an external reference voltage

from 0.1V to V_CC. With an extended input conversion

■

range of –12.5% V_REFto 112.5% V_REF(V_REF= FS_SET

–

ZS_SET), the LTC2401/LTC2402 smoothly resolve the off-

set and overrange problems of preceding sensors or

signal conditioning circuits.

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APPLICATIO S

■

Weight Scales

The LTC2401/LTC2402 communicate through a 2- or

3-wire digital interface that is compatible with SPI and

MICROWIRE^TMprotocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

■

Direct Temperature Measurement

■

Gas Analyzers

Strain-Gage Transducers

Instrumentation

Data Acquisition

Industrial Process Control

■

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TYPICAL APPLICATIO

Pseudo Differential Bridge Digitizer

2.7V TO 5.5V

V

CC

1µF

1

2

4

3

5

= INTERNAL OSC/50Hz REJECTION

V

1

10

CC

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2402

SET

FS

9

SCK

SDO

CS

2

3

4

5

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SET

SCK

SDO

CS

SET

CC

ANALOG

INPUT RANGE

TO 1.12V

8

3-WIRE

SPI INTERFACE

CH0

CH1

ZS

3-WIRE

SPI INTERFACE

CH1

CH0

ZS

7

–0.12V

REF

(V

REF

= FS

– ZS

)

SET

10

F

O

SET

INTERNAL OSCILLATOR

60Hz REJECTION

0V TO FS

– 100mV

GND

SET

GND

6

24012 TA01

24012TA02

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.

1

LTC2401/LTC2402

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ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Operating Temperature Range

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (V_CC+ 0.3V)

Reference Input Voltage to GND .. –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

LTC2401/LTC2402C ................................ 0°C to 70°C

LTC2401/LTC2402I ............................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

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W

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PACKAGE/ORDER INFORMATION

ORDER PART NUMBER

TOP VIEW

LTC2401CMS

LTC2401IMS

V

CC

10 F

1

2

3

4

5

10 F

O

LTC2402CMS

LTC2402IMS

V

SET

V

1

2

3

CC

O

FS

9

8

7

6

SCK

SDO

CS

9

8

7

6

SCK

SDO

CS

SET

CH1

CH0

IN

NC 4

SET

ZS

SET

ZS

5

GND

MS10 PART MARKING

MS10 PACKAGE

10-LEAD PLASTIC MSOP

MS10 PACKAGE

10-LEAD PLASTIC MSOP

LTMB

LTMC

LTMD

LTME

T_JMAX= 125°C, θ_JA= 130°C/W

Consult factory for Military grade parts.

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CONVERTER CHARACTERISTICS _{The ● denotes specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. V_REF= FS_SET– ZS_SET. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

24

TYP

MAX

UNITS

Bits

Resolution

●

No Missing Codes Resolution

Integral Nonlinearity

0.1V ≤ FS

≤ V , ZS = 0V (Note 5)

SET

24

Bits

SET

CC

FS = 2.5V, ZS = 0V (Note 6)

●

2

4

10

15

ppm of V

SET

REF

FS = 5V, ZS = 0V (Note 6)

SET

Offset Error

2.5V ≤ FS

≤ V , ZS = 0V

●

0.5

0.01

4

2

ppm of V

SET

CC

SET

REF

Offset Error Drift

Full-Scale Error

2.5V ≤ FS

≤ V , ZS = 0V

ppm of V /°C

REF

CC

SET

≤ V , ZS = 0V

●

10

ppm of V

REF

CC

SET

Full-Scale Error Drift

Total Unadjusted Error

≤ V , ZS = 0V

0.04

ppm of V /°C

REF

CC

SET

FS = 2.5V, ZS = 0V

5

10

ppm of V

SET

REF

FS = 5V, ZS = 0V

SET

Output Noise

V

IN

= 0V (Note 13)

3

µV

RMS

Normal Mode Rejection 60Hz ±2%

Normal Mode Rejection 50Hz ±2%

Power Supply Rejection, DC

(Note 7)

(Note 8)

●

110

130

100

110

dB

FS = 2.5V, ZS = 0V, V = 0V

SET

IN

Power Supply Rejection, 60Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Note 7)

SET

IN

Power Supply Rejection, 50Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Note 8)

SET

IN

2

LTC2401/LTC2402

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A ALOG I PUT A D REFERE CE

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_REF= FS_SET– ZS_SET. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Voltage Range

(Note 14)

●

–0.125 • V

1.125 • V

REF

IN

REF

FS

SET

Full-Scale Set Range

Zero-Scale Set Range

Input Sampling Capacitance

Reference Sampling Capacitance

Input Leakage Current

0.1 + ZS

0

V

CC

V

SET

ZS

FS – 0.1

SET

V

SET

C

10

15

1

pF

nA

S(IN)

S(REF)

I

CS = V

●

–10

–12

10

12

IN(LEAK)

REF(LEAK)

CC

V

= 2.5V, CS = V

1

^{Reference Leakage Curre}U ^nt

REF

CC

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The ● denotes specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

●

2.5

2.0

V

IH

IL

IH

IL

CC

CS, F

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

CS, F

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 9)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 9)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 9)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 9)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 9)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F

O

Digital Input Capacitance

SCK

(Note 9)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 10)

O

– 0.5

V

CC

Low Level Output Voltage

SCK

I = 1.6mA (Note 10)

O

0.4

10

V

I

High-Z Output Leakage

SDO

–10

µA

OZ

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POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

2.7

5.5

V

CC

I

CC

Conversion Mode

Sleep Mode

CS = 0V (Note 12)

●

200

20

300

30

µA

CS = V (Note 12)

CC

3

LTC2401/LTC2402

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TI I G CHARACTERISTICS ^The● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.5

TYP

MAX

307.2

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

0.5

390

µs

LEO

F

= 0V

O

●

130.66

156.80

133.33

160

EOSC

136

163.20

(in kHz)

ms

CONV

F = V

O

CC

External Oscillator (Note 11)

20480/f

f

Internal SCK Frequency

Internal Oscillator (Note 10)

External Oscillator (Notes 10, 11)

19.2

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 10)

(Note 9)

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

●

2000

ESCK

250

1.64

LESCK

External SCK High Period

ns

HESCK

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

External Oscillator (Notes 10, 11)

●

1.67

1.70

ms

256/f

(in kHz)

EOSC

t

External SCK 32-Bit Data Output Time

CS ↓ to SDO Low Z

CS ↑ to SDO High Z

CS ↓ to SCK ↓

(Note 9)

●

32/f

(in kHz)

ms

ns

DOUT_ESCK

1

ESCK

0

150

t2

t3

t4

(Note 10)

(Note 9)

0

CS ↓ to SCK ↑

50

t

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

200

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

50

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 9: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output. In this mode of operation, the

SCK pin has a total equivalent load capacitance C_LOAD= 20pF.

Note 11: The external oscillator is connected to the F_Opin. The external

oscillator frequency, f_EOSC, is expressed in kHz.

Note 3: V_CC= 2.7 to 5.5V unless otherwise specified. Input source

resistance = 0Ω.

Note 4: Internal Conversion Clock source with the F_Opin tied

to GND or to V_CCor to external conversion clock source with

f

_EOSC= 153600Hz unless otherwise specified.

Note 12: The converter uses the internal oscillator.

Note 5: Guaranteed by design, not subject to test.

F_O= 0V or F_O= V_CC

.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer

curve. The deviation is measured from the center of the quantization

band.

Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 14: For reference voltage values V_REF> 2.5V, the extended input

of –0.125 • V_REFto 1.125 • V_REFis limited by the absolute maximum

Note 7: F_O= 0V (internal oscillator) or f_EOSC= 153600Hz ±2%

(external oscillator).

Note 8: F_O= V_CC(internal oscillator) or f_EOSC= 128000Hz ±2%

(external oscillator).

rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V_REF

≤

0.267V + 0.89 • V_CC, the input voltage range is –0.3V to 1.125 • V_REF

For 0.267V + 0.89 • V_CC< V_REF≤ V_CC, the input voltage range is –0.3V

to V_CC+ 0.3V.

.

4

LTC2401/LTC2402

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PIN FUNCTIONS

SDO (Pin 8): Three-State Digital Output. During the data

output period, this pin is used for serial data output. When

the chip select CS is HIGH (CS = V_CC), the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods, this pin can be used as a conversion status out-

put. The conversion status can be observed by pulling CS

LOW.

V_CC(Pin 1): Positive Supply Voltage. Bypass to GND

(Pin 4) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

FS_SET(Pin 2): Full-Scale Set Input. This pin defines the

full-scale input value. When V_IN= FS_SET, the ADC outputs

full scale (FFFFF_H). The total reference voltage is

FS_SET– ZS_SET

.

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal

Serial Clock Operation mode, SCK is used as digital output

fortheinternalserialinterfaceclockduringthedataoutput

period. In the External Serial Clock Operation mode, SCK

is used as digital input for the external serial interface. An

internal pull-up current source is automatically activated

in Internal Serial Clock Operation mode. The Serial Clock

mode is determined by the level applied to SCK at power

up and the falling edge of CS.

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input

voltage range is –0.125 • V_REFto 1.125 • V_REF. For

V_REF> 2.5V, the input voltage range may be limited by the

absolute maximum rating of –0.3V to V_CC+ 0.3V. Conver-

sions are performed alternately between CH0

and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on

the LTC2401.

ZS_SET(Pin 5): Zero-Scale Set Input. This pin defines the

zero-scale input value. When V_IN= ZS_SET, the ADC

outputs zero scale (00000_H).

F_O(Pin 10): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to V_CC(F_O= V_CC), the

converter uses its internal oscillator and the digital filter’s

first null is located at 50Hz. When the F_Opin is connected

to GND (F_O= 0V), the converter uses its internal oscillator

and the digital filter’s first null is located at 60Hz. When F_O

GND (Pin 6): Ground. Shared pin for analog ground,

digitalground,referencegroundandsignalground.Should

be connected directly to a ground plane through a mini-

mum length trace or it should be the single-point-ground

in a single-point grounding system.

isdrivenbyanexternalclocksignalwithafrequencyf_EOSC

,

CS (Pin 7): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW on CS wakes up the ADC. A

LOW-to-HIGH transition on this pin disables the SDO

digitaloutput.ALOW-to-HIGHtransitiononCSduringthe

Data Output transfer aborts the data transfer and starts a

new conversion.

the converter uses this signal as its clock and the digital

filter first null is located at a frequency f_EOSC/2560.

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LTC2401/LTC2402

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APPLICATIO S I FOR ATIO

Table 1. LTC2401/LTC2402 Status Bits

Output Data Format

Bit 31

EOC

Bit 30

CH0/CH1

Bit 29

SIG

Bit 28

EXR

TheLTC2401/LTC2402serialoutputdatastreamis32bits

long. The first 4 bits represent status information indicat-

ingthesign, selectedchannel, inputrangeandconversion

state. Thenext24bitsaretheconversionresult, MSBfirst.

The remaining 4 bits are sub LSBs beyond the 24-bit level

that may be included in averaging or discarded without

loss of resolution.

Input Range

> V

V

0

0/1

1

0

1

IN

REF

0 < V ≤ V

IN

REF

+

–

V

= 0 /0

1/0

0

IN

< 0

Bit 27 (fifth output bit) is the most significant bit (MSB).

Bits 27-4 are the 24-bit conversion result MSB first.

Bit 4 is the least significant bit (LSB).

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may

be included in averaging or discarded without loss of

resolution.

Bit 30 (second output bit) is LOW if the last conversion

was performed on CH0 and HIGH for CH1.

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 1. Whenever CS is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bit is LOW. The sign bit changes state during the zero

code.

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 31 (EOC) can be captured on the first rising

edge of SCK. Bit 30 is shifted out of the device on the first

Bit 28 (forth output bit) is the extended input range (EXR)

indicator. If the input is within the normal input range

0 ≤ V_IN≤ V_REF, this bit is LOW. If the input is outside the

normal input range, V_IN> V_REFor V_IN< 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

EXT

BIT 27

MSB

BIT 4

BIT 0

SDO

SCK

LSB

24

CH0/CH1

Hi-Z

1

2

3

4

5

27

28

32

SLEEP

DATA OUTPUT

CONVERSION

24012 F01

Figure 1. Output Data Timing

6

LTC2401/LTC2402

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APPLICATIO S I FOR ATIO

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falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 31st SCK and may be latched on

the rising edge of the 32nd SCK pulse. On the falling edge

of the 32nd SCK pulse, SDO goes HIGH indicating a new

conversion cycle has been initiated. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

throughthesensor.Thewiresconnectingthesensortothe

ADC form parasitic resistors R_P1and R_P2. The excitation

currentalsoflowsthroughparasiticresistorsR_P1andR_P2,

as shown in Figure 2. The voltage drop across these

parasitic resistors leads to systematic offset and full-scale

errors.

In order to eliminate the errors associated with these

parasitic resistors, the LTC2401/LTC2402 include a full-

scale set input (FS_SET) and a zero-scale set input

(ZS_SET). As shown in Figure 3, the FS_SETpin acts as a zero

input full-scale sense input. Errors due to parasitic resis-

tance R_P1in series with the half-bridge sensor are

As long as the voltage on the V_INpin is maintained within

the –0.3V to (V_CC+ 0.3V) absolute maximum operating

range, a conversion result is generated for any input value

from –0.125 • V_REFto 1.125 • V_REF. For input voltages

greaterthan1.125•V_REF,theconversionresultisclamped

to the value corresponding to 1.125 • V_REF. For input

voltages below –0.125 • V_REF, the conversion result is

+

–

R

P1

V

FULL-SCALE ERROR

clamped to the value corresponding to –0.125 • V_REF

.

+

–

I

SENSOR

SENSOR OUTPUT

EXCITATION

Single Ended Half-Bridge Digitizer

with Reference and Ground Sensing

+

R

V

P2

OFFSET ERROR

–

Sensors convert real world phenomena (temperature,

pressure, gas levels, etc.) into a voltage. Typically, this

voltage is generated by passing an excitation current

24012 F02

Figure 2. Errors Due to Excitation Currents

Table 2. LTC2401/LTC2402 Output Data Format

Bit 31

EOC

Bit 30

CH SELECT

Bit 29

SIG

Bit 28

EXR

Bit 27

MSB

Bit 26

Bit 25

Bit 24

Bit 23

…

Bit 4

Bit 3-0

Input Voltage

> 9/8 • V

LSB SUB LSBs*

V

0

CH0/CH1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

...

1

0

1

0

1

0

1

0

1

0

1

0

X

IN

REF

9/8 • V

1

REF

V

+ 1LSB

1

REF

1

3/4V + 1LSB

1

REF

3/4V

1

REF

1/2V + 1LSB

1

REF

1/2V

1

REF

1/4V + 1LSB

1

REF

1/4V

1

REF

+

–

0 /0

1/0**

–1LSB

0

–1/8 • V

REF

V

< –1/8 • V

REF

IN

*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.

**The sign bit changes state during the 0 code.

7

LTC2401/LTC2402

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APPLICATIO S I FOR ATIO

removed by the FS_SETinput to the ADC. The absolute full-

scale output of the ADC (data out = FFFFFF_HEX) will occur

atV_IN=V_B=FS_SET,seeFigure4.Similarly,theoffseterrors

The LTC2402 is ideal for applications requiring continu-

ous monitoring of two input sensors. As shown in

Figure 5, the LTC2402 can monitor both a thermocouple

temperature probe and a cold junction temperature sen-

sor. Absolute temperature measurements can be

performed with a variety of thermocouples using digital

cold junction compensation.

due to R_P2are removed by the ground sense input ZS_SET

TheabsolutezerooutputoftheADC(dataout=000000_HEX

.

)

occurs at V_IN= V_A= ZS_SET. Parasitic resistors R_P3to R_P5

have negligible errors due to the 1nA (typ) leakage current

at pins FS_SET, ZS_SETand V_IN. The wide dynamic input

range (–300mV to 5.3V) and low noise (0.6ppm RMS)

enable the LTC2401 or the LTC2402 to directly digitize the

output of the bridge sensor.

The selection between CH0 and CH1 is automatic. Initially,

after power-up, a conversion is performed on CH0. For

each subsequent conversion, the input channel selection

12.5%

EXTENDED

RANGE

FFFFF

H

1

V

CC

R

I

= 0

P1

DC

LTC2401

SET

2

3

V

FS

V

B

R

DC

P3

= 0

9

8

7

SCK

3-WIRE

SPI INTERFACE

I

EXCITATION

SDO

CS

IN

R

DC

P4

= 0

5

6

00000

V

H

12.5%

A

ZS

SET

R

P5

EXTENDED

RANGE

R

10

P2

GND

F

O

ZS

FS

SET

24012 F03

V

IN

24012 F04

Figure 3. Half-Bridge Digitizer with

Zero-Scale and Full-Scale Sense

Figure 4. Transfer Curve with Zero-Scale and Full-Scale Set

2.7V TO 5.5V

1

LTC2402

10

V

F

O

CC

2

9

8

7

6

12k

FS

SCK

SDO

CS

SET

PROCESSOR

COLD JUNCTION

3

4

5

CH1

CH0

ZS

THERMISTOR

24012 F05

100Ω

GND

SET

+

–

ISOLATION

BARRIER

THERMOCOUPLE

Figure 5. Isolated Temperature Measurement

8

LTC2401/LTC2402

W U U

APPLICATIO S I FOR ATIO

U

is alternated. Embedded within the serial data output is a

status bit indicating which channel corresponds to the

conversion result. If the conversion was performed on

CH0, this bit (Bit 30) is LOW and is HIGH if the conversion

was performed on CH1 (see Figure 6).

typically look at a small differential signal sitting on a

large common mode voltage; they need accurate

measurements of the differential signal independent of

the common mode input voltage. Many applications

currently using fully differential analog-to-digital con-

verters for any of the above reasons may migrate to a

pseudo differential conversion using the LTC2402.

There are no extra control or status pins required to

perform the alternating 2-channel measurements. The

LTC2402 only requires two digital signals (SCK and SDO).

This simplification is ideal for isolated temperature mea-

surements or systems where minimal control signals are

available.

Direct Connection to a Full Bridge

TheLTC2402interfacesdirectlytoa4-or6-wirebridge,as

shown in Figure 7. Like the LTC2401, the LTC2402 in-

cludes a FS_SETand a ZS_SETfor sensing the excitation

voltage directly across the bridge. This eliminates errors

due to excitation currents flowing through parasitic resis-

tors. The LTC2402 also includes two single ended input

channels which can tie directly to the differential output of

the bridge. The two conversion results may be digitally

subtracted yielding the differential result.

Pseudo Differential Applications

Generally, designers choose fully differential topologies

for several reasons. First, the interface to a 4- or 6-wire

bridge is simple (it is a differential output). Second, they

requiregoodrejectionoflinefrequencynoise. Third, they

SCK

SDO

• • •

CH1 DATA OUT

CH0 DATA OUT

24012 F06

EOC

CH1

CH0

Figure 6. Embedded Selected Channel Indicator

I

EXCITATION

5V

1

= 0

DC

V

CC

2

FS

SET

LTC2402

9

SCK

SDO

CS

350Ω

3

4

8

3-WIRE

SPI INTERFACE

CH1

CH0

7

350Ω

10

I

= 0

DC

F

O

5

ZS

SET

GND

24012 F07

Figure 7. Pseudo Differential Strain Guage Application

9

LTC2401/LTC2402

W U U

U

APPLICATIO S I FOR ATIO

The LTC2402’s single ended rejection of line frequencies

(±2%) and harmonics is better than 110dB. Since the

device performs two independent single ended conver-

sions each with >110dB rejection, the overall common

mode and differential rejection is much better than the

80dB rejection typically found in other differential input

delta-sigma converters.

the noise level of the device (3µV_RMS) divided by square

rootof2, independentofthecommonmodeinputvoltage.

Typically, a bridge sensor outputs 2mV/V full scale. With

a 5V excitation, this translates to a full-scale output of

10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414),

this circuit yields 2,300 counts with no averaging or

amplification. Ifmorecountsarerequired, severalconver-

sions may be averaged (the number of effective counts is

increased by a factor of square root of 2 for each doubling

of averages).

In addition to excellent rejection of line frequency noise,

the LTC2402 also exhibits excellent single ended noise

rejection over a wide range of frequencies due to its 4^th

order sinc filter. Each single ended conversion indepen-

dentlyrejectshighfrequencynoise(>60Hz). Caremustbe

taken to insure noise at frequencies below 15Hz and at

multiples of the ADC sample rate (15,600Hz) are not

present. For this application, it is recommended the

LTC2402 is placed in close proximity to the bridge sensor

in order to reduce the noise injected into the ADC input. By

performingthreesuccessiveconversions(CH0-CH1-CH0),

the drift and low frequency noise can be measured and

compensated for digitally.

An RTD Temperature Digitizer

RTDs used in remote temperature measurements often

have long lead lengths between the ADC and RTD sensor.

These long lead lengths lead to voltage drops due to

excitation current in the interconnect to the RTD. This

voltagedropcanbemeasuredanddigitallyremovedusing

the LTC2402 (see Figure 8).

The excitation current (typically 200µA) flows from the

ADC through a long lead length to the remote temperature

sensor (RTD). This current is applied to the RTD, whose

resistance changes as a function of temperature (100Ω to

400Ωfor0°Cto800°C).Thesameexcitationcurrentflows

back to the ADC ground and generates another voltage

drop across the return leads. In order to get an accurate

measurement of the temperature, these voltage drops

must be measured and removed from the conversion

result.Assumingtheresistanceisapproximatelythesame

Theabsoluteaccuracy(lessthan10ppmtotalerror)ofthe

LTC2402 enables extremely accurate measurement of

small signals sitting on large voltages. Each of the two

pseudo differential measurements performed by the

LTC2402 is absolutely accurate independent of the com-

mon mode voltage output from the bridge. The pseudo

differential result obtained from digitally subtracting the

two single ended conversion results is accurate to within

5V

1

V

CC

2

FS

SET

LTC2402

9

8

7

I

= 200µA

SCK

SDO

CS

EXCITATION

4

3

5

3-WIRE

SPI INTERFACE

CH0

CH1

+

–

R1

EXCITATION

P

t

V

RTD

100Ω

10

I

= 0

F

DC

O

ZS

SET

R2

GND

24012 F08

Figure 8. RTD Remote Temperature Measurement

10

LTC2401/LTC2402

W U U

APPLICATIO S I FOR ATIO

U

for the forward and return paths (R1 = R2), the auxiliary

channel on the LTC2402 can measure this drop. These

errors are then removed with simple digital correction.

During power-up, the LTC2402 becomes active at V_CC

2.3V, while the isolated side of the LTC1535 must wait for

_CC2to reach its undervoltage lockout threshold of 4.2V.

=

V

Below 4.2V, the LTC1535’s driver outputs Y and Z are in a

high impedance state, allowing the 1kΩ pull-down to

define the logic state at SCK. When the LTC2402 first

becomes active, it samples SCK; a logic “0” provided by

the 1kΩ pull-down invokes the external serial clock mode.

In this mode, the LTC2402 is controlled by a single clock

line from the nonisolated side of the barrier, through the

LTC1535’sdriveroutputY.Theentirepower-upsequence,

from the time power is applied to V_CC1until the LT1761’s

output has reached 5V, is approximately 1ms.

The result of the first conversion on CH0 corresponds to

aninputvoltageofV_RTD+R1•I_EXCITATION.Theresultofthe

second conversion (CH1) is –R1 • I_EXCITATION.Note, the

LTC2402’s input range is not limited to the supply rails, it

has underrange capabilities. The device’s input range is

–300mV to V_REF+ 300mV. Adding the two conversion

results together, the voltage drop across the RTD’s leads

are cancelled and the final result is V_RTD

.

An Isolated, 24-Bit Data Acquisition System

DatareturnstothenonisolatedsidethroughtheLTC1535’s

receiver at RO. An internal divider on receiver input B sets

a logic threshold of approximately 3.4V at input A, facili-

tating communications with the LTC2402’s SDO output

without the need for any external components.

The LTC1535 is useful for signal isolation. Figure 9 shows

a fully isolated, 24-bit differential input A/D converter

implemented with the LTC1535 and LTC2402. Power on

the isolated side is regulated by an LT1761-5.0 low noise,

low dropout micropower regulator. Its output is suitable

for driving bridge circuits and for ratiometric applications.

1/2 BAT54C

LT1761-5

IN

OUT

+

10µF

16V

SHDN BYP

GND

+

10µF

10V

TANT

T1

1µF

2

10µF

CERAMIC

+

10µF

1/2 BAT54C

10V

TANT

2

LTC2402

ST1 ST2

V

CC2

“SDO”

RO

RE

DE

DI

A

B

Y

Z

F

O

V

CC

LTC1535

G1 G2

SCK FS

SET

“SCK”

V

SDO

CS

CH1

CH0

CC1

1k

LOGIC 5V

GND ZS

SET

+

10µF

10V

TANT

= LOGIC COMMON

1

2

1

2

24012 F09

= FLOATING COMMON

ISOLATION

BARRIER

1

2

T1 = COILTRONICS CTX02-14659

OR SIEMENS B78304-A1477-A3

Figure 9. Complete, Isolated 24-Bit Data Acquisition System

11

LTC2401/LTC2402

U W

U

PACKAGE I FOR ATIO

Dimensions in inches (millimeters) unless otherwise noted.

MS10 Package

10-Lead Plastic MSOP

(LTC DWG # 05-08-1661)

0.118 ± 0.004*

(3.00 ± 0.102)

10 9

8

7 6

0.118 ± 0.004**

(3.00 ± 0.102)

0.193 ± 0.006

(4.90 ± 0.15)

1

2

3

4 5

0.040 ± 0.006

(1.02 ± 0.15)

0.034 ± 0.004

(0.86 ± 0.102)

0.007

(0.18)

0° – 6° TYP

SEATING

PLANE

0.009

(0.228)

REF

0.021 ± 0.006

(0.53 ± 0.015)

0.006 ± 0.004

(0.15 ± 0.102)

0.0197

(0.50)

BSC

MSOP (MS10) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

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24012i LT/TP 0100 4K • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 2000

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC2401
厂家：	Linear
描述：	1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10 1 / 2通道24位微功耗，采用MSOP - 10无延迟ADC
文件：	总12页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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