LTC2408C [Linear]
4-/8-Channel 24-Bit uPower No Latency ADCs; 4- / 8通道的24位微功耗无延迟的ADC
| 型号： | LTC2408C |
| 厂家： | 
Linear |
| 描述： | 4-/8-Channel 24-Bit uPower No Latency ADCs |
| 文件： | 总36页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2404/LTC2408
4-/8-Channel 24-Bit µPower
No Latency ∆ΣTM ADCs
U
FEATURES
DESCRIPTIO
The LTC®2404/LTC2408 are 4-/8-channel 2.7V to 5.5V
micropower 24-bit A/D converters with an integrated
oscillator, 4ppm INL and 0.3ppm RMS noise. They use
delta-sigma technology and provide single cycle digital
filter settling time (no latency delay) for multiplexed
applications. The first conversion after the channel is
changedisalwaysvalid.ThroughasinglepintheLTC2404/
LTC2408 can be configured for better than 110dB rejec-
tion at 50Hz or 60Hz ±2%, or can be driven by an external
oscillator for a user defined rejection frequency in the
range 1Hz to 120Hz. The internal oscillator requires no
external frequency setting components.
■
Pin Compatible 4-/8-Channel 24-Bit ADCs
■
Single Conversion Digital Filter Settling Time
Simplifies Multiplexing
4ppm INL, No Missing Codes
4ppm Full-Scale Error
0.5ppm Offset
0.3ppm Noise
■
■
■
■
■
Internal Oscillator—No External Components
Required
■
110dB Min, 50Hz/60Hz Notch Filter
■
Reference Input Voltage: 0.1V to VCC
■
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
Single Supply 2.7V to 5.5V Operation
The converters accept any external reference voltage from
0.1VtoVCC. Withtheirextendedinputconversionrangeof
–12.5% VREF to 112.5% VREF the LTC2404/LTC2408
smoothly resolve the offset and overrange problems of
preceding sensors or signal conditioning circuits.
■
■
Low Supply Current (200µA) and Auto Shutdown
U
APPLICATIO S
■
Weight Scales
The LTC2404/LTC2408 communicate through a flexible
4-wire digital interface which is compatible with SPI and
MICROWIRETM protocols.
■
Direct Temperature Measurement
■
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
6-Digit DVMs
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
■
MICROWIRE is a trademark of National Semiconductor Corporation.
■
■
■
U
TYPICAL APPLICATIO
Total Unadjusted Error vs Output Code
0.1V TO V
2.7V TO 5.5V
CC
10
7
4
3
V
2, 8
8
6
1µF
V
MUXOUT
ADCIN
REF
CC
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
9
CH0
4
23
20
19
25
21
24
10 CH1
11 CH2
12 CH3
13 CH4*
14 CH5*
15 CH6*
17 CH7*
CSADC
CSMUX
SCK
2
ANALOG
INPUTS
0
24-BIT
4-/8-CHANNEL
MUX
+
∆∑ ADC
MPU
CLK
–2
–4
–6
–8
–10
–0.12V
TO
REF
1.12V
D
REF
IN
–
SDO
V
CC
LTC2404/LTC2408
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
26
6
COM
F
O
GND
0
8,338,608
OUTPUT CODE (DECIMAL)
16,777,215
2404/08 TA01
1, 5, 16, 18, 22, 27, 28
*THESE PINS ARE NO CONNECTS ON THE LTC2404
2404/08 TA02
1
LTC2404/LTC2408
W W
U W
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Operating Temperature Range
Supply Voltage (VCC) to GND.......................–0.3V to 7V
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
LTC2404C/LTC2408C .............................. 0°C to 70°C
LTC2404I/LTC2408I ........................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W U
PACKAGE/ORDER INFORMATION
ORDER
ORDER
TOP VIEW
TOP VIEW
PART NUMBER
PART NUMBER
1
2
GND
GND
1
2
GND
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
GND
V
V
CC
CC
LTC2404CG
LTC2404IG
LTC2408CG
LTC2408IG
3
F
3
F
V
V
REF
O
O
REF
4
SCK
4
SCK
ADCIN
GND
ADCIN
GND
5
SDO
5
SDO
6
CSADC
GND
6
CSADC
GND
COM
COM
7
7
MUXOUT
MUXOUT
8
D
8
D
IN
V
V
IN
CC
CC
9
CSMUX
CLK
9
CSMUX
CLK
CH0
CH1
CH2
CH3
NC
CH0
CH1
CH2
CH3
CH4
CH5
10
11
12
13
14
10
11
12
13
14
GND
NC
GND
CH7
GND
NC
GND
CH6
NC
G PACKAGE
28-LEAD PLASTIC SSOP
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
TJMAX = 125°C, θJA = 130°C/W
Consult factory for Military grade parts.
U
CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
2.5V ≤ V ≤ V , (Note 5)
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
●
24
Bits
REF
CC
V
V
= 2.5V (Note 6)
= 5V (Note 6)
●
●
2
4
10
15
ppm of V
ppm of V
REF
REF
REF
REF
Offset Error
2.5V ≤ V ≤ V
●
0.5
0.01
4
2
ppm of V
REF
CC
CC
CC
CC
REF
Offset Error Drift
Full-Scale Error
2.5V ≤ V ≤ V
ppm of V /°C
REF
REF
2.5V ≤ V ≤ V
●
10
ppm of V
REF
REF
Full-Scale Error Drift
Total Unadjusted Error
2.5V ≤ V ≤ V
0.02
ppm of V /°C
REF
REF
V
V
= 2.5V
= 5V
5
10
ppm of V
ppm of V
REF
REF
REF
REF
Output Noise
V
= 0V (Note 13)
1.5
µV
RMS
IN
Normal Mode Rejection 60Hz ±2%
(Note 7)
●
110
130
dB
2
LTC2404/LTC2408
CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
U
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
130
100
110
110
MAX
UNITS
dB
Normal Mode Rejection 50Hz ±2%
Power Supply Rejection DC
Power Supply Rejection 60Hz ±2%
Power Supply Rejection 50Hz ±2%
(Note 8)
●
110
V
V
V
= 2.5V, V = 0V
dB
REF
REF
REF
IN
= 2.5V, V = 0V, (Note 7)
dB
IN
= 2.5V, V = 0V, (Note 8)
dB
IN
U
U
U
U
A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
–0.125 • V
0.1
TYP
MAX
UNITS
V
V
V
C
C
Input Voltage Range
(Note 14)
●
●
1.125 • V
REF
IN
REF
Reference Voltage Range
Input Sampling Capacitance
Reference Sampling Capacitance
Input Leakage Current
Reference Leakage Current
On Channel Leakage Current
MUX On-Resistance
V
CC
V
REF
10
15
1
pF
S(IN)
pF
S(REF)
IN(LEAK)
REF(LEAK)
IN(MUX)
I
I
I
CS = V
●
●
●
–10
–12
10
nA
nA
nA
CC
V
= 2.5V, CS = V
1
12
REF
CC
V = 2.5V (Note 15)
S
±20
R
I
I
= 1mA, V = 2.7V
= 1mA, V = 5V
●
●
250
120
300
250
Ω
Ω
ON
OUT
OUT
CC
CC
MUX ∆R vs Temperature
0.5
20
%/°C
%
ON
∆R vs V (Note 15)
ON
S
I
I
t
t
t
MUX Off Input Leakage
MUX Off Output Leakage
MUX Break-Before-Make Interval
Enable Turn-On Time
Channel Off, V = 2.5V
●
●
±20
±20
nA
nA
ns
S(OFF)
D(OFF)
OPEN
ON
S
Channel Off, V = 2.5V
D
125
290
490
190
70
V = 1.5V, R = 3.4k, C = 15pF
ns
S
L
L
Enable Turn-Off Time
V = 1.5V, R = 3.4k, C = 15pF
ns
OFF
S
L
L
QIRR
QINJ
MUX Off Isolation
V
= 2V , R = 1k, f = 100kHz
dB
pC
pF
IN
P-P
L
Charge Injection
R = 0Ω, C = 1000pF, V = 1V
±1
S
L
S
C
C
Input Off Capacitance (MUX)
Output Off Capacitance (MUX)
10
S(OFF)
D(OFF)
10
pF
3
LTC2404/LTC2408
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
V
V
V
High Level Input Voltage
●
●
●
●
●
●
2.5
2.0
V
V
IH
IL
IH
IL
CC
CS, F
2.7V ≤ V ≤ 3.3V
O
CC
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V
O
CC
High Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 9)
2.5
2.0
V
V
CC
2.7V ≤ V ≤ 3.3V (Note 9)
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 9)
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V (Note 9)
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
10
µA
µA
pF
pF
V
IN
IN
CS, F
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 9)
10
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 9)
IN
High Level Output Voltage
SDO
I = –800µA
O
●
●
●
●
●
V
V
– 0.5V
– 0.5V
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO
I = 1.6mA
O
0.4V
V
High Level Output Voltage
SCK
I = –800µA (Note 10)
O
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 10)
O
0.4V
10
V
I
High-Z Output Leakage
SDO
–10
2
µA
OZ
+
V
V
H
MUX High Level Input Voltage
MUX Low Level Input Voltage
V = 3V
●
●
V
V
IN MUX
+
L
V = 2.4V
0.8
IN MUX
W U
POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
I
CC
Conversion Mode
Sleep Mode
CS = 0V (Note 12)
●
●
200
20
300
30
µA
µA
CS = V (Note 12)
CC
Multiplexer Supply Current
All Logic Inputs Tied Together
●
15
40
µA
CC(MUX)
V
IN
= 0V or 5V
4
LTC2404/LTC2408
W U
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.56
0.5
TYP
MAX
307.2
390
UNITS
kHz
µs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
●
●
●
EOSC
HEO
0.5
390
µs
LEO
F = 0V
●
●
●
130.66
156.80
133.33
160
EOSC
136
163.20
(in kHz)
ms
ms
ms
CONV
O
F = V
O
CC
External Oscillator (Note 11)
20480/f
f
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
19.2
kHz
kHz
ISCK
f
/8
EOSC
D
Internal SCK Duty Cycle
(Note 10)
(Note 9)
(Note 9)
(Note 9)
45
55
%
kHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
●
●
●
2000
ESCK
250
250
1.64
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.67
1.70
ms
ms
256/f
(in kHz)
EOSC
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
(Note 9)
●
●
●
●
●
●
●
●
●
32/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
0
0
150
150
150
1
2
(Note 10)
(Note 9)
0
3
CS ↓ to SCK ↑
50
4
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
200
KQMAX
KQMIN
(Note 5)
15
50
t
t
5
6
50
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input
is 0Ω.
Note 12: The converter uses the internal oscillator.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
FO = 0V or FO = VCC
.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 5: Guaranteed by design, not subject to test.
Note 14: For reference voltage values VREF > 2.5V the extended input
of –0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF
0.267V + 0.89 • VCC the input voltage range is –0.3V to 1.125 • VREF
≤
.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is –0.3V
to VCC + 0.3V.
Note 15: VS is the voltage applied to a channel input. VD is the voltage
applied to the MUX output.
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
5
LTC2404/LTC2408
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error
(3V Supply)
Negative Extended Input Range
Total Unadjusted Error (3V Supply)
INL (3V Supply)
10
5
10
5
10
5
V
V
= 3V
= 3V
V
V
= 3V
= 3V
V
V
= 3V
= 3V
CC
REF
CC
REF
CC
REF
T
= 90°C
A
T
= –55°C, –45°C, 25°C, 90°C
A
T
A
= 25°C
0
0
0
T
T
= –45°C
= –55°C
A
A
T
= –55°C, –45°C, 25°C, 90°C
A
–5
–5
–5
–10
–10
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
–0.05 –0.10 –0.15 –0.20 –0.25 –0.30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
24048 G01
24048 G02
24048 G03
Total Unadjusted Error
(5V Supply)
Positive Extended Input Range
Total Unadjusted Error (3V Supply)
INL (5V Supply)
10
8
10
5
10
5
V
V
= 5V
= 5V
CC
REF
V
V
= 3V
REF
CC
= 3V
6
4
T
A
= –55°C
2
T
A
= –45°C
0
0
0
T
= –55°C, –45°C, 25°C, 90°C
A
–2
–4
–6
–8
–10
T
= 90°C
T = 25°C
A
A
–5
–5
–10
–10
3.0
3.1
3.2
3.3
0
1
2
3
4
5
0
1
2
3
4
5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
24048 G04
24048 G05
24048 G06
Positive Extended Input Range
Total Unadjusted Error (5V Supply)
Negative Extended Input Range
Total Unadjusted Error (5V Supply)
Offset Error vs Reference Voltage
20
15
10
5
10
5
10
5
V
V
= 5V
= 5V
V
T
= 5V
V
V
= 5V
= 5V
CC
REF
CC
A
CC
REF
= 25°C
T
= 90°C
A
T
= –55°C
= –45°C
A
T
A
= 25°C
0
0
T
A
T
= –45°C
= –55°C
A
T
A
= 90°C
T = 25°C
A
–5
–5
T
A
–10
–10
0
0
–0.05 –0.10 –0.15 –0.20 –0.25 –0.30
INPUT VOLTAGE (V)
5.0
5.1
5.2
5.3
0
1
2
3
4
5
INPUT VOLTAGE (V)
REFERENCE VOLTAGE (V)
24048 G07
24048 G08
24048 G10
6
LTC2404/LTC2408
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Reference Voltage
Offset Error vs VCC
RMS Noise vs VCC
5.0
2.5
20
15
10
5
5.0
V
T
= 2.5V
V
T
= 2.5V
REF
A
V
T
= 5V
REF
A
CC
A
= 25°C
= 25°C
= 25°C
0
2.5
–2.5
0
2.7
–5.0
0
0
1
2
3
4
5
2.7
3.2
3.7
4.2
4.7
5.2
3.2
3.7
4.2
4.7
5.2
V
CC
V
CC
REFERENCE VOLTAGE (V)
24048 G10
24048 G11
24048 G12
RMS Noise vs CODE OUT
Noise Histogram
Offset Error vs Temperature
1500
1000
500
0
5.0
2.5
1.00
0.75
0.50
0.25
0
V
V
V
= 5V
= 5V
V
V
V
= 5V
= 5V
V
V
V
T
= 5V
= 5V
CC
REF
IN
CC
REF
IN
CC
REF
IN
A
= 0V
= 0V
= –0.3V TO 5.3V
= 25°C
0
–2.5
–5.0
–1.0
–0.5
0
0.5
1.0
1.5
–50 –25
0
25 50 75 100 125
0
7FFFFF
FFFFFF
TEMPERATURE (°C)
OUTPUT CODE (ppm)
CODE OUT (HEX)
24048 G13
24048 G15
24048 G14
Full-Scale Error
vs Reference Voltage
Full-Scale Error vs Temperature
Full-Scale Error vs VCC
5.0
2.5
6
5
4
3
2
1
0
10.0
7.5
5.0
2.5
0
V
V
V
= 5V
REF
= 5V
V
V
= 5V
REF
CC
CC
IN
= 5V
= V
IN
0
–2.5
V
V
A
= 2.5V
REF
IN
= 2.5V
T
= 25°C
–5.0
–50 –25
0
25 50 75 100 125
2.7
3.2
3.7
4.2
4.7
5.2
0
1
2
3
4
5
TEMPERATURE (°C)
V
CC
REFERENCE VOLTAGE (V)
24048 G16
24048 G18
24048 G17
7
LTC2404/LTC2408
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Sleep Current vs Temperature
Conversion Current vs Temperature
PSRR vs Frequency at VCC
0
230
30
25
20
15
V
V
= 4.1V
= 0V
CC
IN
220
210
V
= 5.5V
= 4.1V
= 2.7V
CC
CC
–20
T
= 25°C
A
O
F
= 0
V
= 5.5V
CC
–40
–60
V
200
190
180
170
160
V
= 2.7V
CC
V
CC
–80
–100
–120
10
5
15,360Hz
10k
153,600Hz
1M
150
0
1
100
–25
0
50
75 100 125
50
100 125
–50
25
–50 –25
0
25
75
FREQUENCY AT V (Hz)
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
24048 G21
24048 G19
24048 G20
Rejection vs Frequency at VIN
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
–10
–30
0
0
–20
V
V
T
= 4.1V
= 0V
V
V
V
F
= 5V
V
V
T
= 4.1V
= 0V
CC
IN
CC
CC
IN
= 5V
REF
–20
= 25°C
= 2.5V
= 25°C
A
0
IN
A
O
F
= 0
= 0
F
= 0
O
–50
–70
–40
–60
–40
–60
–90
–110
–130
–80
–100
–120
–80
–100
–120
0
50
100
150
200
250
1
50
100
150
200
250
15200
15300 15350 15400 15450 15500
15250
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
CC
IN
24048 G22
24048 G24
24048 G23
Rejection vs Frequency at VIN
Rejection vs Frequency at VIN
Rejection vs Frequency at VIN
0
–60
–70
0
–20
–40
V
V
V
= 5V
CC
= 5V
REF
–20
= 2.5V
IN
F
= 0
O
–80
–40
–60
–90
–60
–80
–100
–110
–120
–130
–140
–80
–100
–120
–100
–120
–140
SAMPLE RATE = 15.36kHz ±2%
15100
15200
15300
15400
15500
–12
–8
–4
0
4
8
12
f /2
S
f
0
S
FREQUENCY AT V (Hz)
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
IN
INPUT FREQUENCY
24048 G26
24048 G25
24048 F23
8
LTC2404/LTC2408
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Resolution vs Maximum
Output Rate
INL vs Maximum Output Rate
24
22
20
18
16
14
12
10
8
24
V
V
0
= 5V
REF
= EXTERNAL
F = EXTERNAL
O
CC
= 5V
(20480 × MAXIMUM
22
20
18
16
14
12
10
8
F
OUTPUT RATE)
(20480 × MAXIMUM
OUTPUT RATE)
T
T
= 25°C
= 90°C
A
A
V
CC
= V
REF
= 5V
T
A
= 25°C
V
= V
= 3V
CC
REF
T
= 90°C
A
LOG(V /RMS NOISE)
REF
*RESOLUTION =
LOG (2)
0
5
10 15 20 25 30 35 40 45 50 55 60
MAXIMUM OUTPUT RATE (Hz)
24048 G27
0
5
10 15 20 25 30 35 40 45 50 55 60
MAXIMUM OUTPUT RATE (Hz)
24048 G28
U
U
U
PIN FUNCTIONS
GND (Pins 1, 5, 16, 18, 22, 27, 28): Ground. Should be
connected directly to a ground plane through a minimum
length trace or it should be the single-point-ground in a
single point grounding system.
CH4(Pin13):AnalogMultiplexerInput. Noconnectonthe
LTC2404.
CH5(Pin14):AnalogMultiplexerInput. Noconnectonthe
LTC2404.
VCC (Pins 2, 8): Positive Supply Voltage. 2.7V ≤ VCC
≤
CH6(Pin15):AnalogMultiplexerInput. Noconnectonthe
LTC2404.
5.5V. Bypass to GND with a 10µF tantalum capacitor in
parallel with 0.1µF ceramic capacitor as close to the part
as possible.
CH7(Pin17):AnalogMultiplexerInput. Noconnectonthe
LTC2404.
VREF (Pin3):ReferenceInput.Thereferencevoltagerange
is 0.1V to VCC.
CLK (Pin 19): Shift Clock for Data In. This clock synchro-
nizes the serial data transfer into the MUX. For normal
operation, drive this pin in parallel with SCK.
ADCIN (Pin 4): Analog Input. The input voltage range is
–0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input
voltage range may be limited by the pin absolute maxi-
mum rating of –0.3V to VCC + 0.3V.
CSMUX (Pin 20): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
COM(Pin6):SignalGround.Shouldbeconnecteddirectly
to a ground plane through minimum length trace.
MUXOUT(Pin7):MUXOutput.Thispinistheoutputofthe
multiplexer. Tie to ADCIN for normal operation.
DIN (Pin 21): Digital Data Input. The multiplexer address
is shifted into this input on the last four rising CLK edges
before CSMUX goes low.
CH0 (Pin 9): Analog Multiplexer Input.
CH1 (Pin 10): Analog Multiplexer Input.
CH2 (Pin 11): Analog Multiplexer Input.
CH3 (Pin 12): Analog Multiplexer Input.
CSADC (Pin 23): ADC Chip Select Input. A low on this pin
enables the SDO digital output and following each conver-
sion, the ADC automatically enters the Sleep mode and
remains in this low power state as long as CSADC is high.
9
LTC2404/LTC2408
U
U
U
PIN FUNCTIONS
A high on this pin also disables the SDO digital output. A
low-to-high transition on CSADC during the Data Output
state aborts the data transfer and starts a new conversion.
Fornormaloperation,drivethispininparallelwithCSMUX.
isshiftedoutofSDOonthefallingedgeofSCK. Fornormal
operation, drive this pin in parallel with CLK.
FO (Pin 26): Digital input which controls the ADC’s notch
frequencies and conversion time. When the FO pin is
connectedtoVCC (FO =VCC), theconverterusesitsinternal
oscillator and the digital filter first null is located at 50Hz.
When the FO pin is connected to GND (FO = OV), the
converter uses its internal oscillator and the digital filter
first null is located at 60Hz. When FO is driven by an
external clock signal with a frequency fEOSC, the converter
uses this signal as its clock and the digital filter first null is
located at a frequency fEOSC/2560. The resulting output
word rate is fEOSC/20480.
SDO (Pin 24): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CSADC is high (CSADC = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin can be used as a conversion status
output. The conversion status can be observed by pulling
CSADC low.
SCK(Pin25):ShiftClockforDataOut. Thisclocksynchro-
nizes the serial data transfer of the ADC data output. Data
U
U
W
FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
F
O
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
(INT/EXT)
∫
∫
∫
SDO
SERIAL
INTERFACE
∑
ADC
SCK
COM
CSADC
V
REF
DECIMATING FIR
CSMUX
CHANNEL
SELECT
DAC
D
IN
CLK
24048 BD
TEST CIRCUITS
V
CC
3.4k
SDO
SDO
3.4k
C
= 20pF
LOAD
C
= 20pF
LOAD
HI-Z TO V
OH
OH
V
OL
V
OH
TO V
HI-Z TO V
TO HI-Z
24048 TC01
OL
V
V
TO V
OL
OH
OL
TO HI-Z
24048 TC02
10
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
Converter Operation Cycle
CONVERT
TheLTC2404/LTC2408arelowpower,4-/8-channeldelta-
sigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selectionmaybeperformedwhilethedeviceisinthesleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input
(DIN). By tying SCK to CLK and CSADC to CSMUX, the
interface requires only four wires.
CHANNEL SELECT
(SLEEP)
SLEEP
CSADC
AND
SCK
1
0
DATA OUTPUT
(CHANNEL SELECT)
24048 F01
Initially, the LTC2404 or LTC2408 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Figure 1. LTC2408 State Transition Diagram
edge of SCK, see Figure 3. The data output state is
concluded once 32 bits are read out of the ADC or when
CSADCisbroughtHIGH.Thedeviceautomaticallyinitiates
a new conversion and the cycle repeats.
Channel selection for the next conversion cycle is per-
formed while the device is in the sleep state or at the end
of the data output state. A specific channel is selected by
applyinga4-bitserialwordtotheDIN pinontherisingedge
ofCLKwhileCSMUXisHIGH,seeFigure3andTable3.The
channel is selected based on the last four bits clocked into
the DIN pin before CSMUX goes low. If DIN is all 0’s, the
previous channel remains selected.
Through timing control of the CSADC and SCK pins, the
LTC2404/LTC2408 offer two modes of operation: internal
or external SCK. These modes do not require program-
ming configuration registers; moreover, they do not dis-
turbthecyclicoperationdescribedabove. Thesemodesof
operation are described in detail in the Serial Interface
Timing Modes section.
In the example, Figure 3, the MUX channel is selected
during the sleep state, just before the data output state
begins. Once the channel selection is complete, the device
remains in the sleep state as long as CSADC remains
HIGH.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50 or 60Hz plus
their harmonics. In order to reject these frequencies in
excess of 110dB, a highly accurate conversion clock is
required. The LTC2404/LTC2408 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
externalfrequencysettingcomponentssuchascrystalsor
oscillators.Clockedbytheon-chiposcillator,theLTC2404/
LTC2408 reject line frequencies (50 or 60Hz ±2%) a
minimum of 110dB.
Once CSADC is pulled low, the device begins outputting
theconversionresult.Thereisnolatencyintheconversion
result. Since there is no latency, the first conversion
following a change in input channel is valid and corre-
sponds to that channel. The data output corresponds to
theconversionjustperformed. Thisresultisshiftedouton
the serial data output pin (SDO) under the control of the
serial clock (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
11
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
V
CC
+ 0.3V
Ease of Use
9/8V
The LTC2404/LTC2408 data output has no latency, filter
settlingorredundantdataassociatedwiththeconversion
cycle.Thereisaone-to-onecorrespondencebetweenthe
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
REF
V
REF
ABSOLUTE
MAXIMUM
INPUT
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
1/2V
REF
RANGE
The LTC2404/LTC2408 perform offset and full-scale cali-
brations every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
0
–1/8V
REF
–0.3V
24048 F02
Figure 2. LTC2404/LTC2408 Input Range
The LTC2404/LTC2408 converts input signals within the
extended input range of –0.125 • VREF to 1.125 • VREF
.
Power-Up Sequence
For large values of VREF this range is limited to a voltage
rangeof–0.3Vto(VCC +0.3V).Beyondthisrangetheinput
ESDprotectiondevicesbegintoturnonandtheerrorsdue
to the input leakage current increase rapidly.
The LTC2404/LTC2408 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. When the VCC voltage rises
above this critical threshold, the converter creates an
internal power-on-reset (POR) signal with duration of
approximately 0.5ms. The POR signal clears all internal
registers within the ADC and initiates a conversion. At
power-up,themultiplexerchannelisdisabledandshould
be programmed once the device enters the sleep state.
TheresultsofthefirstconversionfollowingaPORarenot
valid since a multiplexer channel was disabled.
Input signals applied to VIN may extend below ground by
–300mVandaboveVCCby300mV.Inordertolimitanyfault
current, a resistor of up to 5k may be added in series with
any channel input pin (CH0 to CH7) without affecting the
performance of the device. In the physical layout, it is im-
portanttomaintaintheparasiticcapacitanceoftheconnec-
tion between this series resistance and the channel input
pin as low as possible; therefore, the resistor should be
located as close as practical to the channel input pin. The
effectoftheseriesresistanceontheconverteraccuracycan
be evaluated from the curves presented in the Analog In-
put/Reference Current section. In addition, a series resis-
torwillintroduceatemperaturedependentoffseterrordue
to the input leakage current. A 1nA input leakage current
Reference Voltage Range
The LTC2404/LTC2408 can accept a reference voltage
from 0V to VCC. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2404/LTC2408 voltage reference is
100mV to VCC.
will develop a 1ppm offset error on a 5k resistor if VREF
=
5V. This error has a very strong temperature dependency.
Output Data Format
TheLTC2404/LTC2408serialoutputdatastreamis32bits
long. The first 4 bits represent status information indicat-
ing the sign, input range and conversion state. The next 24
bits are the conversion result, MSB first. The remaining 4
bits are sub LSBs beyond the 24-bit level that may be in-
cludedinaveragingordiscardedwithoutlossofresolution.
Input Voltage Range
Theconverterisabletoaccommodatesystemleveloffset
and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
12
LTC2404/LTC2408
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APPLICATIONS INFORMATION
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CSADC pin is
LOW. This bit is HIGH during the conversion and goes
LOW when the conversion is complete.
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CSADC is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bitisLOW.Thesignbitchangesstateduringthezerocode.
In order to shift the conversion result out of the device,
CSADC must first be driven LOW. EOC is seen at the SDO
pinofthedeviceonceCSADCispulledLOW.EOCchanges
in real time from HIGH to LOW at the completion of a
conversion. This signal may be used as an interrupt for an
external microcontroller. Bit 31 (EOC) can be captured on
the first rising edge of SCK. Bit 30 is shifted out of the
device on the first falling edge of SCK. The final data bit
(Bit0)isshiftedoutonthefallingedgeofthe31stSCKand
may be latched on the rising edge of the 32nd SCK pulse.
Onthefallingedgeofthe32ndSCKpulse,SDOgoesHIGH
indicating a new conversion cycle has been initiated. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0 ≤ VIN ≤ VREF, this bit is LOW. If the input is outside the
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2404/LTC2408 Status Bits
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
EXR
Input Range
> V
V
0
0
0
0
0
0
0
0
1
1
1
0
0
1
IN
REF
0 < V ≤ V
IN
REF
+
–
V
V
= 0 /0
1/0
0
IN
IN
As long as the voltage on the VIN pin is maintained within
the –0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 • VREF to 1.125 • VREF. For input voltages
greaterthan1.125•VREF,theconversionresultisclamped
to the value corresponding to 1.125 • VREF. For input
voltages below –0.125 • VREF, the conversion result is
< 0
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
clamped to the value corresponding to –0.125 • VREF
.
t
CONV
CSMUX/CSADC
SDO
HI-Z
HI-Z
EOC
“0”
SIG
EXT
MSB
LSB
BIT 31 BIT 30
BIT 0
SCK/CLK
D
IN
EN
D2
D1
D0
DON’T CARE
24048 F03
Figure 3. Typical Data Input/Output Timing
13
LTC2404/LTC2408
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APPLICATIONS INFORMATION
Table 3. Logic Table for Channel Selection
Channel Selection
CHANNEL STATUS
EN
0
D2
X
0
D1
X
0
D0
X
0
Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
DIN pin on the rising edge of CLK, see Figure 3. Table 3
showsthebit combinations for channelselection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previousconversioniscomplete.Inordertoguaranteethe
conversioniscomplete,themultiplexeraddressingshould
be delayed a minimum tCONV (approximately 133ms for a
60Hz notch) after the data out is read.
All Off
CH0
1
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
CH4*
1
1
0
0
CH5*
1
1
0
1
CH6*
1
1
1
0
CH7*
1
1
1
1
*Not used for the LTC2404.
Frequency Rejection Selection (FO Pin Connection)
While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.
The LTC2404/LTC2408 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, FO (Pin 26) should be connected to GND
(Pin 1) while for 50Hz rejection the FO pin should be
connected to VCC (Pin 2).
Table 2. LTC2404/LTC2408 Output Data Format
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
EXR
Bit 27
MSB
Bit 26
Bit 25
Bit 24
Bit 23
…
Bit 4
LSB
Bit 3-0
SUB LSBs*
Input Voltage
> 9/8 • V
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
0
1
0
1
0
1
0
1
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IN
REF
9/8 • V
1
REF
V
V
+ 1LSB
1
REF
REF
1
3/4V
3/4V
1/2V
1/2V
1/4V
1/4V
+ 1LSB
+ 1LSB
+ 1LSB
1
REF
REF
REF
REF
REF
REF
1
1
1
1
1
+
–
0 /0
1/0**
–1LSB
0
0
0
–1/8 • V
REF
V
< –1/8 • V
REF
IN
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
14
LTC2404/LTC2408
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APPLICATIONS INFORMATION
–60
–70
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
–80
–90
–100
–110
–120
–130
–140
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2404/
LTC2408 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24048 F04
Figure 4. LTC2404/LTC2408 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
LTC2404/LTC2408 operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the
converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected. If the
change occurs during the data output state and the
converterisintheInternalSCKmode,theserialclockduty
cycle may be affected but the serial data stream will
remain valid.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2404/LTC2408 provide better
than 110dB normal mode rejection in a frequency range
fEOSC/2560 ±4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from fEOSC/2560 is shown in Figure 4.
Whenever an external clock is not present at the F pin the
O
converter automatically activates its internal oscillator
Table 4 summarizes the duration of each state as a
function of FO.
and enters the Internal Conversion Clock mode. The
Table 4. LTC2404/LTC2408 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW (60Hz Rejection)
133ms
160ms
20480/f
O
F = HIGH (50Hz Rejection)
O
External Oscillator
F = External Oscillator
O
(In Seconds)
EOSC
with Frequency f
kHz
EOSC
(f
EOSC
/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = 0 and SCK
DATA OUTPUT
Internal Serial Clock
External Serial Clock with
F = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
O
F = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/f
ms
EOSC
O
Frequency f
kHz
(32 SCK cycles)
EOSC
As Long As CS = LOW But Not Longer Than 32/f ms
SCK
Frequency f
kHz
(32 SCK cycles)
SCK
1
MAXIMUM OUTPUT
WORD RATE
OWR =
inHz
t
CONVERT + tDATAOUTPUT
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LTC2404/LTC2408
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APPLICATIONS INFORMATION
Using an External Clock for Faster Conversion Times
The DC specifications are guaranteed for fEOSC up to a
maximum of 307.2kHz, resulting in a maximum output
wordrateofapproximately15Hz.However,forfasterrates
at reduced performance, frequencies up to 1.22MHz can
be used on the FO pin. Figures 5 and 6 show the INL and
Resolution vs Output Rate.
The conversion time of the LTC2404/LTC2408 is deter-
mined by the conditions on the FO pin. If FO is connected
to GND for 60Hz rejection, the conversion time is 133µs.
IfFO isconnectedtoVCC, theconversiontimeis160µs. For
an externally supplied frequency of fEOSC(kHz), the con-
version time is:
SERIAL INTERFACE
tCONV = 20480/fEOSC (kHz)
The resulting frequency rejection is:
Notch Frequency = 8/tCONV
The LTC2404/LTC2408 transmit the conversion results,
program the channel selection, and receive the start of
conversion command through a synchronous 4-wire in-
terface(SCK=CLK,CSADC=CSMUX).Duringtheconver-
sion and sleep states, this interface can be used to assess
the converter status. While in the sleep state this interface
may be used to program an input channel. During the data
output state it is used to read the conversion result.
The maximum output word rate is:
1
OWR =
inHz
t
CONVERT + tDATAOUTPUT
24
22
20
18
16
14
12
10
8
V
V
0
= 5V
REF
= EXTERNAL
CC
ADC Serial Clock Input/Output (SCK)
= 5V
F
(20480 × MAXIMUM
OUTPUT RATE)
The serial clock signal present on SCK (Pin 25) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
T
= 25°C
A
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2404/LTC2408 creates its own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CSADC pin. If SCK is HIGH or
floatingatpower-uporduringthistransition,theconverter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
T
= 90°C
A
0
5
10 15 20 25 30 35 40 45 50 55 60
MAXIMUM OUTPUT RATE (Hz)
24048 G27
Figure 5. INL vs Maximum Output Rate
24
F
= EXTERNAL
O
(20480 × MAXIMUM
22
20
18
16
14
12
10
8
OUTPUT RATE)
T
T
= 25°C
= 90°C
A
A
Multiplexer Serial Input Clock (CLK)
V
CC
= V
= 5V
REF
Generally, this pin is externally tied to SCK for 4-wire op-
eration.OntherisingedgeofCLK(Pin19)withCSMUXheld
HIGH,dataisseriallyshiftedintothemultiplexer.IfCSMUX
is LOW the CLK input will be disabled and the channel
selection unchanged.
V
CC
= V
= 3V
REF
LOG(V /RMS NOISE)
REF
*RESOLUTION =
LOG (2)
0
5
10 15 20 25 30 35 40 45 50 55 60
MAXIMUM OUTPUT RATE (Hz)
24048 G28
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 24), drives the serial
data during the data output state. In addition, the SDO pin
Figure 6. Resolution vs Maximum Output Rate
16
LTC2404/LTC2408
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is used as an end of conversion indicator during the
shows the logic table for channel selection. In order to
select or change a previously programmed channel, an
enable bit (DIN = 1) must proceed the 3-bit channel select
serialdata. TheusermaysetDIN =0tocontinuallyconvert
on the previously selected channel.
conversion and sleep states.
When CSADC (Pin 23) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CSADC is LOW during the
convert or sleep state, SDO will output EOC. If CSADC is
LOW during the conversion phase, the EOC bit appears
HIGH on the SDO pin. Once the conversion is complete,
EOC goes LOW. The device remains in the sleep state until
the first rising edge of SCK occurs while CSADC = 0.
SERIAL INTERFACE TIMING MODES
The LTC2404/LTC2408’s 4-wire interface is SPI and
MICROWIRE compatible. This interface offers two modes
of operation. These include an internal or external serial
clock. The following sections describe both of these serial
interface timing modes in detail. For both cases the
converter can use the internal oscillator (FO = LOW or FO
= HIGH) or an external oscillator connected to the FO pin.
Refer to Table 5 for a summary.
ADC Chip Select Input (CSADC)
TheactiveLOWchipselect,CSADC(Pin23),isusedtotest
the conversion status and to enable the data output
transfer as described in the previous sections.
In addition, the CSADC signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2404/LTC2408 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CSADC pin after the converter has entered the data output
state (i.e., after the first rising edge of SCK occurs with
CSADC = 0).
External Serial Clock (SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock (SCK) to
shift out the conversion result, see Figure 7. This same
external clock signal drives the CLK pin in order to pro-
gram the multiplexer. A single CS signal drives both the
multiplexer CSMUX and converter CSADC inputs. This
common signal is used to monitor and control the state of
the conversion as well as enable the channel selection.
Multiplexer Chip Select (CSMUX)
The serial clock mode is selected on the falling edge of
CSADC. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CSADC falling
edge.
For 4-wire operation, this pin is tied directly to CSADC or
the output of an inverter tied to CSADC. CSMUX (Pin 20)
is driven HIGH during selection of a multiplexer channel.
On the falling edge of CSMUX, the selected channel is
enabled and drives MUXOUT.
The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. While CSADC is LOW, EOC is output to the SDO
pin. EOC = 1 while a conversion is in progress and EOC =
0 if the device is in the sleep state. Independent of CSADC,
the device automatically enters the low power sleep state
once the conversion is complete.
Data Input (DIN)
The data input to the multiplexer, DIN (Pin 21), is used to
program the multiplexer. The input channel is selected by
serially shifting a 4-bit input word into the DIN pin under
the control of the multiplexer clock, CLK. Data is shifted
into the multiplexer on the rising edge of CLK. Table 3
Table 5. LTC2404/LTC2408 Interface Timing Modes
Conversion
Cycle
Data
Connection
and
SCK
Output
Control
Configuration
External SCK
Internal SCK
Source
External
Internal
Control
Waveforms
CS and SCK
CS and SCK
Figures 7, 8, 9
Figures 10, 11
CS ↓
CS ↓
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LTC2404/LTC2408
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2.7V TO 5.5V
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2404/LTC2408
0.1V
CC
V
CSMUX
CSADC
SCK
CS
REF
TO V
–0.12V
CH0
TO CH7
REF
REF
TO 1.12V
SCK
MUXOUT
ADCIN
GND
CLK
D
IN
SDO
CSADC/
CSMUX
SCK/CLK
SDO
TEST EOC
TEST EOC
BIT31
BIT30 BIT29 BIT28 BIT27 BIT26
SIG EXR MSB
BIT4
LSB
BIT0
TEST EOC
HI-Z
SUB
LSB
HI-Z
HI-Z
D1
D
DON’T CARE
EN
D2
D0
DON’T CARE
IN
24048 F07
Figure 7. External Serial Clock Timing Diagram
While the device is in the sleep state, prior to entering the
data output state, the user may program the multiplexer.
As shown in Figure 7, the multiplexer channel is selected
by serial shifting a 4-bit word into the DIN pin on the rising
edge of CLK (CLK is tied to SCK). The first bit is an enable
bit that must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the falling edge of CSMUX, the new channel is
selectedandwillbevalidforthefirstconversionperformed
followingthedataoutputstate.Clocksignalsappliedtothe
CLK pin while CSMUX is LOW (during the data output
state) will have no effect on the channel selection. Further-
more, if DIN is held LOW or CLK is held LOW during the
sleep state, the channel selection is unchanged.
At the conclusion of the data cycle, CSADC may remain
LOW and EOC monitored as an end-of-conversion inter-
rupt. Alternatively, CSADC may be driven HIGH setting
SDO to HI-Z. As described above, CSADC may be pulled
LOWatanytimeinordertomonitortheconversionstatus.
For each of these operations, CSMUX may be tied to
CSADC without affecting the selected channel.
At the conclusion of the data output cycle, the converter
enters a user transparent calibration cycle prior to actually
performing a conversion on the selected input channel.
Thisenablesa66ms(for60Hznotchfrequency)lookahead
time for the multiplexer input. Following the data output
cycle, the multiplexer input channel may be selected any
time in this 66ms window by pulling CSADC HIGH and
serial shifting data into the DIN pin, see Figure 8.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen while CSADC is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latchedonthe32ndrisingedgeofSCK.Onthe32ndfalling
edge of SCK, the device begins a new conversion. SDO
goesHIGH(EOC=1)indicatingaconversionisinprogress.
While the device is performing the internal calibration, it is
sensitive to ground current disturbances. Error currents
flowing in the ground pin may lead to offset errors. If the
SCK pin is toggling during the calibration, these ground
disturbances will occur. The solution is to either drive the
multiplexer clock input (CLK) separately from the ADC
clock input (SCK), or program the multiplexer in the first
1ms following the data output cycle. The remaining 65ms
may be used to allow the input signal to settle.
18
LTC2404/LTC2408
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APPLICATIONS INFORMATION
CSADC/
CSMUX
SCK/CLK
TEST EOC
TEST EOC
BIT31 BIT30 BIT29 BIT28BIT27BIT26
SIG EXR MSB
BIT4
LSB
BIT0
SUB
LSB
SDO
HI-Z
D
IN
DON’T CARE
EN D2
D1
D0 DON’T CARE
CONVERTER
STATE
CONV
SLEEP
DATA OUTPUT
INTERNAL CALIBRATION
66ms LOOK AHEAD
CONVERSION ON SELECTED CHANNEL
66ms CONVERT
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
24048 F08
Figure 8. Use of Look Ahead to Program Multiplexer After Data Output
2.7V TO 5.5V
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2404/LTC2408
0.1V
CC
V
CSMUX
CSADC
SCK
CS
REF
TO V
–0.12V
CH0
TO CH7
REF
REF
TO 1.12V
SCK
MUXOUT
ADCIN
GND
CLK
D
IN
SDO
CSADC/
CSMUX
SCK/CLK
SDO
TEST EOC
TEST EOC
BIT31
BIT30 BIT29 BIT28 BIT27 BIT26
SIG EXR MSB
BIT9 BIT8
LSB
HI-Z
HI-Z
D1
D
IN
DON’T CARE
EN
D2
D0
DON’T CARE
24048 F09
Figure 9. External Serial Clock with Reduced Data Output Length Timing Diagram
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 32nd falling edge of SCK, see Figure 9. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 32 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.
Internal Serial Clock
This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 10. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
19
LTC2404/LTC2408
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2.7V TO 5.5V
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2404/LTC2408
0.1V
CC
V
CS
CSMUX
REF
TO V
10k
CH0
TO CH7
–0.12V
TO 1.12V
CSADC
SCK
REF
REF
MUXOUT
ADCIN
GND
CLK
D
IN
SDO
CSMUX
CSADC
SCKCLK
SDO
t
EOCtest
TEST EOC
TEST EOC
BIT31 BIT30 BIT29 BIT28 BIT27 BIT26
SIG EXR MSB
BIT4 BIT3 BIT2 BIT1 BIT0
TEST EOC
SUB SUB SUB SUB
LSB
LSB LSB LSB LSB
HI-Z
HI-Z
HI-Z
D
DON’T CARE
EN D2
D1
D0
DON’T CARE
IN
24048 F10
Figure 10. Internal Serial Clock Timing Diagram
state. Theinternalserialclock(SCK)generatedbytheADC
is applied to the multiplexer clock input (CLK).
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time tEOCtest after the
falling edge of CSADC (if EOC = 0) or tEOCtest after EOC
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of tEOCtest is 23µs if the device is using its
internal oscillator (F0 = logic LOW or HIGH). If FO is driven
by an external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC. IfCSADCispulledHIGHbeforetimetEOCtest, the
device remains in the sleep state. The conversion result is
held in the internal static shift register.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (HI-Z) or pulled
HIGHpriortothefallingedgeofCSADC.Thedevicewillnot
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
If CSADC remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edgeofSCK.Theinternallygeneratedserialclockisoutput
WhentestingEOC,iftheconversioniscomplete(EOC=0),
thedevicewillexitthesleepstateandenterthedataoutput
20
LTC2404/LTC2408
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to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latchedonthefirstrisingedgeofSCKandthelastbitofthe
conversionresultonthe32ndrisingedgeofSCK. Afterthe
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 32nd
rising edge of SCK, see Figure 11. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). DIN is latched into the multiplexer on the rising
edge of CLK. As shown in Figure 10, the multiplexer
channel is selected by serial shifting a 4-bit word into the
DIN pin on the rising edge of CLK. The first bit is an enable
bitwhichmustbeHIGHinordertoprogramachannel.The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If DIN is held LOW during the data
outputstate,thepreviouschannelselectionremainsvalid.
Whenever SCK is LOW, the LTC2404/LTC2408’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
2.7V TO 5.5V
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2404/LTC2408
0.1V
CC
V
CS
CSMUX
REF
TO V
10k
CH0
TO CH7
–0.12V
TO 1.12V
CSADC
SCK
REF
REF
MUXOUT
ADCIN
GND
CLK
D
IN
SDO
CSMUX
CSADC
SCKCLK
SDO
t
EOCtest
TEST EOC
TEST EOC
BIT31 BIT30 BIT29 BIT28 BIT27 BIT26
SIG EXR MSB
BIT12 BIT11 BIT10 BIT9 BIT8
TEST EOC
HI-Z
HI-Z
HI-Z
D
DON’T CARE
EN D2
D1
D0
DON’T CARE
IN
24048 F11
Figure 11. Internal Serial Clock with Reduced Data Output Length Timing Diagram
21
LTC2404/LTC2408
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mode.However,certainapplicationsmayrequireanexter-
nal driver on SCK. If this driver goes HI-Z after outputting
a LOW signal, the LTC2404/LTC2408’s internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CSADC, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes HI-Z. On the next CSADC falling edge, the
device will remain in the internal SCK timing mode.
develop a 2.5µV offset signal. For a reference voltage VREF
= 2.5V, this represents a 1ppm offset error.
Inanalternativeconfiguration,theCOMpinoftheconverter
canbethesingle-point-groundinasinglepointgrounding
system. The input signal ground, the reference signal
ground, the digital drivers ground (usually the digital
ground)andthepowersupplyground(theanalogground)
should be connected in a star configuration with the com-
mon point located as close to the COM pin as possible.
Asimilarsituationmayoccurduringthesleepstatewhen
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as tEOCtest), the
internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions
where CSADC remains LOW after detecting EOC = 0. This
situation is easily avoided by adding an external 10k pull-
up resistor to the SCK pin.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.
While a digital input signal is in the 0.5V to (VCC – 0.5V)
range, the CMOS input receiver draws additional current
from the power supply. It should be noted that, when any
one of the digital input signals (FO, CSADC, CSMUX, DIN,
CLK and SCK in External SCK mode of operation) is within
this range, the LTC2404/LTC2408 power supply current
mayincreaseevenifthesignalinquestionisatavalidlogic
level. For micropower operation and in order to minimize
the potential errors due to additional ground pin current,
it is recommended to drive all digital input signals to full
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
DIGITAL SIGNAL LEVELS
The LTC2404/LTC2408’s digital interface is easy to use.
Its digital inputs (FO, CSADC, CSMUX, CLK, DIN and SCK
in External SCK mode of operation) accept standard TTL/
CMOS logic levels and can tolerate edge rates as slow as
100µs.However,someconsiderationsarerequiredtotake
advantageofexceptionalaccuracyandlowsupplycurrent.
Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Under-
shoot and overshoot can occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to LTC2404/LTC2408.
For reference, on a regular FR-4 board, signal propaga-
tion velocity is approximately 183ps/inch for internal
traces and 170ps/inch for surface traces. Thus, a driver
generating a control signal with a minimum transition
time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
areusedandmultiplereflectionsmayoccur.Thesolution
is to carefully terminate all transmission lines close to
their characteristic impedance.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
InordertopreservetheaccuracyoftheLTC2404/LTC2408,
it is very important to minimize the ground path imped-
ance which may appear in series with the input and/or
reference signal and to reduce the current which may flow
through this path. The COM pin (Pin 6) should be con-
nected to a low resistance ground plane through a mini-
mum length trace. The use of multiple via holes is recom-
mended to further reduce the connection resistance. The
LTC2404/LTC2408’spowersupplycurrentflowingthrough
the 0.01Ω resistance of the common ground pin will
Parallel termination near the LTC2404/LTC2408 input
pins will eliminate this problem but will increase the driver
22
LTC2404/LTC2408
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APPLICATIONS INFORMATION
powerdissipation.Aseriesresistorbetween27Ωand56Ω
placed near the driver or near the LTC2404/LTC2408 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
performance of the device. It simply results in an offset/
full-scale shift, see Figure 13. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at VIN (CIN > 0.01µF) and small capaci-
tance at VIN (CIN < 0.01µF).
If the total capacitance at VIN (see Figure 14) is small
(<0.01µF), relativelylargeexternalsourceresistances(up
to 20k for 20pF parasitic capacitance) can be tolerated
withoutanyoffset/full-scaleerror.Figures15and16show
a family of offset and full-scale error curves for various
Driving the Input and Reference
The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched ca-
pacitornetwork.Thisnetworkconsistsofcapacitorsswitch-
ing between the analog input (ADCIN), COM (Pin 6) and
the reference (VREF). The result is small current spikes
seenatbothADCINandVREF. Asimplifiedinputequivalent
circuit is shown in Figure 12.
The key to understanding the effects of this dynamic input
current is based on a simple first order RC time constant
model. Using the internal oscillator, the internal switched
capacitor network of the LTC2404/LTC2408 is clocked at
153,600Hz corresponding to a 6.5µs sampling period.
Fourteentimeconstantsarerequiredeachtimeacapacitor
is switched in order to achieve 1ppm settling accuracy.
TUE
0
V
/2
V
REF
REF
V
24048 F13
IN
Therefore, the equivalent time constant at VIN and VREF
should be less than 6.5µs/14 = 460ns in order to achieve
1ppm accuracy.
Figure 13. Offset/Full-Scale Shift
R
SOURCE
CH0 TO
CH7
INTPUT
Input Current (VIN)
C
PAR
20pF
SIGNAL
C
IN
LTC2404/
LTC2408
SOURCE
If complete settling occurs on the input, conversion re-
sultswillbeuneffectedbythedynamicinputcurrent. Ifthe
settling is incomplete, it does not degrade the linearity
24048 F14
Figure 14. An RC Network at CH0 to CH7
ADCV
CC
(PIN 2)
R
SW
I
I
REF
REF
5k
V
REF
MUXV
ADCV
CC
(PIN 2)
CC
(PIN 8)
SELECTED
CHANNEL
±I
AVERAGE INPUT CURRENT:
DC
R
75Ω
R
SW
SW
5k
I
I
I
I
= 0.25(V – 0.5 • V ) • f • C
IN(MUX)
IN(MUX)
IN(LEAK)
IN(LEAK)
DC
IN REF EQ
CHX
MUXOUT
ADCIN
C
EQ
I
10pF (TYP)
R
SW
5k
24048 F12
COM
f
f
= 50Hz, INTERNAL OSCILLATOR: f = 128kHz
= 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz
OUT
OUT
EXTERNAL OSCILLATOR: 2.56kHz ≤ f ≤ 307.2kHz
Figure 12. LTC2404/LTC2408 Equivalent Analog Input Circuit
23
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
300
250
50
C
= 1µF
= 10µF
V
V
V
= 5V
= 5V
IN
= 25°C
IN
CC
REF
V
V
V
= 5V
= 5V
CC
REF
IN
C
IN
= 0V
= 0V
40
30
20
10
0
T
A
T
= 25°C
A
200
150
C
= 0.1µF
IN
C
= 0pF
= 100pF
IN
C
IN
C
IN
= 1000pF
100
50
0
C
= 0.01µF
C
IN
= 0.01µF
IN
0
100 200 300 400 500 600 700 800 900 1000
(Ω)
1
10
100
1k
10k
100k
R
SOURCE
R
(Ω)
SOURCE
24048 F17
24048 F15
Figure 15. Offset vs RSOURCE (Small C)
Figure 17. Offset vs RSOURCE (Large C)
0
0
V
V
V
T
= 5V
= 5V
V
V
V
T
= 5V
= 5V
CC
REF
IN
A
CC
REF
IN
C
= 0.01µF
IN
= 5V
= 5V
–50
–10
–20
–30
–40
–50
= 25°C
= 25°C
A
–100
–150
C
= 0.1µF
C
IN
= 1000pF
= 0pF
IN
IN
C
IN
= 100pF
C
C
IN
= 1µF
IN
C
= 10µF
C
= 0.01µF
IN
–200
–250
–300
1
10
100
R
1k
10k
100k
0
200
400
R
600
(Ω)
800
1000
(Ω)
SOURCE
SOURCE
24048 F16
24048 F18
Figure 16. Full-Scale Error vs RSOURCE (Small C)
Figure 18. Full-Scale Error vs RSOURCE (Large C)
small valued input capacitors (CIN < 0.01µF) as a function
capacitance applied to the MUXOUT/ADCIN results in
linearity errors. The 75Ω on-resistance of the multiplexer
switch is nonlinear with input voltage. If the capacitance at
node MUXOUT/ADCIN is less than 0.01µF, the linearity is
not degraded. On the other hand, excessive capacitance
(>0.01µF) results in incomplete settling as a function of
the multiplexer on-resistance. Hence, the nonlinearity of
the multiplexer switch is seen in the overall transfer
characteristic.
of input source resistance.
For large input capacitor values (CIN > 0.01µF), the input
spikesareaveragedbythecapacitorintoaDCcurrent. The
gain shift becomes a linear function of input source
resistance independent of input capacitance, see Figures
17 and 18. The equivalent input impedance is 1.66MΩ.
This results in ±1.5µA of input dynamic current at the
extreme values of VIN (VIN = 0V and VIN = VREF, when
VREF = 5V). This corresponds to a 0.3ppm shift in offset
and full-scale readings for every 1Ω of input source
resistance.
In addition to the input current spikes, the input ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±10nA
max), resultsinafixedoffsetshiftof10µVfora10ksource
resistance.
While large capacitance applied to one of the multiplexer
channel inputs may result in offset/full-scale shifts, large
24
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
Reference Current (VREF
)
constants tied to the reference input. If the capacitance at
node VREF is small (CVREF < 0.01µF), the reference input
can tolerate large external resistances without reduction
in INL, see Figure 21. If the external capacitance is large
(CVREF > 0.01µF), the linearity will be degraded by
0.15ppm/Ω independent of capacitance at VREF, see
Figure 22.
Similar to the analog input, the reference input has a
dynamic input current. This current has negligible effect
on the offset. However, the reference current at VIN = VREF
is similar to the input current at full-scale. For large values
of reference capacitance (CVREF > 0.01µF), the full-scale
error shift is 0.3ppm/Ω of external reference resistance
independent of the capacitance at VREF, see Figure 19. If
the capacitance tied to VREF is small (CVREF < 0.01µF), an
input resistance of up to 20k (20pF parasitic capacitance
at VREF) may be tolerated, see Figure 20.
In addition to the dynamic reference current, the VREF ESD
protection diodes have a temperature dependent leakage
current.Thisleakagecurrent,nominally1nA(±10nAmax),
results in a fixed full-scale shift of 10µV for a 10k source
resistance.
Unlike the analog input, the integral nonlinearity of the
device can be degraded with excessive external RC time
600
50
V
V
V
= 5V
V
V
= 5V
REF
T = 25°C
A
CC
CC
= 5V
= 5V
REF
500
40
= 5V
IN
T
= 25°C
A
C
VREF
VREF
= 0pF
VREF
C
= 100pF
400
300
30
20
C
= 1000pF
C
= 10µF
VREF
C
= 0.01µF
VREF
C
= 1µF
VREF
200
100
0
10
0
C
= 0.1µF
VREF
C
= 0.01µF
VREF
–10
0
200
400
600
800
1000
1
10
100
1k
10k
(Ω)
100k
RESISTANCE AT V
(Ω)
RESISTANCE AT V
REF
REF
24048 F19
24048 F21
Figure 19. Full-Scale Error vs RVREF (Large C)
Figure 21. INL Error vs RVREF (Small C)
160
140
120
100
80
50
V
V
V
= 5V
= 5V
V
V
= 5V
= 5V
CC
REF
IN
CC
REF
T = 25°C
A
40
= 5V
T
= 25°C
A
C
= 0.1µF
= 1µF
VREF
C
VREF
30
20
C
VREF
= 100pF
= 1000pF
VREF
C
C
= 10µF
VREF
C
= 0.01µF
VREF
60
10
C
VREF
= 0.01µF
40
0
C
VREF
= 0pF
20
–10
–20
0
–20
10
100
10k
100k
0
800
1000
1
1k
200
400
600
RESISTANCE AT V
(Ω)
RESISTANCE AT V (Ω)
REF
REF
24048 F22
24048 F20
Figure 20. Full-Scale Error vs RVREF (Small C)
Figure 22. INL Error vs RVREF (Large C)
25
LTC2404/LTC2408
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APPLICATIONS INFORMATION
ANTIALIASING
The LTC2408’s Resolution and Accuracy Allows You
to Measure Points in a Ladder of Sensors
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2404/LTC2408 signifi-
cantly simplify antialiasing filter requirements.
In many industrial processes, for example, cracking tow-
ers in petroleum refineries, a group of temperature mea-
surements must be related to one another. A series of
platinum RTDs that sense slow changing temperatures
canbeconfiguredintoaresistiveladder,usingtheLTC2408
to sense each node. This approach allows a single excita-
tion current passed through the entire ladder, reducing
total supply current consumption. In addition, this ap-
proach requires only one high precision resistor, thereby
reducingcost. Agroupofuptoseventemperaturescanbe
measured as a group by a single LTC2408 in a loop-pow-
ered remote acquisition unit. In the example shown in
Figure 24, the excitation current is 240µA at 0°C. The
LTC2408 requires 300µA, leaving nearly 3.5mA for the
remainder of the remote transmitter.
The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(fS), see Figure 23. The modulator sampling frequency is
256 • FO, where FO is the notch frequency (typically 50Hz
or 60Hz). The bandwidth of signals not rejected by the
digitalfilterisnarrow(≈0.2%)comparedtothebandwidth
of the frequencies rejected.
As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2404/LTC2408. If passive RC components are
placed in front of the LTC2404/LTC2408, the input dy-
namic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of input dynamic current.
The resistance of any of the RTDs (PT1 to PT7) is deter-
mined from the voltage across it, as compared to the
voltage drop across the reference resistor (R1). This is a
ratiometricimplementationwherethevoltagedropacross
R1 is given by VREF – VCH1. Channel 7 is used to measure
the voltage on a representative length of wire. If the same
type and length of wire is used for all connections, then
errors associated with the voltage drops across all wiring
can be removed in software. The contribution of wiring
drop can be scaled if wire lengths are not equal.
The modulator contained within the LTC2404/LTC2408
can handle large-signal level perturbations without satu-
rating. Signal levels up to 40% of VREF do not saturate the
analog modulator. These signals are limited by the input
ESDprotectionto300mVbelowgroundand300mVabove
VCC.
Gain can be added to this circuit as the total voltage drop
across all the RTDs is small compared to ADC full-scale
range. The maximum recommended gain is 40, as limited
by both amplifier noise contribution, as well as the maxi-
mum voltage developed at CH0 when all sensors are at the
maximum temperature specified for platinum RTDs.
0
–20
–40
–60
–80
Adding gain requires that one of the resistors (PT1 to PT7)
be a precision resistor in order to eliminate the error asso-
ciated with the gain setting resistors R2 and R3. Note, that
if a precision (100Ω to 400Ω) resistor is used in place of
one of the RTDs (PT7 recommended), R1 does not need
to be a high precision resistor. Although the substitution
of a precision reference resistor for an RTD to determine
gain may suggest that R2 and R3 (and R1) need not be
precise, temperature fluctuations due to airflow may ap-
pear as noise that cannot be removed in firmware. Conse-
–100
–120
–140
f /2
S
f
0
S
INPUT FREQUENCY
24048 F23
Figure 23. Sync4 Filter Rejection
26
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
5V
300µA
R2
6
+
0.1µF
47µF
OPTIONAL
GAIN
5V
LTC1634-2.5
3
2
BLOCK
7
+
4
5
6
LTC1050
R1
20.1k
0.1%
–
4
R3
R2
UP TO SEVERAL
HUNDRED FEET.
ALL SAME
5V
WIRE TYPE
OPTIONAL
PROTECTION
RESISTORS
5k MAX
7
4
3
V
2, 8
1µF
PT1
100Ω
V
MUXOUT
ADCIN
REF
CC
9
CH0
PLATINUM
RTD
23
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
CSADC
20
CSMUX
25
24-BIT
SCK
PT2
PT7
8-CHANNEL
MUX
19
+
∆∑ ADC
CLK
21
D
IN
24
SDO
TO PT3-PT6
V
CC
LTC2408
GND
26
6
COM
F
O
2404/08 F24
1, 5, 16, 18, 22, 27, 28
Figure 24. Measuring Up to Seven RTD Temperatures with One Reference Resistor and One Reference Current
quently, these resistors should be low temperature coef-
ficient devices. The use of higher resistance RTDs is not
recommended in this topology, although the inclusion of
one 1000Ω RTD at the top on the ladder will have minimal
impact on the lower elements. The same caveat applies to
fast changing temperatures. Any fast changing sensors
should be at the top of the ladder.
characteristicsorsignalinversion/noninversioncouldbe
selected. The R/2R ladder can be purchased as a network
to ensure tight temperature tracking. Alternatively, resis-
tors in a ladder or as separate dividers can be assembled
from discrete resistors. In the configuration shown, the
channel resistance of the multiplexer does not contribute
much to the error budget, as only input op amp current
flows through the switch. The LTC1050 was chosen for
its low input current and offset voltage, as well as its
ability to drive the input of a ∆Σ ADC.
The LTC2408’s Uncommitted Multiplexer Finds Use in
a Programmable Gain Scheme
If the multiplexer in the LTC2408 is not committed to
channel selection, it can be used to select various signal-
processing options such as different gains, filters or at-
tenuator characteristics. In Figure 25, the multiplexer is
shown selecting different taps on an R/2R ladder in the
feedback loop of an amplifier. This example allows selec-
tion of gain from 1 to 128 in binary steps. Other feedback
networks could be used to provide gains tailored for
specific purposes. (For example, 1x, 1.1x, 1.41x, 2x,
2.028x,5x,10x,40x,etc.)Alternatively,differentbandpass
Insert Gain or Buffering After the Multiplexer
SeparateMUXOUTandADCINterminalspermitinsertion
of a gain stage between the MUX and the ADC. If passive
filtering is used at the input to the ADC, a buffer amplifier
is strongly recommended to avoid errors resulting from
thedynamicADCinputcurrent. Ifantialiasingisrequired,
it should be placed at the input to the MUX. If bandwidth
limitingisrequiredtoimprovenoiseperformance, afilter
with a –3dB point at 1500Hz will reduce the effective total
27
LTC2404/LTC2408
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APPLICATIONS INFORMATION
5V
3
AV = 1, 2, 4...128
6
V
IN
+
LTC1050
2
–
5V
0.1V TO V
3
CC
7
4
2, 8
V
CC
1µF
10k
10k
10k
10k
10k
10k
10k
10k
2
V
REF
MUXOUT
ADCIN
9
CH0
20k
20k
20k
20k
20k
20k
20k
23
20
25
19
21
24
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
4
CSADC
CSMUX
SCK
8
24-BIT
∆∑ ADC
8-CHANNEL
MUX
+
CLK
16
32
64
128
D
IN
SDO
V
CC
LTC2408
GND
26
6
COM
F
O
2404/08 F25
1, 5, 16, 18, 22, 27, 28
Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128
5V
OPTIONAL
BANDWIDTH
3
2
7
LIMIT
+
6
LTC1050
MAY BE REQUIRED BY OTHER
AMPLIFIERS (IS REQUIRED BY
BIPOLAR AMPLIFIERS)
C1
0.022µF
–
R4
5K
4
R3
200k
R1
5.1k
R2
5.1K
C2
OPTIONAL GAIN
AND ROLL-OFF
5V
7
4
3
V
2, 8
V
CC
10µF
MUXOUT
ADCIN
REF
9
CH0
23
20
25
19
21
24
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
CSADC
CSMUX
SCK
24-BIT
8-CHANNEL
MUX
ANALOG
INPUTS
+
∆∑ ADC
CLK
D
IN
SDO
V
CC
LTC2408
GND
26
6
COM
F
O
2404/08 F26
1, 5, 16, 18, 22, 27, 28
Figure 26. Inserting Gain Between the Multiplexer and the ADC Input
28
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
noise bandwidth of the system to 6Hz. The noise band-
width of the LTC2408 without any input bandwidth lim-
iting is approximately 150Hz. A roll-off at 1500Hz
eliminates all higher order images of the base bandwidth
of 6Hz. In the example shown, the optional bandwidth-
limitingfilterhasa–3dBpointat1450Hz. Thisfiltercanbe
inserted after the multiplexer provided that higher source
impedance prior to the multiplexer does not reduce the
–3dB frequency, extending settling time, and resulting in
charge sharing between samples. The settling time of this
filter to 20+ bits of accuracy is less than 2ms. In the pres-
ence of external wideband noise, this filter reduces the
apparent noise by a factor of 5. Note that the noise band-
width for noise developed in the amplifier is 150Hz. In the
example shown, the gain of the amplifier is set to 40, the
pointatwhichamplifiernoisegaindominatestheLTC2408
noise. Input voltage range as shown is then 0V to 125mV
DC. The recommended capacitor at C2 for a gain of 40
would be 560pF.
T
hecodebeginsbydeclaringvariablesandallocatingfour
memory locations to store the 32-bit conversion result
andafifthlocationtostoretheMUXchanneladdress.This
isfollowedbyinitializingPORTD’sSPIconfiguration. The
program then enters the main sequence. It begins by
sending the MUX channel data. It then activates the
LTC2408’s serial interface by setting the SS output low,
sendingalogiclowtoCSADC/CSMUX. Thisalsoactivates
theselectedMUXchannel.Itnextwaitsinaloopforalogic
low on the data line, signifying end-of-conversion. After
the loop is satisfied, four SPI transfers are completed,
retrieving the conversion. The main sequence ends by
settingSShigh.ThisplacestheLTC2408’sserialinterface
in a high impedance state and initiates another conver-
sion. The program in Figure 30 modifies the MUX channel
selection routine in Figure 28’s listing for selection of 16
channels. Figure 29 shows the connections between the
LTC1391, LTC2408 and the 68HC11 controller.
Interfacing the LTC2404/LTC2408 to the 68HC11
Microcontroller
19
CLK
SCK
SD0
CSADC
CSMUX
68HC11
SCK (PD4)
MISO (PD2)
SS (PD5)
25
24
23
20
21
LTC2408
The listing in Figure 28 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring
it for SPI data transfer between the controller and the
LTC2408. The program shows how to select and enable a
MUXchannelandretrieveconversiondata.Figure27shows
the simple 4-wire SPI connection.
MOSI (PD3)
D
IN
24048 F27
Figure 27. Connecting the LTC2408 to a
68HC11 MCU Using the SPI Serial Interface
**********************************************************
*
*
*
* This example program loads multiplexer channels selection data into
* the LTC2408’s internal MUX and then transfers the LTC2408’s 32-bit *
* output conversion result to four consecutive 8-bit memory locations. *
*
*
**********************************************************
*
***************************************
* 68HC11 register definitions
*
***************************************
*
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
$1008
Port D data register
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
Port D data direction register
SPI control register
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPI data register; Read-Buffer; Write-Shifter
EQU
EQU
$1009
$1028
EQU
EQU
$1029
$102A
* RAM variables to hold the LTC2408’s 32 conversion result
*
29
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
DIN1
DIN2
DIN3
DIN4
MUX
*
EQU
EQU
EQU
EQU
EQU
$00
$01
$02
$03
$04
This memory location holds the LTC2408’s bits 31 - 24
This memory location holds the LTC2408’s bits 23 - 16
This memory location holds the LTC2408’s bits 15 - 08
This memory location holds the LTC2408’s bits 07 - 00
This memory location holds the MUX address data
***************************************
* Start GETDATA Routine
*
***************************************
*
ORG
LDS
$C000
$CFFF
#$2F
Program start location
Top of C page RAM, beginning location of stack
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
*
INIT1
*
LDAA
STAA
LDAA
STAA
PORTD
#$38
DDRD
*
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
STAA
#$50
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher
E-Clock frequencies, change the above value of $50 to a
value that ensures the SCK frequency is 2MHz or less.)
*
*
*
*
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory
locations that hold the conversion data
*
LDY
#$1000
*
*******************************
* The next routine sends data to the
* LTC2408 an sets its MUX channel
*
*
*******************************
*
LDAA
ORAA
STAA
$MUX
#$08
Retrieve MUX address
Set the MUX’s ENABLE bit
SPDR
Transfer Accum. A contents to SPI register to initiate
serial transfer
Get SPI transfer status
WAITMUX If the transfer is not finished, read status
*
WAITMUX LDAA
SPSR
BPL
*
***************************************
* Enable the LTC2408
*
***************************************
*
BCLR
PORTD,Y %00100000 This sets the SS* output bit to a logic
low, selecting the LTC2408
*
*
***************************************
* The next short loop waits for the
* LTC2408’s conversion to finish before
* starting the SPI data transfer
*
*
*
***************************************
*
CONVEND LDAA
PORTD
Retrieve the contents of port D
Look at bit 2
Bit 2 = Hi; the LTC2408’s conversion is not
complete
Bit 2 = Lo; the LTC2408’s conversion is complete
Branch to the loop’s beginning while bit 2 remains
high
ANDA
#%00000100
*
*
*
BNE
CONVEND
*
30
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
*
***************************************
* The SPI data transfer
*
***************************************
*
TRFLP1
LDAA
STAA
#$0
Load accumulator A with a null byte for SPI transfer
This writes the byte into the SPI data register and
starts the transfer
SPDR
*
WAIT1
*
LDAA
BPL
SPSR
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
WAIT1
The SPIF (SPI transfer complete flag) bit is the SPSR’s
*
*
MSB and is set to one at the end of an SPI transfer. The
branch will occur while SPIF is a zero.
Load accumulator A with the current byte of LTC2408 data
that was just received
Transfer the LTC2408’s data to memory
Increment the pointer
LDAA
SPDR
0,X
*
STAA
INX
CPX
BNE
#DIN4+1 Has the last byte been transferred/exchanged?
TRFLP1 If the last byte has not been reached, then proceed to
the next byte for transfer/exchage
*
*
BSET
PORTD,Y %00100000 This sets the SS* output bit to a logic
high, de-selecting the LTC2408
Restore the A register
PULA
PULY
PULX
RTS
Restore the Y register
Restore the X register
Figure 28. LTC2408-68HC11 MCU Digital Interface Routine
5V
7
4
3
V
2, 8
V
CC
10µF
ADCIN
MUXOUT
REF
9
TO
17
CH0 TO
CH7
23
20
25
19
21
24
CSADC
CSMUX
SCK
68HC11
SS (PD5)
24-BIT
+
∆∑ ADC
CLK
SCK (PD4)
MOSI (PD3)
MISO (PD2)
LTC1391
D
IN
1
2
3
4
5
6
7
8
15
CH8
CH9
S0
S1
S2
S3
S4
S5
S6
S7
D
SDO
V
CC
LTC2408
GND
CH10
CH11
CH12
CH13
CH14
CH15
26
6
COM
F
O
10
11
13
12
CLK
CS
1, 5, 16, 18, 22, 27, 28
D
OUT
2404/08 F29
D
IN
Figure 29. Combining the LTC2408 with the LTC1391 for 16 Input Channels
31
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
*****************************************************************************
*
*
*
*
*
*
* This example program loads multiplexer channels selection data into
* either the LTC2408’s internal MUX or an external LTC1391 MUX. It then
* transfers the LTC2408’s 32-bit output conversion result to four
* consecutive 8-bit memory locations.
*
*
*****************************************************************************
*
***************************************
* 68HC11 register definitions
*
***************************************
*
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
$1008
Port D data register
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
Port D data direction register
SPI control register
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPI data register; Read-Buffer; Write-Shifter
EQU
EQU
$1009
$1028
EQU
EQU
$1029
$102A
* RAM variables to hold the LTC2408’s 32 conversion result
*
DIN1
DIN2
DIN3
DIN4
MUX
*
EQU
EQU
EQU
EQU
EQU
$00
$01
$02
$03
$04
This memory location holds the LTC2408’s bits 31 - 24
This memory location holds the LTC2408’s bits 23 - 16
This memory location holds the LTC2408’s bits 15 - 08
This memory location holds the LTC2408’s bits 07 - 00
This memory location holds the MUX address data
***************************************
* Start GETDATA Routine
*
***************************************
*
ORG
$C000
#$2F
Program start location
INIT1
*
LDAA
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
STAA
LDAA
STAA
PORTD
#$38
DDRD
*
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
STAA
#$50
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher
E-Clock frequencies, change the above value of $50 to a
value that ensures the SCK frequency is 2MHz or less.)
*
*
*
*
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory
locations that hold the conversion data
*
LDY
#$1000
*
***************************************
* The next routine sends data to the
* LTC2408 an sets its MUX channel
*
*
***************************************
*
LDAA
TAB
SUBA
BLE
TBA
ORAA
BRA
MUX
Retrieve MUX address
Save contents of Accum. A
Is the MUX address in the low nibble
#$07
ENLWMX If it is, branch to enable the LTC2408’s internal MUX
Restore contents of Accum. A
#$80
Enable the LTC1391 external MUX
MUXSPI Go to SPI transfer2400
32
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
ENLWMX TBA
ORAA
Restore contents of Accum. A
Set the MUX’s ENABLE bit
Transfer Accum. A contents to SPI register to initiate
serial transfer
Get SPI transfer status
WAITMUX If the transfer is not finished, read status
#$08
MUXSPI STAA
*
SPDR
WAITMUX LDAA
SPSR
BPL
*
***************************************
* Enable the LTC2408
*
***************************************
*
BCLR
PORTD,Y %00100000 This sets the SS* output bit to a logic
low, selecting the LTC2408
*
*
***************************************
* The next short loop waits for the
* LTC2408’s conversion to finish before
* starting the SPI data transfer
*
*
*
***************************************
*
CONVEND LDAA
PORTD
Retrieve the contents of port D
ANDA
#%00000100
Look at bit 2
Bit 2 = Hi; the LTC2408’s conversion is not
complete
Bit 2 = Lo; the LTC2408’s conversion is complete
Branch to the loop’s beginning while bit 2 remains
high
*
*
*
BNE
CONVEND
*
*
***************************************
* The SPI data transfer
*
***************************************
*
TRFLP1
LDAA
STAA
#$0
Load accumulator A with a null byte for SPI transfer
This writes the byte into the SPI data register and
starts the transfer
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
MSB and is set to one at the end of an SPI transfer. The
branch will occur while SPIF is a zero.
Load accumulator A with the current byte of LTC2408 data
that was just received
Transfer the LTC2408’s data to memory
Increment the pointer
SPDR
*
WAIT1
*
LDAA
BPL
SPSR
*
*
LDAA
SPDR
0,X
*
STAA
INX
CPX
BNE
#DIN4+1 Has the last byte been transferred/exchanged?
TRFLP1 If the last byte has not been reached, then proceed to
the next byte for transfer/exchage
*
*
BSET
PORTD,Y %00100000 This sets the SS* output bit to a logic
high, de-selecting the LTC2408
Restore the A register
PULA
PULY
PULX
RTS
Restore the Y register
Restore the X register
Figure 30. LTC2408/LTC1391-684C11 MCU Digital Interface Routine
An 8-Channel DC-to-Daylight Digitizer
type, is located some distance from the ADC or operates
in a high ambient noise environment, the LTC2408’s low
power dissipation allows circuit operation in close prox-
imity to the sensor. As a result, conditioning the sensor
output can be greatly simplified through the use of single-
ended arrangements. In those applications where differ-
ential signal conditioning is required, chopper
ThecircuitinFigure31showsanexampleoftheLTC2408’s
flexibility in digitizing a number of real-world physical
phenomena—from DC voltages to ultraviolet light. All of
the examples implement single-ended signal condition-
ing. Althoughdifferentialsignalconditioningisapreferred
approach in applications where the sensor is a bridge-
33
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
amplifier-based or self-contained instrumentation ampli-
fiers (also available from LTC) can be used with the
LTC2408.
Two channels (CH3 and CH4) of the LTC2408 are used to
accommodate a 3-wire 100Ω, Pt RTD in a unique circuit
that allows true RMS/RF signal power measurement from
audio to gigahertz (GHz) frequencies. The unique feature
ofthiscircuitisthatthesignalpowerdissipatedinthe50Ω
termination in the form of heat is measured by the 100Ω
RTD. Two readings are required to compensate for the
RTD’s lead-wire resistance. The reading on CH4 is multi-
plied by 2 and subtracted from the reading on CH3 to
determine the exact value of the RTD.
With the resistor network connected to CH0, the LTC2408
isabletomeasureDCvoltagesfrom1mVto1kVinasingle
range without the need for autoranging. The 990k resistor
should be a 1W resistor rated for high voltage operation.
Alternatively, the 990k resistor can be replaced with a
seriesconnectionofseverallowercost,lowerpowermetal
film resistors.
While the LTC2408 is capable of measuring signals over a
range of six decades, the implementation (mechanical,
electrical and thermal) of this technique ultimately deter-
mines the performance of the circuit. The thermal resis-
tanceoftheassembly(the50Ω/RTDmasstoitsenclosure)
will determine the sensitivity of the circuit. The dynamic
range of the circuit will be determined by the maximum
temperature the assembly is rated to withstand, approxi-
mately 850°C. Details of the implementation are quite
involved and are beyond the scope of this document.
Please contact LTC directly for a more comprehensive
treatment of this implementation.
The circuit connected to CH1 shows an LT1793 FET input
operational amplifier used as an electrometer for high
impedance, low frequency applications such as measur-
ing pH. The circuit has been configured for a gain of 21;
thus, the input signal range is –15mV ≤ VIN ≤ 250mV. An
amplifier circuit is necessary in these applications be-
cause high output impedance sensors cannot drive
switched-capacitor ADCs directly. The LT1793 was cho-
sen for its low input bias current (10pA, max) and low
noise (8nV/√Hz) performance. As shown, the use of a
driven guard (and TeflonTM standoffs) is recommended in
high impedance sensor applications; otherwise, PC board
surface leakage current effects can degrade results.
In the circuit connected to the LTC2408’s CH5 input, a
thermistor is configured in a half-bridge arrangement that
could be used to measure the case temperature of the
RTD-basedthermalpowermeasurementschemedescribed
previously. In general, thermistors yield very good resolu-
tion over a limited temperature range. Measurement reso-
lution of 0.001°C is possible; however, thermistor
self-heating effects, thermistor initial tolerance and circuit
thermal construction can combine to limit achievable
resolution. For the half-bridge arrangement shown, the
LTC2408canmeasuretemperaturechangesover5orders
of magnitude.
The circuit connected to CH2 illustrates a precision half-
wave rectifier that uses the LTC2408’s internal ∆Σ ADC as
an integrator. This circuit can be used to measure 60Hz,
120Hz or from 400Hz to 1kHz with good results. The
LTC2408’s internal sinc4 filter effectively eliminates any
frequency in this range. Above 1kHz, limited amplifier
gain-bandwidthproductandtransientovershootbehavior
can combine to degrade performance. The circuit’s dy-
namicrangeislimitedbyoperationalamplifierinputoffset
voltage and the system’s overall noise floor. Using an
LTC1050 chopper-stabilized operational amplifier with a
VOS of 5µV, the dynamic range of this application covers
approximately 5 orders of magnitude. The circuit configu-
ration is best implemented with a precision, 3-terminal,
2-resistor 10k network (for example, an IRC PFC-D net-
work) for R6 and R7 to maintain gain and temperature
stability. Alternatively, discrete resistors with 0.1% initial
tolerance and 5ppm/°C temperature coefficient would
also be adequate for most applications.
Connected to the LTC2408’s CH6 input, an infrared ther-
mocouple (Omega Engineering OS36-1) can be used in
limited range, noncontact temperature measurement ap-
plications or applications where high levels of infrared
light must be measured. Given the LTC2408’s 0.3ppmRMS
noise performance, measurement resolution using infra-
red thermocouples is approximately 0.03°C—equivalent
to the resolution of a conventional Type J thermocouple.
Teflon is a trademark of Dupont Company.
34
LTC2404/LTC2408
U
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APPLICATIONS INFORMATION
These infrared thermocouples are self-contained: 1) they
do not require external cold junction compensation; 2)
they cannot use conventional open thermocouple detec-
tion schemes; and 3) their output impedances are high,
approximately 3kΩ. Alternatively, conventional thermo-
couples can be connected directly to the LTC2408 (not
shown) and cold junction compensation can be provided
byanexternaltemperaturesensorconnectedtoadifferent
channel(seethethermistorcircuitonCH5)orbyusingthe
LT1025, a monolithic cold-junction compensator IC.
The photodiode chosen (Hammatsu S1336-5BK) pro-
duces an output of 500mA per watt of optical illumina-
tion. The output of the photodiode is dependent on two
factors: active detector area (2.4mm • 2.4mm) and
illumination intensity. With the 5k resistor, optical inten-
sities up to 368W/m2 at 960nM (direct sunlight is ap-
proximately1000W/m2)canbemeasuredbytheLTC2408.
With a resolution of 300pA, the optical dynamic range
covers 6 orders of magnitude.
The application circuits shown connected to the LTC2408
demonstrate the mix-and-match capabilities of this multi-
plexed-input, high resolution ∆Σ ADC. Very low level
signals and high level signals can be accommodated with
a minimum of additional circuitry.
The components connected to CH7 are used to sense
daylightorphotodiodecurrentwitharesolutionof300pA.
In the figure, the photodiode is biased in photoconduc-
tive mode; however, the LTC2408 can accommodate
either photovoltaic or photoconductive configurations.
U
PACKAGE DESCRIPTIO
Dimensions in millimeters (inches) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
7.65 – 7.90
(0.301 – 0.311)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G28 SSOP 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
35
LTC2404/LTC2408
U
TYPICAL APPLICATION
DC
VOLTMETER
INPUT
R1
GUARD RING
900k
5V
0.1%, 1W, 1000 WVDC
7
ELECTROMETER
INPUT
1mV TO 1000V
3
2
R5
5k, 1%
+
R2
4.7k
6
(pH, PIEZO)
LT1793
0.1%
0V TO 5V
–
4
–60mV TO 4V
–5V
R3, 10k
LT1236CS8-5
R4
1k
6
2
5V
OUT IN
8V
REF
C1, 0.1µF
+
+
5V
MAX
GND
4
10µF
100µF
3-WIRE R-PACK
60Hz
R6
R7
5V
10k, 0.1%
10k, 0.1%
AC
INPUT
5V
7
4
3
V
2, 8
1µF
SERIAL DATA LINK
1µF
R9
1k
1%
R10
7
V
MUXOUT
ADCIN
REF
CC
5k
IN914
6
IN914
2
3
–
1%
9
CH0
RT
MICROWIRE AND
SPI COMPATABLE
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
LTC1050
23
20
CSADC
R8
100Ω, 5%
+
CSMUX
CLK
4
19, 25
21
24-BIT
8-CHANNEL
MUX
20mV TO 80mV
+
∆∑ ADC
MPU
–5V
D
IN
R11
24
SDO
–
24.9k, 0.1%
V
REF
5V
LTC2408
GND
INTERNAL OSC
60Hz–RF
26
6
COM
F
O
SELECTED FOR
RF POWER
60Hz REJECTION
<1mV
J1
J2
100Ω
24048 F31
1, 5, 16, 18, 22, 27, 28
Pt RTD
50Ω
(3-WIRE)
FORCE SENSE
2.7V AT 0°C
0.9V AT 40°C
–2.2mV to 16mV
0V to 4V
R12
24.9k, 0.1%
J3
V
REF
5V
50Ω LOAD
BONDED TO
RTD ON
INSULATED
MOUNTING
LOCAL
TEMP
THERMISTOR
10kΩ NTC
5V
DAYLIGHT
HAMAMATSU
PHOTODIODE
S1336-5BK
OMEGA
0S36-01
INFRARED
R13
5k
0.1%
INFRARED
THERMOCOUPLE
Fiugre 31. Measure DC to Daylight Using the LTC2408
RELATED PARTS
PART NUMBER
LTC1050
LT1236
DESCRIPTION
COMMENTS
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference
No External Components, 5µV Offset, 1.6µV
0.05% Max Initial Accuracy, 5ppm/°C Drift
P–P
LT1793
Low Noise JFET Input Op Amp
24-Bit Micropower ∆Σ ADC in SO-8
10pA Max Input Bias Current, Low Voltage Noise: 8nV
<4ppm INL, No Missing Codes, 4ppm Full Scale
LTC2400
24048f LT/TP 0100 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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