LTC2410C [Linear]
24-Bit No Latency ADC with Differential Input and Differential Reference; 24位差分输入和差分参考无延迟ADC
| 型号： | LTC2410C |
| 厂家： | 
Linear |
| 描述： | 24-Bit No Latency ADC with Differential Input and Differential Reference |
| 文件： | 总44页 (文件大小：781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC2410
24-Bit No Latency ∆ΣTM ADC
with Differential Input and
Differential Reference
U
April 2000
DESCRIPTIO
FEATURES
The LTC®2410 is a 2.7V to 5.5V micropower 24-bit
differential ∆Σ analog to digital converter with an inte-
grated oscillator, 2ppm INL and 0.16ppm RMS noise. It
uses delta-sigma technology and provides single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2410 can be configured for better than
110dB input differential mode rejection at 50Hz or 60Hz
±2%, oritcanbedrivenbyanexternaloscillatorforauser
defined rejection frequency. The internal oscillator re-
quires no external frequency setting components.
■
Differential Input and Differential Reference with
GND to VCC Common Mode Range
■
2ppm INL, No Missing Codes
■
2.5ppm Full-Scale Error
0.1ppm Offset
0.16ppm Noise
■
■
■
Single Conversion Settling Time for Multiplexed
Applications
■
Internal Oscillator—No External Components
Required
110dB Min, 50Hz/60Hz Notch Filter
■
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full-
■
24-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)
■
Single Supply 2.7V to 5.5V Operation
scale differential input range is from –0.5VREF to 0.5VREF
.
■
Low Supply Current (200µA) and Auto Shutdown
The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be indepen-
dently set anywhere within the GND to VCC range of the
LTC2410. The DC common mode input rejection is better
than 140dB.
■
Fully Differential UVersion of LTC2400
APPLICATIO S
■
Direct Sensor Digitizer
■
Weight Scales
The LTC2410 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
■
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
6-Digit DVMs
■
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
■
■
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TYPICAL APPLICATIO S
V
2.7V TO 5.5V
CC
1µF
V
CC
1µF
= INTERNAL OSC/50Hz REJECTION
2
14
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
V
CC
F
O
2
3
+
LTC2410
REF
V
12 SDO
13 SCK
11 CS
CC
3
4
+
–
BRIDGE
IMPEDANCE
100Ω TO10k
13
REFERENCE
VOLTAGE
REF
REF
5
+
SCK
IN
IN
3-WIRE
SPI INTERFACE
LTC2410
6
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
–
+
4
ANALOG INPUT RANGE
REF
IN
SDO
CS
GND
F
O
–0.5V
TO 0.5V
REF
REF
–
1, 7, 8
14
IN
1, 7, 8, 9, 10, 15, 16
9, 10,
GND
2410 TA01
15, 16
2410 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LTC2410
W W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
ORDER PART NUMBER
Supply Voltage (VCC) to GND.......................–0.3V to 7V
Analog Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2410C ............................................... 0°C to 70°C
LTC2410I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
GND
V
CC
LTC2410CGN
LTC2410IGN
+
F
O
REF
–
SCK
SDO
CS
REF
+
IN
GN PART MARKING
–
IN
GND
GND
GND
GND
2410
2410I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1V ≤ V ≤ V , –0.5 • V
≤ V ≤ 0.5 • V , (Note 5)
●
24
Bits
REF
CC
–
REF
IN
REF
+
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
●
●
1
2
ppm of V
INCM
REF
REF
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
14
ppm of V
CC
INCM
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
●
●
●
0.5
2.5
µV
CC
+
–
GND ≤ IN = IN ≤ V , (Note 14)
CC
+
–
Offset Error Drift
2.5V ≤ REF ≤ V , REF = GND,
10
nV/°C
ppm of V
CC
+
–
GND ≤ IN = IN ≤ V
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
Output Noise
2.5V ≤ REF ≤ V , REF = GND,
2.5
12
12
CC
REF
+
+
–
+
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
0.04
2.5
ppm of V /°C
REF
CC
+
+
–
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V
REF
CC
+
+
–
+
IN = 0.25 • REF , IN = 0.75 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
0.04
ppm of V /°C
REF
CC
+
+
–
+
IN = 0.25 • REF , IN = 0.75 • REF
+
–
REF = 2.5V, REF = GND, V
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 1.25V
5
10
ppm of V
ppm of V
INCM
REF
REF
+
–
= 2.5V
CC
INCM
+
5V ≤ V ≤ 5.5V, REF = 5V, V – = GND,
GND ≤ IN = IN ≤ 5V, (Note 13)
0.8
µV
RMS
CC
REF
–
+
2
LTC2410
U
CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
●
●
●
●
●
●
130
140
dB
CC
–
+
GND ≤ IN = IN ≤ 5V
+
–
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ REF ≤ V , REF = GND,
140
140
110
110
130
dB
dB
dB
dB
dB
CC
–
+
GND ≤ IN = IN ≤ 5V, (Note 7)
+
–
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ REF ≤ V , REF = GND,
CC
–
+
GND ≤ IN = IN ≤ 5V, (Note 8)
Input Normal Mode Rejection
(Note 7)
140
140
140
60Hz ±2%
Input Normal Mode Rejection
(Note 8)
50Hz ±2%
+
–
Reference Common Mode
Rejection DC
2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,
CC
–
+
V
= 2.5V, IN = IN = GND
REF
+
–
–
+
Power Supply Rejection, DC
REF = 2.5V, REF = GND, IN = IN = GND
100
110
110
dB
dB
dB
+
–
–
+
Power Supply Rejection, 60Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)
+
–
–
+
Power Supply Rejection, 50Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 8)
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A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
●
●
●
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
V
Input Differential Voltage Range
– V /2
V
IN
REF
REF
+
–
(IN – IN )
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
●
●
●
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
V
Reference Differential Voltage Range
V
CC
REF
+
–
(REF – REF )
+
+
C (IN )
IN Sampling Capacitance
18
18
18
18
1
pF
pF
pF
pF
nA
nA
nA
nA
S
–
–
C (IN )
IN Sampling Capacitance
S
+
+
C (REF )
REF Sampling Capacitance
S
–
–
C (REF )
REF Sampling Capacitance
S
+
+
+
I
I
I
I
(IN )
IN DC Leakage Current
CS = V , IN = GND
●
●
●
●
–10
–10
–10
–10
10
DC_LEAK
DC_LEAK
DC_LEAK
DC_LEAK
CC
–
–
–
(IN )
IN DC Leakage Current
CS = V , IN = GND
1
10
10
10
CC
+
+
+
(REF )
REF DC Leakage Current
CS = V , REF = 5V
1
CC
–
–
–
(REF )
REF DC Leakage Current
CS = V , REF = GND
1
CC
3
LTC2410
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
IH
V
IL
V
IH
V
IL
High Level Input Voltage
●
●
●
●
●
●
2.5
2.0
V
V
CC
CS, F
2.7V ≤ V ≤ 3.3V
O
CC
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V
O
CC
High Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 9)
2.5
2.0
V
V
CC
2.7V ≤ V ≤ 3.3V (Note 9)
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 9)
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V (Note 9)
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
10
µA
µA
pF
pF
V
IN
IN
CS, F
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 9)
10
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 9)
IN
High Level Output Voltage
SDO
I = –800µA
O
●
●
●
●
●
V
V
– 0.5V
– 0.5V
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO
I = 1.6mA
O
0.4V
V
High Level Output Voltage
SCK
I = –800µA (Note 10)
O
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 10)
O
0.4V
10
V
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
CC
Conversion Mode
Sleep Mode
CS = 0V (Note 12)
●
●
200
20
300
30
µA
µA
CS = V (Note 12)
CC
4
LTC2410
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.56
0.25
0.25
TYP
MAX
2000
390
UNITS
kHz
µs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
●
●
●
EOSC
HEO
390
µs
LEO
F = 0V
●
●
●
130.86
157.03
133.53
160.23
EOSC
136.20
163.44
(in kHz)
ms
ms
ms
CONV
O
F = V
O
CC
External Oscillator (Note 11)
20510/f
f
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
19.2
kHz
kHz
ISCK
f
/8
EOSC
D
Internal SCK Duty Cycle
(Note 10)
(Note 9)
(Note 9)
(Note 9)
●
●
●
●
45
55
%
kHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
2000
ESCK
250
250
1.64
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.67
1.70
ms
ms
256/f
(in kHz)
EOSC
t
t
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
(Note 9)
●
●
●
●
●
●
●
●
●
32/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
1
ESCK
0
0
200
200
200
t2
t3
t4
(Note 10)
(Note 9)
0
CS ↓ to SCK ↑
50
t
t
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
220
50
KQMAX
KQMIN
(Note 5)
15
50
t
t
5
6
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 2: All voltage values are with respect to GND.
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
V
IN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
FO = 0V or FO = VCC
.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 14: Guaranteed by design and test correlation.
5
LTC2410
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PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a ground plane through a low impedance
connection.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from–0.5•(VREF)to0.5•(VREF). Outsidethisinputrange
the converter produces unique overrange and underrange
output codes.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
isdrivenbyanexternalclocksignalwithafrequencyfEOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
6
LTC2410
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FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
F
O
(INT/EXT)
+
IN
IN
+
–
–
∫
∫
∫
SDO
SERIAL
INTERFACE
∑
ADC
SCK
CS
+
REF
REF
–
DECIMATING FIR
–
+
DAC
2410 FD
V
CC
TEST CIRCUITS
1.69k
SDO
SDO
1.69k
C
= 20pF
LOAD
C
= 20pF
LOAD
Hi-Z TO V
OH
OH
V
OL
V
OH
TO V
Hi-Z TO V
OL
OL
TO Hi-Z
V
V
TO V
2410 TA03
OH
OL
TO Hi-Z
2410 TA04
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
CONVERT
Converter Operation Cycle
SLEEP
The LTC2410 is a low power, delta-sigma analog-to-
digitalconverterwithaneasytouse3-wireserialinterface.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2410 F01
Initially, the LTC2410 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
Whileinthissleepstate,powerconsumptionisreducedby
an order of magnitude. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Figure 1. LTC2410 State Transition Diagram
7
LTC2410
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APPLICATIO S I FOR ATIO
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.
The LTC2410 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
specttotime,supplyvoltagechangeandtemperaturedrift.
Power-Up Sequence
The LTC2410 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi-
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
Through timing control of the CS and SCK pins, the
LTC2410 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turbthecyclicoperationdescribedabove. Thesemodesof
operation are described in detail in the Serial Interface
Timing Modes section.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2410 starts a normal conversion cycle and
followsthesuccessionofstatesdescribedabove. Thefirst
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2410 incorporates a highly accurate on-
chip oscillator. This eliminates the need for external fre-
quency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2410
achieves a minimum of 110dB rejection at the line fre-
quency (50Hz or 60Hz ±2%).
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
ficationfortheREF+ andREF– pinscoverstheentirerange
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2410 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is deter-
mined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter’s overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external FO signal) at substantially higher output data
rates (see the Output Data Rate section).
Ease of Use
The LTC2410 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle.Thereisaone-to-onecorrespondencebetweenthe
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
8
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Input Voltage Range
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits the LTC2410 converts the
bipolar differential input signal, VIN = IN+ – IN–, from
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
–FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF
=
REF+ –REF–.Outsidethisrangetheconverterindicatesthe
overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
betweentheseseriesresistorsandthecorrespondingpins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. The effect of the
series resistance on the converter accuracy can be evalu-
ated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if VREF = 5V.
This error has a very strong temperature dependency.
The function of these bits is summarized in Table 1.
Table 1. LTC2410 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
Input Range
EOC
DMY
SIG MSB
V
≥ 0.5 • V
0
0
0
0
0
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
0
IN
REF
–0.5 • V ≤ V < 0V
0
REF
IN
V
< –0.5 • V
0
IN
REF
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Output Data Format
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
The LTC2410 serial output data stream is 32 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 24 bits are the conversion
result, MSB first. The remaining 5 bits are sub LSBs
beyond the 24-bit level that may be included in averaging
or discarded without loss of resolution. The third and
fourth bit together are also used to indicate an underrange
condition(thedifferentialinputvoltageisbelow–FS)oran
overrangecondition(thedifferentialinputvoltageisabove
+FS).
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
deviceonceCSispulledLOW.EOCchangesrealtimefrom
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
risingedgeofSCK. Bit30isshiftedoutofthedeviceonthe
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
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on the rising edge of the 32nd SCK pulse. On the falling
edgeofthe32ndSCKpulse,SDOgoesHIGHindicatingthe
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
AslongasthevoltageontheIN+ andIN–pinsismaintained
within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS=0.5•VREF.Fordifferentialinputvoltagesgreaterthan
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO)
TheLTC2410internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejec-
tion, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
CS
BIT 31
EOC
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 5
BIT 0
SDO
SCK
LSB
24
Hi-Z
1
2
3
4
5
26
27
32
SLEEP
DATA OUTPUT
CONVERSION
2410 F03
Figure 3. Output Data Timing
Table 2. LTC2410 Output Data Format
Differential Input Voltage
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
V
*
IN
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
IN
REF
+
–
*The differential input voltage V = IN – IN .
IN
+
–
**The differential reference voltage V = REF – REF .
REF
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–80
–85
synchronized with an outside source, the LTC2410 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
While operating with an external conversion clock of a
frequency fEOSC, the LTC2410 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/2560(%)
2410 F04
EOSC
Figure 4. LTC2410 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
Whenever an external clock is not present at the FO pin the
converterautomaticallyactivatesitsinternaloscillatorand
enters the Internal Conversion Clock mode. The LTC2410
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
notbeaffected.Ifthechangeoccursduringthedataoutput
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
SERIAL INTERFACE PINS
The LTC2410 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Table 3. LTC2410 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
O
F = HIGH
O
160ms, Output Data Rate ≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator
F = External Oscillator
20510/f
s, Output Data Rate ≤ f
/20510 Readings/s
EOSC
O
EOSC
with Frequency f
kHz
EOSC
(f
EOSC
/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
External Serial Clock with
F = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
O
F = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/f
ms
EOSC
O
Frequency f
kHz
(32 SCK cycles)
EOSC
As Long As CS = LOW But Not Longer Than 32/f ms
SCK
Frequency f
kHz
(32 SCK cycles)
SCK
11
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Serial Clock Input/Output (SCK)
described in the previous sections.
The serial clock signal present on SCK (Pin 13) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2410 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2410 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internalorexternalSCKmodeisselectedonpower-upand
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO. Tying a
capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor’s
value, see Figures 12 to 14.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
SERIAL INTERFACE TIMING MODES
The LTC2410’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2-or3-wireI/O,singlecycleconversionandautostart.The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW or FO = HIGH) or
an external oscillator connected to the FO pin. Refer to
Table 4 for a summary.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
Chip Select Input (CS)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The active LOW chip select, CS (Pin 11), is used to test the
conversionstatusandtoenablethedataoutputtransferas
Table 4. LTC2410 Interface Timing Modes
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
SCK
Configuration
Source
External
External
Internal
Internal
Internal
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 5, 6
Figure 7
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal SCK, Autostart Conversion
CS ↓
CS ↓
Figures 8, 9
Figure 10
Figure 11
Continuous
Internal
Internal
C
EXT
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The serial clock mode is selected on the falling edge of CS.
Toselecttheexternalserialclockmode,theserialclockpin
(SCK) must be LOW during each CS falling edge.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
deviceautomaticallyentersthelowpowersleepstateonce
the conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
risingedgeofSCKisseenwhileCSisLOW.Dataisshifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, thedevicebeginsanewconversion. SDOgoesHIGH
(EOC = 1) indicating a conversion is in progress.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after VCC exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2410
3
4
+
–
REFERENCE
VOLTAGE
REF
REF
SCK
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
SUB LSB
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2410 F05
Figure 5. External Serial Clock, Single Cycle Operation
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2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2410
3
4
+
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 9
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2410 F06
Figure 6. External Serial Clock, Reduced Data Output Length
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result is
loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
Onthe32ndfallingedgeofSCK,SDOgoesHIGH(EOC = 1)
indicating a new conversion has begun.
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
WhentestingEOC,iftheconversioniscomplete(EOC=0),
thedevicewillexitthesleepstateandenterthedataoutput
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
duringthefallingedgeofEOC).ThevalueoftEOCtest is23µs
if the device is using its internal oscillator (F0 = logic LOW
or HIGH). If FO is driven by an external oscillator of
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
14
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2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
2
14
13
V
F
O
CC
LTC2410
3
+
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2410 F07
Figure 7. External Serial Clock, CS = 0 Operation
2.7V TO 5.5V
V
CC
V
CC= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
1µF
2
14
13
V
F
O
CC
10k
LTC2410
3
4
+
–
REFERENCE
VOLTAGE
REF
REF
SCK
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2410 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
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frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled
HIGH before time tEOCtest, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edgeofSCK.Theinternallygeneratedserialclockisoutput
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latchedonthefirstrisingedgeofSCKandthelastbitofthe
conversionresultonthe32ndrisingedgeofSCK. Afterthe
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Whenever SCK is LOW, the LTC2410’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certainapplicationsmayrequireanexternaldriveronSCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2410’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
2.7V TO 5.5V
V
CC
V
CC= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
1µF
2
14
13
V
F
O
CC
LTC2410
10k
3
+
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF REF
–
IN
1, 7, 8, 9, 10, 15, 16
<t
EOCtest
GND
>t
EOCtest
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2410 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
16
LTC2410
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A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sionstatus.Ifthedeviceisinthesleepstate(EOC=0),SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as tEOCtest), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
thenimmediatelybeginsoutputtingdata.Thedataoutput
cyclebeginsonthefirstrisingedgeofSCKandendsafter
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH(EOC=1)indicatinganewconversionisinprogress.
SCK remains HIGH during the conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after VCC exceeds 2.2V. An internal
2.7V TO 5.5V
V
CC= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
1µF
2
14
V
F
O
CC
LTC2410
3
+
13
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
IN
SDO
CS
–0.5V
TO 0.5V
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2410 F10
SLEEP
Figure 10. Internal Serial Clock, Continuous Operation
17
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Internal Serial Clock, Autostart Conversion
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltageatCSfallsbelowaninternalthreshold(≈1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
modetheanalogvoltageontheCSpincannotbeobserved
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
F
O
CC
LTC2410
3
+
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
IN
SDO
CS
–0.5V
TO 0.5V
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
C
EXT
V
CC
CS
GND
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 0
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
2410 F11
Figure 11. Internal Serial Clock, Autostart Operation
18
LTC2410
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7
6
5
4
3
2
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
PRESERVING THE CONVERTER ACCURACY
The LTC2410 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
V
= 5V
CC
1
0
V
= 3V
CC
10
100
100000
1
1000
10000
CAPACITANCE ON CS (pF)
2400 F12
Figure 12. CS Capacitance vs tSAMPLE
Digital Signal Levels
8
7
6
The LTC2410’s digital interface is easy to use. Its digital
inputs(FO,CSandSCKinExternalSCKmodeofoperation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs.However,someconsiderationsarerequiredtotake
advantage of the exceptional accuracy and low supply
current of this converter.
V
= 5V
CC
5
V
= 3V
CC
4
3
2
1
0
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
10
100
10000
100000
0
1000
CAPACITANCE ON CS (pF)
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
inExternalSCKmodeofoperation)iswithinthisrange,the
LTC2410 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
2400 F13
Figure 13. CS Capacitance vs Output Rate
300
250
V
V
= 5V
= 3V
CC
CC
200
150
signals to full CMOS levels [VIL < 0.4V and VOH
(VCC – 0.4V)].
>
100
50
0
During the conversion period, the undershoot and/or
overshootofafastdigitalsignalconnectedtotheLTC2410
pins may severely disturb the analog to digital conversion
process.Undershootandovershootcanoccurbecauseof
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2410.
Forreference,onaregularFR-4board,signalpropagation
1
10
100
1000
10000 100000
CAPACITANCE ON CS (pF)
2400 F14
Figure 14. CS Capacitance vs Supply Current
19
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velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2410 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitorsareswitchingbetweenthesefourpinstransfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 15.
Parallel termination near the LTC2410 pin will eliminate
thisproblembutwillincreasethedriverpowerdissipation.
A series resistor between 27Ω and 56Ω placed near the
driver or near the LTC2410 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 15), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Whenusingtheinternaloscillator(FO =LOWorHIGH), the
LTC2410’sfront-endswitched-capacitornetworkisclocked
at 76800Hz corresponding to a 13µs sampling period.
Thus, for settling errors of less than 1ppm, the driving
sourceimpedanceshouldbechosensuchthatτ ≤13µs/14
= 920ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2/fEOSC and, for a settling
Particular attention must be given to the connection of the
FO signal when the LTC2410 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converterinputterminalsmayresultintoaDCoffseterror.
Such perturbations may occur due to asymmetric capaci-
tivecouplingbetweentheFO signaltraceandtheconverter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formedbytheFO connectiontrace, theterminationandthe
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
error of less than 1ppm, τ ≤ 0.14/fEOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
theINLperformanceoftheconverter. Figure15showsthe
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
20
LTC2410
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V
CC
I
+
REF
R
(TYP)
SW
20k
I
V
IN + VINCM − VREFCM
LEAK
I IN+
=
=
(
)
)
AVG
AVG
0.5• REQ
−VIN + VINCM − VREFCM
0.5• REQ
V
+
REF
I IN−
I
LEAK
(
V
CC
V2
I
+
1.5• VREF − VINCM + VREFCM
IN
IN
I REF+
=
−
(
)
R
(TYP)
20k
SW
AVG
I
I
0.5• REQ
V
REF • REQ
LEAK
LEAK
V2
V
+
−1.5• VREF − VINCM + VREFCM
0.5• REQ
IN
IN
I REF−
=
+
(
)
C
EQ
AVG
V
REF • REQ
18pF
where:
(TYP)
V
CC
I
–
–
VREF = REF+ −REF−
IN
IN
R
R
(TYP)
SW
I
I
REF+ + REF−
LEAK
LEAK
20k
VREFCM
=
V
2
V
IN = IN+ −IN−
IN+ − IN−
V
CC
V
INCM
=
I
–
–
REF
2
(TYP)
SW
20k
I
I
LEAK
LEAK
REQ = 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch F = LOW
(
(
)
)
O
2410 F15
V
REF
REQ = 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch F = HIGH
REQ = 0.555• 1012 / fEOSC EXTERNAL OSCILLATOR
O
(
)
SWITCHING FREQUENCY
f
f
= 76800Hz INTERNAL OSCILLATOR (F = LOW OR HIGH)
SW
SW
O
= 0.5 • f
EXTERNAL OSCILLATOR
EOSC
Figure 15. LTC2410 Equivalent Analog Input Circuit
R
SOURCE
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 16. The CPAR capacitor
includes the LTC2410 pin capacitance (5pF typical) plus
thecapacitanceofthetestfixtureusedtoobtaintheresults
shown in Figures 17 and 18. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
by Figures 17 and 18. For simplicity two distinct situations
can be considered.
+
IN
C
C
PAR
V
V
+ 0.5V
C
C
INCM
INCM
IN
IN
IN
IN
20pF
LTC2410
R
SOURCE
–
IN
2410 F16
PAR
20pF
– 0.5V
Figure 16. An RC Network at IN+ and IN–
50
0
C
= 0.01µF
IN
V
= 5V
CC
+
REF = 5V
C
= 0.001µF
IN
C
–
REF = GND
40
30
20
10
0
–10
–20
–30
–40
–50
+
–
= 100pF
IN
IN = GND
IN = 2.5V
C
= 0pF
IN
F
= GND
= 25°C
O
A
T
V
= 5V
CC
+
–
REF = 5V
C
= 0.01µF
REF = GND
IN
+
–
IN = 5V
C
= 0.001µF
IN
C
IN = 2.5V
F
= GND
O
= 100pF
IN
C
T
= 25°C
A
= 0pF
IN
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
(Ω)
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
(Ω)
R
R
SOURCE
SOURCE
2410 F17
2410 F18
Figure 17. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 18. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
21
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For relatively small values of input capacitance (CIN
<
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance,indirectdistortionmayresultfromthemodu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, itisadvisabletocarefullymatchthesourceimped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.23ppm. When FO is
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performancewithoutsignificantbenefitsofsignalfiltering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2410 can maintain its exceptional accuracy while
operatingwithrelativelargevaluesofsourceresistanceas
shown in Figures 17 and 18. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linearsettlingprocessoftheinputamplifiers.ForsmallCIN
values, the settling on IN+ and IN– occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
driven by an external oscillator with a frequency fEOSC
,
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 1.78 • 10–6 • fEOSCppm. Figure 21
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and IN– pins when large CIN values are
used.
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm for each
ohm of source resistance driving IN+ or IN–. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differentialinputresistanceis2.16MΩwhichwillgenerate
a gain error of approximately 0.23ppm for each ohm of
source resistance driving IN+ or IN–. When FO is driven by
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential input
resistance is 0.28 • 1012/fEOSCΩ and each ohm of
source resistance driving IN+ or IN– will result in
1.78 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
thisgainerror.Thetypical+FSand–FSerrorsasafunction
of the sum of the source resistance seen by IN+ and IN– for
large values of CIN are shown in Figures 19 and 20.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications a one-time cali-
bration operation may be sufficient.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
22
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300
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
inasmalloffsetshift. A100Ωsourceresistancewillcreate
a 0.1µV typical and 1µV maximum offset voltage.
V
= 5V
CC
C
= 1µF, 10µF
IN
+
REF = 5V
–
REF = GND
240
180
120
60
+
–
IN = 3.75V
IN = 1.25V
F
= GND
= 25°C
O
A
T
C
IN
= 0.1µF
Reference Current
C
IN
= 0.01µF
In a similar fashion, the LTC2410 samples the differential
reference pins REF+ and REF– transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
notchangetheconverteroffsetbutitmaydegradethegain
and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
0
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
SOURCE
2410 F19
Figure 19. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
Forrelativelysmallvaluesoftheexternalreferencecapaci-
tors(CREF <0.01µF),thevoltageonthesamplingcapacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gainperformancewithoutsignificantbenefitsofreference
filtering and the user is advised to avoid them.
C
= 0.01µF
IN
–60
–120
–180
–240
–300
C
= 0.1µF
IN
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
IN = 1.25V
IN = 3.75V
F
= GND
= 25°C
O
A
C
= 1µF, 10µF
Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internaloscillatorand60Hznotch), thetypicaldifferential
reference resistance is 1.3MΩ which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistancedrivingREF+ orREF–. WhenFO =HIGH(internal
oscillator and 50Hz notch), the typical differential refer-
enceresistanceis1.56MΩwhichwillgenerateagainerror
of approximately 0.32ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
externaloscillatorwithafrequencyfEOSC (externalconver-
sion clock operation), the typical differential reference
resistance is 0.20 • 1012/fEOSCΩ and each ohm of source
resistance drving REF+ or REF– will result in
2.47 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
IN
T
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
SOURCE
2410 F20
Figure 20. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
120
V
= 5V
CC
+
100
80
REF = 5V
A
B
–
REF = GND
+
–
IN = IN = V
INCM
60
40
C
D
E
F
20
0
–20
–40
–60
–80
–100
–120
F
= GND
= 25°C
SOURCEIN
= 10µF
O
G
T
A
R
– = 500Ω
C
IN
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
(V)
INCM
A: ∆R = +400Ω
E: ∆R = –100Ω
IN
IN
IN
IN
IN
IN
B: ∆R = +200Ω
F: ∆R = –200Ω
C: ∆R = +100Ω
G: ∆R = –400Ω
IN
D: ∆R = 0Ω
2410 F21
Figure 21. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
23
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REF+ and REF– pins and external capacitance CREF con-
nected to these pins are shown in Figures 22, 23, 24
and 25.
external oscillator with a frequency fEOSC, every 100Ω of
source resistance driving REF+ or REF– translates into
about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure 26 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
tworeferencepinsisadditivewithrespecttothisINLerror.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
WhenFO =LOW(internaloscillatorand60Hznotch),every
100ΩofsourceresistancedrivingREF+ orREF– translates
into about 1.34ppm additional INL error. When FO = HIGH
(internaloscillatorand50Hznotch), every100Ωofsource
resistance driving REF+ or REF– translates into about
1.1ppm additional INL error. When FO is driven by an
0
50
C
= 0.01µF
REF
V
= 5V
CC
+
REF = 5V
C
= 0.001µF
REF
–
REF = GND
–10
–20
–30
–40
–50
40
30
20
10
0
+
–
C
= 100pF
IN = 5V
REF
IN = 2.5V
C
= 0pF
REF
F
= GND
= 25°C
O
A
T
V
= 5V
CC
+
–
REF = 5V
C
= 0.01µF
REF = GND
REF
+
–
IN = GND
C
= 0.001µF
REF
IN = 2.5V
F
= GND
O
C
= 100pF
REF
T
= 25°C
A
C
= 0pF
REF
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
(Ω)
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
(Ω)
R
R
SOURCE
SOURCE
2410 F22
2410 F23
Figure 22. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 23. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
0
450
C
= 0.01µF
= 0.1µF
REF
V
= 5V
CC
C
REF
= 1µF, 10µF
+
REF = 5V
–
REF = GND
–90
–180
–270
–360
–450
360
270
180
90
+
–
IN = 1.25V
IN = 3.75V
F
= GND
= 25°C
O
A
C
T
REF
C
REF
= 0.1µF
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
IN = 3.75V
C
REF
= 0.01µF
IN = 1.25V
C
= 1µF, 10µF
F
= GND
= 25°C
REF
O
A
T
0
0
100 200 300 400 500 600 700 800 9001000
(Ω)
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
R
SOURCE
SOURCE
2410 F24
2410 F25
Figure 24. +FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
Figure 25. –FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
24
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15
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2410 output data rate can be increased
asdesired. Thedurationoftheconversionphaseis20510/
R
= 1000Ω
12
9
SOURCE
R
= 500Ω
SOURCE
6
3
0
–3
–6
–9
–12
–15
R
= 100Ω
SOURCE
fEOSC. If fEOSC = 153600Hz, the converter behaves as if the
internal oscillator is used and the notch is set at 60Hz.
There is no significant difference in the LTC2410 perfor-
mance between these two operation modes.
–0.5–0.4–0.3–0.2–0.1
V
0
/V
0.1 0.2 0.3 0.4 0.5
INDIF REFDIF
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
V
= 5V
F
C
T
= GND
O
CC
REF+ = 5V
= 10µF
REF
REF– = GND
= 25°C
A
+
–
V
= 0.5 • (IN + IN ) = 2.5V
2410 F26
INCM
Figure 26. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF– for
Large CREF Values (CREF ≥ 1µF)
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2410’s exceptional common mode rejec-
tion and by carefully eliminating common mode to differ-
ential mode conversion sources in the input circuit. The
user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry in
the circuits driving the IN+ and IN– pins.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
valueovertheentiretemperatureandvoltagerange). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2410 typical
performance can be inferred from Figures 17, 18, 22 and
Inadditiontothereferencesamplingcharge,thereference
pinsESDprotectiondiodeshaveatemperaturedependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
23 in which the horizontal axis is scaled by 153600/fEOSC
.
Output Data Rate
Third, an increase in the frequency of the external oscilla-
torabove460800Hz(amorethan3×increaseintheoutput
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a pro-
gressive degradation in the converter accuracy and linear-
When using its internal oscillator, the LTC2410 can pro-
duceupto7.5readingspersecondwithanotchfrequency
of 60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH). The actual output
25
LTC2410
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500
450
400
350
300
250
200
150
100
50
ity. Typical measured performance curves for output data
rates up to 100 readings per second are shown in Fig-
ures 27, 28, 29, 30, 31, 32, 33 and 34. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 20 readings per second, the
userisadvisedtomaximizethepowersupplyvoltageused
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
V
= 5V
CC
+
REF = 5V
–
REF = GND
V
V
= 2.5V
INCM
= 0V
IN
F
= EXTERNAL OSCILLATOR
O
T
= 85°C
A
T
= 25°C
A
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
Input Bandwidth
The combined effect of the internal Sinc4 digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2410 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz (FO = LOW),
the 3dB input bandwidth is 3.63Hz. When the internal
oscillator is used with the notch set at 50Hz (FO = HIGH),
the 3dB input bandwidth is 3.02Hz. If an external conver-
sionclockgeneratoroffrequencyfEOSC isconnectedtothe
2410 F27
Figure 27. Offset Error vs Output Data Rate and Temperature
7000
V
= 5V
CC
+
6000
5000
4000
3000
2000
1000
0
REF = 5V
–
REF = GND
+
–
IN = 3.75V
IN = 1.25V
F
= EXTERNAL OSCILLATOR
FO pin, the 3dB input bandwidth is 0.236 • 10–6 • fEOSC
.
O
Due to the complex filtering and calibration algorithms
utilized,theconverterinputbandwidthisnotmodeledvery
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2410 input bandwidth is shown in Fig-
ure 35 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2410 input bandwidth can be derived from Figure 35,
FO = LOW curve in which the horizontal axis is scaled by
T
= 85°C
A
T
= 25°C
A
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2410 F28
Figure 28. +FS Error vs Output Data Rate and Temperature
fEOSC/153600.
0
The conversion noise (800nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is
62.75nV√Hz for an infinite bandwidth source and
76.8nV√Hz for a single 0.5MHz pole source. From these
numbers, it is clear that particular attention must be given
to the design of external amplification circuits. Such
circuits face the simultaneous requirements of very low
bandwidth (just a few Hz) in order to reduce the output
referred noise and relatively high bandwidth (at least
500kHz) necessary to drive the input switched-capacitor
network. A possible solution is a high gain, low bandwidth
amplifier stage followed by a high bandwidth unity-gain
buffer.
–1000
T
= 85°C
A
–2000
–3000
–4000
–5000
–6000
–7000
T
A
= 25°C
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
IN = 1.25V
IN = 3.75V
F
= EXTERNAL OSCILLATOR
O
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2410 F29
Figure 29. –FS Error vs Output Data Rate and Temperature
26
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24
23
22
22
20
18
16
14
12
10
8
RESOLUTION = LOG (V /INL )
MAX
2
REF
T
= 25°C
A
21
20
19
18
17
16
15
14
13
12
T
= 85°C
T = 25°C
A
A
T
= 85°C
A
V
= 5V
CC
+
V
= 5V
REF = 5V
CC
+
–
REF = 5V
REF = GND
–
REF = GND
V
V
F
= 2.5V
INCM
V
= 2.5V
= 0V
INCM
IN
–2.5V < V < 2.5V
= EXTERNAL OSCILLATOR
RESOLUTION = LOG (V /NOISE )
RMS
IN
O
F
O
= EXTERNAL OSCILLATOR
2
REF
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2410 F30
2410 F31
Figure 31. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 30. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
250
24
23
V
= 5V
225
200
175
150
125
100
75
CC
V
= 5V
REF
+
REF = GND
22
21
20
19
18
17
16
15
14
13
12
V
V
= 2.5V
INCM
= 0V
V
= 2.5V
IN
REF
F
= EXTERNAL OSCILLATOR
= 25°C
O
A
T
V
= 5V
CC
–
REF = GND
V
= 5V
REF
V
V
F
= 2.5V
INCM
= 0V
IN
V
= 2.5V
REF
= EXTERNAL OSCILLATOR
= 25°C
50
O
T
A
25
RESOLUTION = LOG (V /NOISE )
RMS
2
REF
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2410 F32
2410 F33
Figure 32. Offset Error vs Output
Data Rate and Reference Voltage
Figure 33. Resolution (NoiseRMS ≤ 1LSB) vs
Output Data Rate and Reference Voltage
22
RESOLUTION =
LOG (V /INL
)
20
18
16
14
12
10
8
2
REF
MAX
V
= 2.5V
V
= 5V
REF
REF
T
= 25°C
= 5V
A
CC
V
–
REF = GND
= 0.5 • REF
+
V
INCM
–0.5V • V
< V < 0.5 • V
REF
IN REF
F
= EXTERNAL OSCILLATOR
O
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2410 F34
Figure 34. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage
27
LTC2410
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0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2410 significantly
simplifies antialiasing filter requirements.
F
= HIGH
F = LOW
O
O
TheSinc4 digitalfilterprovidesgreaterthan120dBnormal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2410’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode sig-
nal filtering both in the analog and digital domain. Inde-
pendent of the operating mode, fS = 256 • fN = 2048 •
fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2410 F35
Figure 35. Input Signal Bandwidth Using the Internal Oscillator
0
F
= HIGH
O
–10
–20
–30
–40
The combined normal mode rejection performance is
shown in Figure 36 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure 37 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for the
external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth.Magnifieddetailsofthenormalmoderejection
curves are shown in Figure 38 (rejection near DC) and
Figure 39 (rejection at fS = 256fN) where fN represents the
notch frequency. These curves have been derived for the
external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
–50
–60
–70
–80
–90
–100
–110
–120
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
S S S S S S S S S S S S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2410 F36
Figure 36. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
F
F
= LOW OR
O
O
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 40 and 41. Typical measured values of
the normal mode rejection of the LTC2410 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 40 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2410 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure 41
superimposed over the theoretical calculated curve.
= EXTERNAL OSCILLATOR,
f
= 10 • f
EOSC
S
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f
S S S S S S S S S S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2410. If passive RC components are placed in
2410 F37
Figure 37. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
28
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0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250f 252f 254f 256f 258f 260f 262f
N
0
f
2f
N
3f
4f
N
5f
6f
7f
8f
N
N
N
N
N
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT SIGNAL FREQUENCY (Hz)
2410 F39
2410 F38
Figure 38. Input Normal Mode Rejection
Figure 39. Input Normal Mode Rejection
0
–20
V
–40
–60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2410 F40
Figure 40. Input Normal Mode Rejection vs Input Frequency
0
–20
V
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2410 F41
Figure 41. Input Normal Mode Rejection vs Input Frequency
29
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front of the LTC2410, the input dynamic current should be
considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects of
dynamic input current.
for large input signal levels. With a reference voltage
REF = 5V, the LTC2410 has a full-scale differential input
V
range of 5V peak-to-peak. Figures 42 and 43 show mea-
surement results for the LTC2410 normal mode rejection
ratio with a 7.5V peak-to-peak (150% of full scale) input
signalsuperimposedoverthemoretraditionalnormalmode
rejectionratioresultsobtainedwitha5Vpeak-to-peak(full
scale) input signal. In Figure 42, the LTC2410 uses the
internal oscillator with the notch set at 60Hz (FO = LOW)
and in Figure 43 it uses the internal oscillator with the
notch set at 50Hz (FO = HIGH). It is clear that the LTC2410
rejectionperformanceismaintainedwithnocompromises
in this extreme situation. When operating with large input
signal levels, the user must observe that such signals do
not violate the device absolute maximum ratings.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from po-
tential instabilities at large input signal levels. The propri-
etaryarchitectureusedfortheLTC2410thirdordermodu-
lator resolves this problem and guarantees a predictable
stable behavior at input signal levels of up to 150% of full
scale. In many industrial applications, it is not uncommon
to have to measure microvolt level signals superimposed
over volt level perturbations and LTC2410 is eminently
suitedforsuchtasks.Whentheperturbationisdifferential,
the specification of interest is the normal mode rejection
0
V
V
= 5V
= 7.5V
V
= 5V
IN(P-P)
CC
+
REF = 5V
REF = GND
IN(P-P)
–20
–
(150% OF FULL SCALE)
V
= 2.5V
= GND
INCM
–40
F
O
T
A
= 25°C
–60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2410 F3a
Figure 42. Measured Input Normal Mode Rejection vs Input Frequency
0
V
= 5V
V
= 5V
–20
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2410 F4a
Figure 43. Measured Input Normal Mode Rejection vs Input Frequency
30
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SYNCHRONIZATION OF MULTIPLE LTC2410s
Increasing the Output Rate Using Mulitple LTC2410s
Since the LTC2410’s absolute accuracy (total unadjusted
error) is 5ppm, applications utilizing multiple synchro-
nized ADCs are possible.
A second application uses multiple LTC2410s to increase
the effective output rate by 4×, see Figure 45. In this case,
four LTC2410s are interleaved under the control of sepa-
rate CS signals. This increases the effective output rate
from 7.5Hz to 30Hz (up to a maximum of 60Hz). Addition-
ally, the one-shot output spectrum is unfolded allowing
further digital signal processing of the conversion results.
SCK and SDO may be common to all four LTC2410s. The
four CS rising edges equally divide one LTC2410 conver-
sion cycle (7.5Hz for 60Hz notch frequency). In order to
synchronize the start of conversion to CS, 31 or less SCK
clock pulses must be applied to each ADC.
Simultaneous Sampling with Two LTC2410s
OnesuchapplicationissynchronizingmultipleLTC2410s,
see Figure 44. The start of conversion is synchronized to
the rising edge of CS. In order to synchronize multiple
LTC2410s, CS is a common input to all the ADCs.
To prevent the converters from autostarting a new con-
version at the end of data output read, 31 or fewer SCK
clocksignalsareappliedtotheLTC2410insteadof32(the
32nd falling edge would start a conversion). The exact
timing and frequency for the SCK signal is not critical
since it is only shifting out the data. In this case, two
LTC2410’s simultaneously start and end their conversion
cycles under the external control of CS.
Both the synchronous and 4×output rate applications use
the external serial clock and single cycle operation with
reduced data output length (see Serial Interface Timing
Modes section and Figure 6). An external oscillator clock
is applied commonly to the FO pin of each LTC2410 in
order to synchronize the sampling times. Both circuits
may be extended to include more LTC2410s.
SCK2
SCK1
EXTERNAL OSCILLATOR
(153,600HZ)
LTC2410
#1
LTC2410
#2
V
CC
F
V
F
O
O
CC
+
–
+
–
REF
REF
SCK
SDO
CS
REF
REF
SCK
SDO
CS
µCONTROLLER
+
+
IN
IN
–
–
IN
IN
GND
GND
CS
SDO1
SDO2
V +
REF
V –
REF
CS
SCK1
SCK2
SDO1
SDO2
31 OR LESS CLOCK CYCLES
31 OR LESS CLOCK CYCLES
2410 F44
Figure 44. Synchronous Conversion—Extendable
31
LTC2410
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APPLICATIO S I FOR ATIO
V
V
+
–
REF
REF
EXTERNAL OSCILLATOR
(153,600HZ)
LTC2410
#1
LTC2410
#2
LTC2410
#3
LTC2410
#4
V
CC
F
O
V
CC
F
V
CC
F
V
F
O
O
O
CC
+
–
+
–
+
–
+
–
REF
REF
SCK
SDO
CS
REF
REF
SCK
SDO
CS
REF
REF
SCK
SDO
CS
REF
REF
SCK
SDO
CS
+
+
+
+
IN
IN
IN
IN
–
–
–
–
IN
IN
IN
IN
GND
GND
GND
GND
µCONTROLLER
SCK
SDO
CS1
CS2
CS3
CS4
CS1
CS2
CS3
CS4
31 OR LESS
CLOCK PULSES
SCK
SDO
2410 F45
Figure 45. Actual Frequency Rate LTC2410 System
BRIDGE APPLICATIONS
not an issue. For those systems that require accurate
measurement of a small incremental change on a signifi-
cant tare weight, the lack of history effects in the LTC2400
family is of great benefit.
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2410 is 5V, remote sensing of applied excitation
without additional circuitry requires that excitation be
limited to 5V. This gives only 10mV full scale, which can
beresolvedto1partin10000withoutaveraging.Formany
solid state sensors, this is still better than the sensor. For
example, averaging 64 samples however reduces the
noise level by a factor of eight, bringing the resolving
power to 1 part in 80000, comparable to better weighing
systems. Hysteresis and creep effects in the load cells are
typically much greater than this. Most applications that
require strain measurements to this level of accuracy are
measuring slowly changing phenomena, hence the time
required to average a large number of readings is usually
For those applications that cannot be fulfilled by the
LTC2410 alone, compensating for error in external ampli-
fication can be done effectively due to the “no latency”
feature of the LTC2410. No latency operation allows
samples of the amplifier offset and gain to be interleaved
withweighingmeasurements.Theuseofcorrelateddouble
sampling allows suppression of 1/f noise, offset and
thermocouple effects within the bridge. Correlated double
samplinginvolvesalternatingthepolarityofexcitationand
dealing with the reversal of input polarity mathematically.
Alternatively, bridge excitation can be increased to as
much as ±10V, if one of several precision attenuation
32
LTC2410
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techniquesisusedtoproduceaprecisiondivideoperation
on the reference signal. Another option is the use of a
reference within the 5V input range of the LTC2410 and
developing excitation via fixed gain, or LTC1043 based
voltage multiplication, along with remote feedback in the
excitation amplifiers, as shown in Figures 34 and 35.
devices, RFI suppression and wiring. The LTC2410 exhib-
its extremely low temperature dependent drift. As a result,
exposure to external ambient temperature ranges does
not compromise performance. The incorporation of any
amplification considerably complicates thermal stability,
as input offset voltages and currents, temperature coeffi-
cient of gain settling resistors all become factors.
Figure 46 shows an example of a simple bridge connec-
tion. Note that it is suitable for any bridge application
where measurement speed is not of the utmost impor-
tance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance.Often,largeweighingapplicationsinvolveload
cells located at each load bearing point, the output of
which can be summed passively prior to the signal pro-
cessing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
oftheoutputofmultipleLTC2410’sprovidesthebenefitof
arootsquarereductioninnoise. Thelowpowerconsump-
tion of the LTC2410 makes it attractive for multidrop
communication schemes where the ADC is located within
the load-cell housing.
The circuit in Figure 47 shows an example of a simple
amplification scheme. This example produces a differen-
tial output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentationamplifierisnotnecessary,astheLTC2410
has common mode rejection far beyond that of most
amplifiers. The LTC1051 is a dual autozero amplifier that
can be used to produce a gain of 15 before its input
referred noise dominates the LTC2410 noise. This ex-
ampleshowsagainof34, thatisdeterminedbyafeedback
network built using a resistor array containing 8 individual
resistors. The resistors are organized to optimize tem-
peraturetrackinginthepresenceofthermalgradients.The
second LTC1051 buffers the low noise input stage from
the transient load steps produced during conversion.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor match-
ing due to individual error contribution being reduced. A
gain of 34 may seem low, when compared to common
practiceinearliergenerationsofload-cellinterfaces, how-
ever the accuracy of the LTC2410 changes the rationale.
Achieving high gain accuracy and linearity at higher gains
may prove difficult, while providing little benefit in terms
of noise reduction.
A direct connection to a load cell is perhaps best incorpo-
rated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
LT1019
+
R1
2
V
REF
3
4
12
13
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of –158ppm. Worst-case gain error at a gain of 34,
is –54ppm. The use of the LTC1051A reduces the worst-
case gain error to –33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noiseseeslittleimprovement1 andgainaccuracyispoten-
tially compromised.
+
REF
REF
SDO
SCK
350Ω
BRIDGE
–
5
11
+
IN
CS
LTC2410
6
14
–
IN
F
O
GND
R2
1, 7, 8, 9,
10, 15, 16
2410 F46
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation ampli-
fier in that it does not have the high noise level common in
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 46. Simple Bridge Connection
33
LTC2410
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the output stage that usually dominates when an instru-
mentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.1µVRMS. The buffer stages
canalsobeconfiguredtoprovidegainofupto50withhigh
gain stability and linearity.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output,assignalswingisoftenmuchgreater.Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For
singlevariableelementbridges, thenonlinearityofthehalf
bridge output can be eliminated completely; if the refer-
ence arm of the bridge is used as the reference to the ADC,
as shown in Figure 49. The LTC2410 can accept inputs up
to 1/2 VREF. Hence, the reference resistor R1 must be at
least 2x the highest value of the variable resistor.
Figure 48 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridgecanbemadetoactinconjunctionwiththefeedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resis-
tors which match the temperature coefficient of the load-
cell elements, good results can be achieved without the
needforresistorswithahighdegreeofabsoluteaccuracy.
Thecommonmodevoltageinthiscase, isagainafunction
of the bridge output. Differential gain as used with a 350Ω
bridge is AV = 1+ R2/(R1+175Ω). Common mode gain is
half the differential gain. The maximum differential signal
that can be used is 1/4 VREF, as opposed to 1/2 VREF in the
2-amplifier topology above.
In the case of 100Ω platinum RTD’s, this would suggest a
value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 49 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
1Input referred noise for AV = 34 for approximately 0.05µVRMS, whereas at a gain of 50, it would be
0.048µVRMS
.
5V
REF
0.1µF
5V
8
3
2
+
–
0.1µF
0.1µF
1
U1A
4
5V
2
8
3
2
350Ω
BRIDGE
+
–
V
CC
1
3
4
12
+
–
U2A
REF
REF
SDO
15
14
4
5
12
13
SCK
1
4
RN1
16
5
11
+
6
11
7
10
8
9
IN
CS
2
3
13
LTC2410
6
5
6
5
–
+
+
–
7
7
6
14
–
IN
U2B
U1B
F
O
GND
1, 7, 8, 9,
10, 15, 16
2410 F47
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
Figure 47. Using Autozero Amplifiers to Reduce Input Referred Noise
34
LTC2410
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reference inputs do not have the same rejection. If 60Hz or
other noise is present on the reference input, a low pass
filterisrecommendedasshowninFigure50.Notethatyou
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
Abetterapproachistoproducealowpassfilterdecoupled
from the input lines with a high value resistor (R3).
The circuit shown in Figure 50 shows a more rigorous
example of Figure 49, with increased noise suppression
and more protection for remote applications.
Figure51showsanexampleofgainintheexcitationcircuit
and remote feedback from the bridge. The LTC1043’s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
gainerrororduetooffsetvoltages.A1µV/°Coffsetvoltage
drift translates into 0.05ppm/°C gain error. Simpler alter-
natives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiersmusthavehighopen-loopgainorgainerrorwill
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative refer-
ence input is sampling the same external node as the
positive input, but may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptalby low. If instead the single 25k resistor is re-
placed with a 10k 5% and a 10k 0.1% negative reference
resistor, the noise level introduced at the reference, at
least at higher frequencies, will be reduced. A filter can be
introduced into the network, in the form of one or more
capacitors,orferritebeads,aslongasthesamplingpulses
are not translated into an error. The reference voltage is
alsoreduced, butthisisnotundesirable, asitwilldecrease
the value of the LSB, although, not the input referred noise
level.
5V
+
10µF
0.1µF
5V
350Ω
2
BRIDGE
0.1µV
V
7
CC
3
3
4
+
–
+
REF
REF
175Ω
1µF
6
LTC1050S8
+
2
–
20k
20k
5
+
+
4
IN
1µF
R1
4.98k
R2
46.4k
LTC2410
6
–
IN
GND
1, 7, 8, 9,
10, 15, 16
46.4k
2410 F48
A
= 9.98 1 +
V
(
)
4.99k + 175Ω
Figure 48. Bridge Amplification Using a Single Amplifier
35
LTC2410
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The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 53 shows the use of an LTC2410 with a differential
multiplexer. This is an inexpensive multiplexer that will
contribute some error due to leakage if used directly with
the output from the bridge, or if resistors are inserted as
a protection mechanism from overvoltage. Although the
bridge output may be within the input range of the A/D and
multiplexer in normal operation, some thought should be
given to fault conditions that could result in full excitation
voltage at the inputs to the multiplexer or ADC. The use of
amplification prior to the multiplexer will largely eliminate
errors associated with channel leakage developing error
voltages in the source impedance.
Figure 52 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2410 of 2.5V, maximizing the AC input range for
applications where induced 60Hz could reach amplitudes
up to 2VRMS
.
The last two example circuits could be used where mul-
tiple bridge circuits are involved and bridge output can be
multiplexed onto a single LTC2410, via an inexpensive
multiplexer such as the 74HC4052.
V
S
2.7V TO 5.5V
2
V
CC
3
4
+
–
R1
25.5k
0.1%
REF
REF
LTC2410
5
6
+
IN
IN
PLATINUM
100Ω
–
RTD
GND
1, 7, 8, 9,
10, 15, 16
2410 F49
Figure 49. Remote Half Bridge Interface
5V
5V
2
R2
V
10k
CC
3
4
+
–
0.1%
REF
REF
+
R3
10k
5%
560Ω
1µF
R1
10k, 5%
LTC1050
–
LTC2410
10k
10k
5
6
+
IN
IN
PLATINUM
100Ω
–
RTD
GND
1, 7, 8, 9,
10, 15, 16
2410 F50
Figure 50. Remote Half Bridge Sensing with Noise Suppression on Reference
36
LTC2410
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15V
U1
15V
15V
7
LTC1043
4
200Ω
10V
5V
3
2
8
7
+
LT1236-5
10V
20Ω
*
6
+
+
Q1
2N3904
LTC1150
1µF
11
12
47µF
0.1µF
–
4
–15V
33Ω
14
13
10µF
0.1µF
1k
17
350Ω
BRIDGE
5V
0.1µF
2
V
CC
LTC2410
+
3
4
REF
–
REF
33Ω
5
6
+
IN
–
IN
U2
15V
7
GND
LTC1043
1, 7, 8, 9,
10, 15, 16
Q2
2N3904
3
2
5
15
8
6
+
*
6
LTC1150
2
3
20Ω
–
4
–15V
–15V
18
0.1µF
1k
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
5V
U2
LTC1043
4
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
7
*
11
12
1µF
FILM
200Ω
14
13
–10V
17
–10V
2410 F51
Figure 51. LTC1043 Provides Precise 3X Reference for Excitation Voltages
37
LTC2410
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15V
5V
3
2
+
LT1236-5
20Ω
1/2
LT1112
1
+
Q1
2N3904
C3
47µF
C1
0.1µF
–
C1
0.1µF
22Ω
RN1
10k
10V
5V
1
2
3
2
RN1
10k
V
CC
4
350Ω BRIDGE
TWO ELEMENTS
VARYING
LTC2410
+
3
REF
4
–
REF
5
6
+
IN
–5V
–
IN
8
RN1
10k
GND
1, 7, 8, 9,
10, 15, 16
RN1
10k
7
5
6
15V
C2
0.1µF
33Ω
×2
RN1 IS CADDOCK T914 10K-010-02
8
6
–
Q2, Q3
2N3904
×2
20Ω
1/2
LT1112
7
5
+
4
–15V
2410 F52
–15V
Figure 52. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
5V
5V
+
16
47µF
12
14
15
11
V
CC
+
–
REF
REF
LTC2410
74HC4052
1
5
13
3
+
IN
IN
–
2
4
TO OTHER
DEVICES
GND
1, 7, 8
6
8
9
10
A0
A1
2410 F53
Figure 53. Use a Differential Multiplexer to Expand Channel Capability
38
LTC2410
U
TYPICAL APPLICATIO S
TheperformanceoftheLTC2410canbeverifiedusingthe
demonstration board DC291A, see Figure 56 for the
schematic. This circuit uses the computer’s serial port to
generate power and the SPI digital signals necessary for
starting a conversion and reading the result. It includes a
Labview application software program (see Figure 57)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and
with an external source, linearity. As exemplified in the
schematic, the LTC2410 is extremely easy to use. This
demonstrationboardandassociatedsoftwareisavailable
by contacting Linear Technology.
Sample Driver for LTC2410 SPI Interface
TheLTC2410hasaverysimpleserialinterfacethatmakes
interfacingtomicroprocessorsandmicrocontrollersvery
easy.
The listing in Figure 55 is a simple assembler routine for
the68HC11microcontroller.ItusesPORTD,configuring
it for SPI data transfer between the controller and the
LTC2410. Figure 54 shows the simple 3-wire SPI
connection.
The code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result.
ThisisfollowedbyinitializingPORTD’sSPIconfiguration.
The program then enters the main sequence. It activates
the LTC2410’s serial interface by setting the SS output
low, sending a logic low to CS. It next waits in a loop for
a logic low on the data line, signifying end-of-conversion.
After the loop is satisfied, four SPI transfers are com-
pleted,retrievingtheconversion.Themainsequenceends
by setting SS high. This places the LTC2410’s serial
interface in a high impedance state and initiates another
conversion.
68HC11
SCK (PD4)
MISO (PD2)
SS (PD5)
13
12
11
SCK
LTC2410 SDO
CS
2410 F54
Figure 54. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface
39
LTC2410
U
TYPICAL APPLICATIO S
*****************************************************
* This example program transfers the LTC2410's 32-bit output
*
* conversion result into four consecutive 8-bit memory locations. *
*****************************************************
*68HC11 register definition
PORTD EQU
*
$1008
Port D data register
" – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD"
Port D data direction register
SPI control register
"SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0"
SPI status register
DDRD
SPSR
*
EQU
EQU
$1009
$1028
SPSR
EQU
EQU
$1029
$102A
*
"SPIF,WCOL, – ,MODF; – , – , – , – "
SPI data register; Read-Buffer; Write-Shifter
SPDR
*
* RAM variables to hold the LTC2410's 32 conversion result
*
DIN1
DIN2
DIN3
DIN4
*
EQU
EQU
EQU
EQU
$00
$01
$02
$03
This memory location holds the LTC2410's bits 31 - 24
This memory location holds the LTC2410's bits 23 - 16
This memory location holds the LTC2410's bits 15 - 08
This memory location holds the LTC2410's bits 07 - 00
**********************
* Start GETDATA Routine *
**********************
*
ORG
$C000
Program start location
INIT1
*
LDS
LDAA
#$CFFF Top of C page RAM, beginning location of stack
#$2F
–,–,1,0;1,1,1,1
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
LDAA
STAA
PORTD Keeps SS* a logic high when DDRD, bit 5 is set
#$38
DDRD
–,–,1,1;1,0,0,0
SS*, SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output
LDAA
STAA
#$50
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
*
*
*
*
(This assumes an E-Clock frequency of 4MHz. For higher E-
Clock frequencies, change the above value of $50 to a value
that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory locations
that hold the conversion data
*
LDY
#$1000
BCLR
PORTD, Y %00100000
This sets the SS* output bit to a logic
low, selecting the LTC2410
*
*
40
LTC2410
U
TYPICAL APPLICATIO S
**********************************
* The next short loop waits for the
* LTC2410's conversion to finish before
* starting the SPI data transfer
*
*
*
**********************************
*
CONVEND LDAA
PORTD
#%00000100
Retrieve the contents of port D
Look at bit 2
ANDA
*
*
Bit 2 = Hi; the LTC2410's conversion is not
complete
*
Bit 2 = Lo; the LTC2410's conversion is complete
Branch to the loop's beginning while bit 2 remains
high
BNE
CONVEND
*
*
********************
* The SPI data transfer *
********************
*
TRFLP1 LDAA
#$0
SPDR
Load accumulator A with a null byte for SPI transfer
This writes the byte in the SPI data register and starts
the transfer
STAA
*
WAIT1
LDAA
BPL
SPSR
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
The SPIF (SPI transfer complete flag) bit is the SPSR's MSB
and is set to one at the end of an SPI transfer. The branch
will occur while SPIF is a zero.
WAIT1
*
*
LDAA
SPDR
0,X
Load accumulator A with the current byte of LTC2410 data
that was just received
Transfer the LTC2410's data to memory
STAA
INX
Increment the pointer
CPX
BNE
#DIN4+1 Has the last byte been transferred/exchanged?
TRFLP1 If the last byte has not been reached, then proceed to the
next byte for transfer/exchange
PORTD,Y %00100000 This sets the SS* output bit to a logic high,
de-selecting the LTC2410
*
*
BSET
PULA
PULY
PULX
RTS
Restore the A register
Restore the Y register
Restore the X register
Figure 55. This is an Example of 68HC11 Code That Captures the LTC2410’s
Conversion Results Over the SPI Serial Interface Shown in Figure 54
41
LTC2410
U
TYPICAL APPLICATIO S
D1
BAV74LT1
2
U1
U2
V
JP1
V
JP2
1
1
J1
EXT
CC
CC
LT1460ACN8-2.5
LT1236ACN8-5
R1
JUMPER
JUMPER
V
10Ω
1
3
1
2
6
2
6
2
3
1
V
V
V
V
IN
OUT
GND
IN
OUT
GND
J2
GND
2
+
+
+
+
C1
C2
C3
C4
4
4
10µF
35V
22µF
10µF
100µF
25V
35V
16V
P1
DB9
R2
3Ω
1
6
2
7
3
8
4
9
5
JP3
JUMPER
U3E
U3F
74HC14
74HC14
1
3
R3
51k
10
11
12
13
2
JP4
V
CC
JUMPER
1
3
1
1
J3
CC
V
+
C5
2
BANANA JACK
C6
10µF
35V
1
U3B
74HC14
U3A
74HC14
J4
0.1µF
J5
GND
V
EXT
R4
51k
2
11
CS
4
5
3
6
2
9
1
8
BANANA JACK
V
CC
1
3
14
13
12
16
15
10
J6
+
–
+
REF
F
O
REF
4
5
6
REF
SCK
SDO
GND
GND
GND
U3C
74HC14
U3D
74HC14
BANANA JACK
R5
R6
3k
V
V
+
IN
IN
1
J7
49.9Ω
U4
LTC2410CGN
–
–
REF
1
BANANA JACK
R7
22k
1
J8
IN
3
2
GND GND GND GND
V
+
Q1
MMBT3904LT1
1
7
8
9
BANANA JACK
R8
51k
1
2
1
J9
IN
JP5
JUMPER
V
–
V
CC
BANANA JACK
NOTES:
1
J10
GND
BYPASS CAP
FOR U3
C7
0.1µF
INSTALL JUMBER JP1 AT PIN 1 AND PIN 2
INSTALL JUMBER JP2 AT PIN 1 AND PIN 2
INSTALL JUMBER JP3 AT PIN 1 AND PIN 2
2410 F56
Figure 56. 24-Bit A/D Demo Board Schematic
Figure 57. Display Graphic
42
LTC2410
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
0.015 ± 0.004
(0.38 ± 0.10)
16 15 14 13 12 11 10 9
× 45° 0.053 – 0.068
0.004 – 0.0098
(0.102 – 0.249)
(1.351 – 1.727)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
1
2
3
4
5
6
7
8
U
W
PCB LAYOUT A D FIL
Silkscreen Top
Top Layer
43
LTC2410
U
W
PCB LAYOUT A D FIL
Bottom Layer
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LT1025
Micropower Therocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
Precise Charge, Balanced Switching, Low Power
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
No External Components 5µV Offset, 1.6µV Noise
P-P
LT1236A-5
LT1460
0.05% Max, 5ppm/°C Drift
Micropower Series Reference
0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions
0.3ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.3ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
20-Bit, No Latency ∆Σ ADC in SO-8
LTC2401/LTC2402
LTC2404/LTC2408
LTC2420
2410i LT/TP 0400 4K • PRINTED IN USA
44 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000
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