LTC2414CGN_技术文档

LTC2414/LTC2418

8-/16-Channel

24-Bit No Latency ∆Σ^TMADCs

U

FEATURES

DESCRIPTIO

■

8-/16-Channel Single-Ended or 4-/8-Channel

The LTC^®2414/LTC2418 are 8-/16-channel (4-/8-differ-

ential) micropower 24-bit ∆Σ analog-to-digital convert-

ers. They operate from 2.7V to 5.5V and include an

integrated oscillator, 2ppm INL and 0.2ppm RMS noise.

Theyusedelta-sigmatechnologyandprovidesinglecycle

settling time for multiplexed applications. Through a

single pin, the LTC2414/LTC2418 can be configured for

better than 110dB differential mode rejection at 50Hz or

60Hz ± 2%, or they can be driven by an external oscillator

for a user-defined rejection frequency. The internal oscil-

lator requires no external frequency setting components.

Differential Inputs (LTC2414/LTC2418)

■

Low Supply Current (200µA, 4µA in Autosleep)

■

Differential Input and Differential Reference

with GND to V_CCCommon Mode Range

■

2ppm INL, No Missing Codes

■

2.5ppm Full-Scale Error and 0.5ppm Offset

■

0.2ppm Noise

■

No Latency: Digital Filter Settles in a Single Cycle

Each Conversion Is Accurate, Even After a New

Channel is Selected

■

Single Supply 2.7V to 5.5V Operation

The LTC2414/LTC2418 accept any external differential

reference voltage from 0.1V to V_CCfor flexible ratiometric

and remote sensing measurement applications. They can

be configured to take 4/8 differential channels or

8/16 single-ended channels. The full-scale bipolar input

rangeisfrom–0.5V_REFto0.5V_REF.Thereferencecommon

mode voltage, V_REFCM, and the input common mode volt-

age, V_INCM, may be independently set within GND to V_CC.

TheDCcommonmodeinputrejectionisbetterthan140dB.

■

Internal Oscillator—No External Components

Required

■

110dB Min, 50Hz/60Hz Notch Filter

U

APPLICATIO S

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

Gas Analyzers

Strain Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

The LTC2414/LTC2418 communicate through a flexible

4-wire digital interface that is compatible with SPI and

MICROWIRE^TMprotocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

■

U

TYPICAL APPLICATIO

Total Unadjusted Error

vs Input Voltage

2.7V TO 5.5V

3

1µF

V

= 5V

CC

11

9

= 5V

= V

REF

+

V

CC

REF

V

CC

2

1

= 2.5V

REFCM

21 CH0

22 CH1

INCM

= 50Hz REJECTION

19

F

= GND

O

F

O

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

•

T

= 25°C

A

20

28 CH7

1

SDI

SCK

SDO

CS

16-CHANNEL

MUX

18

17

16

0

CH8

+

–

DIFFERENTIAL

24-BIT ∆Σ ADC

4-WIRE

SPI INTERFACE

THERMOCOUPLE

•

T

= –45°C

A

T

A

= 85°C

–1

–2

–3

8

CH15

10 COM

–

12 REF

15

–2.5 –2 –1.5 –1 –0.5

0 0.5 1.0 1.5 2.0 2.5

INPUT VOLTAGE (V)

GND

LTC2418

241418 TA01a

2414/18 TA01b

241418fa

1

LTC2414/LTC2418

W W U W

(Notes 1, 2)

ABSOLUTE AXI U RATI GS

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (V_CC+ 0.3V)

Reference Input Voltage to GND .. –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

Operating Temperature Range

LTC2414/LTC2418C ................................ 0°C to 70°C

LTC2414/LTC2418I ............................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

U W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

1

2

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

SDI

1

2

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

SDI

28

27

26

25

24

23

22

21

20

19

18

17

16

15

28

27

26

25

24

23

22

21

20

19

18

17

16

15

NC

CH8

CH9

3

CH10

CH11

CH12

CH13

CH14

CH15

4

5

6

7

8

9

V

CC

10

11

12

13

14

F

10

11

12

13

14

F

O

COM

O

+

SCK

SDO

CS

SCK

SDO

CS

REF

–

REF

NC

GND

GN PACKAGE

28-LEAD PLASTIC SSOP

GN PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W

ORDER PART NUMBER

PART MARKING

ORDER PART NUMBER

PART MARKING

LTC2414CGN

LTC2414IGN

LTC2418CGN

LTC2418IGN

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.

241418fa

2

LTC2414/LTC2418

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4)

A

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes) 0.1V ≤ V

≤ V , –0.5 • V

≤ V ≤ 0.5 • V

(Note 5)

●

24

Bits

REF

CC

REF

IN

REF

+

–

Integral Nonlinearity

4.5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V (Note 6)

1

2

5

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

= 2.5V (Note 6)

14

10

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V (Note 6)

INCM

+

–

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

GND ≤ IN = IN ≤ V (Note 14)

2.5

µV

CC

+

–

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

20

nV/°C

ppm of V

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

Negative Full-Scale Error Drift

Total Unadjusted Error

2.5V ≤ REF ≤ V , REF = GND,

●

2.5

12

CC

REF

+

–

+

IN = 0.75 • REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

2.5

ppm of V /°C

REF

CC

+

–

+

IN = 0.75 • REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V

REF

CC

+

–

IN = 0.25 • REF , IN = 0.75 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

ppm of V /°C

REF

CC

+

–

IN = 0.25 • REF , IN = 0.75 • REF

+

–

4.5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V

= 2.5V

3

6

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V

INCM

+

Output Noise

5V ≤ V ≤ 5.5V, REF = 5V, V – = GND,

1

µV

RMS

CC

REF

–

+

GND ≤ IN = IN ≤ 5V (Note 13)

U

CO VERTER CHARACTERISTICS

The

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4)

A

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,

●

130

140

dB

CC

–

+

GND ≤ IN = IN ≤ 5V (Note 5)

+

–

Input Common Mode Rejection

60Hz ±2%

2.5V ≤ REF ≤ V , REF = GND,

140

110

130

dB

CC

–

+

GND ≤ IN = IN ≤ 5V (Notes 5, 7)

+

–

Input Common Mode Rejection

50Hz ±2%

2.5V ≤ REF ≤ V , REF = GND,

CC

–

+

GND ≤ IN = IN ≤ 5V (Notes 5, 8)

Input Normal Mode Rejection

60Hz ±2%

(Notes 5, 7)

140

Input Normal Mode Rejection

(Notes 5, 8)

50Hz ±2%

+

–

Reference Common Mode

Rejection DC

2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,

CC

–

+

V

REF

= 2.5V, IN = IN = GND (Note 5)

+

–

+

Power Supply Rejection, DC

REF = 2.5V, REF = GND, IN = IN = GND

110

120

dB

+

–

+

Power Supply Rejection, 60Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND (Note 7)

+

–

+

Power Supply Rejection, 50Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND (Note 8)

241418fa

3

LTC2414/LTC2418

U

A ALOG I PUT A D REFERE CE

The

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. (Note 3)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

IN

Absolute/Common Mode IN Voltage

●

GND – 0.3

V

+ 0.3

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3

/2

V

Input Differential Voltage Range

– V /2

V

IN

REF

+

–

(IN – IN )

+

–

+

REF

Absolute/Common Mode REF Voltage

●

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1

CC

V

Reference Differential Voltage Range

V

REF

CC

+

–

(REF – REF )

+

C (IN )

IN Sampling Capacitance

18

1

pF

nA

S

–

C (IN )

IN Sampling Capacitance

S

+

C (REF )

REF Sampling Capacitance

S

–

C (REF )

REF Sampling Capacitance

S

+

I

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = GND

●

–10

10

DC_LEAK

CC

–

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = 5V

1

10

CC

+

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = 5V

1

CC

–

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = GND

1

CC

Off Channel to In Channel Isolation

(R = 100Ω)

IN

DC

1Hz

f = 15,3600Hz

S

140

dB

t

I

MUX Break-Before-Make Interval

Channel Off Leakage Current

2.7V ≤ V ≤ 5.5V

70

100

1

300

10

ns

OPEN

CC

Channel at V and GND

●

–10

nA

S(OFF)

CC

U

The

●

denotes specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at T = 25°C. (Note 3)

A

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

IH

V

IL

V

IH

V

IL

High Level Input Voltage

●

2.5

2.0

V

CC

CS, F , SDI

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

CS, F , SDI

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 9)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 9)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 9)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 9)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F , SDI

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 9)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F , SDI

O

Digital Input Capacitance

SCK

(Note 9)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5

CC

OH

241418fa

4

LTC2414/LTC2418

U

The

●

denotes specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at T = 25°C. (Note 3)

A

SYMBOL

PARAMETER

CONDITIONS

I = 1.6mA

MIN

TYP

MAX

UNITS

V

OL

V

OH

V

OL

Low Level Output Voltage

SDO

●

0.4

V

O

High Level Output Voltage

SCK

I = –800µA (Note 10)

O

V

– 0.5

V

CC

Low Level Output Voltage

SCK

I = 1.6mA (Note 10)

O

0.4

10

I

Hi-Z Output Leakage

SDO

–10

µA

OZ

W U

POWER REQUIRE E TS

The

otherwise specifications are at T = 25°C. (Note 3)

●

denotes specifications which apply over the full operating temperature range,

A

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

2.7

5.5

V

CC

I

CC

Conversion Mode

Sleep Mode

CS = 0V (Note 12)

●

200

4

2

300

10

µA

CS = V (Note 12)

CC

CS = V , 2.7V ≤ V ≤ 3.3V (Note 12)

CC

W U

TI I G CHARACTERISTICS ^The

●

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 3)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.25

TYP

MAX

2000

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

390

µs

LEO

F = 0V

●

130.86

157.03

133.53

160.23

EOSC

136.20

163.44

(in kHz)

ms

CONV

O

F = V

O

CC

External Oscillator (Note 11)

20510/f

f

Internal SCK Frequency

Internal Oscillator (Note 10)

External Oscillator (Notes 10, 11)

19.2

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 10)

(Note 9)

●

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

External SCK High Period

2000

ESCK

250

1.64

LESCK

ns

HESCK

DOUT_ISCK

Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12)

External Oscillator (Notes 10, 11)

●

1.67

1.70

ms

256/f

(in kHz)

EOSC

t

External SCK 32-Bit Data Output Time (Note 9)

●

32/f

(in kHz)

ms

DOUT_ESCK

ESCK

241418fa

5

LTC2414/LTC2418

W U

TI I G CHARACTERISTICS ^The

●

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 3)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

200

UNITS

ns

t

CS ↓ to SDO Low

CS ↑ to SDO High Z

CS ↓ to SCK ↓

●

1

t2

t3

t4

0

ns

(Note 10)

(Note 9)

0

ns

CS ↓ to SCK ↑

50

ns

t

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

SDI Setup Before SCK↑

SDI Hold After SCK↑

220

50

ns

KQMAX

KQMIN

(Note 5)

15

50

ns

t

ns

5

6

ns

t

(Note 5)

100

ns

7

8

t

ns

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 8: F_O= V_CC(internal oscillator) or f_EOSC= 128000Hz ±2%

(external oscillator).

Note 2: All voltage values are with respect to GND.

Note 9: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output. In this mode of operation the

SCK pin has a total equivalent load capacitance C_LOAD= 20pF.

Note 3: V_CC= 2.7V to 5.5V unless otherwise specified.

V_REF= REF⁺– REF^–, V_REFCM= (REF⁺+ REF^–)/2; V_IN= IN⁺– IN^–,

V

_INCM= (IN⁺+ IN^–)/2, IN⁺and IN^–are defined as the selected positive

and negative input respectively.

Note 4: F_Opin tied to GND or to V_CCor to external conversion clock

source with f_EOSC= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 11: The external oscillator is connected to the F_Opin. The external

oscillator frequency, f_EOSC, is expressed in kHz.

Note 12: The converter uses the internal oscillator.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer

curve. The deviation is measured from the center of the quantization

band.

F_O= 0V or F_O= V_CC

.

Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 7: F_O= 0V (internal oscillator) or f_EOSC= 153600Hz ± 2%

(external oscillator).

Note 14: Guaranteed by design and test correlation.

241418fa

6

LTC2414/LTC2418

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error

(V = 5V, V

= 5V)

(V = 2.7V, V

= 2.5V)

(V = 5V, V

= 2.5V)

CC

REF

CC

REF

CC

REF

8

6

3

2

3

2

F

= GND

= 2.7V

F

= GND

= 5V

F

= GND

= 5V

CC

O

CC

O

CC

O

T

= –45°C

A

V

= 2.5V

= V

= 5V

= V

= 2.5V

= V = 1.25V

REFCM

REF

INCM

REF

INCM

= 1.25V

REFCM

= 2.5V

INCM

REFCM

4

1

T

= 25°C

2

A

T

A

= 25°C

0

T = 85°C

A

T

= 85°C

A

T

= –45°C

A

–2

–4

–6

–8

–1

–2

–3

T

= 85°C

–1

–2

–3

T

= 25°C

A

T

= –45°C

A

–1.25

–0.75

–0.25

0.25

0.75

1.25

–2.5 –2.0–1.5–1.0 –0.5

0

0.5 1.0 1.5 2.0 2.5

–1.25

–0.75

–0.25

0.25

0.75

1.25

INPUT VOLTAGE (V)

241418 G03

241418 G01

241418 G02

Integral Nonlinearity

CC

Integral Nonlinearity

(V = 5V, V

= 2.5V)

(V = 2.7V, V

= 2.5V)

REF

(V = 5V, V

= 5V)

CC

REF

CC

REF

8

6

3

2

3

2

F

= GND

= 5V

F

= GND

= 2.7V

CC

REF

F

= GND

= 5V

O

CC

O

CC

V

T

= –45°C

= 2.5V

= V

= 2.5V

= V = 1.25V

REFCM

= 5V

= V

A

REF

= 1.25V

= 2.5V

REFCM

INCM

REFCM

INCM

4

T

= –45°C

A

1

T = 25°C

A

T

A

= 85°C

2

T

A

= 25°C

0

–2

–4

–6

–8

T

= 25°C

T

= 85°C

A

–1

–2

–3

–1

–2

–3

T

= –45°C

T

= 85°C

A

–1.25 –0.75

–0.25

0.25

0.75

1.25

–1.25

–0.75

–0.25

0.25

0.75

1.25

–2.5 –2.0–1.5–1.0 –0.5

0 0.5 1.0 1.5 2.0 2.5

INPUT VOLTAGE (V)

241418 G05

241418 G06

241418 G04

Noise Histogram

(V = 5V, V = 5V)

Noise Histogram

(V = 2.7V, V

Long Term ADC Readings

RMS NOISE = 0.19ppm

= 2.5V)

REF

CC

REF

CC

14

12

10

8

30

25

20

15

10

5

1.0

0.5

10,000 CONSECUTIVE READINGS

F

= GND

= 25°C

= 5V

V

= 5V

F

= GND

= 25°C

= 2.7V

F

= GND

= 25°C

= 5V

O

A

REF

O

A

CC

O

A

CC

T

= 0V

T

IN

INCM

V

CC

= 2.5V

V

GAUSSIAN

= 2.5V

= 5V

DISTRIBUTION

m = –0.48ppm

σ = 0.375ppm

REF

DISTRIBUTION

m = –0.24ppm

σ = 0.183ppm

REF

= 0V

IN

INCM

= 2.5V

0

= 2.5V

INCM

6

–0.5

–1.0

–1.5

4

2

0

–1.2

–0.6

0

0.6

–2.4

–1.2 –0.6

0

0.6

)

1.2

0

20

30

40

50

60

–1.8

10

OUTPUT CODE (ppm OF V

)

TIME (HOURS)

REF

241418 G08

241418 G07

LTXXXX • TPCXX

241418fa

7

LTC2414/LTC2418

U W

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Input Differential

Voltage

RMS Noise vs Temperature (T )

RMS Noise vs V

A

INCM

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

F

= GND

O

A

T

= 25°C

V

= 5V

CC

= 5V

REF

= 2.5V

INCM

F

= GND

O

A

T

= 25°C

F

= GND

O

V

= 5V

CC

+

V

= 5V

CC

REF

IN

INCM

REF = 5V

–

= 5V

REF = GND

= 0V

V

= 0V

IN

INCM

= GND

3

(V)

4

6

–50 –25

0

25

50

75 100

–2.5 –2.0–1.5–1.0 –0.5

INPUT DIFFERENTIAL VOLTAGE (V)

0

0.5 1.0 1.5 2.0 2.5

–1

0

1

2

5

TEMPERATURE (°C)

V

INCM

241418 G12

241418 G10

241418 G11

Offset Error vs V

RMS Noise vs V

INCM

CC

REF

1.0

0.9

0.8

0.7

0.6

0.5

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

1.0

0.9

0.8

0.7

0.6

0.5

F

= GND

F

= GND

= 25°C

= 0V

O

A

O

A

IN

F

= GND

O

A

T

= 25°C

T

= 25°C

V

= 5V

V

CC

V

= 5V

CC

+

REF = 5V

= GND

INCM

= 0V

IN

INCM

–

+

REF = GND

REF = 2.5V

REF = GND

= GND

–

V

= 0V

5

IN

REF = GND

–1

1

2

3

4

6

2.7

3.5 3.9 4.3

4.7 5.1 5.5

3.1

0

1

2

3

4

5

V

(V)

V

(V)

INCM

CC

V

(V)

REF

241418 G13

241418 G15

241418 G14

Offset Error vs V

Offset Error vs Temperature

Offset Error vs V

REF

CC

1.0

0.8

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

1.0

0.8

F

= GND

O

A

F

= GND

F

= GND

O

T

= 25°C

V

= 5V

T

= 25°C

CC

REF

IN

INCM

A

CC

IN

V

= 0V

IN

INCM

= 5V

V

= 5V

= 0V

0.6

= GND

= 0V

+

REF = 2.5V

REF = GND

0.4

= GND

0.4

INCM

–

REF = GND

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

2.7

3.5 3.9 4.3

(V)

4.7 5.1 5.5

3.1

0

1

2

3

4

5

–45 –30 –15

0

15 30 45 60 75 90

V

TEMPERATURE (°C)

CC

V

(V)

REF

241418 G16

241418 G17

241418 G18

241418fa

8

LTC2414/LTC2418

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Full-Scale Error vs V

Full-Scale Error vs Temperature

Full-Scale Error vs V

REF

CC

5

4

3

5

4

5

4

3

2

1

0

F

= GND

O

V

= 5V

CC

REF

= 5V

= 2.5V

3

INCM

+FS ERROR

2

+FS ERROR

F

= GND

O

A

1

T

= 25°C

V

= 2.5V

= 0.5V

REF

0

INCM

REF

–

–1

–2

–3

–4

–5

–1 REF = GND

–FS ERROR

–2

–3

–4

–5

F

= GND

O

–FS ERROR

T

= 25°C

A

CC

INCM

–3

–4

–5

V

= 5V

= 0.5V

REF

–

REF = GND

0

–60

20

TEMPERATURE (°C)

60 80

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

–40 –20

0

40

100

2.7

3.1

3.5 3.9 4.3

(V)

4.7 5.1 5.5

V

REF

CC

241418 G21

241418 G19

241418 G20

PSRR vs Frequency at V

CC

0

–20

0

–20

F

= GND

F

= GND

= 25°C

= 4.1V

F

= GND

O

A

O

A

CC

O

A

T

= 25°C

T

= 25°C

–20

–40

V

= 4.1V ± 0.7V

V

= 4.1V ±1.4V

CC

DC

P-P

DC

CC

DC

+

REF = 2.5V

–

–40

REF = GND

+

–

+

–

+

–

IN = GND

–60

SDI = GND

–80

–100

–120

–140

–100

–120

–140

–100

–120

–140

15250

15300

FREQUENCY AT V (Hz)

15350

15400

15450

1

100 1000 10000 100000 1000000

FREQUENCY AT V (Hz)

0

30 60 90 120 150 180 210 240

FREQUENCY AT V (Hz)

10

CC

241418 G24

241418 G22

241418 G23

Sleep Mode Current

vs Temperature

Conversion Current

Supply Current at Elevated

vs Temperature

Output Rates (F Over Driven)

O

1000

900

800

700

600

500

400

300

200

100

6

5

4

3

2

1

0

240

230

220

210

200

190

180

170

160

CS = V

O

SCK = NC

SDO = NC

SDI = GND

CS = GND

CC

= GND

V

= 5.5V

CC

F

= EXT OSC

O

+

IN = GND

–

IN = GND

V

CC

= 5.5V

V

= 5V

CC

V

= 5V

CC

SCK = NC

SDO = NC

SDI = GND

CS = GND

T

= 25°C

A

= 5V

CC

F

= GND

O

V

= V

CC

REF

SCK = NC

SDO = NC

SDI = GND

V

= 3V

CC

V

= 3V

V

CC

= 3V

CC

V

= 2.7V

CC

V

= 2.7V

CC

40

15 30

0

TEMPERATURE (°C)

0

10 20 30

50 60 70 80 90 100

–45 –30 –15

45 60 75 90

15 30

0

TEMPERATURE (°C)

–45 –30 –15

45 60 75 90

OUTPUT DATA RATE (READINGS/SEC)

241418 G26

241418 G27

241418 G25

241418fa

9

LTC2414/LTC2418

U

PI FU CTIO S

CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog

Inputs. May be programmed for single-ended or differen-

tial mode. CH8 to CH15 (Pin 1 to Pin 8) not connected on

the LTC2414.

is in a high impedance state. During the Conversion and

Sleep periods, this pin is used as the conversion status

output. The conversion status can be observed by pulling

CS LOW.

V_CC(Pin 9): Positive Supply Voltage. Bypass to GND

(Pin 15) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as the digital

outputfortheinternalserialinterfaceclockduringtheData

Output period. In External Serial Clock Operation mode,

SCK is used as the digital input for the external serial

interface clock during the Data Output period. A weak

internal pull-up is automatically activated in Internal Serial

ClockOperationmode.TheSerialClockOperationmodeis

determined by the logic level applied to the SCK pin at

power up or during the most recent falling edge of CS.

COM (Pin 10): The common negative input (IN^–) for all

single-ended multiplexer configurations. The voltage on

Channel 0 to 15 and COM input pins can have any value

between GND – 0.3V and V_CC+ 0.3V. Within these limits,

the two selected inputs (IN⁺and IN^–) provide a bipolar

inputrange(V_IN=IN⁺–IN^–)from–0.5•V_REFto0.5•V_REF

.

Outside this input range, the converter produces unique

overrange and underrange output codes.

F_O(Pin 19): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to V_CC(F_O= V_CC), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the F_Opin is connected

to GND (F_O= 0V), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When F_O

REF⁺(Pin 11), REF^–(Pin 12): Differential Reference

Input. The voltage on these pins can have any value

between GND and V_CCas long as the positive reference

input, REF⁺, is maintained more positive than the negative

reference input, REF ^–, by at least 0.1V.

GND (Pin 15): Ground. Connect this pin to a ground plane

through a low impedance connection.

isdrivenbyanexternalclocksignalwithafrequencyf_EOSC

,

theconvertersusethissignalastheirsystemclockandthe

digital filter first null is located at a frequency f_EOSC/2560.

CS (Pin 16): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

SDI (Pin 20): Serial Digital Data Input. During the Data

Output period, this pin is used to shift in the multiplexer

address started from the first rising SCK edge. During the

Conversion and Sleep periods, this pin is in the DON’T

CAREstate. However, aHIGHorLOWlogiclevelshouldbe

maintained on SDI in the DON’T CARE mode to avoid an

excessive current in the SDI input buffers.

SDO (Pin 17): Three-State Digital Output. During the Data

Output period, this pin is used as the serial data output.

When the chip select CS is HIGH (CS = V_CC), the SDO pin

NC Pins: Do Not Connect.

241418fa

10

LTC2414/LTC2418

U

W

FU CTIO AL BLOCK DIAGRA

INTERNAL

OSCILLATOR

V

CC

GND

F

AUTOCALIBRATION

AND CONTROL

O

(INT/EXT)

+

–

REF

CH0

CH1

+

–

+

–

IN

DIFFERENTIAL

3RD ORDER

∆Σ MODULATOR

SDI

•

MUX

SCK

SDO

CS

SERIAL

INTERFACE

CH15

COM

DECIMATING FIR

ADDRESS

241418 F01

Figure 1

TEST CIRCUITS

V

CC

1.69k

C

SDO

= 20pF

1.69k

C

LOAD

= 20pF

LOAD

241418 TA03

241418 TA02

Hi-Z TO V

OL

OH

V

TO V

V

OL

V

OH

TO V

OH

OL

TO Hi-Z

W U U

U

APPLICATIO S I FOR ATIO

CS is HIGH. While in the sleep state, power consumption

is reduced by nearly two orders of magnitude. The conver-

sion result is held indefinitely in a static shift register while

the converter is in the sleep state.

CONVERTER OPERATION

Converter Operation Cycle

TheLTC2414/LTC2418aremultichannel,lowpower,delta-

sigma analog-to-digital converters with an easy-to-use

4-wireserialinterface(seeFigure1).Theiroperationismade

upofthreestates.Theconverteroperatingcyclebeginswith

the conversion, followed by the low power sleep state and

ends with the data input/output (see Figure 2). The 4-wire

interface consists of serial data input (SDI), serial data out-

put (SDO), serial clock (SCK) and chip select (CS).

Once CS is pulled LOW, the device exits the low power

mode and enters the data output state. If CS is pulled HIGH

beforethefirstrisingedgeofSCK, thedevicereturnstothe

low power sleep mode and the conversion result is still

held in the internal static shift register. If CS remains LOW

after the first rising edge of SCK, the device begins output-

ting the conversion result and inputting channel selection

bits. Taking CS high at this point will terminate the data

output state and start a new conversion. The channel

selection control bits are shifted in through SDI from the

241418fa

Initially, the LTC2414 or LTC2418 performs a conversion.

Once the conversion is complete, the device enters the

sleep state. The part remains in the sleep state as long as

11

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

systemclock.TheLTC2414/LTC2418incorporateahighly

accurate on-chip oscillator. This eliminates the need for

externalfrequencysettingcomponentssuchascrystalsor

oscillators.Clockedbytheon-chiposcillator,theLTC2414/

LTC2418achieveaminimumof110dBrejectionattheline

frequency (50Hz or 60Hz ±2%).

POWER UP

+

–

IN = CH0, IN = CH1

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

Ease of Use

The LTC2414/LTC2418 data output has no latency, filter

settling delay or redundant data associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog voltages is easy.

TRUE

DATA OUTPUT

ADDRESS INPUT

241418 F02

Figure 2. LTC2414/LTC2418 State Transition Diagram

The LTC2414/LTC2418 perform offset and full-scale cali-

brationsineveryconversioncycle.Thiscalibrationistrans-

parent to the user and has no effect on the cyclic operation

described above. The advantage of continuous calibration

isextremestabilityofoffsetandfull-scalereadingswithre-

specttotime,supplyvoltagechangeandtemperaturedrift.

first rising edge of SCK and depending on the control bits,

the converter updates its channel selection immediately

and is valid for the next conversion. The details of channel

selectioncontrolbitsaredescribedintheInputDataMode

section. The output data is shifted out the SDO pin under

the control of the serial clock (SCK). The output data is

updated on the falling edge of SCK allowing the user to

reliably latch data on the rising edge of SCK (see Figure 3).

The data output state is concluded once 32 bits are read

out of the ADC or when CS is brought HIGH. The device

automatically initiates a new conversion and the cycle

repeats.

Power-Up Sequence

The LTC2414/LTC2418 automatically enter an internal

reset state when the power supply voltage V_CCdrops

below approximately 2V. This feature guarantees the

integrity of the conversion result and of the serial interface

mode selection. (See the 3-wire I/O sections in the Serial

Interface Timing Modes section.)

Through timing control of the CS and SCK pins, the

LTC2414/LTC2418 offer several flexible modes of opera-

tion (internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turbthecyclicoperationdescribedabove. Thesemodesof

operation are described in detail in the Serial Interface

Timing Modes section.

When the V_CCvoltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a typical duration of 1ms. The POR signal

clears all internal registers. Following the POR signal, the

LTC2414/LTC2418 start a normal conversion cycle and

follow the succession of states described above. The first

conversion result following POR is accurate within the

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or

Reference Voltage Range

The LTC2414/LTC2418 accept a truly differential external

reference voltage. The absolute/common mode voltage

241418fa

12

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

specification for the REF⁺and REF^–pins covers the entire

range from GND to V_CC. For correct converter operation,

the REF⁺pin must always be more positive than the REF^–

pin.

current will develop a 1ppm offset error on a 5k resistor if

V_REF= 5V. This error has a very strong temperature

dependency.

Input Data Format

The LTC2414/LTC2418 can accept a differential reference

voltage from 0.1V to V_CC. The converter output noise is

determined by the thermal noise of the front-end circuits,

and, as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

significantly improve the converter’s effective resolution.

On the other hand, a reduced reference voltage will im-

prove the converter’s overall INL performance. A reduced

reference voltage will also improve the converter perfor-

mance when operated with an external conversion clock

(externalF_Osignal)atsubstantiallyhigheroutputdatarates.

When the LTC2414/LTC2418 are powered up, the default

selectionusedforthefirstconversionisIN⁺=CH0andIN^–

= CH1 (Address = 00000). In the data input/output mode

following the first conversion, a channel selection can be

updated using an 8-bit word. The LTC2414/LTC2418

serial input data is clocked into the SDI pin on the rising

edge of SCK (see Figure 3). The input is composed of an

8-bitwordwiththefirst3bitsactingascontrolbitsandthe

remaining 5 bits as the channel address bits.

The first 2 bits are always 10 for proper updating opera-

tion. The third bit is EN. For EN = 1, the following 5 bits are

used to update the input channel selection. For EN = 0,

previous channel selection is kept and the following bits

are ignored. Therefore, the address is updated when the 3

control bits are 101 and kept for 100. Alternatively, the 3

control bits can be all zero to keep the previous address.

This alternation is intended to simplify the SDI interface

allowing the user to simply connect SDI to ground if no

update is needed. Combinations other than 101, 100 and

000 of the 3 control bits should be avoided.

Input Voltage Range

The two selected pins are labeled IN⁺and IN^–(see Tables

1 and 2). Once selected (either differential or single-ended

multiplexing mode), the analog input is differential with a

common mode range for the IN⁺and IN^–input pins ex-

tending from GND – 0.3V to V_CC+ 0.3V. Outside

these limits, the ESD protection devices begin to turn on

and the errors due to input leakage current increase rap-

idly. Within these limits, the LTC2414/LTC2418 convert

the bipolar differential input signal, V_IN= IN⁺– IN^–, from

When update operation is set (101), the following 5 bits

are the channel address. The first bit, SGL, decides if the

differential selection mode (SGL = 0) or the single-ended

selection mode is used (SGL = 1). For SGL = 0, two

adjacent channels can be selected to form a differential

input;forSGL=1, oneofthe8channels(CH0-CH7)forthe

LTC2414 or one of the 16 channels (CH0-CH15) for the

LTC2418 is selected as the positive input and the COM pin

is used as the negative input. For the LTC2414, the lower

half channels (CH0-CH7) are used and the channel ad-

dress bit A2 should be always 0, see Table 1. While for the

LTC2418, all the 16 channels are used and the size of the

corresponding selection table (Table 2) is doubled from

that of the LTC2414 (Table 1). For a given channel selec-

tion, the converter will measure the voltage between the

two channels indicated by IN⁺and IN^–in the selected row

of Tables 1 or 2.

–FS = –0.5 • V_REFto +FS = 0.5 • V_REFwhere V_REF

=

REF⁺– REF^–. Outside this range the converters indicate

the overrange or the underrange condition using distinct

output codes.

Input signals applied to IN⁺and IN^–pins may extend

300mV below ground or above V_CC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN⁺or IN^–pins without affecting the performance

of the device. In the physical layout, it is important to

maintain the parasitic capacitance of the connection be-

tween these series resistors and the corresponding pins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. In addition, series

resistors will introduce a temperature dependent offset

error due to the input leakage current. A 1nA input leakage

241418fa

13

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

CS

BIT31

EOC

BIT30

DMY

BIT29

SIG

BIT28 BIT27 BIT26 BIT25

BIT24

BIT6

LSB

BIT5

SGL

BIT4

BIT3

A2

BIT2

A1

BIT1

A0

BIT0

ODD/

SIGN

SDO

SCK

SDI

MSB

B22

PARITY

Hi-Z

CONVERSON RESULT

ADDRESS CORRESPONDING TO RESULT

ODD/

SIGN

1

0

EN

SGL

A2

A1

A0

DON’T CARE

CONVERSION

SLEEP

DATA INPUT/OUTPUT

241418 F03a

Figure 3a. Input/Output Data Timing

CONVERSION RESULT

N – 1

CONVERSION RESULT

N

CONVERSION RESULT

N + 1

SDO

Hi-Z

ADDRESS

N – 1

ADDRESS

N

ADDRESS

N + 1

SCK

SDI

DON’T CARE

ADDRESS

N

ADDRESS

N + 1

ADDRESS

N + 2

OUTPUT

N

OUTPUT

N – 1

OUTPUT

N + 1

OPERATION

CONVERSION N

CONVERSION N + 1

241418 F03b

Figure 3b. Typical Operation Sequence

Table 1. Channel Selection for the LTC2414 (Bit A2 Should Always Be 0)

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL

0

SIGN A2 A1 A0

0

1

2

3

4

5

6

IN

7

COM

+

–

+

–

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IN

+

–

+

–

0

IN

+

–

+

–

0

IN

+

–

+

–

0

IN

+

0

IN

+

0

IN

+

0

IN

+

0

IN

–

1

IN

–

1

IN

–

1

IN

–

1

IN

+

–

1

IN

+

–

1

IN

+

–

1

IN

+

–

1

IN

*Default at power up

241418fa

14

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

Table 2. Channel Selection for the LTC2418

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL SIGN

A2 A1 A0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 COM

+

–

+

–

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

IN

+

IN

+

IN

+

IN

+

IN

–

+

IN

–

+

IN

–

+

IN

–

IN

–

IN

–

IN

–

IN

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

*Default at power up

Output Data Format

indicatewhichchanneltheconversionjustperformedwas

selected. The address bits programmed during this data

output phase select the input channel for the next conver-

sion cycle. These address bits are output during the sub-

sequent data read, as shown in Figure 3b. The last bit is a

241418fa

TheLTC2414/LTC2418serialoutputdatastreamis32bits

long. The first 3 bits represent status information indicat-

ing the sign and conversion state. The next 23 bits are the

conversion result, MSB first. The next 5 bits (Bit 5 to Bit 1)

15

LTC2414/LTC2418

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U

APPLICATIO S I FOR ATIO

paritybitrepresentingtheparityoftheprevious31bits.The

parity bit is useful to check the output data integrity espe-

cially when the output data is transmitted over a distance.

The third and fourth bits together are also used to indicate

anunderrangecondition(thedifferentialinputvoltageisbe-

low –FS) or an overrange condition (the differential input

voltage is above +FS).

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

register.

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 31 (EOC) can be captured on the first rising

edge of SCK. Bit 30 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 31st SCK and may be latched on

the rising edge of the 32nd SCK pulse. On the falling edge

of the 32nd SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 4 summarizes

the output data format.

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 29 also

provides the underrange or overrange indication. If both

Bit 29 and Bit 28 are HIGH, the differential input voltage is

above +FS. If both Bit 29 and Bit 28 are LOW, the

differential input voltage is below –FS.

As long as the voltage applied to any channel (CH0-CH15,

COM) is maintained within the –0.3V to (V_CC+ 0.3V)

absolutemaximumoperatingrange, aconversionresultis

generated for any differential input voltage V_INfrom

–FS = –0.5 • V_REFto+FS = 0.5 • V_REF. For differential input

voltagesgreaterthan+FS,theconversionresultisclamped

to the value corresponding to the +FS + 1LSB. For differ-

ential input voltages below –FS, the conversion result is

clamped to the value corresponding to –FS – 1LSB.

The function of these bits is summarized in Table 3.

Table 3. LTC2414/LTC2418 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

Input Range

EOC

DMY

SIG

MSB

V

≥ 0.5 • V

0

1

0

1

0

IN

REF

Frequency Rejection Selection (F_O)

0V ≤ V < 0.5 • V

0

1

IN

REF

The LTC2414/LTC2418 internal oscillator provides better

than 110dB normal mode rejection at the line frequency

and all its harmonics for 50Hz ±2% or 60Hz ±2%. For

60Hz rejection, F_Oshould be connected to GND while for

50Hz rejection the F_Opin should be connected to V_CC.

–0.5 • V ≤ V < 0V

0

REF

IN

V

< –0.5 • V

0

IN

REF

Bits 28-6 are the 23-bit conversion result MSB first.

Bit 6 is the least significant bit (LSB).

The selection of 50Hz or 60Hz rejection can also be made

by driving F_Oto an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

Bits 5-1 are the corresponding channel selection bits for

the present conversion result with bit SGL output first as

shown in Figure 3.

Bit 0 is the parity bit representing the parity of the previous

31 bits. Including the parity bit, the total numbers of 1’s

and 0’s in the output data are always even.

241418fa

16

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

Table 4. LTC2414/LTC2418 Output Data Format

Differential Input Voltage

V *

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bit 27

Bit 26

Bit 25

…

Bit 6

LSB

IN

V * ≥ 0.5 • V **

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

…

0

1

0

1

0

1

0

1

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

REF

0.25 • V ** – 1LSB

REF

0

–1LSB

–0.25 • V **

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

REF

V * < –0.5 • V **

0

IN

REF

+

–

*The differential input voltage V = IN – IN .

IN

+

–

**The differential reference voltage V = REF – REF .

REF

–80

–85

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2414/

LTC2418 can operate with an external conversion clock.

The converter automatically detects the presence of an

external clock signal at the F_Opin and turns off the internal

oscillator. The frequency f_EOSCof the external signal must

be at least 2560Hz (1Hz notch frequency) to be detected.

The external clock signal duty cycle is not significant as

long as the minimum and maximum specifications for the

high and low periods t_HEOand t_LEOare observed.

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–12

–8

–4

0

4

8

12

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f /2560(%)

EOSC

241418 F04

While operating with an external conversion clock of a

frequencyf_EOSC, theconverterprovidesbetterthan110dB

normal mode rejection in a frequency range f_EOSC/2560

±4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from f_EOSC/2560

is shown in Figure 4.

Figure 4. LTC2414/LTC2418 Normal Mode Rejection

When Using an External Oscillator of Frequency f

EOSC

serial clock duty cycle may be affected but the serial data

stream will remain valid.

WheneveranexternalclockisnotpresentattheF_Opin, the

converterautomaticallyactivatesitsinternaloscillatorand

enters the Internal Conversion Clock mode. The converter

operation will not be disturbed if the change of conversion

clock source occurs during the sleep state or during the

data output state while the converter uses an external

serial clock. If the change occurs during the conversion

state, the result of the conversion in progress may be

outside specifications but the following conversions will

notbeaffected.Ifthechangeoccursduringthedataoutput

state and the converter is in the Internal SCK mode, the

Table 5 summarizes the duration of each state and the

achievable output data rate as a function of F_O.

SERIAL INTERFACE PINS

The LTC2414/LTC2418 transmit the conversion results

and receive the start of conversion command through a

synchronous 4-wire interface. During the conversion and

sleep states, this interface can be used to assess the con-

verter status and during the data I/O state it is used to read

the conversion result and write in channel selection bits.

241418fa

17

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

Table 5. LTC2414/LTC2418 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

(60Hz Rejection)

133ms, Output Data Rate ≤ 7.5 Readings/s

O

F = HIGH

(50Hz Rejection)

160ms, Output Data Rate ≤ 6.2 Readings/s

O

External Oscillator

F = External Oscillator

20510/f

s, Output Data Rate ≤ f

/20510 Readings/s

O

EOSC

with Frequency f

kHz

EOSC

(f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock

F = LOW/HIGH

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.67ms

(32 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

(32 SCK cycles)

ms

EOSC

O

Frequency f

kHz

EOSC

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/f ms

(32 SCK cycles)

SCK

Frequency f

kHz

SCK

Serial Clock Input/Output (SCK)

Serial Data Output (SDO)

The serial clock signal present on SCK (Pin 18) is used to

synchronizethedatatransfer.Eachbitofdataisshiftedout

the SDO pin on the falling edge of the serial clock and each

input bit is shifted in the SDI pin on the rising edge of the

serial clock.

The serial data output pin, SDO (Pin 17), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2414/LTC2418 create their own serial

clock by dividing the internal conversion clock by 8. In the

External SCK mode of operation, the SCK pin is used as

input. The internal or external SCK mode is selected on

power-up and then reselected every time a HIGH-to-LOW

transition is detected at the CS pin. If SCK is HIGH or float-

ing at power-up or during this transition, the converter

enters the internal SCK mode. If SCK is LOW at power-up

or during this transition, the converter enters the external

SCK mode.

When CS (Pin 16) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase, theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 16), is used to test the

conversion status and to enable the data input/output

transfer as described in the previous sections.

Serial Data Input (SDI)

Theserialdatainputpin,SDI(Pin20),isusedtoshiftinthe

channelcontrolbitsduringthedataoutputstatetoprepare

the channel selection for the following conversion.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2414/LTC2418 will abort any

serial data transfer in progress and start a new conversion

cycle anytime a LOW-to-HIGH transition is detected at the

CS pin after the converter has entered the data input/

output state (i.e., after the first rising edge of SCK occurs

When CS (Pin 16) is HIGH or the converter is in the con-

version state, the SDI input is ignored and may be driven

HIGH or LOW. When CS goes LOW and the conversion is

complete, SDO goes low and then SDI starts to shift in bits

on the rising edge of SCK.

with CS = LOW). If the device has not finished loading the

241418fa

18

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

last input bit A0 of SDI by the time CS pulled HIGH, the

address information is discarded and the previous

address is kept.

nal serial clock, 3- or 4-wire I/O, single cycle conversion.

The following sections describe each of these serial inter-

face timing modes in detail. In all these cases, the con-

verter can use the internal oscillator (F_O= LOW or F_O=

HIGH) or an external oscillator connected to the F_Opin.

Refer to Table 6 for a summary.

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by F_O.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

SERIAL INTERFACE TIMING MODES

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

The LTC2414/LTC2418’s 4-wire interface is SPI and

MICROWIRE compatible. This interface offers several

flexible modes of operation. These include internal/exter-

Table 6. LTC2414/LTC2418 Interface Timing Modes

SCK

Conversion

Cycle

Control

Data

Output

Control

Connection

and

Waveforms

Configuration

Source

External

Internal

External SCK, Single Cycle Conversion

External SCK, 3-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 5, 6

Figure 7

Internal SCK, Single Cycle Conversion

Internal SCK, 3-Wire I/O, Continuous Conversion

CS ↓

Figures 8, 9

Figure 10

Continuous

Internal

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

+

11

20

18

REFERENCE

VOLTAGE

0.1V TO V

REF

SDI

12

21

28

1

–

SCK

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

TEST EOC

(OPTIONAL)

CH15

COM

15

10

GND

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 6

LSB

BIT 0

PARITY

SDO

Hi-Z

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

DATA OUTPUT

A0

CONVERSION

241418 F05

SLEEP

Figure 5. External Serial Clock, Single Cycle Operation

241418fa

19

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

The serial clock mode is selected on the falling edge of CS.

Toselecttheexternalserialclockmode,theserialclockpin

(SCK) must be LOW during each CS falling edge.

and the last bit of the conversion result can be latched on

the 32nd rising edge of SCK. On the 32nd falling edge of

SCK, thedevicebeginsanewconversion. SDOgoesHIGH

(EOC = 1) indicating a conversion is in progress.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the device is in the sleep state. Independent of CS, the

deviceautomaticallyentersthelowpowersleepstateonce

the conversion is complete.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CSHIGHanytimebetweenthefirstrisingedgeandthe32nd

falling edge of SCK, see Figure 6. On the rising edge of CS,

the device aborts the data output state and immediately

initiates a new conversion. If the device has not finished

loading the last input bit A0 of SDI by the time CS is pulled

HIGH, the address information is discarded and the previ-

ous address is kept. This is useful for systems not requir-

ingall32bitsofoutputdata,abortinganinvalidconversion

cycle or synchronizing the start of a conversion.

Whenthedeviceisinthesleepstate,itsconversionresult

is held in an internal static shift register. The device

remainsinthesleepstateuntilthefirstrisingedgeofSCK

is seen while CS is LOW. The input data is then shifted in

via the SDI pin on the rising edge of SCK (including the

first rising edge) and the output data is shifted out of the

SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

11

12

21

28

1

20

18

+

REFERENCE

VOLTAGE

REF

SDI

–

SCK

0.1V TO V

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

SDO

CS

16

ANALOG

INPUTS

CH8

•

8

CH15

TEST EOC

(OPTIONAL)

15

10

COM

GND

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 9

BIT 8

SDO

Hi-Z

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

SLEEP

DATA OUTPUT

CONVERSION

241418 F06

DATA

OUTPUT

SLEEP

Figure 6. External Serial Clock, Reduced Data Output Length

241418fa

20

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

External Serial Clock, 3-Wire I/O

each falling edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 32nd falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun.

This timing mode utilizes a 3-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

typically 1ms after V_CCexceeds approximately 2V. The

level applied to SCK at this time determines if SCK is

internal or external. SCK must be driven LOW prior to the

endofPORinordertoentertheexternalserialclocktiming

mode.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion ends. On the falling edge of

EOC, the conversion result is loaded into an internal static

shift register. The input data is then shifted in via the SDI

pin on the rising edge of SCK (including the first rising

edge) and the output data is shifted out of the SDO pin on

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

+

11

20

18

REFERENCE

VOLTAGE

REF

SDI

12

21

28

1

–

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

CH15

COM

15

10

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 6

LSB

BIT 0

SDO

PARITY

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

DATA OUTPUT

A0

CONVERSION

241418 F07

Figure 7. External Serial Clock, CS = 0 Operation

241418fa

21

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

V

CC

11

20

18

+

REFERENCE

VOLTAGE

0.1V TO V

10k

REF

SDI

12

21

28

1

–

SCK

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

CH15

15

10

COM

GND

TEST EOC

<t

EOCtest

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 6

LSB

BIT 0

SDO

PARITY

Hi-Z

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

DATA OUTPUT

CONVERSION

241418 F08

SLEEP

Figure 8. Internal Serial Clock, Single Cycle Operation

used to shift the conversion result into external circuitry.

EOC can be latched on the first rising edge of SCK and the

last bit of the conversion result on the 32nd rising edge of

SCK. After the 32nd rising edge, SDO goes HIGH (EOC =

1), SCK stays HIGH and a new conversion starts.

WhentestingEOC,iftheconversioniscomplete(EOC= 0),

the device will exit the low power mode during the EOC

test. In order to allow the device to return to the low power

sleep state, CS must be pulled HIGH before the first rising

edge of SCK. In the internal SCK timing mode, SCK goes

HIGHandthedevicebeginsoutputtingdataattimet_EOCtest

after the falling edge of CS (if EOC = 0) or t_EOCtestafter EOC

goes LOW (if CS is LOW during the falling edge of EOC).

Thevalueoft_EOCtestis23µsifthedeviceisusingitsinternal

oscillator (F_O= logic LOW or HIGH). If F_Ois driven by an

external oscillator of frequency f_EOSC, then t_EOCtestis

3.6/f_EOSC. If CS is pulled HIGH before time t_EOCtest, the

device returns to the sleep state and the conversion result

is held in the internal static shift register.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. If the device has not finished loading the

last input bit A0 of SDI by the time CS is pulled HIGH, the

address information is discarded and the previous ad-

dress is still kept. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.

241418fa

If CS remains LOW longer than t_EOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data I/O cycle concludes

after the 32nd rising edge. The input data is then shifted in

viatheSDIpinontherisingedgeofSCK(includingthefirst

rising edge) and the output data is shifted out of the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

22

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

V

CC

11

20

18

+

REFERENCE

VOLTAGE

0.1V TO V

10k

REF

SDI

12

21

28

1

–

SCK

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

CH15

TEST EOC

(OPTIONAL)

15

10

COM

GND

>t

<t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 8

SDO

Hi-Z

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

CONVERSION

(1)

(0)

EN

SGL

A2

A1

A0

SLEEP

DATA OUTPUT

DATA

OUTPUT

2411 F09

SLEEP

Figure 9. Internal Serial Clock, Reduced Data Output Length

Whenever SCK is LOW, the LTC2414/LTC2418’s internal

pull-up at pin SCK is disabled. Normally, SCK is not exter-

nallydrivenifthedeviceisintheinternalSCKtimingmode.

However, certain applications may require an external

driveronSCK.IfthisdrivergoesHi-ZafteroutputtingaLOW

signal, the LTC2414/LTC2418’s internal pull-up remains

disabled. Hence, SCK remains LOW. On the next falling

edgeofCS,thedeviceisswitchedtotheexternalSCKtiming

mode. By adding an external 10k pull-up resistor to SCK,

this pin goes HIGH once the external driver goes Hi-Z. On

the next CS falling edge, the device will remain in the in-

ternal SCK timing mode.

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 3-Wire I/O,

Continuous Conversion

This timing mode uses a 3-wire interface. The conversion

resultisshiftedoutofthedevicebyaninternallygenerated

serialclock(SCK)signal, seeFigure10. CSmaybeperma-

nently tied to ground, simplifying the user interface or

isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately1msafterV_CCexceeds2V. Aninternalweak

pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

period defined above as t_EOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

internal pull-up may not be adequate to return SCK to a

HIGHlevelbeforeCSgoeslowagain. Thisisnotaconcern

under normal conditions where CS remains LOW after

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

241418fa

23

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

9

19

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2414/

LTC2418

+

11

20

18

REFERENCE

VOLTAGE

0.1V TO V

REF

SDI

12

21

28

1

–

SCK

CC

3-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

CH15

15

10

COM

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

BIT 24

BIT 6

LSB

BIT 0

SDO

PARITY

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

DATA OUTPUT

CONVERSION

241418 F10

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data input/

output cycle begins on the first rising edge of SCK and

ends after the 32nd rising edge. The input data is then

shifted in via the SDI pin on the rising edge of SCK

(including the first rising edge) and the output data is

shifted out of the SDO pin on each falling edge of SCK.

The internally generated serial clock is output to the SCK

pin. Thissignalmaybeusedtoshifttheconversionresult

into external circuitry. EOC can be latched on the first

risingedgeofSCKandthelastbitoftheconversionresult

can be latched on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1) indicating a

newconversionisinprogress.SCKremainsHIGHduring

the conversion.

quency perturbations and so on. Nevertheless, in order to

preserve the extreme accuracy capability of this part,

some simple precautions are desirable.

Digital Signal Levels

The LTC2414/LTC2418’s digital interface is easy to use.

Itsdigitalinputs(SDI,F_O,CSandSCKinExternalSCKmode

of operation) accept standard TTL/CMOS logic levels and

the internal hysteresis receivers can tolerate edge rates as

slowas100µs.However,someconsiderationsarerequired

to take advantage of the exceptional accuracy and low

supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

While a digital input signal is in the range 0.5V to

(V_CC– 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (SDI, F_O, CS and

SCK in External SCK mode of operation) is within this

range, the power supply current may increase even if the

signal in question is at a valid logic level. For micropower

PRESERVING THE CONVERTER ACCURACY

TheLTC2414/LTC2418aredesignedtoreduceasmuchas

possible the conversion result sensitivity to device

decoupling, PCB layout, antialiasing circuits, line fre-

241418fa

24

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

operation, it is recommended to drive all digital input

signals to full CMOS levels [V_IL< 0.4V and

Such perturbations may occur due to asymmetric capaci-

tivecouplingbetweentheF_Osignaltraceandtheconverter

input and/or reference connection traces. An immediate

solution is to maintain maximum possible separation

between the F_Osignal trace and the input/reference sig-

nals. When the F_Osignal is parallel terminated near the

converter, substantial AC current is flowing in the loop

formedbytheF_Oconnectiontrace, theterminationandthe

ground return path. Thus, perturbation signals may be

inductively coupled into the converter input and/or refer-

ence. In this situation, the user must reduce to a minimum

the loop area for the F_Osignal as well as the loop area for

the differential input and reference connections.

V

_OH> (V_CC– 0.4V)].

During the conversion period, the undershoot and/or

overshoot of a fast digital signal connected to the pins

may severely disturb the analog to digital conversion

process.Undershootandovershootcanoccurbecauseof

the impedance mismatch at the converter pin when the

transition time of an external control signal is less than

twice the propagation delay from the driver to LTC2414/

LTC2418. For reference, on a regular FR-4 board, signal

propagation velocity is approximately 183ps/inch for

internal traces and 170ps/inch for surface traces. Thus, a

driver generating a control signal with a minimum transi-

tion time of 1ns must be connected to the converter pin

through a trace shorter than 2.5 inches. This problem

becomes particularly difficult when shared control lines

are used and multiple reflections may occur. The solution

is to carefully terminate all transmission lines close to

their characteristic impedance.

Driving the Input and Reference

The input and reference pins of the LTC2414/LTC2418

convertersaredirectlyconnectedtoanetworkofsampling

capacitors. Depending upon the relation between the

differential input voltage and the differential reference

voltage, these capacitors are switching between these

four pins transferring small amounts of charge in the

process. A simplified equivalent circuit is shown in

Figure 11.

Parallel termination near the LTC2414/LTC2418 pin will

eliminate this problem but will increase the driver power

dissipation. A series resistor between 27Ω and 56Ω

placed near the driver or near the LTC2414/LTC2418 pin

will also eliminate this problem without additional power

dissipation. The actual resistor value depends upon the

trace impedance and connection topology.

For a simple approximation, the source impedance R_S

driving an analog input pin (IN⁺, IN^–, REF⁺or REF^–) can be

considered to form, together with R_SWand C_EQ(see

Figure 11), a first order passive network with a time

constant τ = (R_S+ R_SW) • C_EQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The differential input and refer-

ence architecture reduce substantially the converter’s

sensitivity to ground currents.

Particular attention must be given to the connection of the

F_Osignal when the LTC2414/LTC2418 are used with an

external conversion clock. This clock is active during the

conversion time and the normal mode rejection provided

by the internal digital filter is not very high at this fre-

quency. A normal mode signal of this frequency at the

converter reference terminals may result into DC gain and

INL errors. A normal mode signal of this frequency at the

converterinputterminalsmayresultintoaDCoffseterror.

Whenusingtheinternaloscillator(F_O=LOWorHIGH), the

LTC2414/LTC2418’s front-end switched-capacitor net-

work is clocked at 76800Hz corresponding to a 13µs

sampling period. Thus, for settling errors of less than

1ppm, the driving source impedance should be chosen

suchthatτ≤13µs/14=920ns. Whenanexternaloscillator

of frequency f_EOSCis used, the sampling period is 2/f_EOSC

and, for a settling error of less than 1ppm, τ ≤ 0.14/f_EOSC

.

241418fa

25

LTC2414/LTC2418

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U

APPLICATIO S I FOR ATIO

source impedance result in only small errors. Such values

for C_INwill deteriorate the converter offset and gain

performancewithoutsignificantbenefitsofsignalfiltering

and the user is advised to avoid them. Nevertheless, when

small values of C_INare unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the

LTC2414/LTC2418 can maintain its exceptional accuracy

while operating with relative large values of source resis-

tance as shown in Figures 13 and 14. These measured

results may be slightly different from the first order

approximation suggested earlier because they include the

effect of the actual second order input network together

with the nonlinear settling process of the input amplifiers.

For small C_INvalues, the settling on IN⁺and IN^–occurs

almost independently and there is little benefit in trying to

match the source impedance for the two pins.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

theINLperformanceoftheconverter. Figure11showsthe

mathematical expressions for the average bias currents

flowing through the IN⁺and IN^–pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 12. The C_PARcapacitor

includestheLTC2414/LTC2418pincapacitance(5pFtypi-

cal) plus the capacitance of the test fixture used to obtain

the results shown in Figures 13 and 14. A careful imple-

mentation can bring the total input capacitance (C_IN

+

Larger values of input capacitors (C_IN> 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When F_O= LOW (internal oscillator and 60Hz notch), the

C_PAR) closer to 5pF thus achieving better performance

than the one predicted by Figures 13 and 14. For simplic-

ity, two distinct situations can be considered.

For relatively small values of input capacitance (C_IN

<

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

V + V_INCM− V_REFCM

V

CC

IN

I IN⁺

=

I

+

REF

(

)

AVG

R

(TYP)

0.5• R_EQ

SW

I

LEAK

20k

−V + V_INCM− V_REFCM

IN

V

I IN⁻

REF

(

0.5• R_EQ

V²

V

CC

1.5• V_REF− V

+ V_REFCM

INCM

IN

I

+

IN

I REF⁺

=

−

(

)

(TYP)

20k

SW

AVG

0.5• R_EQ

V_REF• R_EQ

I

LEAK

V²

V

+

IN

−1.5• V_REF− V

+ V_REFCM

INCM

IN

I REF⁻

+

C

EQ

(

18pF

AVG

0.5• R_EQ

V_REF• R_EQ

(TYP)

V

CC

where:

I

–

IN

R

(TYP)

20k

SW

V_REF= REF⁺− REF⁻

I

LEAK

V

+

REF + REF⁻

⎛

⎞

V_REFCM

=

⎜

⎟

2

⎝

⎠

V

CC

I

–

= IN⁺− IN⁻

IN

REF

V

(TYP)

20k

SW

I

LEAK

+

−

⎛

⎞

2414/18 F11

IN − IN

V

REF

V

INCM

=

⎜

⎟

2

⎝

⎠

R_EQ= 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch F_O= LOW

(

)

SWITCHING FREQUENCY

R_EQ= 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch F_O= HIGH

f

= 76800Hz INTERNAL OSCILLATOR (F = LOW OR HIGH)

(

)

SW

O

= 0.5 • f

EOSC

EXTERNAL OSCILLATOR

R_EQ= 0.555• 10¹²/ f_EOSCEXTERNAL OSCILLATOR

(

)

Figure 11. LTC2414/LTC2418 Equivalent Analog Input Circuit

241418fa

26

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

R

SOURCE

+

IN

C

PAR

≅20pF

V

+ 0.5V

C

INCM

IN

LTC2414/

LTC2418

R

SOURCE

–

IN

2414/18 F12

C

PAR

V

INCM

– 0.5V

IN

≅20pF

+

–

Figure 12. An RC Network at IN and IN

50

40

30

20

10

0

C

= 0.01µF

IN

V

= 5V

CC

+

REF = 5V

C

IN

= 0.001µF

–

REF = GND

–10

–20

–30

–40

–50

+

–

C

= 100pF

IN

IN = 1.25V

IN = 3.75V

C

= 0pF

IN

F

= GND

= 25°C

O

A

T

V

= 5V

CC

+

–

REF = 5V

C

= 0.01µF

REF = GND

IN

+

–

IN = 3.75V

C

= 0.001µF

IN

C

IN = 1.25V

F

= GND

= 25°C

O

= 100pF

IN

C

T

A

= 0pF

IN

1

10

100

1k

10k

100k

1

10

100

1k

10k

100k

R

(Ω)

R

(Ω)

SOURCE

2414/18 F13

2414/18 F14

+

–

+

–

Figure 13. +FS Error vs R

at IN or IN (Small C )

IN

Figure 14. –FS Error vs R

at IN or IN (Small C )

IN

SOURCE

typical differential input resistance is 1.8MΩ which will IN⁺and IN^–and with the difference between the input and

generate a gain error of approximately 0.28ppm for each reference common mode voltages. While the input drive

ohm of source resistance driving IN⁺or IN^–. When F_O= circuit nonzero source impedance combined with the

HIGH (internal oscillator and 50Hz notch), the typical converter average input current will not degrade the INL

differentialinputresistanceis2.16MΩwhichwillgenerate performance,indirectdistortionmayresultfromthemodu-

a gain error of approximately 0.23ppm for each ohm of lation of the offset error by the common mode component

source resistance driving IN⁺or IN^–. When F_Ois driven by of the input signal. Thus, when using large C_INcapacitor

an external oscillator with a frequency f_EOSC(external values, it is advisable to carefully match the source imped-

conversion clock operation), the typical differential input anceseenbytheIN⁺andIN^–pins.WhenF_O=LOW(internal

resistance is 0.28 • 10¹²/f_EOSCΩ and each ohm of oscillator and 60Hz notch), every 1Ω mismatch in source

source resistance driving IN⁺or IN^–will result in impedance transforms a full-scale common mode input

1.78 • 10^–6• f_EOSCppm gain error. The effect of the source signal into a differential mode input signal of 0.28ppm.

resistance on the two input pins is additive with respect to WhenF_O=HIGH(internaloscillatorand50Hznotch),every

thisgainerror.Thetypical+FSand–FSerrorsasafunction 1Ω mismatch in source impedance transforms a full-scale

of the sum of the source resistance seen by IN⁺and IN^–for common mode input signal into a differential mode input

large values of C_INare shown in Figures 15 and 16.

signal of 0.23ppm. When F_Ois driven by an external

oscillator with a frequency f_EOSC, every 1Ω mismatch in

source impedance transforms a full-scale common

mode input signal into a differential mode input signal of

241418fa

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

27

LTC2414/LTC2418

W U U

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APPLICATIO S I FOR ATIO

1.78 • 10^–6• f_EOSCppm. Figure 17 shows the typical offset

error due to input common mode voltage for various

values of source resistance imbalance between the IN⁺

and IN^–pins when large C_INvalues are used.

300

V

= 5V

CC

C

= 1µF, 10µF

IN

+

REF = 5V

–

REF = GND

240

180

120

60

+

–

IN = 3.75V

IN = 1.25V

F

= GND

= 25°C

O

A

T

C

= 0.1µF

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

IN

C

= 0.01µF

IN

0

100 200 300 400 500 600 700 800 9001000

R

(Ω)

SOURCE

Themagnitudeofthedynamicinputcurrentdependsupon

thesizeoftheverystableinternalsamplingcapacitorsand

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN⁺and

IN^–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

2414/18 F15

+

–

Figure 15. +FS Error vs R

at IN or IN (Large C )

SOURCE

IN

0

C

= 0.01µF

= 0.1µF

IN

–60

–120

C

IN

V

= 5V

CC

+

–180

–240

–300

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

O

A

C

IN

= 1µF, 10µF

T

0

100 200 300 400 500 600 700 800 9001000

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

inasmalloffsetshift. A100Ωsourceresistancewillcreate

a 0.1µV typical and 1µV maximum offset voltage.

R

(Ω)

SOURCE

2414/18 F16

+

–

Figure 16. –FS Error vs R

at IN or IN (Large C )

SOURCE

IN

120

V

= 5V

CC

+

100

80

REF = 5V

A

B

–

REF = GND

+

–

IN = IN = V

INCM

60

Reference Current

40

C

D

E

F

In a similar fashion, the LTC2414/LTC2418 samples the

differential reference pins REF⁺and REF^–transferring

small amount of charge to and from the external driving

circuits thus producing a dynamic reference current. This

current does not change the converter offset, but it may

degrade the gain and INL performance. The effect of this

current can be analyzed in the same two distinct situa-

tions.

20

0

–20

–40

–60

–80

–100

–120

F

= GND

= 25°C

O

G

T

R

C

A

– = 500Ω

SOURCEIN

IN

= 10µF

0

0.5

1

1.5

2

2.5

3

(V)

3.5

4

4.5

5

V

INCM

A: ∆R = +400Ω

E: ∆R = –100Ω

IN

B: ∆R = +200Ω

F: ∆R = –200Ω

IN

Forrelativelysmallvaluesoftheexternalreferencecapaci-

tors(C_REF<0.01µF),thevoltageonthesamplingcapacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

C: ∆R = +100Ω

IN

G: ∆R = –400Ω

IN

D: ∆R = 0Ω

IN

2414/18 F17

Figure 17. Offset Error vs Common Mode Voltage

+

–

(V

= IN = IN ) and Input Source Resistance Imbalance

INCM

IN

(∆R = R

+ – R

–) for Large C Values (C ≥ 1µF)

SOURCEIN

SOURCEIN IN IN

241418fa

28

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

of approximately 0.32ppm for each ohm of source resis-

tance driving REF⁺or REF^–. When F_Ois driven by an

externaloscillatorwithafrequencyf_EOSC(externalconver-

sion clock operation), the typical differential reference

resistance is 0.20 • 10¹²/f_EOSCΩ and each ohm of source

resistance driving REF⁺or REF^–will result in

2.47 • 10^–6• f_EOSCppm gain error. The effect of the source

resistance on the two reference pins is additive with

respect to this gain error. The typical +FS and –FS errors

for various combinations of source resistance seen by the

REF⁺and REF^–pins and external capacitance C_REFcon-

nected to these pins are shown in Figures 18, 19, 20

and 21.

values for C_REFwill deteriorate the converter offset and

gainperformancewithoutsignificantbenefitsofreference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (C_REF> 0.01µF) may

be required as reference filters in certain configurations.

Suchcapacitorswillaveragethereferencesamplingcharge

and the external source resistance will see a quasi con-

stant reference differential impedance. When F_O= LOW

(internaloscillatorand60Hznotch), thetypicaldifferential

reference resistance is 1.3MΩ which will generate a gain

error of approximately 0.38ppm for each ohm of source

resistancedrivingREF⁺orREF^–. WhenF_O=HIGH(internal

oscillator and 50Hz notch), the typical differential refer-

enceresistanceis1.56MΩwhichwillgenerateagainerror

50

0

C

= 0.01µF

REF

V

= 5V

CC

+

C

= 0.001µF

REF = 5V

REF

–

40

30

20

10

0

REF = GND

–10

–20

–30

–40

–50

+

–

C

= 100pF

REF

IN = 3.75V

IN = 1.25V

C

= 0pF

REF

F

= GND

= 25°C

O

A

T

V

= 5V

CC

+

–

REF = 5V

REF = GND

C

= 0.01µF

REF

+

–

IN = 1.25V

C

= 0.001µF

REF

IN = 3.75V

F

= GND

= 25°C

O

C

= 100pF

REF

T

A

C

= 0pF

REF

1

10

100

R

1k

10k

100k

1

10

100

R

1k

(Ω)

10k

100k

(Ω)

SOURCE

2414/18 F19

2414/18 F18

+

–

+

–

Figure 18. +FS Error vs R

at REF or REF (Small C )

IN

Figure 19. –FS Error vs R

at REF or REF (Small C )

IN

SOURCE

450

0

–90

C

= 0.01µF

= 0.1µF

V

= 5V

REF

CC

C

= 1µF, 10µF

REF

+

REF = 5V

–

REF = GND

360

270

180

90

+

–

IN = 1.25V

IN = 3.75V

F

= GND

O

–180

C

T

= 25°C

A

REF

C

= 0.1µF

REF

V

= 5V

CC

+

–270

–360

–450

REF = 5V

–

REF = GND

+

–

IN = 3.75V

C

= 0.01µF

REF

IN = 1.25V

C

= 1µF, 10µF

F

= GND

= 25°C

REF

O

A

T

0

100 200 300 400 500 600 700 800 9001000

0

100 200 300 400 500 600 700 800 9001000

R

(Ω)

R

(Ω)

SOURCE

2414/18 F21

2414/18 F20

+

–

+

–

Figure 20. +FS Error vs R

at REF and REF (Large C

)

REF

Figure 21. –FS Error vs R

at REF and REF (Large C

)

REF

SOURCE

241418fa

29

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

WhenF_O=LOW(internaloscillatorand60Hznotch),every

100ΩofsourceresistancedrivingREF⁺orREF^–translates

into about 1.34ppm additional INL error. When F_O= HIGH

(internaloscillatorand50Hznotch), every100Ωofsource

resistance driving REF⁺or REF^–translates into about

1.1ppm additional INL error. When F_Ois driven by an

external oscillator with a frequency f_EOSC, every 100Ω of

source resistance driving REF⁺or REF^–translates into

about 8.73 • 10^–6• f_EOSCppm additional INL error.

Figure 22 shows the typical INL error due to the source

resistance driving the REF⁺or REF^–pins when large C_REF

values are used. The effect of the source resistance on the

tworeferencepinsisadditivewithrespecttothisINLerror.

In general, matching of source impedance for the REF⁺

and REF^–pins does not help the gain or the INL error. The

user is thus advised to minimize the combined source

impedance driving the REF⁺and REF^–pins rather than to

try to match it.

an external clock. When relatively stable resistors

(50ppm/°C) are used for the external source impedance

seen by REF⁺and REF^–, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

valueovertheentiretemperatureandvoltagerange). Even

for the most stringent applications a onetime calibration

operation may be sufficient.

Inadditiontothereferencesamplingcharge,thereference

pinsESDprotectiondiodeshaveatemperaturedependent

leakage current. This leakage current, nominally 1nA

(±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05µV typical and 0.5µV maxi-

mum full-scale error.

Output Data Rate

When using its internal oscillator, the LTC2414/LTC2418

can produce up to 7.5 readings per second with a notch

frequency of 60Hz (F_O= LOW) and 6.25 readings per

second with a notch frequency of 50Hz (F_O= HIGH). The

actual output data rate will depend upon the length of the

sleep and data output phases which are controlled by the

user and which can be made insignificantly short. When

operated with an external conversion clock (F_Oconnected

to an external oscillator), the LTC2414/LTC2418 output

dataratecanbeincreasedasdesireduptothatdetermined

by the maximum f_EOSCfrequency of 2000kHz. The dura-

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0.5%. Such a specification can also be easily achieved by

tion of the conversion phase is 20510/f_EOSC. If f_EOSC

=

15

153600Hz, the converter behaves as if the internal oscil-

lator is used and the notch is set at 60Hz. There is no

significant difference in the LTC2414/LTC2418 perfor-

mance between these two operation modes.

R

= 1000Ω

12

9

SOURCE

R

= 500Ω

SOURCE

6

3

0

An increase in f_EOSCover the nominal 153600Hz will

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

–3

–6

–9

–12

–15

R

= 100Ω

SOURCE

–0.5–0.4–0.3–0.2–0.1

0

/V

0.1 0.2 0.3 0.4 0.5

First, a change in f_EOSCwill result in a proportional change

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line

frequency. In many applications, the subsequent perfor-

mance degradation can be substantially reduced by rely-

ing upon the LTC2414/LTC2418’s exceptional common

V

INDIF REFDIF

V

= 5V

F = GND

O

CC

REF+ = 5V

C

= 10µF

REF

REF– = GND

T = 25°C

A

+

–

V

= 0.5 • (IN + IN ) = 2.5V

2414/18 F22

INCM

+

–

Figure 22. INL vs Differential Input Voltage (V = IN – IN )

IN

+

–

and Reference Source Resistance (R

at REF and REF for

SOURCE

Large C

Values (C

≥ 1µF)

REF

241418fa

30

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

mode rejection and by carefully eliminating common

mode to differential mode conversion sources in the input

circuit. The user should avoid single-ended input filters

and should maintain a very high degree of matching and

symmetry in the circuits driving the IN⁺and IN^–pins.

200

160

120

80

T

A

= 25°C

40

0

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

input and/or reference capacitors (C_IN, C_REF) are used, the

previous section provides formulae for evaluating the

effect of the source resistance upon the converter perfor-

mance for any value of f_EOSC. If small external input and/

or reference capacitors (C_IN, C_REF) are used, the effect of

theexternalsourceresistanceupontheLTC2414/LTC2418

typical performance can be inferred from Figures 12, 13,

18and19inwhichthehorizontalaxisisscaledby153600/

–40

–80

–120

V

= 5V

CC

= 5V

REF

T

= 85°C

A

= 2.5V

IN

INCM

= 2.5V

–160 SDI = GND

= EXTERNAL OSCILLATOR

F

O

–200

40

50 60 70 80 90 100

0

10 20 30

OUTPUT DATA RATE (READINGS/SEC)

2414/18 F23

Figure 23. Offset Error vs Output Data Rate and Temperature

2000

0

f_EOSC

.

T

= 25°C

A

–2000

–4000

–6000

–8000

–10000

–12000

Third, an increase in the frequency of the external oscilla-

tor above 460800Hz (a more than 3× increase in the

output data rate) will start to decrease the effectiveness of

the internal autocalibration circuits. This will result in a

progressive degradation in the converter accuracy and

linearity.Typicalmeasuredperformancecurvesforoutput

data rates up to 100 readings per second are shown in

Figures 23, 24, 25, 26, 27, 28, 29and30. Inordertoobtain

the highest possible level of accuracy from this converter

at output data rates above 20 readings per second, the

userisadvisedtomaximizethepowersupplyvoltageused

and to limit the maximum ambient operating temperature.

In certain circumstances, a reduction of the differential

reference voltage may be beneficial.

V

= 5V

CC

REF

IN

T = 85°C

A

= 2.5V

INCM

SDI = GND

F

= EXTERNAL OSCILLATOR

O

0

30 40 50 60 70 80 90 100

10 20

OUTPUT DATA RATE (READINGS/SEC)

2414/18 F24

Figure 24. +FS Error vs Output Data Rate and Temperature

12000

V

= 5V

CC

REF

IN

INCM

= 5V

10000

8000

6000

4000

2000

0

= 2.5V

T

= 85°C

A

= 2.5V

SDI = GND

= EXTERNAL OSCILLATOR

F

O

Input Bandwidth

The combined effect of the internal Sinc⁴digital filter and

of the analog and digital autocalibration circuits deter-

mines the LTC2414/LTC2418 input bandwidth. When the

internal oscillator is used with the notch set at 60Hz

(F_O= LOW), the 3dB input bandwidth is 3.63Hz. When the

internal oscillator is used with the notch set at 50Hz

(F_O= HIGH), the 3dB input bandwidth is 3.02Hz. If an

external conversion clock generator of frequency f_EOSCis

connected to the F_Opin, the 3dB input bandwidth is 0.236

T

= 25°C

A

–2000

0

30 40 50 60 70 80 90 100

10 20

OUTPUT DATA RATE (READINGS/SEC)

2414/18 F25

Figure 25. –FS Error vs Output Data Rate and Temperature

• 10^–6• f_EOSC

.

241418fa

31

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

22

24

200

150

100

50

RESOLUTION = LOG (V /INL )

MAX

F

= EXTERNAL OSCILLATOR

2

REF

O

23

20

22

V

= 5V

CC

–

REF = GND

V

T

= 25°C

A

= 0V

IN

INCM

21

20

19

18

17

16

15

14

13

12

18

16

14

12

10

8

= 2.5V

V

= 5V

REF

T

= 85°C

T = 25°C

A

SDI = GND

= 25°C

A

T

= 85°C

A

T

A

V

= 5V

CC

+

V

= 5V

CC

REF = 5V

+

–

REF = 5V

REF = GND

V

–

REF = GND

= 2.5V

INCM

V

= 2.5V

INCM

= 0V

V

REF

= 2.5V

IN

0

–2.5V < V < 2.5V

IN

SDI = GND

= EXTERNAL OSCILLATOR

SDI = GND

F

O

F

= EXTERNAL OSCILLATOR

O

RESOLUTION = LOG (V /NOISE )

RMS

2

REF

–50

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

40

50 60 70 80 90 100

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30

OUTPUT DATA RATE (READINGS/SEC)

2414/18 F27

2414/18 F26

2414/18 F28

Figure 26. Resolution (Noise

≤ 1LSB)

Figure 27. Resolution (INL

≤ 1LSB)

Figure 28. Offset Error vs Output

Data Rate and Reference Voltage

RMS

vs Output Data Rate and Temperature

22

24

23

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

RESOLUTION =

V

= 5V

REF

LOG (V /INL

)

20

18

16

14

12

10

8

2

REF

MAX

22

21

20

19

18

17

16

15

14

13

12

V

= 2.5V

F

= HIGH

F = LOW

O

REF

O

V

= 2.5V

REF

V

= 5V

REF

V

= 5V

REF

CC

–

REF = GND

T

= 25°C

A

V

= 2.5V

INCM

V

= 5V

CC

–

= 0V

IN

REF = GND

= 0.5 • REF

+

SDI = GND

V

INCM

F

= EXTERNAL OSCILLATOR

O

A

–0.5V • V

< V < 0.5 • V

REF IN

T

= 25°C

SDI = GND

F = EXTERNAL OSCILLATOR

O

RESOLUTION = LOG (V /NOISE

)

2

REF

RMS

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2414/18 F30

2414/18 F29

2414/18 F31

Figure 31. Input Signal Bandwidth

Using the Internal Oscillator

Figure 29. Resolution (Noise

≤ 1LSB) vs

Figure 30. Resolution (INL

≤ 1LSB) vs

RMS

MAX

Output Data Rate and Reference Voltage

Due to the complex filtering and calibration algorithms

utilized,theconverterinputbandwidthisnotmodeledvery

accurately by a first order filter with the pole located at the

3dB frequency. When the internal oscillator is used, the

shapeoftheLTC2414/LTC2418inputbandwidthisshown

inFigure 31forF_O=LOWandF_O=HIGH.Whenanexternal

oscillator of frequency f_EOSCis used, the shape of the

LTC2414/LTC2418 input bandwidth can be derived from

Figure 31, F_O= LOW curve in which the horizontal axis is

scaled by f_EOSC/153600.

free converter. The noise spectral density is 78nV/√Hz for

an infinite bandwidth source and 107nV/√Hz for a single

0.5MHz pole source. From these numbers, it is clear that

particular attention must be given to the design of external

amplification circuits. Such circuits face the simultaneous

requirements of very low bandwidth (just a few Hz) in

order to reduce the output referred noise and relatively

high bandwidth (at least 500kHz) necessary to drive the

input switched-capacitor network. A possible solution is a

high gain, low bandwidth amplifier stage followed by a

high bandwidth unity-gain buffer.

The conversion noise (1µV_RMStypical for V_REF= 5V) can

be modeled by a white noise source connected to a noise

241418fa

32

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

100

10

1

When external amplifiers are driving the LTC2414/

LTC2418, the ADC input referred system noise calculation

can be simplified by Figure 32. The noise of an amplifier

driving the LTC2414/LTC2418 input pin can be modeled

as a band limited white noise source. Its bandwidth can be

approximated by the bandwidth of a single pole lowpass

filter with a corner frequency f_i. The amplifier noise spec-

tral density is n_i. From Figure 32, using f_ias the x-axis

selector, we can find on the y-axis the noise equivalent

bandwidth freq_iof the input driving amplifier. This band-

widthincludesthebandlimitingeffectsoftheADCinternal

calibration and filtering. The noise of the driving amplifier

referred to the converter input and including all these

effectscanbecalculatedasN =n_i•√freq_i.Thetotalsystem

noise (referred to the LTC2414/LTC2418 input) can now

be obtained by summing as square root of sum of squares

the three ADC input referred noise sources: the LTC2414/

LTC2418 internal noise (1µV), the noise of the IN⁺driving

amplifier and the noise of the IN^–driving amplifier.

F

= LOW

= HIGH

O

0.1

1

10 100 1k 10k 100k 1M

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

2414/18 F32

Figure 32. Input Referred Noise Equivalent Bandwidth

of an Input Connected White Noise Source

0

F

= HIGH

O

–10

–20

–30

–40

–50

If the F_Opin is driven by an external oscillator of frequency

f_EOSC, Figure32canstillbeusedfornoisecalculationifthe

x-axis is scaled by f_EOSC/153600. For large values of the

ratio f_EOSC/153600, the Figure 32 plot accuracy begins to

decrease, but in the same time the LTC2414/LTC2418

noise floor rises and the noise contribution of the driving

amplifiers lose significance.

–60

–70

–80

–90

–100

–110

–120

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f

S S S S S S S S S S S S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2414/18 F33

Normal Mode Rejection and Antialiasing

Figure 33. Input Normal Mode Rejection,

Internal Oscillator and 50Hz Notch

One of the advantages delta-sigma ADCs offer over con-

ventional ADCs is on-chip digital filtering. Combined with

a large oversampling ratio, the LTC2414/LTC2418 signifi-

cantly simplify antialiasing filter requirements.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

F

= LOW OR

O

= EXTERNAL

OSCILLATOR,

f

= 10 • f

EOSC

S

TheSinc⁴digitalfilterprovidesgreaterthan120dBnormal

mode rejection at all frequencies except DC and integer

multiples of the modulator sampling frequency (f_S). The

LTC2414/LTC2418’s autocalibration circuits further sim-

plify the antialiasing requirements by additional normal

modesignalfilteringbothintheanaloganddigitaldomain.

Independent of the operating mode, f_S= 256 • f_N= 2048

• f_OUTMAXwhere f_Nin the notch frequency and f_OUTMAXis

the maximum output data rate. In the internal oscillator

mode with a 50Hz notch setting, f_S= 12800Hz and with a

60Hz notch setting f_S= 15360Hz. In the external oscillator

mode, f_S= f_EOSC/10.

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f

S S S S S S S S S S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2414/18 F34

Figure 34. Input Normal Mode Rejection, Internal

Oscillator and 60Hz Notch or External Oscillator

241418fa

33

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

The combined normal mode rejection performance is

shown in Figure 33 for the internal oscillator with 50Hz

notch setting (F_O= HIGH) and in Figure 34 for the internal

oscillator with 60Hz notch setting (F_O= LOW) and for the

external oscillator mode. The regions of low rejection

occurring at integer multiples of f_Shave a very narrow

bandwidth.Magnifieddetailsofthenormalmoderejection

curves are shown in Figure 35 (rejection near DC) and

Figure 36 (rejection at f_S= 256f_N) where f_Nrepresents the

notch frequency. These curves have been derived for the

external oscillator mode but they can be used in all

operating modes by appropriately selecting the f_Nvalue.

operating with an internal oscillator and a 60Hz notch

setting are shown in Figure 37 superimposed over the

theoretical calculated curve. Similarly, typical measured

values of the normal mode rejection of the LTC2414/

LTC2418 operating with an internal oscillator and a 50Hz

notch setting are shown in Figure 38 superimposed over

the theoretical calculated curve.

As a result of these remarkable normal mode specifica-

tions, minimal (if any) antialias filtering is required in front

of the LTC2414/LTC2418. If passive RC components are

placed in front of the LTC2414/LTC2418, the input dy-

namic current should be considered (see Input Current

section). In cases where large effective RC time constants

are used, an external buffer amplifier may be required to

minimize the effects of dynamic input current.

The user can expect to achieve in practice this level of

performance using the internal oscillator as it is demon-

strated by Figures 37 and 38. Typical measured values of

the normal mode rejection of the LTC2414/LTC2418

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

250f 252f 254f 256f 258f 260f 262f

0

f

N

2f

3f

4f

5f

6f

7f

8f

N

INPUT SIGNAL FREQUENCY (Hz)

2414/18 F36

2414/18 F35

Figure 35. Input Normal Mode Rejection

Figure 36. Input Normal Mode Rejection

0

–20

0

–20

MEASURED DATA

CALCULATED DATA

V

= 5V

MEASURED DATA

CALCULATED DATA

V

= 5V

CC

+

REF = 5V

REF = GND

REF = 5V

REF = GND

–

V

= 2.5V

V

= 2.5V

= 5V

INCM

–40

= 5V

V

IN(P-P)

SDI = GND

F

T

= GND

= 25°C

F

T

= 5V

= 25°C

O

–60

A

–80

–100

–120

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2414/18 F37

2414/18 F38

Figure 37. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full Scale (60Hz Notch)

Figure 38. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full Scale (50Hz Notch)

241418fa

34

LTC2414/LTC2418

W U U

APPLICATIO S I FOR ATIO

U

Traditional high order delta-sigma modulators, while

providing very good linearity and resolution, suffer from

potential instabilities at large input signal levels. The pro-

prietary architecture used for the LTC2414/LTC2418 third

order modulator resolves this problem and guarantees a

predictable stable behavior at input signal levels of up to

150% of full scale. In many industrial applications, it is not

uncommon to have to measure microvolt level signals

superimposed over volt level perturbations and LTC2414/

LTC2418 is eminently suited for such tasks. When the

perturbation is differential, the specification of interest is

the normal mode rejection for large input signal levels.

WithareferencevoltageV_REF= 5V,theLTC2414/LTC2418

hasafull-scaledifferentialinputrangeof5Vpeak-to-peak.

Figures 39 and 40 show measurement results for the

LTC2414/LTC2418normalmoderejectionratiowitha7.5V

peak-to-peak (150% of full scale) input signal superim-

posed over the more traditional normal mode rejection

ratio results obtained with a 5V peak-to-peak (full scale)

input signal. In Figure 39, the LTC2414/LTC2418 uses the

internal oscillator with the notch set at 60Hz (F_O= LOW)

and in Figure 40 it uses the internal oscillator with the

notch set at 50Hz (F_O= HIGH). It is clear that the LTC2414/

LTC2418rejectionperformanceismaintainedwithnocom-

promises in this extreme situation. When operating with

large input signal levels, the user must observe that such

signals do not violate the device absolute maximum

ratings.

0

–20

V

= 5V

= 7.5V

V

= 5V

IN(P-P)

CC

+

REF = 5V

REF = GND

IN(P-P)

–

(150% OF FULL SCALE)

V

= 2.5V

INCM

SDI = GND

–40

F

= GND

O

T

A

= 25°C

–60

–80

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

2414/18 F39

Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)

0

V

= 5V

= 7.5V

V

= 5V

IN(P-P)

CC

+

REF = 5V

REF = GND

IN(P-P)

–20

–40

–

(150% OF FULL SCALE)

V

= 2.5V

INCM

SDI = GND

F

= 5V

O

T

A

= 25°C

–60

–80

–100

–120

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2414/18 F40

Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)

241418fa

35

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

BRIDGE APPLICATIONS

weighed, the average weight over an extended period of

time is of concern and short term weight is not readily

determined due to movement of contents, or mechanical

resonance.Often,largeweighingapplicationsinvolveload

cells located at each load bearing point, the output of

which can be summed passively prior to the signal pro-

cessing circuitry, actively with amplification prior to the

ADC, or can be digitized via multiple ADC channels and

summed mathematically. The mathematical summation

oftheoutputofmultipleLTC2414/LTC2418’sprovidesthe

benefit of a root square reduction in noise. The low power

consumptionoftheLTC2414/LTC2418makesitattractive

for multidrop communication schemes where the ADC is

located within the load-cell housing.

Typical strain gauge based bridges deliver only 2mV/Volt

of excitation. As the maximum reference voltage of the

LTC2414/LTC2418 is 5V, remote sensing of applied exci-

tation without additional circuitry requires that excitation

be limited to 5V. This gives only 10mV full scale input

signal, which can be resolved to 1 part in 10000 without

averaging. For many solid state sensors, this is still better

than the sensor. Averaging 64 samples however reduces

the noise level by a factor of eight, bringing the resolving

power to 1 part in 80000, comparable to better weighing

systems. Hysteresis and creep effects in the load cells are

typically much greater than this. Most applications that

require strain measurements to this level of accuracy are

measuring slowly changing phenomena, hence the time

required to average a large number of readings is usually

not an issue. For those systems that require accurate

measurement of a small incremental change on a signifi-

cant tare weight, the lack of history effects in the LTC2400

family is of great benefit.

LT1019

+

0.1µF

10µF

0.1µF

R1

9

V

CC

11

20

18

17

16

+

–

REF

SDI

SCK

SDO

CS

350Ω

BRIDGE

12

REF

For those applications that cannot be fulfilled by the

LTC2414/LTC2418alone,compensatingforerrorinexter-

nal amplification can be done effectively due to the “no

latency” feature of the LTC2414/LTC2418. No latency

operation allows samples of the amplifier offset and gain

tobeinterleavedwithweighingmeasurements. Theuseof

correlated double sampling allows suppression of 1/f

noise, offset and thermocouple effects within the bridge.

Correlateddoublesamplinginvolvesalternatingthepolar-

ity of excitation and dealing with the reversal of input

polarity mathematically. Alternatively, bridge excitation

can be increased to as much as ±10V, if one of several

precision attenuation techniques is used to produce a

precision divide operation on the reference signal. An-

other option is the use of a reference within the 5V input

range of the LTC2414/LTC2418 and developing excitation

via fixed gain, or LTC1043 based voltage multiplication,

along with remote feedback in the excitation amplifiers, as

shown in Figures 46 and 47.

21

CH0

LTC2414/

LTC2418

22

19

CH1

F

O

GND

15

R2

2414/18 F41

R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS

Figure 41. Simple Bridge Connection

A direct connection to a load cell is perhaps best incorpo-

rated into the load-cell body, as minimizing the distance to

the sensor largely eliminates the need for protection

devices, RFI suppression and wiring. The LTC2414/

LTC2418 exhibits extremely low temperature dependent

drift. As a result, exposure to external ambient tempera-

ture ranges does not compromise performance. The in-

corporation of any amplification considerably compli-

cates thermal stability, as input offset voltages and cur-

rents, temperature coefficient of gain settling resistors all

become factors.

Figure 41 shows an example of a simple bridge connec-

tion. Note that it is suitable for any bridge application

where measurement speed is not of the utmost impor-

tance. For many applications where large vessels are

241418fa

36

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

changes the rationale. Achieving high gain accuracy and

linearity at higher gains may prove difficult, while provid-

ing little benefit in terms of noise reduction.

The circuit in Figure 42 shows an example of a simple

amplification scheme. This example produces a differen-

tial output with a common mode voltage of 2.5V, as

determined by the bridge. The use of a true three amplifier

instrumentationamplifierisnotnecessary,astheLTC2414/

LTC2418 has common mode rejection far beyond that of

most amplifiers. The LTC1051 is a dual autozero amplifier

that can be used to produce a gain of 15 before its input

referred noise dominates the LTC2414/LTC2418 noise.

This example shows a gain of 34, that is determined by a

feedback network built using a resistor array containing 8

individual resistors. The resistors are organized to opti-

mize temperature tracking in the presence of thermal

gradients. The second LTC1051 buffers the low noise

input stage from the transient load steps produced during

conversion.

At a gain of 100, the gain error that could result from

typical open-loop gain of 160dB is –1ppm, however,

worst-case is at the minimum gain of 116dB, giving a gain

error of –158ppm. Worst-case gain error at a gain of 34,

is –54ppm. The use of the LTC1051A reduces the worst-

case gain error to –33ppm. The advantage of gain higher

than 34, then becomes dubious, as the input referred

noise sees little improvement and gain accuracy is poten-

tially compromised.

Note that this 4-amplifier topology has advantages over

the typical integrated 3-amplifier instrumentation ampli-

fier in that it does not have the high noise level common in

the output stage that usually dominates when and instru-

mentation amplifier is used at low gain. If this amplifier is

used at a gain of 10, the gain error is only 10ppm and input

referred noise is reduced to 0.1µV_RMS. The buffer stages

canalsobeconfiguredtoprovidegainofupto50withhigh

gain stability and linearity.

The gain stability and accuracy of this approach is very

good, due to a statistical improvement in resistor match-

ing. A gain of 34 may seem low, when compared to

common practice in earlier generations of load-cell inter-

faces, however the accuracy of the LTC2414/LTC2418

5V

REF

0.1µF

5V

8

3

2

+

–

0.1µF

1

U1A

4

5V

2

8

2

3

350Ω

BRIDGE

–

+

V

CC

1

11

12

20

+

–

U2A

REF

SDI

15

14

4

5

12

18

17

16

SCK

SD0

CS

1

4

RN1

16

21

6

11

7

10

8

9

CH0

2

3

13

LTC2414/

LTC2418

6

5

6

5

–

+

–

+

7

22

19

CH1

U2B

U1B

F

O

GND

15

2414/18 F42

RN1 = 5k × 8 RESISTOR ARRAY

U1A, U1B, U2A, U2B = 1/2 LTC1051

Figure 42. Using Autozero Amplifiers to Reduce Input Referred Noise

241418fa

37

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

Remote Half Bridge Interface

Figure 43 shows an example of a single amplifier used to

produce single-ended gain. This topology is best used in

applications where the gain setting resistor can be made

to match the temperature coefficient of the strain gauges.

If the bridge is composed of precision resistors, with only

one or two variable elements, the reference arm of the

bridgecanbemadetoactinconjunctionwiththefeedback

resistor to determine the gain. If the feedback resistor is

incorporated into the design of the load cell, using resis-

tors which match the temperature coefficient of the load-

cell elements, good results can be achieved without the

needforresistorswithahighdegreeofabsoluteaccuracy.

Thecommonmodevoltageinthiscase, isagainafunction

of the bridge output. Differential gain as used with a 350Ω

bridge is A_V= (R1+ R2)/(R1+175Ω). Common mode gain

is half the differential gain. The maximum differential

signal that can be used is 1/4 V_REF, as opposed to 1/2 V_REF

in the 2-amplifier topology above.

As opposed to full bridge applications, typical half bridge

applications must contend with nonlinearity in the bridge

output,assignalswingisoftenmuchgreater.Applications

include RTD’s, thermistors and other resistive elements

that undergo significant changes over their span. For

singlevariableelementbridges, thenonlinearityofthehalf

bridge output can be eliminated completely; if the refer-

ence arm of the bridge is used as the reference to the ADC,

as shown in Figure 44. The LTC2414/LTC2418 can accept

inputs up to 1/2 V_REF. Hence, the reference resistor R1

must be at least 2x the highest value of the variable

resistor.

In the case of 100Ω platinum RTD’s, this would suggest a

value of 800Ω for R1. Such a low value for R1 is not

advisable due to self-heating effects. A value of 25.5k is

shown for R1, reducing self-heating effects to acceptable

levels for most sensors.

5V

V

S

+

2.7V TO 5.5V

10µF

0.1µF

5V

9

350Ω

9

BRIDGE

V

CC

11

0.1µV

+

REF

R1

25.5k

0.1%

V

CC

7

3

2

11

12

LTC2414/

LTC2418

–

+

–

+

REF

175Ω

1µF

6

12

21

LTC1050S8

REF

+

–

20k

21

CH0

+

4

CH0

1µF

PLATINUM

100Ω

R1

4.99k

R2

46.4k

LTC2414/

LTC2418

22

CH1

RTD

GND

15

22

CH1

GND

15

2410 F50

R1 + R2

2410 F49

A

= 9.95 =

V

(

)

R1 + 175Ω

Figure 43. Bridge Amplification Using a Single Amplifier

Figure 44. Remote Half Bridge Interface

241418fa

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LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

are not translated into an error. The reference voltage is

alsoreduced, butthisisnotundesirable, asitwilldecrease

the value of the LSB, although, not the input referred noise

level.

The basic circuit shown in Figure 44 shows connections

for a full 4-wire connection to the sensor, which may be

located remotely. The differential input connections will

reject induced or coupled 60Hz interference, however, the

reference inputs do not have the same rejection. If 60Hz or

other noise is present on the reference input, a low pass

filterisrecommendedasshowninFigure45.Notethatyou

cannot place a large capacitor directly at the junction of R1

and R2, as it will store charge from the sampling process.

Abetterapproachistoproducealowpassfilterdecoupled

from the input lines with a high value resistor (R3).

The circuit shown in Figure 45 shows a more rigorous

example of Figure 44, with increased noise suppression

and more protection for remote applications.

Figure46showsanexampleofgainintheexcitationcircuit

and remote feedback from the bridge. The LTC1043’s

provide voltage multiplication, providing ±10V from a 5V

reference with only 1ppm error. The amplifiers are used at

unity gain and introduce very little error due to gain error

or due to offset voltages. A 1µV/°C offset voltage drift

translates into 0.05ppm/°C gain error. Simpler alterna-

tives, with the amplifiers providing gain using resistor

arrays for feedback, can produce results that are similar to

bridge sensing schemes via attenuators. Note that the

amplifiersmusthavehighopen-loopgainorgainerrorwill

be a source of error. The fact that input offset voltage has

relatively little effect on overall error may lead one to use

low performance amplifiers for this application. Note that

the gain of a device such as an LF156, (25V/mV over

temperature) will produce a worst-case error of –180ppm

at a noise gain of 3, such as would be encountered in an

inverting gain of 2, to produce –10V from a 5V reference.

The use of a third resistor in the half bridge, between the

variable and fixed elements gives essentially the same

result as the two resistor version, but has a few benefits.

If, for example, a 25k reference resistor is used to set the

excitation current with a 100Ω RTD, the negative refer-

ence input is sampling the same external node as the

positive input and may result in errors if used with a long

cable. For short cable applications, the errors may be

acceptably low. If instead the single 25k resistor is re-

placed with a 10k 5% and a 10k 0.1% reference resistor,

the noise level introduced at the reference, at least at

higher frequencies, will be reduced. A filter can be intro-

duced into the network, in the form of one or more

capacitors,orferritebeads,aslongasthesamplingpulses

5V

9

R2

V

10k

CC

11

12

+

–

0.1%

REF

+

R3

10k

5%

560Ω

1µF

R1

LTC1050

10k, 5%

–

LTC2414/

LTC2418

10k

21

22

CH0

CH1

PLATINUM

100Ω

RTD

GND

15

2410 F51

Figure 45. Remote Half Bridge Sensing with Noise Suppression on Reference

241418fa

39

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

The error associated with the 10V excitation would be

–80ppm. Hence, overall reference error could be as high

as 130ppm, the average of the two.

is configured to provide 10V and –5V excitation to the

bridge, producing a common mode voltage at the input to

the LTC2414/LTC2418 of 2.5V, maximizing the AC input

range for applications where induced 60Hz could reach

Figure 47 shows a similar scheme to provide excitation

using resistor arrays to produce precise gain. The circuit

amplitudes up to 2V_RMS

.

15V

U1

15V

7

LTC1043

4

200Ω

10V

5V

3

2

8

7

+

LT1236-5

10V

0.1µF

20Ω

6

+

Q1

2N3904

LTC1150

1µF

11

12

47µF

*

–

4

–15V

33Ω

14

13

10µF

0.1µF

1k

17

10V

350Ω

BRIDGE

5V

0.1µF

9

V

CC

LTC2414/

LTC2418

REF

11

12

+

–10V

–

REF

33Ω

21

22

CH0

CH1

U2

15V

7

GND

15

LTC1043

Q2

2N3906

3

2

5

15

8

6

+

6

LTC1150

2

3

20Ω

*

–

4

–15V

18

0.1µF

1k

*FLYING CAPACITORS ARE

1µF FILM (MKP OR EQUIVALENT)

5V

U2

LTC1043

4

SEE LTC1043 DATA SHEET FOR

DETAILS ON UNUSED HALF OF U1

7

11

12

1µF

FILM

*

200Ω

14

13

–10V

17

–10V

2410 F52

Figure 46. LTC1043 Provides Precise 4X Reference for Excitation Voltages

241418fa

40

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

15V

5V

3

2

+

LT1236-5

C1

20Ω

1/2

LT1112

1

+

Q1

C3

47µF

2N3904

0.1µF

–

C1

0.1µF

22Ω

RN1

10k

10V

5V

1

2

3

9

RN1

10k

V

CC

4

350Ω BRIDGE

TWO ELEMENTS

VARYING

LTC2414/

LTC2418

11

+

REF

12

–

REF

21

22

CH0

CH1

–5V

8

RN1

10k

GND

15

RN1

10k

7

5

6

15V

C2

0.1µF

33Ω

×2

RN1 IS CADDOCK T914 10K-010-02

8

6

–

Q2, Q3

2N3906

×2

20Ω

1/2

LT1112

7

5

+

4

–15V

2410 F53

–15V

Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier

MULTIPLE CHANNEL USAGE

reduce the self-heating effects. R1 can also be broken into

two resistors, one 25k to set the excitation current and the

other a high accuracy 1k resistor to set the reference

voltage, assuming 100Ω platinum RTDs. This results in a

reduced reference voltage and a reduced common mode

difference between the reference and the input signal,

which improves the conversion linearity and reduces total

error.

The LTC2414/LTC2418 have up to sixteen input channels

and this feature provides a very flexible and efficient

solution in applications where more than one variable

need to be measured.

Measurements of a Ladder of Sensors

In industrial process, it is likely that a large group of real

world phenomena need to be monitored where the speed

is not critical. One example is the cracking towers in

petroleum refineries where a group of temperature mea-

surements need to be taken and related. This is done by

passing an excitation current through a ladder of RTDs.

TheconfigurationusingasingleLTC2418tomonitorupto

eight RTDs in differential mode is shown in Figure 48. A

high accuracy R1 is used to set the excitation current and

the reference voltage. A larger value of 25k is selected to

Each input should be taken close to the related RTD to

minimize the error caused by parasitic wire resistance.

TheinterferenceonasignaltransmissionlinefromRTDto

the LTC2418 is rejected due to the excellent common

moderejectionandthedigitalLPFincludedintheLTC2418.

It should be noted that the input source resistance of CHO

can have a maximum value of 800Ω • 8 = 6.4k, so the

parasitic capacitance and resistance of the connection

wires need to be minimized in order not to degrade the

converter performance.

241418fa

41

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

5V

Figure 49 shows the 4-wire SPI connection between the

LTC2414/LTC2418 and a PIC16F84 microcontroller. The

sample program for CC5X compiler in Figure 50 can be

used to program the PIC16F84 to control the LTC2414/

LTC2418. It uses PORT B to interface with the device.

0.1µF

+

10µF

11

9

V

CC

+

–

REF

R1

25k

12

21

22

23

24

7

0.1%

The program begins by declaring variables and allocating

four memory locations to store the 32-bit conversion

result. In execution, it first initiates the PORT B to the

proper SPI configuration and prepares channel address.

The LTC2414/LTC2418 is activated by setting the CS low.

Then the microcontroller waits until a logic LOW is de-

tectedonthedataline, signifyingend-of-conversion. After

a LOW is detected, a subroutine is called to exchange data

between the LTC2414/LTC2418 and the microcontroller.

The main loop ends by setting CS high, ending the data

output state.

LTC2418

CH0

CH1

CH2

CH3

PT1

100Ω

RTD

20

18

17

16

19

SDI

SCK

SDO

CS

PT2

100Ω

RTD

4-WIRE

SPI

•

CH14

CH15

PT8

100Ω

RTD

8

F

O

GND

15

The performance of the LTC2414/LTC2418 can be verified

using the demonstration board DC434A, see Figure 51 for

the schematic. This circuit uses the computer’s serial port

togeneratepowerandtheSPIdigitalsignalsnecessaryfor

starting a conversion and reading the result. It includes a

2418 F48

Figure 48. Measurement of a Ladder of Sensors Using

Differential Mode

Multichannel Bridge Digitizer and Digital Cold

Junction Compensation

PIC16F84

18

20

17

16

8

9

10

11

RB2

RB3

RB4

RB5

SCK

SDI

SDO

CS

The bridge application as shown in Figures 41, 42, and 43

can be expanded to multiple bridge transducers. Figure 54

shows the expansion for simple bridge measurement.

Also included is the temperature measurement.

LTC2414/

LTC2418

2414/18 F49

In Figure 54, CH0 to CH13 are configured as differential to

measureuptosevenbridgetransducersusingtheLTC2418.

CH14 and CH15 are configured as single-ended. CH14

measures the thermocouple while CH15 measures the

output of the cold junction sensor (diode, thermistor,

etc.). The measured cold junction sensor output is then

used to compensate the thermocouple output to find the

absolute temperature. The final temperature value may

then be used to compensate the temperature effects of the

bridge transducers.

Figure 49. Connecting the LTC2414/LTC2418 to

a PIC16F84 MCU Using the SPI Serial Interface

LabVIEW^TMapplication software program (see Figure 52)

which graphically captures the conversion results. It can

beusedtodeterminenoiseperformance,stabilityandwith

an external source linearity. As exemplified in the sche-

matic, the LTC2414/LTC2418 is extremely easy to use.

This demonstration board and associated software is

available by contacting Linear Technology.

Sample Driver for LTC2414/LTC2418 SPI Interface

The LTC2414/LTC2418 have a simple 4-wire serial inter-

face and it is easy to program microprocessors and

microcontrollers to control the device.

241418fa

42

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

// LTC2418 PIC16F84 Interface Example

// Written for CC5X Compiler

// Processor is PIC16F84 running at 10 MHz

#include <16f84.h>

#include <int16cxx.h>

#pragma origin = 0x4

#pragma config |= 0x3fff, WDTE=off,FOSC=HS

// global pin definitions:

#pragma bit rx_pin

#pragma bit tx_pin

#pragma bit sck

#pragma bit sdi

#pragma bit sdo

@ PORTB.0

@ PORTB.1

@ PORTB.2

@ PORTB.3

@ PORTB.4

@ PORTB.5

//input

//output

//input

//output

#pragma bit cs_bar

// Global Variables

uns8 result_3;

uns8 result_2;

uns8 result_1;

uns8 result_0;

// Conversion result MS byte

// ..

// Conversion result LS byte

void shiftbidir(char nextch);

// function prototype

void main( void)

{

INTCON=0b00000000;

TRISA=0b00000000;

TRISB=0b00010001;

// no interrupts

// all PORTA pins outputs

// according to definitions above

char channel;

// next channel to send

while(1)

{

/* channel bit fields are 7:6, 10 always; 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */

channel = 0b10101000;

cs_bar=0;

// CH0,1 DIFF.

// activate ADC

while(sdo==1)

{

// test for end of conversion

// wait if conversion is not complete

}

shiftbidir(channel);

cs_bar = 1;

// read ADC, send next channel

// deactivate ADC

/* At this point global variables result 3,2,1 contain the 24 bit conversion result. Variable result3

contains the corresponding channel information in the following fields:

bits 7:6, 00 always, 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */

}

// end of loop

}

// end of main

Figure 50. Sample Program in CC5X for PIC16F84

241418fa

43

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

////////// Bidirectional Shift Routine for ADC //////////

void shiftbidir(char nextch)

{

int i;

for(i=0;i<2;i++)

// send config bits 7:6,

// ignore EOC/ and DMY bits

{

sdi=nextch.7;

nextch = rl(nextch);

sck=1;

sck=0;

// put data on pin

// get next config bit ready

// clock high

// clock low

}

for(i=0;i<8;i++)

{

// send config, read byte 3

sdi=nextch.7;

// put data on pin

nextch = rl(nextch);

// get next config bit ready

result_3 = rl(result_3);// get ready to load lsb

result_3.0 = sdo;

sck=1;

sck=0;

// load lsb

// clock high

// clock low

}

for(i=0;i<8;i++)

{

// read byte 2

result_2 = rl(result_2);// get ready to load lsb

result_2.0 = sdo;

sck=1;

sck=0;

// load lsb

// clock high

// clock low

}

for(i=0;i<8;i++)

{

// read byte 1

result_1 = rl(result_1);// get ready to load lsb

result_1.0 = sdo;

sck=1;

sck=0;

// load lsb

// clock high

// clock low

}

result_0=0;

for(i=0;i<6;i++)

// ensure bits 7:6 are zero

// read byte 0

{

result_0 = rl(result_0);// get ready to load lsb

result_0.0 = sdo;

sck=1;

// load lsb

// clock high

sck=0;

// clock low

}

Figure 50. Sample Program in CC5X for PIC16F84 (cont)

241418fa

44

LTC2414/LTC2418

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APPLICATIO S I FOR ATIO

U

REMOVE TO

DISCONNECT

V

D1

BAV74LT1

CC

JP1

V

U1

CC

V

AND

JMPR

U2

CC

5V REF

E1

1

LT1460ACN8-2.5

R1

LT1236ACN8-5

V

2.5V

EXT

CC

V

CC

10Ω

1

3

V

IN

V

IN

OUT

E2

+

C2

2

3

C1

10µF

35V

C3

10µF

35V

+

C4

NC

GND

22µF

GND

100µF

16V

25V

R2

3Ω

JP2

JMPR

P1

DB9

BANANA

JACK

J1

2.5V 5V

2

1

3

1

6

2

7

3

8

4

9

5

JP3

JMPR

VEX

U3E

U3F

R3

V

CC

50Hz/60Hz

2

74HC14

J2

J3

51k

E3

1

3

+

–

V

CC

REF

+

C5

10µF

35V

JP4

C6

0.1µF

JMPR

J4

2

1

3

JP5

GND

U3B

74HC14

U3A

74HC14

9

E4

R4

51k

JMPR

GND

V

GND NC

CC

U5

LTC2418CGN

2

4

6

8

11

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

19

18

17

16

20

REF+

REF–

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

F

U3C

U3D

74HC14

R6

3k

R5

49.9Ω

O

12

21

22

23

24

25

26

27

28

1

2

3

4

5

6

7

8

74HC14

SCK

SDO

CS

10

SDI

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

R7

V

CC

22k

P2

CON40A

10

11

12

13

14

3

4

5

6

2

16

Q1

MMBT3904LT1

V

CC

SER

A

B

C

D

E

F

G

H

R8

51k

U4

74HC165

V

CC

13

14

15

NC

GND

9

7

8

QH

GND

CLK

INH

SH/LD

C7

C8

0.1µF

15

1

0.1µF

V

CC

COM

10

BYPASS

CAPACITOR

FOR U3 AND U4

2

JP6

JMPR

1

3

2414/18 F51

GND NC

Figure 51. Demo Board Schematic

241418fa

45

LTC2414/LTC2418

W U U

U

APPLICATIO S I FOR ATIO

Figure 52. LTC2418 Demo Program Display

Bottom Layer

Top Layer

Top Silkscreen

Figure 53. PCB Layout and Film

241418fa

46

LTC2414/LTC2418

U

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

0.386 – 0.393*

(9.804 – 9.982)

0.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0.004 – 0.009

0.015 ± 0.004

(0.38 ± 0.10)

0.053 – 0.069

× 45°

(1.351 – 1.748)

(0.102 – 0.249)

0.0075 – 0.0098

(0.191 – 0.249)

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.008 – 0.012

(0.203 – 0.305)

0.0250

(0.635)

BSC

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN28 (SSOP) 1098

241418fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

47

LTC2414/LTC2418

U

TYPICAL APPLICATIO

5V

0.1µF

+

10µF

9

V

CC

11

+

REF

LTC2418

–

12

21

REF

LTC2418

CH0

THERMOCOUPLE

THERMISTOR

20

18

17

16

19

22

23

24

7

CH1

SDI

SCK

SDO

CS

CH2

CH3

•

CH14

CH15

COM

8

F

O

10

GND

15

2418 F54

Figure 54. Multichannel Bridge Digitizer and Digital Cold Junction Compensation

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1019

Precision Bandgap Reference, 2.5V, 5V

Micropower Thermocouple Cold Junction Compensator

Precision Chopper Stabilized Op Amp

3ppm/°C Drift, 0.05% Max Initial Accuracy

80µA Supply Current, 0.5°C Initial Accuracy

LT1025

LTC1050

No External Components 5µV Offset, 1.6µV Noise

P-P

LT1236A-5

LT1460

Precision Bandgap Reference, 5V

0.05% Max Initial Accuracy, 5ppm/°C Drift

Micropower Series Reference

0.075% Max Initial Accuracy, 10ppm/°C Max Drift

LTC2400

24-Bit, No Latency ∆Σ ADC in SO-8

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411

LTC2401/LTC2402

LTC2404/LTC2408

LTC2410

1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

24-Bit, Fully Differential, No Latency ∆Σ ADC

24-Bit, Fully Differential, No Latency∆Σ ADC in MSOP

24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC

24-Bit, Fully Differential, No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate

20-Bit, No Latency ∆Σ ADC in SO-8

LTC2411

LTC2411-1

LTC2413

Simultaneous 50Hz and 60Hz Rejection, 800nV

Pin Compatible with the LTC2410/LTC2413

Noise

RMS

LTC2415/LTC2415-1

LTC2420

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

1.2ppm Noise, Pin Compatible with LTC2404/LTC2408

LTC2424/LTC2428

4-/8-Channel, 20-Bit, No Latency ∆Σ ADC

241418fa

LT 1105 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

48

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2414CGN
厂家：	Linear
描述：	8-/16-Channel 24-Bit No Latency TM ADCs 8位/ 16通道24位无延迟TM的ADC
文件：	总48页 (文件大小：787K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2414CGN [Linear]

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