LTC2415-1IGN#TRPBF [Linear]
LTC2415 - 24-Bit No Latency Delta Sigma ADC with Differential Input and Differential Reference; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC2415-1IGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC2415 - 24-Bit No Latency Delta Sigma ADC with Differential Input and Differential Reference; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总42页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2415/LTC2415-1
™
24-Bit No Latency ∆Σ
ADCs with Differential Input and
Differential Reference
DESCRIPTION
FEATURES
The LTC®2415/2415-1 are micropower 24-bit differential
∆Σ analog to digital converters with integrated oscillator,
2ppm INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply
range.Theyusedelta-sigmatechnologyandprovidesingle
cycle settling time for multiplexed applications. Through a
single pin, the LTC2415 can be configured for better than
110dB input differential mode rejection at 50Hz or 60Hz
2ꢀ, or it can be driven by an external oscillator for a
user defined rejection frequency. The LTC2415-1 can be
configured for better than 87dB input differential mode
rejectionovertherangeof49Hzto61.2Hz(50Hzand60Hz
2ꢀ simultaneously). The internal oscillator requires no
external frequency setting components.
n
2× Speed Up Version of the LTC2410/LTC2413:
15Hz Output Rate, 50Hz or 60Hz Notch—LTC2415;
13.75Hz Output Rate, Simultaneous 50Hz/60Hz
Notch—LTC2415-1
n
Differential Input and Differential Reference with
GND to V Common Mode Range
CC
n
n
n
n
2ppm INL, No Missing Codes
2.5ppm Gain Error
0.23ppm Noise
Single Conversion Settling Time for Multiplexed
Applications
n
n
Internal Oscillator—No External Components
Required
24-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)
The converters accept any external differential reference
voltage from 0.1V to V for flexible ratiometric and re-
CC
n
n
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200µA) and Auto Shutdown
mote sensing measurementconfigurations. The full-scale
differential input range is from –0.5V
to 0.5V . The
REF
REF
reference common mode voltage, V
, and the input
REFCM
APPLICATIONS
n
common mode voltage, V
, may be independently set
anywhere within the GND to V range of the LTC2415/
INCM
CC
Direct Sensor Digitizer
LTC2415-1. The DC common mode input rejection is
n
Weight Scales
better than 140dB.
n
Direct Temperature Measurement
Gas Analyzers
Strain Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
6-Digit DVMs
n
The LTC2415/LTC2415-1 communicate through a flexible
3-wire digital interface which is compatible with SPI and
MICROWIRE protocols.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load
and No Latency ∆Σ are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
n
n
n
n
n
TYPICAL APPLICATION
V
CC
1µF
2.7V TO 5.5V
V
CC
1µF
= INTERNAL OSC/50Hz REJECTION (LTC2415)
2
14
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2415)
= INTERNAL 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
O
2
3
LTC2415/
+
REF
V
12 SDO
13 SCK
11 CS
CC
LTC2415-1
+
BRIDGE
IMPEDANCE
100Ω TO 10k
5
+
3
4
IN
IN
13
3-WIRE
SPI INTERFACE
REFERENCE
VOLTAGE
LTC2415/
REF
REF
SCK
6
–
LTC2415-1
–
0.1V TO V
CC
–
3-WIRE
SPI INTERFACE
4
REF
GND
F
O
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
1, 7, 8
9, 10,
15, 16
14
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
2415 TA02
2415 TA01
2415fa
1
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltage (V ) to GND....................... –0.3V to 7V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
GND
Analog Input Pins Voltage
V
CC
+
to GND......................................–0.3V to (V + 0.3V)
CC
F
O
REF
REF
IN
Reference Input Pins Voltage
–
+
–
SCK
SDO
CS
to GND......................................–0.3V to (V + 0.3V)
CC
Digital Input Voltage to GND .........–0.3V to (V + 0.3V)
CC
IN
Digital Output Voltage to GND.......–0.3V to (V + 0.3V)
CC
GND
GND
GND
GND
Operating Temperature Range
LTC2415C/LTC2415-1C ............................ 0°C to 70°C
LTC2415I/LTC2415-1I ..........................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
GN PACKAGE
16-LEAD PLASTIC SSOP
= 125°C, θ = 95°C/W
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC2415CGN#PBF
LTC2415IGN#PBF
LTC2415-1CGN#PBF
LTC2415-1IGN#PBF
TAPE AND REEL
PART MARKING
2415
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
TEMPERATURE RANGE
0°C to 70°C
LTC2415CGN#TRPBF
LTC2415IGN#TRPBF
LTC2415-1CGN#TRPBF
LTC2415-1IGN#TRPBF
2415I
–40°C to 85°C
0°C to 70°C
24151
24151I
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
24
Bits
REF
CC
REF
IN
–
REF
+
+
Integral Nonlinearity
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
1
2
5
ppm of V
ppm of V
ppm of V
CC
INCM
REF
REF
REF
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
14
2
CC
INCM
= 1.25V, (Note 6)
+
–
REF = 2.5V, REF = GND, V
INCM
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
0.5
mV
CC
+
–
GND ≤ IN = IN ≤ V , (Note 14)
CC
+
–
Offset Error Drift
Positive Gain Error
Positive Gain Error Drift
Negative Gain Error
2.5V ≤ REF ≤ V , REF = GND,
20
nV/°C
CC
+
–
GND ≤ IN = IN ≤ V
CC
+
–
●
●
2.5V ≤ REF ≤ V , REF = GND,
2.5
0.03
2.5
12
12
ppm of V
REF
CC
+
+
–
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V /°C
REF
CC
+
+
–
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V
REF
CC
+
+
–
+
IN = 0.25 • REF , IN = 0.75 • REF
2415fa
2
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ppm of V /°C
+
–
Negative Gain Error Drift
2.5V ≤ REF ≤ V , REF = GND,
0.03
CC
REF
+
+
–
+
IN = 0.25 • REF , IN = 0.75 • REF
+
–
Output Noise
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND,
1.1
µV
RMS
CC
–
+
GND ≤ IN = IN ≤ V , (Note 13)
CC
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
l
l
l
l
l
l
l
l
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
130
140
dB
CC
–
+
GND ≤ IN = IN ≤ V
CC
+
–
Input Common Mode Rejection
60Hz 2ꢀ (LTC2415)
2.5V ≤ REF ≤ V , REF = GND,
140
140
110
110
140
87
dB
dB
dB
dB
dB
dB
dB
CC
–
+
GND ≤ IN = IN ≤ V , (Note 7)
CC
+
–
Input Common Mode Rejection
50Hz 2ꢀ (LTC2415)
2.5V ≤ REF ≤ V , REF = GND,
CC
–
+
GND ≤ IN = IN ≤ V , (Note 8)
CC
Input Normal Mode Rejection
60Hz 2ꢀ (LTC2415)
(Note 7)
140
140
Input Normal Mode Rejection
50Hz 2ꢀ (LTC2415)
(Note 8)
+
–
Input Common Mode Rejection
49Hz to 61.2Hz (LTC2415-1)
2.5V ≤ REF ≤ V , REF = GND,
CC
Input Normal Mode Rejection
49Hz to 61.2Hz (LTC2415-1)
F = GND
O
Input Normal Mode Rejection
External Oscillator
87
External Clock f /2560 14ꢀ
EOSC
(LTC2415-1)
l
l
Input Normal Mode Rejection
External Oscillator
110
130
140
140
dB
dB
External Clock f
(LTC2415-1)
/2560 4ꢀ
EOSC
+
–
Reference Common Mode
Rejection DC
2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,
CC
–
+
V
= 2.5V, IN = IN = GND
REF
+
–
–
+
Power Supply Rejection, DC
REF = V , REF = GND, IN = IN = GND
100
120
120
dB
dB
dB
CC
+
–
–
+
Power Supply Rejection, 60Hz 2ꢀ REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)
+
–
–
+
Power Supply Rejection, 50Hz 2ꢀ REF = 2.5V, REF = GND, IN = IN = GND, (Note 8)
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
●
●
●
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
V
Input Differential Voltage Range
–V /2
REF
V
IN
REF
+
–
(IN – IN )
+
–
+
●
●
●
REF
REF
Absolute/Common Mode REF Voltage
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
V
Reference Differential Voltage Range
V
CC
REF
+
–
(REF – REF )
2415fa
3
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
18
18
18
18
1
MAX
UNITS
pF
+
+
C (IN )
IN Sampling Capacitance
S
–
–
C (IN )
IN Sampling Capacitance
pF
S
+
+
C (REF )
REF Sampling Capacitance
pF
S
–
–
C (REF )
REF Sampling Capacitance
pF
S
+
+
+
●
●
●
●
I
I
I
I
(IN ) IN DC Leakage Current
CS = V , IN = GND
–10
–10
–10
–10
10
10
10
10
nA
DC_LEAK
DC_LEAK
DC_LEAK
DC_LEAK
CC
–
–
–
(IN ) IN DC Leakage Current
CS = V , IN = GND
1
nA
CC
+
+
+
(REF ) REF DC Leakage Current
CS = V , REF = 5V
1
nA
CC
–
–
–
(REF ) REF DC Leakage Current
CS = V , REF = GND
1
nA
CC
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3)
SYMBOL PARAMETER
CONDITIONS
2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
●
●
●
●
●
●
V
IH
V
IL
V
IH
V
IL
High Level Input Voltage
CS, F
2.5
2.0
V
V
V
V
V
V
V
V
µA
µA
pF
pF
V
CC
2.7V ≤ V ≤ 3.3V
O
CC
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
0.6
CC
2.7V ≤ V ≤ 5.5V
O
CC
High Level Input Voltage
SCK
Low Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 9)
2.5
2.0
CC
2.7V ≤ V ≤ 3.3V (Note 9)
CC
4.5V ≤ V ≤ 5.5V (Note 9)
0.8
0.6
10
CC
2.7V ≤ V ≤ 5.5V (Note 9)
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
IN
IN
CS, F
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 9)
10
IN
IN
CC
C
C
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
High Level Output Voltage
SDO
Low Level Output Voltage
SDO
(Note 9)
IN
●
●
I = –800µA
O
V
V
– 0.5
OH
OL
CC
I = 1.6mA
O
0.4
V
●
●
●
V
V
High Level Output Voltage
SCK
Low Level Output Voltage
SCK
I = –800µA (Note 10)
O
– 0.5
V
V
OH
OL
CC
I = 1.6mA (Note 10)
O
0.4
10
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Supply Voltage
Supply Current
2.7
5.5
V
CC
I
CC
l
l
Conversion Mode
Sleep Mode
CS = 0V (Note 12)
200
20
300
30
µA
µA
CS = V (Note 12)
CC
2415fa
4
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL PARAMETER
CONDITIONS
MIN
2.56
0.25
0.25
TYP
MAX
500
390
390
UNITS
kHz
µs
l
l
l
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time (LTC2415)
EOSC
HEO
µs
LEO
l
l
l
F = 0V
65.43
78.52
66.77
80.12
EOSC
72.8
EOSC
68.1
81.72
ms
ms
ms
CONV
O
F = V
O
CC
External Oscillator (Note 11)
10278/f
(in kHz)
l
l
Conversion Time (LTC2415-1)
Internal SCK Frequency
F = 0V
71.3
74.3
ms
ms
O
External Oscillator (Note 11)
10278/f
(in kHz)
f
Internal Oscillator (Note 10), LTC2415
Internal Oscillator (Note 10), LTC2415-1
External Oscillator (Notes 10, 11)
19.2
17.5
kHz
kHz
kHz
ISCK
f
/8
EOSC
l
l
l
l
D
Internal SCK Duty Cycle
(Note 10)
(Note 9)
(Note 9)
(Note 9)
45
55
ꢀ
kHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
External SCK High Period
2000
ESCK
250
250
LESCK
ns
HESCK
DOUT_ISCK
l
l
l
Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12), LTC2415
Internal Oscillator (Notes 10, 12), LTC2415-1
1.64
1.80
1.67
1.83
EOSC
1.70
1.86
ms
ms
ms
External Oscillator (Notes 10, 11)
256/f
(in kHz)
l
l
l
l
l
l
l
l
l
t
t
External SCK 32-Bit Data Output Time (Note 9)
CS ↓ to SDO Low Z
32/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
0
0
200
200
200
1
t2
t3
t4
t
CS ↑ to SDO High Z
(Note 10)
(Note 9)
0
CS ↓ to SCK ↓
50
CS ↓ to SCK ↑
220
50
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
KQMAX
t
(Note 5)
15
50
KQMIN
t
t
5
6
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: F = V (internal oscillator) or f
oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
= 128000Hz 2ꢀ (external
O
CC
EOSC
Note 2: All voltage values are with respect to GND.
SCK during the data output is f
and is expressed in kHz.
ESCK
Note 3: V = 2.7 to 5.5V unless otherwise specified.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
CC
+
–
+
–
V
V
= REF – REF , V
= (REF + REF )/2;
= (IN + IN )/2.
REF
REFCM
+
–
+
–
= IN – IN , V
has a total equivalent load capacitance C
= 20pF.
IN
INCM
LOAD
Note 4: F pin tied to GND or to V or to external conversion clock source
Note 11: The external oscillator is connected to the F pin. The external
O
CC
O
with f
= 153600Hz unless otherwise specified.
oscillator frequency, f , is expressed in kHz.
EOSC
EOSC
Note 5: Guaranteed by design, not subject to test.
Note 12: The converter uses the internal oscillator.
F = 0V or F = V
Note 13: The output noise includes the contribution of the internal
.
CC
O
O
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
calibration operations.
Note 7: F = 0V (internal oscillator) or f
oscillator).
= 153600Hz 2ꢀ (external
Note 14: Refer to Offset Accuracy and Drift in the Applications Information
section.
O
EOSC
2415fa
5
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
Total Unadjusted Error Over
Temperature (VCC = 5V,
VREF = 5V)
Total Unadjusted Error Over
Temperature (VCC = 5V,
VREF = 2.5V)
Total Unadjusted Error Over
Temperature (VCC = 2.7V,
VREF = 2.5V)
106.5
106.0
105.5
105.0
104.5
104.0
103.5
215
213
211
209
207
205
125
121
117
113
109
105
V
V
V
= 5V
+
–
CC
T
= 90°C
V
V
V
= 2.7V
REF = 2.5V
A
CC
= 5V
REF
= 2.5V
REF = GND
T = 90°C
A
REF
= 2.5V
INCM
= 1.25V
F = GND
+
INCM
O
REF = 5V
–
T
= 90°C
A
REF = GND
F
= GND
O
T
= 25°C
A
V
V
V
= 5V
CC
T
T
= –45°C
T
= 25°C
A
A
A
= 2.5V
REF
= 1.25V
INCM
+
= 25°C
REF = 2.5V
T
= –45°C
A
–
T
= –45°C
A
REF = GND
F
= GND
O
–1.25 –0.75 –0.25
V
0.25
(V)
0.75
1.25
–1.25 –0.75 –0.25
0.25
(V)
IN
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
V
0
(V)
0.5
1
1.5
2
2.5
V
IN
IN
2415 G02
2415 G03
2415 G01
Integral Nonlinearity Over
Temperature (VCC = 5V,
VREF = 5V)
Integral Nonlinearity Over
Temperature (VCC = 5V,
VREF = 2.5V)
Integral Nonlinearity Over
Temperature (VCC = 2.7V,
VREF = 2.5V)
10
8
1.5
1.0
2.5
2.0
+
–
V
V
V
= 5V
= 5V
V
V
V
= 5V
REF = 2.5V
CC
REF
CC
T
= 90°C
A
T
T
= –45°C
= 25°C
= 2.5V
REF = GND
A
A
REF
= 2.5V
= 1.25V
F = GND
O
INCM
INCM
6
1.5
+
REF = 5V
T
= 25°C
A
–
REF = GND
F
4
1.0
0.5
= GND
O
2
0.5
0
0
0
T
T
= 25°C
A
A
T
= 90°C
–2
–4
–6
–8
–10
A
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
= –45°C
T
= 90°C
A
+
–
V
V
V
= 2.7V
REF = 2.5V
CC
T
= –45°C
A
= 2.5V
REF = GND
REF
INCM
= 1.25V
F = GND
O
–1.25 –0.75 –0.25
V
0.25
(V)
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
V
0
0.5
1
1.5
2
2.5
–0.75 –0.25
V
0.25
(V)
0.75
1.25
–1.25
(V)
IN
IN
IN
2415 G06
2415 G04
2415 G05
Noise Histogram
Noise Histogram
Noise Histogram
(Output Rate = 15Hz,
VCC = 5V, VREF = 5V)
(Output Rate = 45Hz,
VCC = 5V, VREF = 5V)
(Output Rate = 15Hz,
VCC = 5V, VREF = 2.5V)
12
10
8
12
10
8
10
8
10,000 CONSECUTIVE GAUSSIAN
READINGS
10,000 CONSECUTIVE
READINGS
GAUSSIAN
10,000 CONSECUTIVE
READINGS
GAUSSIAN
DISTRIBUTION
DISTRIBUTION
m = –103.5ppm
σ = 0.27ppm
DISTRIBUTION
m = –104.0ppm
σ = 0.25ppm
V
V
V
= 5V
m = –209.2ppm
V
V
V
= 5V
= 5V
V
V
V
= 5V
= 5V
CC
CC
REF
IN
CC
REF
= 0V
IN
= 2.5V
σ = 0.56ppm
REF
= 0V
= 0V
IN
+
+
+
REF = 2.5V
REF = 5V
REF = 5V
–
–
–
REF = GND
6
REF = GND
REF = GND
+
–
+
–
+
–
IN = 1.25V
IN = 2.5V
IN = 2.5V
6
6
IN = 1.25V
IN = 2.5V
IN = 2.5V
F
= GND
= 25C
F
= GND
= 25°C
F
= 460800Hz
T = 25°C
A
O
A
O
A
4
O
T
T
4
4
2
2
2
0
0
0
–212
–210.5
–209
–207.5
–206
–105.5
–104.8
–104
–103.3
–102.5
–105
–104.5
–104
–103.5
–103
OUTPUT CODE (ppm OF V
)
OUTPUT CODE (ppm OF V
)
OUTPUT CODE (ppm OF V
)
REF
REF
REF
2415 G10
2415 G07
2415 G08
2415fa
6
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
Noise Histogram
Noise Histogram
Noise Histogram
(Output Rate = 45Hz,
VCC = 2.7V, VREF = 2.5V)
10
(Output Rate = 45Hz,
VCC = 5V, VREF = 2.5V)
(Output Rate = 15Hz,
VCC = 2.7V, VREF = 2.5V)
12
10
8
12
10
8
10,000 CONSECUTIVE
READINGS
GAUSSIAN
10,000 CONSECUTIVE
READINGS
GAUSSIAN
10,000 CONSECUTIVE
READINGS
GAUSSIAN
DISTRIBUTION
m = –113.1ppm
σ = 0.59ppm
DISTRIBUTION
m = –209.3ppm
σ = 0.49ppm
DISTRIBUTION
m = –109.8ppm
σ = 0.50ppm
V
V
V
= 2.7V
= 2.5V
V
V
V
= 5V
CC
REF
IN
V
V
V
= 2.7V
= 2.5V
CC
REF
IN
CC
REF
IN
8
6
4
2
0
= 2.5V
= 0V
= 0V
= 0V
+
+
+
REF = 2.5V
REF = 2.5V
REF = 2.5V
–
–
–
REF = GND
REF = GND
REF = GND
+
–
+
–
+
–
IN = 1.25V
IN = 1.25V
IN = 1.25V
6
6
IN = 1.25V
IN = 1.25V
IN = 1.25V
F
= GND
= 25°C
F
= 460800Hz
= 25°C
O
T
F
= 460800Hz
= 25°C
A
O
T
O
A
T
4
A
4
2
2
0
0
–116
–114.5
–113
–111.5
–110
–211.5
–210.5
–209.5
–208.5
–207.5
–112
–110.9
–109.8
–108.6
–107.5
OUTPUT CODE (ppm OF V
)
OUTPUT CODE (ppm OF V
)
REF
OUTPUT CODE (ppm OF V
)
REF
REF
2415 G13
2415 G11
2415 G14
Long-Term Histogram
(60Hrs)
Consecutive ADC Readings vs
Time
RMS Noise vs Input Differential
Voltage
12
10
8
0.5
0.4
0.3
0.2
0.1
0
–101.0
V
V
V
= 5V
= 5V
GAUSSIAN
CC
REF
IN
+
V
V
V
= 5V
IN = 2.5V
CC
DISTRIBUTION
m = –103.9ppm
σ = 0.27ppm
–101.5
–102.0
–102.5
–103.0
–103.5
–104.0
–104.5
–105.0
–105.5
–
= 5V
IN = 2.5V
REF
= 0V
+
= 0V
F
= GND
T = 25°C
A
IN
O
REF = 5V
+
–
REF = 5V
REF = GND
–
+
–
REF = GND
IN = 2.5V
IN = 2.5V
F
= GND
= 25°C
O
A
6
T
V
V
V
= 5V
CC
= 5V
REF
= 2.5V
4
INCM
+
REF = 5V
–
REF = GND
2
F
= GND
= 25°C
O
A
T
0
–103
–103.5
OUTPUT CODE (ppm OF V
–104
–104.5
–105
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
0
5
10 15 20 25 30 35 40 45 50 55 60
TIME (HRS)
)
INPUT DIFFERENTIAL VOLTAGE (V)
REF
2415 G16
2415 G18
2415 G17
RMS Noise vs VINCM
RMS Noise vs Temperature (TA)
RMS Noise vs VCC
1800
1600
1400
1200
1000
1400
1250
1100
950
1560
1520
1480
1440
1400
1360
1320
1280
+
V
V
V
= 5V
IN = V
CC
INCM
INCM
–
= 5V
IN = V
REF
= 0V
F = GND
O
IN
+
REF = 5V
T = 25°C
A
–
REF = GND
V
= 2.5V
V
V
= 5V
REF
CC
IN
+
REF = 2.5V
= 0V
–
+
REF = GND
REF = 5V
+
–
–
IN = GND
REF = GND
+
–
IN = GND
IN = 2.5V
F
= GND
= 25°C
IN = 2.5V
O
A
T
F
= GND
O
800
–0.5 0 0.5
1
1.5
2
2.5
3
3.5
4
4.5 5 5.5
–50
–25
0
25
50
75
100
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
V
INCM
(V)
TEMPERATURE (°C)
V
CC
2415 G19
2415 G20
2415 G21
2415fa
7
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise vs VREF
Offset Error vs VINCM
Offset Error vs Temperature (TA)
–103.8
–104.0
–104.2
–104.4
–104.6
1600
1400
1200
1000
800
–103.0
–103.4
–103.8
–104.2
–104.6
–105.0
V
V
V
= 5V
CC
= 5V
REF
= 0V
IN
+
REF = 5V
–
REF = GND
IN = V
IN = V
+
–
INCM
INCM
= GND
= 25°C
F
O
A
V
V
= 5V
T
CC
IN
= 0V
V
= 5V
CC
+
–
REF = 5V
REF = GND
–
+
–
REF = GND
IN = GND
IN = GND
+
–
IN = 2.5V
IN = 2.5V
F
= GND
= 25°C
O
A
F
= GND
O
T
–50
–25
0
25
50
75
100
0
0.5
1
1.5
2
V
2.5
(V)
3
3.5
4
4.5
5
–0.5 0 0.5
1
1.5
2
2.5
3
3.5 4 4.5 5 5.5
TEMPERATURE (°C)
V
INCM
(V)
REF
2415 G24
2415 G22
2415 G23
+Full-Scale Error vs
Temperature (TA)
Offset Error vs VCC
Offset Error vs VCC and VREF
–103.2
–103.6
–104.0
–104.4
–104.8
–105.2
–110
–130
–150
–170
–190
–210
–230
3
2
V
= 2.5V
REF
+
REF = 2.5V
–
REF = GND
+
–
IN = GND
IN = GND
1
F
= GND
= 25°C
O
A
T
0
V
= 5V
CC
+
–1
–2
–3
REF = 5V
–
REF = GND
+
–
IN = 2.5V
IN = GND
F
= GND
O
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
AND V (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
–45 –30 –15
0
15 30 45 60 75 90
V
CC
V
CC
TEMPERATURE (°C)
REF
2415 G26
2415 G25
2415 G27
–Full-Scale Error vs
Temperature (TA)
+Full-Scale Error vs VCC
+Full-Scale Error vs VREF
5
8
4
0
–1
–2
–3
–4
–5
–6
V
= 2.5V
REF
+
REF = 2.5V
–
4
3
2
1
0
REF = GND
+
–
IN = 1.25V
IN = GND
F
= GND
= 25°C
O
A
T
0
V
= 5V
CC
+
REF = V
V
= 5V
REF
CC
–
+
REF = GND
REF = 5V
+
–
+
–
IN = 0.5 • REF
REF = GND
–4
–8
+
–
IN = GND
IN = GND
F
= GND
= 25°C
IN = 2.5V
O
A
T
F
= GND
O
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
0.5
1
1.5
2
2.5
3
(V)
3.5
4
4.5
5
–45 –30 –15
0
15 30 45 60 75 90
V
CC
V
REF
TEMPERATURE (°C)
2415 G28
2415 G29
2415 G30
2415fa
8
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
–Full-Scale Error vs VCC
–Full-Scale Error vs VREF
PSRR vs Frequency at VCC
0
–1
–2
–3
–4
–5
8
4
0
V
= 4.1V DC + 1.4V AC
CC
+
REF = 2.5V
–20
–40
–
REF = GND
IN = IN = GND
+
–
F
= GND
= 25°C
O
A
T
0
–60
V
= 5V
V
= 2.5V
CC
REF
+
+
–4
–8
–12
REF = V
REF = 2.5V
REF
–
–
REF = GND
REF = GND
–80
+
–
+
–
IN = GND
IN = GND
+
IN = 0.5 • REF
IN = 1.25V
–100
–120
F
= GND
= 25°C
F
= GND
= 25°C
O
A
O
A
T
T
0.5
1
1.5
2
2.5
V
3
(V)
3.5
4
4.5
5
0
50
100
150
200
250
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
FREQUENCY AT V (Hz)
V
CC
CC
REF
2415 G32
2415 G33
2415 G31
Conversion Current vs
Temperature (TA)
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
0
–20
220
210
200
190
180
170
160
150
140
0
–20
+
+
REF = 2.5V
V
V
V
= V
V
= 4.1V DC + 0.7V AC
REF
CC
CC
–
–
+
REF = GND
= GND
REF = 2.5V
REF
+
–
+
–
–
IN = IN = GND
= V = GND
REF = GND
IN = IN = GND
IN
IN
V
CC
= 5.5V
+
–
F
= GND
= 25°C
O
A
T
F
= GND
= 25°C
–40
–40
O
A
F
= GND
T
O
CS = GND
V
V
= 4.1V
= 2.7V
CC
CC
–60
–60
SCK = SDO = N/C
–80
–80
–100
–120
–100
–120
1
100
10000
1000000
–45 –30 –15
0
15 30 45 60 75 90
15200
15300
15400
15500
FREQUENCY AT V (Hz)
TEMPERATURE (°C)
FREQUENCY AT V (Hz)
CC
CC
2415 G34
2415 G36
2415 G35
Conversion Current vs Output
Data Rate
Sleep Current vs
Temperature (TA)
1000
900
800
700
600
500
400
300
200
100
0
25
24
23
22
21
20
19
18
17
16
15
+
–
V
= 5V
CC
V
V
V
= V
CC
REF
+
REF = 5V
= GND
REF
–
+
–
REF = GND
= V = GND
= GND
CS = V
SCK = SDO = N/C
IN
IN
+
–
IN = GND
F
O
IN = GND
CC
F
= EXT OSC
O
CS = GND
SCK =N/C
SDO = N/C
V
V
= 5.5V
= 2.7V
CC
CC
V
CC
= 4.1V
0
10
20
30
40
50
–45 –30 –15
0
15 30 45 60 75 90
OUTPUT DATA RATE (READINGS/SEC)
TEMPERATURE (°C)
2415 G37
2415 G38
2415fa
9
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
PIN FUNCTIONS
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
SDO (Pin 12): Three-State Digital Output. During the Data
pins internally connected for optimum ground current
Output period, this pin is used as serial data output. When
flow and V decoupling. Connect each one of these pins
the chip select CS is HIGH (CS = V ) the SDO pin is in a
CC
CC
to a ground plane through a low impedance connection.
All seven pins must be connected to ground for proper
operation.
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
V
(Pin 2): Positive Supply Voltage. Bypass to GND
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
fortheinternalserialinterfaceclockduringtheDataOutput
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. A weak internal pull-up is
automatically activated in Internal Serial Clock Operation
mode. The Serial Clock Operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
CC
(Pin 1) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
+
–
REF (Pin 3), REF (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
+
GNDandV aslongasthereferencepositiveinput, REF ,
CC
is maintained more positive than the reference negative
–
input, REF , by at least 0.1V.
+
–
IN (Pin 5), IN (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
F (Pin 14): Frequency Control Pin. Digital input that
O
GND – 0.3V and V + 0.3V. Within these limits the con-
CC
controlstheADC’snotchfrequenciesandconversiontime.
+
–
verter bipolar input range (V = IN – IN ) extends from
IN
When the F pin is connected to V (LTC2415 only), the
O
CC
–0.5 • (V ) to 0.5 • (V ). Outside this input range the
REF
REF
converter uses its internal oscillator and the digital filter
converter produces unique overrange and underrange
first null is located at 50Hz. When the F pin is connected
O
output codes.
to GND (F = OV), the converter uses its internal oscillator
O
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
and the digital filter first null is located at 60Hz (LTC2415)
or simultaneous 50Hz/60Hz (LTC2415-1). When F is
O
EOSC
driven by an external clock signal with a frequency f
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
/2560.
EOSC
2415fa
10
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
F
O
(INT/EXT)
+
IN
IN
+
–
–
∫
∫
∫
SDO
SERIAL
INTERFACE
∑
ADC
SCK
CS
+
REF
REF
–
DECIMATING FIR
–
+
DAC
2415 FD
Figure 1. Functional Block Diagram
TEST CIRCUITS
SDO
V
CC
1.69k
C
= 20pF
LOAD
1.69k
C
SDO
Hi-Z TO V
OH
OH
V
V
TO V
TO Hi-Z
= 20pF
OL
OH
LOAD
2415 TA03
Hi-Z TO V
OL
V
V
TO V
OL
OH
OL
TO Hi-Z
2415 TA04
2415fa
11
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
CONVERTER OPERATION
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
Converter Operation Cycle
The LTC2415/LTC2415-1 are low power, delta-sigma
analog-to-digital converters with an easy to use 3-wire
serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins
with the conversion, followed by the sleep state and ends
with the data output (see Figure 2). The 3-wire interface
consists of serial data output (SDO), serial clock (SCK)
and chip select (CS).
Through timing control of the CS and SCK pins, the
LTC2415/LTC2415-1 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
CONVERT
SLEEP
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typicallydesignedtorejectlinefrequenciesof50Hzor60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2415/LTC2415-1 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals
or oscillators. Clocked by the on-chip oscillator, the
LTC2415 achieves a minimum of 110dB rejection at the
line frequency (50Hz or 60Hz 2ꢀ), while the LTC2415-1
achieves a minimum of 87db rejection at 50Hz 2ꢀ and
60Hz 2ꢀ simultaneously.
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2415 F02
Figure 2. LTC2415 State Transition Diagram
Initially, the LTC2415/LTC2415-1 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude if CS is HIGH. The
part remains in the sleep state as long as CS is HIGH.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Ease of Use
The LTC2415/LTC2415-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion
just performed. This result is shifted out on the serial data
out pin (SDO) under the control of the serial clock (SCK).
2415fa
12
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
The LTC2415/LTC2415-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. Theadvantageofcontinuouscalibrationisextreme
stability of full-scale readings with respect to time, supply
voltage change and temperature drift.
TheLTC2415/LTC2415-1canacceptadifferentialreference
voltage from 0.1V to V . The converter output noise is
CC
determined by the thermal noise of the front-end circuits,
and as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
Ontheotherhand,areducedreferencevoltagewillimprove
the converter’s overall INL performance.
Unlike the LTC2410 and LTC2413, the LTC2415 and
LTC2415-1 do not perform an offset calibration every
conversioncycle.ThisenablestheLTC2415/LTC2415-1to
double their output rate while maintaining line frequency
rejection. The initial offset of the LTC2415/LTC2415-1 is
Input Voltage Range
The analog input is truly differential with an absolute/
+
–
common mode range for the IN and IN input pins
within 2mV independent of V . Based on the LTC2415/
REF
extending from GND – 0.3V to V + 0.3V. Outside
LTC2415-1 new modulator architecture, the temperature
drift of the offset is less then 0.01ppm/°C. More informa-
tion on the LTC2415/LTC2415-1 offset is described in the
Offset Accuracy and Drift section of this data sheet.
CC
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Withintheselimits, theLTC2415/LTC2415-1con-
+
–
vert the bipolar differential input signal, V = IN – IN ,
IN
Power-Up Sequence
from –FS = –0.5 • V
to +FS = 0.5 • V
where
REF
REF
+
–
V
REF
= REF – REF . Outside this range, the converters
indicate the overrange or the underrange condition using
The LTC2415/LTC2415-1 automatically enter an internal
reset state when the power supply voltage V drops
CC
distinct output codes.
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
+
–
Input signals applied to IN and IN pins may extend by
300mV below ground and above V . In order to limit any
fault current, resistors of up to 5k may be added in series
CC
+
–
with the IN and IN pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding
pins as low as possible; therefore, the resistors should
be located as close as practical to the pins. The effect of
the series resistance on the converter accuracy can be
evaluated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
WhentheV voltagerisesabovethiscriticalthreshold,the
CC
converter creates an internal power-on-reset (POR) signal
with a duration of approximately 0.5ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2415/LTC2415-1 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
develop a 1ppm offset error on a 5k resistor if V = 5V.
REF
Reference Voltage Range
This error has a very strong temperature dependency.
These converters accept a truly differential external
reference voltage. The absolute/common mode voltage
Output Data Format
+
–
specification for the REF and REF pins covers the entire
rangefromGNDtoV .Forcorrectconverteroperation,the
The LTC2415/LTC2415-1 serial output data stream is 32
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 24 bits
CC
+
–
REF pin must always be more positive than the REF pin.
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are the conversion result, MSB first. The remaining 5 bits
are sub LSBs beyond the 24-bit level that may be included
in averaging or discarded without loss of resolution. The
third and fourth bit together are also used to indicate an
underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
input voltage is above +FS).
SDO remains high impedance and any externally gener-
ated SCK clock pulses are ignored by the internal data
out shift register.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If V is >0, this bit is HIGH. If V is <0,
IN
IN
this bit is LOW.
+
–
As long as the voltage on the IN and IN pins is main-
Bit 28 (fourth output bit) is the most significant bit
(MSB) of the result. This bit in conjunction with Bit 29
also provides the underrange or overrange indication.
If both Bit 29 and Bit 28 are HIGH, the differential input
voltage is above +FS. If both Bit 29 and Bit 28 are LOW,
the differential input voltage is below –FS.
tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum
CC
operating range, a conversion result is generated for any
differential input voltage V from –FS = –0.5 • V
to
IN
REF
+FS = 0.5 • V . For differential input voltages greater
REF
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
The function of these bits is summarized in Table 1.
Table 1. LTC2415/LTC2415-1 Status Bits
Bit 31 Bit 30 Bit 29
Bit 28
MSB
Offset Accuracy and Drift
Input Range
≥ 0.5 • V
EOC
DMY
SIG
Unlike the LTC2410/LTC2413 and the entire LTC2400
family, the LTC2415/LTC2415-1 do not perform an offset
calibrationeverycycle.Thereasonforthisistoincreasethe
dataoutputratewhilemaintaininglinefrequencyrejection.
V
IN
0
0
0
0
0
1
1
0
1
0
REF
0V ≤ V < 0.5 • V
0
1
IN
REF
–0.5 • V ≤ V < 0V
0
0
REF
IN
V
IN
< –0.5 • V
0
0
REF
WhiletheinitialaccuracyoftheLTC2415/LTC2415-1offset
is within 2mV (see Figure 4) several unique properties
of the LTC2415/LTC2415-1 architecture nearly eliminate
the drift of the offset error with respect to temperature
and supply.
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0
may be included in averaging or discarded without loss
of resolution.
AsshowninFigure5, theoffsetvariationwithtemperature
is less than 0.6ppm over the complete temperature range
of –50°C to 100°C. This corresponds to a temperature
drift of 0.004ppm/°C.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
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While the variation in offset with supply voltage is propor-
increased reference voltage with an equal and opposite
magnitude to the supply voltage variation. As a result, by
tional to V (see Figure 4), several characteristics of this
CC
variation can be used to eliminate the effects. First, the
variation with respect to supply voltage is linear. Second,
themagnitudeoftheoffseterrordecreaseswithdecreased
supply voltage. Third, the offset error increases with
tying V to V , the variation with supply can be nearly
CC
REF
eliminated, see Figure 6. The variation with supply is less
than 2ppm over the entire 2.7V to 5.5V supply range.
Table 2. LTC2415/LTC2415-1 Output Data Format
Differential Input Voltage
V *
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
IN
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
IN
REF
+
–
+
–
*The differential input voltage V = IN – IN .
**The differential reference voltage V = REF – REF .
REF
IN
CS
BIT 31
EOC
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 5
BIT 0
SDO
SCK
LSB
24
Hi-Z
1
2
3
4
5
26
27
32
SLEEP
DATA OUTPUT
CONVERSION
2415 F03
Figure 3. Output Data Timing
50
0
–103.0
–103.5
–104.0
–104.5
–105.0
–105.5
–103.8
–104.0
–104.2
–104.4
–104.6
V
V
= 5V
= 5V
V
= 0V
CC
REF
IN
+
IN = GND
PART NO.1
PART NO.2
+
–
REF = 5V IN = GND
–
REF = GND F = GND
O
–50
T
=100°C
=25°C
A
–100
–150
–200
–250
T
A
T
= –50°C
A
PART NO.3
V
A
= 2.5V
3.0
REF
T
= 25°C
2.5
3.5
4.0
(V)
4.5
5.0
5.5
–50
–25
0
25
50
75
100
2.7
3.5 3.9
V
4.3
4.7 5.1
(V)
5.5
3.1
V
TEMPERATURE (°C)
AND V
REF
CC
CC
2415 F04
2415 F05
2415 F06
Figure 4. Offset vs VCC
Figure 5. Offset vs Temperature
Figure 6. Offset vs VCC (VREF = VCC)
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Frequency Rejection Selection LTC2415 (F )
Table 3a summarizes the duration of each state and the
achievable output data rate as a function of F .
O
O
TheLTC2415internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and its har-
monics for 50Hz 2ꢀ or 60Hz 2ꢀ. For 60Hz rejection,
Frequency Rejection Selection LTC2415-1 (F )
O
The LTC2415-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2HzasshowninFigure7b.Forsimultaneous50Hz/60Hz
F should be connected to GND while for 50Hz rejection
O
the F pin should be connected to V .
O
CC
The selection of 50Hz or 60Hz rejection can also be made
rejection, F should be connected to GND.
O
by driving F to an appropriate logic level. A selection
O
In order to achieve 87dB normal mode rejection of 50Hz
2ꢀand60Hz 2ꢀ,twoconsecutiveconversionsmustbe
averaged. By performing a continuous running average of
the two most current results, both simultaneous rejection
isachievedanda2×increaseinthroughputisrealizedrela-
tive to the LTC2413 (see Normal Mode Rejection, Output
Rate and Running Averages sections of this data sheet).
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2415 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the con-
verter must be synchronized with an outside source, the
LTC2415-1canoperatewithanexternalconversionclock.
The converter automatically detects the presence of an
signal at the F pin and turns off the internal oscillator.
O
The frequency f
of the external signal must be at least
EOSC
external clock signal at the F pin and turns off the internal
2560Hz(1Hznotchfrequency)tobedetected.Theexternal
clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
O
EOSC
oscillator. The frequency f
of the external signal must
beatleast2560Hztobedetected.Theexternalclocksignal
duty cycle is not significant as long as the minimum and
maximum specifications for the high and low periods,
low periods t
and t
are observed.
HEO
LEO
While operating with an external conversion clock of a
frequency f , the LTC2415 provides better than 110dB
t
and t , are observed.
HEO
LEO
EOSC
While operating with an external conversion clock of a
frequencyf ,theLTC2415-1providesbetterthan110dB
normal mode rejection in a frequency range f
4ꢀ and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
is shown in Figure 7a.
/2560
EOSC
EOSC
normal mode rejection in a frequency range f
/2560
EOSC
/2560
EOSC
4ꢀ. The normal mode rejection as a function of the
input frequency deviation from f /2560 is shown in
EOSC
Whenever an external clock is not present at the F pin,
O
Figure 7a and Figure 7c shows the normal mode rejection
with running averages included.
the converter automatically activates its internal oscilla-
tor and enters the Internal Conversion Clock mode. The
LTC2415 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Whenever an external clock is not present at the F pin
O
the converter automatically activates its internal oscilla-
tor and enters the Internal Conversion Clock mode. The
LTC2415-1 operation will not be disturbed if the change
of conversion clock source occurs during the sleep state
or during the data output state while the converter uses
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
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data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Serial Interface Pins
The LTC2415/LTC2415-1 transmit the conversion results
and receive the start of conversion command through
a synchronous 3-wire interface. During the conversion
and sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Table 3b summarizes the duration of each state and the
achievable output data rate as a function of F .
O
–80
–80
–85
–60
–70
–90
–100
–100
–120
–130
–140
–90
–80
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–90
–100
–110
–120
–130
–140
48
50
52
54
56
58
60
62
–12
–8
–4
0
4
8
12
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
DEVIATION FROM NOTCH FREQUENCY f
/2560(%)
EOSC
2415 F07b
2415 F07a
2415 F07c
Figure 7a. LTC2415/LTC2415-1 Normal Mode
Rejection When Using an External Oscillator
of Frequency fEOSC without Running Averages
Figure 7b. LTC2415-1 Normal Mode
Rejection When Using an Internal
Oscillator with Running Averages
Figure 7c. LTC2415/LTC2415-1
Normal Mode Rejection When Using
an External Oscillator of Frequency
fEOSC with Running Averages
Table 3a. LTC2415 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW, (60Hz Rejection)
66.6ms, Output Data Rate ≤ 15 Readings/s
80ms, Output Data Rate ≤ 12.4 Readings/s
F = External Oscillator with Frequency 10278/f s, Output Data Rate ≤ f /10278 Readings/s
O
F = HIGH, (50Hz Rejection)
O
External Oscillator
O
EOSC
EOSC
EOSC
f
kHz (f /2560 Rejection)
EOSC
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT Internal Serial Clock F = LOW/HIGH, (Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles)
O
F = External Oscillator with Frequency As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms (32 SCK cycles)
EOSC
O
f
kHz
External Serial Clock with Frequency f
kHz
As Long As CS = LOW But Not Longer Than 32/f ms (32 SCK cycles)
SCK
SCK
Table 3b. LTC2415-1 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW
72.8ms, Output Data Rate ≤ 14 Readings/s
O
Simultaneous 50Hz/60Hz Rejection
External Oscillator
F = External Oscillator with Frequency 10278/f
s, Output Data Rate ≤ f /10278 Readings/s
EOSC EOSC
O
f
kHz (f
/2560 Rejection)
EOSC
EOSC
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT Internal Serial Clock F = LOW/HIGH, (Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.83ms (32 SCK cycles)
O
F = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/f ms (32 SCK cycles)
EOSC
O
Frequency f
kHz
EOSC
External Serial Clock with Frequency f
kHz
As Long As CS = LOW But Not Longer Than 32/f ms (32 SCK cycles)
SCK
SCK
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Serial Clock Input/Output (SCK)
Chip Select Input (CS)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
In the Internal SCK mode of operation, the SCK pin is
an output and the LTC2415/LTC2415-1 create their own
serial clock by dividing the internal conversion clock by
8. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected on power-up and then reselected every time a
HIGH-to-LOW transition is detected at the CS pin. If SCK
is HIGH or floating at power-up or during this transition,
the converter enters the internal SCK mode. If SCK is LOW
at power-up or during this transition, the converter enters
the external SCK mode.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2415/LTC2415-1 will abort any
serial data transfer in progress and start a new conver-
sion cycle anytime a LOW-to-HIGH transition is detected
at the CS pin after the converter has entered the data
output state (i.e., after the first rising edge of SCK occurs
with CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
GroundingCSwillforcetheADCtocontinuouslyconvertat
the maximum output rate selected by F . Tying a capacitor
O
Serial Data Output (SDO)
to CS will reduce the output rate and power dissipation by
a factor proportional to the capacitor’s value, see Figures
15 to 17.
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
SERIAL INTERFACE TIMING MODES
The LTC2415/LTC2415-1 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexiblemodesofoperation.Theseincludeinternal/external
serial clock, 2- or 3-wire I/O, single cycle conversion and
auto-start. The following sections describe each of these
serial interface timing modes in detail. In all these cases,
When CS (Pin 11) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
the converter can use the internal oscillator (F = LOW
O
or F = HIGH) or an external oscillator connected to the
O
F pin. Refer to Table 4 for a summary.
O
Table 4. LTC2415/LTC2415-1 Interface Timing Modes
Configuration
SCK Source
Conversion Cycle
Control
Data Output
Control
Connection and
Waveforms
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
External
External
Internal
Internal
Internal
CS and SCK
SCK
CS and SCK
SCK
Figures 8, 9
Figure 10
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal SCK, Auto-start Conversion
Figures 11, 12
Figure 13
CS ↓
CS ↓
Continuous
Internal
Internal
C
Figure 14
EXT
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External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
The serial clock mode is selected on the falling edge of
CS. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CS falling edge.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 32nd falling edge of SCK, see Figure 9. On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
The serial data output pin (SDO) is Hi-Z as long as CS
is HIGH. At any time during the conversion cycle, CS
may be pulled LOW in order to monitor the state of the
converter. While CS is pulled LOW, EOC is output to the
SDO pin. EOC = 1 while a conversion is in progress and
EOC = 0 if the device is in the sleep state. Independent of
CS, the device automatically enters the sleep state once
the conversion is complete. While in the sleep state, if CS
is high, the LTC2415/LTC2415-1 power consumption is
reduced by an order of magnitude
External Serial Clock, 2-Wire I/O
When the device is in the sleep state (EOC = 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen while CS is LOW. Data is shifted out
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
10. CS may be permanently tied to ground, simplifying
the user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION (LTC2415)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
O
LTC2415/
LTC2415-1
+
3
4
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
SUB LSB
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2415 F08
2415fa
19
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION (LTC2415)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
LTC2415/
O
LTC2415-1
+
3
REFERENCE
VOLTAGE
0.1V TO V
REF
REF
SCK
4
–
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 9
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2415 F09
Figure 9. External Serial Clock, Reduced Data Output Length
approximately 0.5ms after V exceeds 2.2V. The level
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore,theinternalserialclocktimingmodeisautomati-
cally selected if SCK is not externally driven.
CC
applied to SCK at this time determines if SCK is internal
or external. SCK must be driven LOW prior to the end of
PORinordertoentertheexternalserialclocktimingmode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
externalcontrollerindicatingtheconversionresultisready.
EOC = 1 while the conversion is in progress and EOC = 0
once the conversion enters the sleep state. On the falling
edgeofEOC,theconversionresultisloadedintoaninternal
static shift register. The device remains in the sleep state
until the first rising edge of SCK. Data is shifted out the
SDO pin on each falling edge of SCK enabling external
circuitry to latch data on the rising edge of SCK. EOC can
be latched on the first rising edge of SCK. On the 32nd
falling edge of SCK, SDO goes HIGH (EOC = 1) indicating
a new conversion has begun.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.
outputting data at time t
after the falling edge of CS
EOCtest
(if EOC = 0) or t test after EOC goes LOW (if CS is LOW
EOC
2415fa
20
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
2
14
13
V
F
CC
O
LTC2415/
LTC2415-1
+
3
REFERENCE
VOLTAGE
0.1V TO V
REF
REF
SCK
4
–
2-WIRE
INTERFACE
CC
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2415 F10
Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)
2.7V TO 5.5V
V
CC
V
CC
1µF
= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
2
14
13
V
F
CC
O
10k
LTC2415/
LTC2415-1
+
3
4
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2415 F11
Figure 11. Internal Serial Clock, Single Cycle Operation
2415fa
21
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
during the falling edge of EOC). The value of t
is
of SCK, see Figure 12. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
beavoidedbyaddinganexternal10kpull-upresistortothe
SCK pin or by never pulling CS HIGH when SCK is LOW.
EOCtest
23µs (LTC2415), 26µs (LTC2415-1) if the device is using
its internal oscillator (F = logic LOW or HIGH). If F is
O
O
driven by an external oscillator of (LTC2415-1) frequency
f
, thent is3.6/f . IfCSispulledHIGHbefore
EOCtest
EOSC
time t
EOCtest
EOSC
, the device remains in the sleep state. The
conversionresultisheldintheinternalstaticshiftregister.
If CS remains LOW longer than t , the first rising
EOCtest
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this first rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Whenever SCK is LOW, the LTC2415/LTC2415-1 internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nallydrivenifthedeviceisintheinternalSCKtimingmode.
However,certainapplicationsmayrequireanexternaldriver
on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2415/LTC2415-1 internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor
to SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain
in the internal SCK timing mode.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
2.7V TO 5.5V
V
CC
V
CC
1µF
= 50Hz REJECTION (LTC2415)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
LTC2415/
O
10k
LTC2415-1
+
3
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
<t
EOCtest
GND
>t
EOCtest
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2415 F12
Figure 12. Internal Serial Clock, Reduced Data Output Length
2415fa
22
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
period defined above as t
), the internal pull-up is
EOCtest
activated. For a heavy capacitive load on the SCK pin,
the internal pull-up may not be adequate to return SCK
to a HIGH level before CS goes low again. This is not a
concern under normal conditions where CS remains LOW
after detecting EOC = 0. This situation is easily overcome
by adding an external 10k pull-up resistor to the SCK pin.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. Theconversionresultisshiftedoutofthedevice
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V exceeds 2.2V. An internal
CC
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION (LTC2415)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
O
LTC2415/
LTC2415-1
+
3
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
2-WIRE
INTERFACE
0.1V TO V
CC
5
6
12
11
+
ANALOG INPUT RANGE
IN
SDO
CS
–0.5V
TO 0.5V
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2415 F13
SLEEP
Figure 13. Internal Serial Clock, Continuous Operation
2415fa
23
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Internal Serial Clock, Auto-start Conversion
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 17 shows the average supply current as a function
of capacitance on CS.
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verterpowerdissipationinthesleepstate.Intheauto-start
mode,theanalogvoltageontheCSpincannotbeobserved
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at
the CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 14. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 15 and 16. Once the
voltage at CS falls below an internal threshold (≈1.4V),
the device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
The internal serial clock mode is selected every time the
voltageontheCSpincrossesaninternalthresholdvoltage.
An internal weak pull-up at the SCK pin is active while CS
is discharging; therefore, the internal serial clock timing
mode is automatically selected if SCK is floating. It is
important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
2.7V TO 5.5V
V
CC
1µF
= 50Hz REJECTION (LTC2415)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
F
CC
O
LTC2415/
LTC2415-1
+
3
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
2-WIRE
INTERFACE
0.1V TO V
CC
5
6
12
11
+
ANALOG INPUT RANGE
IN
SDO
CS
–0.5V
TO 0.5V
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
C
EXT
V
CC
CS
GND
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 0
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
2415 F14
Figure 14. Internal Serial Clock, Auto-start Operation
2415fa
24
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
7
and the conversion time of the LTC2413 is 146ms, while
the LTC2415-1 is 73ms. In systems where the SDO pin is
monitoredfortheend-of-conversionsignal(SDOgoeslow
once the conversion is complete) these two devices can
be interchanged. In cases where SDO is not monitored, a
wait state is inserted between conversions, the duration
of this wait state must be greater than 66.6ms for the
LTC2415, greater than 133ms for the LTC2410, greater
than 146ms for the LTC2413 and greater than 73ms for
the LTC2415-1.
6
5
4
3
2
V
= 5V
CC
1
0
V
= 3V
CC
10000 100000
CAPACITANCE ON CS (pF)
1
10
100
1000
2415 F15
Figure 15. CS Capacitance vs tSAMPLE
PRESERVING THE CONVERTER ACCURACY
The LTC2415/LTC2415-1 are designed to reduce as much
as possible conversion result sensitivity to device decou-
pling, PCB layout, anti-aliasing circuits, line frequency
perturbationsandsoon.Nevertheless,inordertopreserve
the extreme accuracy capability of this part, some simple
precautions are desirable.
8
7
6
V
= 5V
CC
5
V
= 3V
CC
4
3
2
1
0
Digital Signal Levels
0
10
100
10000 100000
1000
The LTC2415/LTC2415-1 digital interface is easy to use.
CAPACITANCE ON CS (pF)
2415 F16
Its digital inputs (F , CS and SCK in External SCK mode
O
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates
as slow as 100µs. However, some considerations are
required to take advantage of the exceptional accuracy
and low supply current of this converter.
Figure 16. CS Capacitance vs Output Rate
300
250
V
V
= 5V
= 3V
CC
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during conversion.
200
150
CC
100
50
0
While a digital input signal is in the range 0.5V to
(V – 0.5V), the CMOS input receiver draws additional
CC
current from the power supply. It should be noted that,
1
10
100
1000
10000 100000
CAPACITANCE ON CS (pF)
when any one of the digital input signals (F , CS and SCK
O
2415 F17
inExternalSCKmodeofoperation)iswithinthisrange,the
LTC2415/LTC2415-1 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
Figure 17. CS Capacitance vs Supply Current
Timing Compatibility with the LTC2410/LTC2413
digital input signals to full CMOS levels [V < 0.4V and
IL
Alltimingmodesdescribedaboveareidenticalwithrespect
to the LTC2410/LTC2413 and LTC2415/LTC2415-1, with
one exception. The conversion time of the LTC2410 is
133mswhiletheconversiontimeoftheLTC2415is66.6ms
V
OH
> (V – 0.4V)].
CC
Duringtheconversionperiod,theundershootand/orover-
shoot of a fast digital signal connected to the LTC2415/
2415fa
25
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
LTC2415-1 pins may severely disturb the analog to digital
conversionprocess.Undershootandovershootcanoccur
because of the impedance mismatch at the converter pin
when the transition time of an external control signal is
less than twice the propagation delay from the driver to
LTC2415/LTC2415-1. For reference, on a regular FR-4
board,signalpropagationvelocityisapproximately183ps/
inch for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomesparticularlydifficultwhensharedcontrollinesare
used and multiple reflections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
erence signals. When the F signal is parallel terminated
O
near the converter, substantial AC current is flowing in the
loop formed by the F connection trace, the termination
O
and the ground return path. Thus, perturbation signals
may be inductively coupled into the converter input and/
or reference. In this situation, the user must reduce to a
minimum the loop area for the F signal as well as the loop
O
area for the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2415/LTC2415-1
converters are directly connected to a network of sam-
pling capacitors. Depending upon the relation between
the differential input voltage and the differential refer-
ence voltage, these capacitors are switching between
these four pins transferring small amounts of charge in
the process. A simplified equivalent circuit is shown in
Figure 18.
ParallelterminationneartheLTC2415/LTC2415-1pinswill
eliminate this problem but will increase the driver power
dissipation.Aseriesresistorbetween27Ωand56Ωplaced
near the driver or near the LTC2415/LTC2415-1 pins will
also eliminate this problem without additional power dis-
sipation. The actual resistor value depends upon the trace
impedance and connection topology.
For a simple approximation, the source impedance R
S
+
–
+
–
driving an analog input pin (IN , IN , REF or REF ) can
be considered to form, together with R and C (see
SW
EQ
Figure 18), a first order passive network with a time
constant τ = (R + R ) • C . The converter is able to
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
S
SW
EQ
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
When using the internal oscillator (F = LOW or HIGH), the
Particular attention must be given to the connection of
O
LTC2415’sfront-endswitched-capacitornetworkisclocked
at76800Hzcorrespondingtoa13µssamplingperiodandthe
LTC2415-1’s front end is clocked at 69900Hz correspond-
ing to 14.2µs. Thus, for settling errors of less than 1ppm,
the driving source impedance should be chosen such that
τ ≤ 13µs/14 = 920ns (LTC2415) and τ <14.2µs/14 = 1.01µs
the F signal when the LTC2415/LTC2415-1 are used
O
with an external conversion clock. This clock is active
during the conversion time and the normal mode rejection
provided by the internal digital filter is not very high at
this frequency. A normal mode signal of this frequency at
the converter reference terminals may result into DC gain
and INL errors. A normal mode signal of this frequency at
the converter input terminals may result into a DC offset
error. Such perturbations may occur due to asymmetric
(LTC2415-1).Whenanexternaloscillatoroffrequencyf
EOSC
and, for a settling
is used, the sampling period is 2/f
EOSC
error of less than 1ppm, τ ≤ 0.14/f
.
EOSC
capacitive coupling between the F signal trace and the
O
Input Current
converter input and/or reference connection traces. An
immediate solution is to maintain maximum possible
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
2415fa
separation between the F signal trace and the input/ref-
O
26
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
V
CC
V
IN + VINCM − VREFCM
I IN+
=
=
I
+
(
)
)
REF
AVG
AVG
0.5•REQ
R
(TYP)
SW
I
LEAK
20k
−VIN + VINCM − VREFCM
0.5•REQ
I IN−
(
V
+
REF
I
1.5• VREF − VINCM + VREFCM
V2
LEAK
I REF+
=
−
IN
(
)
)
V
CC
AVG
AVG
0.5•REQ
VREF •REQ
I
IN
+
−1.5• VREF − VINCM + VREFCM
0.5•REQ
V2
R
(TYP)
SW
20k
I REF−
=
+
IN
I
I
LEAK
LEAK
(
VREF •REQ
V
+
IN
where:
C
EQ
VREF = REF+ −REF−
18pF
(TYP)
V
CC
REF+ +REF
−
I
IN
–
–
VREFCM
=
R
R
(TYP)
SW
2
I
I
LEAK
LEAK
20k
SWITCHING FREQUENCY
V
IN = IN+ −IN−
V
IN
f
= 76800Hz INTERNAL
SW
IN+ −IN
−
OSCILLATOR (LTC2415)
V
=
INCM
(F = LOW OR HIGH)
O
2
V
CC
f
= 69900Hz INTERNAL
SW
I
–
–
REF
REQ = 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch F = LOW LTC2415
(
(
)
)
OSCILLATOR (LTC2415-1)
O
(TYP)
20k
SW
I
I
LEAK
LEAK
(F = LOW)
O
REQ = 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch F = HIGH LTC2415
REQ = 0.555•1012 / fEOSC EXTERNAL OSCILLATOR
O
f
= 0.5 • f
EXTERNAL OSCILLATOR
SW
EOSC
V
REF
(
)
REQ = 3.97MΩ INTERNAL OSCILLATOR 50Hz / 60Hz Notch F = LOW LTC2415-1
O
2415 F18
Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit
50
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
theINLperformanceoftheconverter. Figure18showsthe
mathematical expressions for the average bias currents
flowing through the IN and IN pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
C
= 0.01µF
IN
C
IN
= 0.001µF
40
30
20
10
0
C
= 100pF
IN
C
IN
= 0pF
+
–
V
= 5V
CC
+
–
REF = 5V
REF = GND
+
–
IN = 5V
IN = 2.5V
The effect of this input dynamic current can be analyzed
F
= GND
= 25°C
O
A
T
using the test circuit of Figure 19. The C
capacitor
PAR
includes the LTC2415/LTC2415-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 20 and 21. A careful
1
10
100
1k
(Ω)
10k
100k
R
SOURCE
2415 F20
Figure 20. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
implementation can bring the total input capacitance (C
IN
+ C ) closer to 5pF thus achieving better performance
PAR
0
V
CC
= 5V
thantheonepredictedbyFigures20and21.Forsimplicity,
two distinct situations can be considered.
+
REF = 5V
–
REF = GND
–10
–20
–30
–40
–50
+
–
IN = GND
IN = 2.5V
R
SOURCE
SOURCE
F
= GND
= 25°C
+
O
A
IN
T
C
PAR
V
V
+ 0.5V
– 0.5V
C
C
INCM
INCM
IN
IN
IN
IN
≅20pF
LTC2415/
LTC2415-1
C
IN
= 0.01µF
C
= 0.001µF
IN
R
–
C
= 100pF
IN
IN
C
IN
= 0pF
2415 F19
C
PAR
≅20pF
1
10
100
1k
10k
100k
R
(Ω)
SOURCE
2415 F21
Figure 21. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 19. An RC Network at IN+ and IN–
2415fa
27
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
For relatively small values of input capacitance (C
<
In addition to this gain error, an offset error term may also
appear. The offset error is proportional to the mismatch
between the source impedance driving the two input
IN
0.01µF), the voltage on the sampling capacitor settles
almostcompletelyandrelativelylargevaluesforthesource
+
–
impedance result in only small errors. Such values for C
pins IN and IN and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large
IN
will deteriorate the converter offset and gain performance
without significant benefits of signal filtering and the user
is advised to avoid them. Nevertheless, when small val-
ues of C are unavoidably present as parasitics of input
IN
multiplexers, wires, connectors or sensors, the LTC2415/
LTC2415-1 can maintain their exceptional accuracy while
operating with relative large values of source resistance
as shown in Figures 20 and 21. These measured results
may be slightly different from the first order approxima-
tion suggested earlier because they include the effect of
the actual second order input network together with the
nonlinear settling process of the input amplifiers. For
C capacitor values, it is advisable to carefully match the
IN
+
–
source impedance seen by the IN and IN pins. When
F = LOW (internal oscillator and 60Hz notch), every 1Ω
O
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.28ppm. When F = HIGH (internal oscillator
O
+
–
small C values, the settling on IN and IN occurs almost
and 50Hz notch), every 1Ω mismatch in source imped-
IN
independently and there is little benefit in trying to match
the source impedance for the two pins.
ance transforms a full-scale common mode input signal
into a differential mode input signal of 0.23ppm. When F
O
is driven by an external oscillator with a frequency f
,
EOSC
Larger values of input capacitors (C > 0.01µF) may
IN
every1Ωmismatchinsourceimpedancetransformsafull-
be required in certain configurations for anti-aliasing or
general input signal filtering. Such capacitors will aver-
age the input sampling charge and the external source
resistance will see a quasi constant input differential
scale common mode input signal into a differential mode
–6
input signal of 1.78 • 10 • f
ppm. Figure 24 shows
EOSC
the typical offset error due to input common mode voltage
forvariousvaluesofsourceresistanceimbalancebetween
impedance. When F = LOW (internal oscillator and 60Hz
O
+
–
the IN and IN pins when large C values are used.
IN
notch), the typical differential input resistance is 1.8MΩ
(LTC2415), 1.97MΩ (LTC2415-1) which will generate
a gain error of approximately 0.28ppm for each ohm of
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
+
–
source resistance driving IN or IN . For the LTC2415,
when F = HIGH (internal oscillator and 50Hz notch), the
O
typical differential input resistance is 2.16MΩ which will
generate a gain error of approximately 0.23ppm for each
+
–
ohm of source resistance driving IN or IN . When F is
O
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5ꢀ. Such
a specification can also be easily achieved by an external
clock.Whenrelativelystableresistors(50ppm/°C)areused
driven by an external oscillator with a frequency f
(ex-
EOSC
ternal conversion clock operation), the typical differential
12
input resistance is 0.28 • 10 /f
Ω and each ohm of
EOSC
+
–
source resistance driving IN or IN will result in
–6
1.78 • 10 • f
ppm gain error. The effect of the source
EOSC
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a func-
+
–
for the external source impedance seen by IN and IN ,
the expected drift of the dynamic current, offset and gain
+
tion of the sum of the source resistance seen by IN and
–
IN for large values of C are shown in Figures 22 and 23.
IN
2415fa
28
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
errors will be insignificant (about 1ꢀ of their respective
valuesovertheentiretemperatureandvoltagerange).Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
inasmalloffsetshift. A100Ωsourceresistancewillcreate
a 0.1µV typical and 1µV maximum offset voltage.
300
0
V
= 5V
CC
C
= 1µF, 10µF
IN
+
C
= 0.01µF
= 0.1µF
IN
REF = 5V
–
REF = GND
240
180
120
60
–60
–120
–180
–240
–300
+
–
IN = 3.75V
IN = 1.25V
F
= GND
= 25°C
O
A
T
C
IN
= 0.1µF
C
IN
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
IN = 1.25V
C
IN
= 0.01µF
IN = 3.75V
F
= GND
= 25°C
O
A
C
IN
= 1µF, 10µF
T
0
0
100 200 300 400 500 600 700 800 9001000
(Ω)
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
SOURCE
R
SOURCE
2415 F22
2415 F23
Figure 22. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 23. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
120
V
= 5V
CC
+
100
REF = 5V
A
–
REF = GND
IN = IN = V
80
+
–
INCM
60
B
40
C
20
D
0
E
–20
F
–40
–60
F
= GND
= 25°C
A
O
G
T
–80
–100
–120
R
C
– = 500Ω
SOURCEIN
= 10µF
IN
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
INCM
(V)
A: ∆R = +400Ω
E: ∆R = –100Ω
IN
IN
B: ∆R = +200Ω
F: ∆R = –200Ω
IN
IN
C: ∆R = +100Ω
G: ∆R = –400Ω
IN
IN
D: ∆R = 0
2415 F24
IN
Figure 24. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
2415fa
29
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Reference Current
Larger values of reference capacitors (C > 0.01µF) may
REF
be required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
andtheexternalsourceresistancewillseeaquasiconstant
reference differential impedance. For the LTC2415, when
In a similar fashion, the LTC2415/LTC2415-1 sample the
+
–
differentialreferencepinsREF andREF transferringsmall
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
F = LOW (internal oscillator and 60Hz notch), the typical
O
differentialreferenceresistanceis1.3MΩwhichwillgener-
ate a gain error of approximately 0.38ppm for each ohm of
+
–
source resistance driving REF or REF . When F = HIGH
O
Forrelativelysmallvaluesoftheexternalreferencecapaci-
(internaloscillatorand50Hznotch), thetypicaldifferential
reference resistance is 1.56MΩ which will generate a gain
error of approximately 0.32ppm for each ohm of source
tors(C <0.01µF),thevoltageonthesamplingcapacitor
REF
settles almost completely and relatively large values for
+
–
the source impedance result in only small errors. Such
resistance driving REF or REF . For the LTC2415-1, the
typical differential reference resistance is 1.43MΩ. When
values for C
will deteriorate the converter offset and
REF
gainperformancewithoutsignificantbenefitsofreference
F isdrivenbyanexternaloscillatorwithafrequencyf
O
EOSC
filtering and the user is advised to avoid them.
(externalconversionclockoperation), thetypicaldifferen-
0
50
C
= 0.01µF
REF
V
= 5V
CC
+
REF = 5V
C
REF
= 0.001µF
–
REF = GND
–10
–20
–30
–40
–50
40
30
20
10
0
+
–
IN = 5V
C
= 100pF
REF
IN = 2.5V
C
= 0pF
REF
F
= GND
= 25°C
O
A
T
V
= 5V
CC
+
–
REF = 5V
C
REF
= 0.01µF
REF = GND
+
–
IN = GND
C
REF
= 0.001µF
IN = 2.5V
F
= GND
= 25°C
O
C
REF
= 100pF
T
A
C
= 0pF
REF
1
10
100
R
1k
(Ω)
10k
100k
1
10
100
R
1k
10k
100k
(Ω)
SOURCE
SOURCE
2415 F25
2415 F26
Figure 25. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 26. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
0
450
C
REF
= 0.01µF
V
= 5V
CC
C
REF
= 1µF, 10µF
+
REF = 5V
–
–90
–180
–270
–360
–450
REF = GND
360
270
180
90
+
–
IN = 1.25V
IN = 3.75V
F
= GND
T = 25°C
A
O
C
= 0.1µF
REF
C
= 0.1µF
REF
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
IN = 3.75V
C
= 0.01µF
REF
IN = 1.25V
C
= 1µF, 10µF
F
= GND
= 25°C
REF
O
A
T
0
0
100 200 300 400 500 600 700 800 9001000
(Ω)
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
R
SOURCE
SOURCE
2415 F27
2415 F28
Figure 27. +FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
Figure 28. –FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
2415fa
30
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
12
+
tial reference resistance is 0.20 • 10 /f
Ω and each
effect of the source resistance on the two reference pins is
additivewithrespecttothisINLerror.Ingeneral,matching
EOSC
–
ohmofsourceresistancedrivingREF orREF willresultin
–6
+
–
2.47 • 10 • f
ppm gain error. The effect of the source
of source impedance for the REF and REF pins does not
help the gain or the INL error. The user is thus advised
to minimize the combined source impedance driving the
EOSC
resistance on the two reference pins is additive with re-
spect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by
+
–
REF and REF pins rather than to try to match it.
+
–
the REF and REF pins and external capacitance C
connected to these pins are shown in Figures 25, 26, 27
REF
The magnitude of the dynamic reference current depends
uponthesizeoftheverystableinternalsamplingcapacitors
andupontheaccuracyoftheconvertersamplingclock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
and 28.
Inadditiontothisgainerror,theconverterINLperformance
is degraded by the reference source impedance. When F
O
= LOW (internaloscillatorand 60Hz notch), every 100Ωof
+
–
sourceresistancedrivingREF orREF translatesintoabout
1.34ppm additional INL error. For the LTC2415, when F
+
used for the external source impedance seen by REF
O
–
= HIGH (internal oscillator and 50Hz notch), every 100Ω
and REF , the expected drift of the dynamic current gain
+
–
of source resistance driving REF or REF translates into
about 1.1ppm additional INL error; and for the LTC2415-1
operating with simultaneous 50Hz/60Hz rejection, every
100Ω of source resistance leads to an additional 1.22ppm
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
of additional INL error. When F is driven by an external
O
EOSC
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA ( 10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
oscillator with a frequency f
, every 100Ω of source
+
–
resistancedrivingREF orREF translatesintoabout8.73•
–6
10 • f
ppm additional INL error. Figure 26 shows the
EOSC
typical INL error due to the source resistance driving the
+
–
REF or REF pins when large C values are used. The
REF
15
V
= 5V
CC
R
= 1000Ω
REF+ = 5V
12
9
SOURCE
REF– = GND
V
+
–
= 0.5 • (IN + IN ) = 2.5V
INCM
R
= 500Ω
SOURCE
F
= GND
O
6
C
= 10µF
REF
3
T
= 25°C
A
0
–3
–6
–9
–12
–15
R
= 100Ω
SOURCE
–0.5–0.4–0.3–0.2–0.1
0
/V
0.1 0.2 0.3 0.4 0.5
V
INDIF REFDIF
2415 F29
Figure 29. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference
Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF)
2415fa
31
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Normal Mode Rejection, Output Rate and Running
Averages
a running average can be performed. By averaging two
1
consecutiveADCreadings,aSinc notchiscombinedwith
the Sinc4 digital filter yielding the frequency response
shown in Figures 33 and 34. In order to preserve the 2×
output rate, adjacent results are averaged with the fol-
lowing algorithm:
4
The LTC2415/LTC2415-1 both contain an identical Sinc
digital filter (see Figures 30 and 31) which offers excellent
line frequency noise rejection. For the LTC2415, a notch
frequency of either 50Hz or 60Hz (see Figure 32) is user
selectable by tying pin F high or low, respectively. On the
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
Result 3 = average (sample 2, sample 3)
…
O
other hand, the LTC2415-1 offers simultaneous rejection
of 50Hz and 60Hz by tying F low. This sets the notch
O
frequency to approximately 55Hz (see Figure 32).
At a notch frequency of 55Hz, the LTC2415-1 rejects 50Hz
2% and 60Hz 2% better than 72dB. In order to achieve
better than 87dB rejection of both 50Hz and 60Hz 2%,
Result N = average (sample n-1, sample n)
0
0
–20
–40
–60
–70
V
V
V
= 5V
= 5V
IN
= 0
CC
REF
–20
= 2.5V
F
O
–80
–40
–60
–90
–60
–80
–100
–110
–120
–130
–140
–80
–100
–120
–100
–120
–140
1
50
100
150
IN
200
250
0
f /2
S
f
S
–12
–8
–4
0
4
8
12
FREQUENCY AT V (Hz)
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
INPUT FREQUENCY
2415 F30
2415 F31
2415 F32
Figure 30. Rejection vs Frequency at VIN
Figure 32. Rejection vs Frequency at VIN
Figure 31. Rejection vs Frequency at VIN
–80
–90
0
–20
–100
–100
–120
–130
–140
–40
–60
–80
–100
–120
48
50
52
54
56
58
60
62
0
20
40
60
80
100
120
140
160
180
200
220
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
2415 F34
2415 F33
Figure 33. Normal Mode Rejection
when Using an Internal Oscillator
Figure 34. Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 100% of Full Scale
2415fa
32
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Sample Driver for LTC2415/LTC2415-1 SPI Interface
The code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result.
ThisisfollowedbyinitializingPORTD’sSPIconfiguration.
The program then enters the main sequence. It activates
the LTC2415/LTC2415-1 serial interface by setting the
SS output low, sending a logic low to CS. It next waits in
a loop for a logic low on the data line, signifying end-of-
conversion. After the loop is satisfied, four SPI transfers
are completed, retrieving the conversion. The main se-
quence ends by setting SS high. This places the LTC2415/
LTC2415-1 serial interface in a high impedance state and
initiates another conversion.
Figure 35 shows the use of an LTC2415/LTC2415-1 with a
differential multiplexer. This is an inexpensive multiplexer
thatwillcontributesomeerrorduetoleakageifuseddirectly
with the output from the bridge, or if resistors are inserted
asaprotectionmechanismfromovervoltage.Althoughthe
bridge output may be within the input range of the A/D and
multiplexer in normal operation, some thought should be
given to fault conditions that could result in full excitation
voltage at the inputs to the multiplexer or ADC. The use of
amplification prior to the multiplexer will largely eliminate
errors associated with channel leakage developing error
voltages in the source impedance.
TheperformanceoftheLTC2415/LTC2415-1canbeverified
using the demonstration board DC291A, see Figure 40 for
the schematic. This circuit uses the computer’s serial port
to generate power and the SPI digital signals necessary
forstartingaconversionandreadingtheresult. Itincludes
a Labview application software program (see Figure 39)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and
with an external source, linearity. As exemplified in the
schematic, the LTC2415/LTC2415-1 are extremely easy
touse. Thisdemonstrationboardandassociatedsoftware
is available by contacting Linear Technology.
The LTC2415/LTC2415-1 have a very simple serial in-
terface that makes interfacing to microprocessors and
microcontrollers very easy.
The listing in Figure 38 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configur-
ing it for SPI data transfer between the controller and the
LTC2415/LTC2415-1. Figure 36 shows the simple 3-wire
SPI connection.
5V
5V
+
16
2
47µF
12
14
15
11
V
CC
3
4
+
–
REF
REF
LTC2415/
LTC2415-1
74HC4052
1
5
5
6
13
3
+
IN
–
IN
2
4
TO OTHER
DEVICES
GND
1, 7, 8, 9,
10, 15, 16
6
8
9
10
A0
A1
2415 F35
Figure 35. Use a Differential Multiplexer to Expand Channel Capability
68HC11
13
12
11
SCK
SDO
CS
SCK (PD4)
MISO (PD2)
SS (PD5)
LTC2415/
LTC2415-1
2415 F36
Figure 36. Connecting the LTC2415/LTC2415-1 to a 68HC11 MCU Using the SPI Serial Interface
2415fa
33
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LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Correlated Double Sampling with the
LTC2415/LTC2415-1
above 10MHz. The conversion spikes that remain at the
outputofotherbipolaramplifierspassthroughthefeedback
network and often overdrive the input of the amplifier,
producing envelope detection. RFI may also be present
on the signal lines from the bridge; C3 and C4 provide RFI
suppression at the signal input, as well as suppressing
transient voltages during bridge commutation.
Figure 37 shows the LTC2415/LTC2415-1 in a correlated
double sampling circuit that achieves a noise floor of
under 100nV. In this scheme, the polarity of the bridge is
alternated every other sample and the result is the average
of a pair of samples of opposite sign. This technique has
the benefit of canceling any fixed DC error components
in the bridge, amplifiers and the converter, as these will
alternate in polarity relative to the signal. Offset voltages
and currents, thermocouple voltages at junctions of dis-
similar metals and the lower frequency components of 1/f
noise are virtually eliminated.
The wideband noise density of the LT1219 is 33nV√Hz,
seemingly much noisier than the lowest noise amplifiers.
However, in the region just below the 1/f corner that is
not well suppressed by the correlated double sampling,
the average noise density is similar to the noise density
of many low noise amplifiers. If the amplifier is rolled off
below about 1500Hz, the total noise bandwidth is deter-
The LTC2415/LTC2415-1 have the virtue of being able to
digitize an input voltage that is outside the range defined
by the reference, thereby providing a simple means to
implement a ratiometric example of correlated double
sampling.
4
mined by the converter’s Sinc filter at about 12Hz. The
useofcorrelateddoublesamplinginvolvesaveragingeven
numbersofsamples;hence, inthissituation, twosamples
would be averaged to give an input-referred noise level of
about 100nV
.
RMS
This circuit uses a bipolar amplifier (LT1219—U1 and
U2) that has neither the lowest noise nor the highest gain.
It does, however, have an output stage that can effec-
tively suppress the conversion spikes from the LTC2415/
LTC2415-1. The LT1219 is a C-LoadTM stable amplifier
that, by design, needs at least 0.1µF output capacitance to
remainstable.The0.1µFceramiccapacitorsattheoutputs
(C1 and C2) should be placed and routed to minimize lead
inductance or their effectiveness in preventing envelope
detection in the input stage will be reduced. Alternatively,
several smaller capacitors could be placed so that lead
inductance is further reduced. This is a consideration
because the frequency content of the conversion spikes
extendsto50MHzormore. Theoutputimpedanceofmost
op amps increases dramatically with frequency but the
effective output impedance of the LT1219 remains low,
determined by the ESR and inductance of the capacitors
Level shift transistors Q4 and Q5 are included to allow
excitation voltages up to the maximum recommended
for the bridge. In the case shown, if a 10V supply is
used, the excitation voltage to the bridge is 8.5V and
the outputs of the bridge are above the supply rail of the
ADC. U1 and U2 are also used to produce a level shift to
bring the outputs within the input range of the converter.
This instrumentation amplifier topology does not require
well-matched resistors in order to produce good CMRR.
However, the use of R2 requires that R3 and R6 match
well, as the common mode gain is approximately –12dB.
If the bridge is composed of four equal 350Ω resistors,
thedifferentialcomponentassociatedwithmismatchofR3
and R6 is nearly constant with either polarity of excitation
and, as with offset, its contribution is canceled.
2415fa
34
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
10V
ELIMINATE FOR 5V
1.5k
1.5k
DIFFERENCE
AMP
OPERATION (CONNECT 2.7k
RESISTORS TO 100Ω
RESISTORS)
10V
0.1µf
Q2
Q3
100Ω
7
3
2
+
–
100Ω
5k
U1
LT1219
6
R2
27k
22Ω
5
C1
0.1µF
22Ω
4
SHDN
5V
Q4
1k
Q5
5V
5V
R4
499Ω
R3 10k
1000pF
1000pF
2.7k
2.7k
5
6
3
4
+
–
C3 2.2nF
C4 2.2nF
IN
IN
350Ω
×4
R5
499Ω
R6 10k
10V
LTC2415/
LTC2415-1
+
POL
REF
0.1µf
6
1k
74HC04
–
+
7
2
3
–
REF
5k
U2
LT1219
Q1
GND
5
C2
22Ω
4
0.1µF
SHDN
R1
61.9Ω
0.1%
33Ω
100Ω
SILICONIX Si9802DY (800) 554-5565
MMBD2907
MMBD3904
Q1:
Q2, Q3:
Q4, Q5:
30pF
30pF
22Ω
2415 F37
Figure 37. Correlated Double Sampling Resolves 100nV
2415fa
35
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
************************************************************
* This example program transfers the LTC2415/LTC2415-1 32-bit output
* conversion result into four consecutive 8-bit memory locations.
************************************************************
*68HC11 register definition
*
*
PORTD EQU
$1008 Port D data register
*
“ – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD”
$1009 Port D data direction register
$1028 SPI control register
DDRD EQU
SPSR EQU
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
$1029 SPI status register
SPSR EQU
*
“SPIF,WCOL, – ,MODF; – , – , – , – “
$102A SPI data register; Read-Buffer; Write-Shifter
SPDR EQU
*
* RAM variables to hold the LTC2415/LTC2415-1’s 32 conversion result
*
DIN1 EQU
DIN2 EQU
DIN3 EQU
DIN4 EQU
*
$00
$01
$02
$03
This memory location holds the LTC2415/LTC2415-1’s bits 31 - 24
This memory location holds the LTC2415/LTC2415-1’s bits 23 - 16
This memory location holds the LTC2415/LTC2415-1’s bits 15 - 08
This memory location holds the LTC2415/LTC2415-1’s bits 07 - 00
**********************
* Start GETDATA Routine *
**********************
*
ORG $C000 Program start location
INIT1 LDS
#$CFFFTop of C page RAM, beginning location of stack
LDAA#$2F –,–,1,0;1,1,1,1
*
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAAPORTD Keeps SS* a logic high when DDRD, bit 5 is set
LDAA#$38 –,–,1,1;1,0,0,0
STAADDRD SS*, SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
*
*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA#$50
STAASPCR The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher E-
Clock frequencies, change the above value of $50 to a value
that ensures the SCK frequency is 2MHz or less.)
PSHX
*
*
GETDATA
PSHY
PSHA
LDX #$0
The X register is used as a pointer to the memory locations
that hold the conversion data
*
LDY #$1000
BCLRPORTD, Y %00100000 This sets the SS* output bit to a logic
low, selecting the LTC2415/LTC2415-1
*
*
2415fa
36
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
********************************************
* The next short loop waits for the
* LTC2415/LTC2415-1’s conversion to finish before
* starting the SPI data transfer
********************************************
*
*
*
*
CONVEND
LDAA PORTD
Retrieve the contents of port D
ANDA#%00000100
Look at bit 2
*
*
*
Bit 2 = Hi; the LTC2415/LTC2415-1’s conversion is not
complete
Bit 2 = Lo; the LTC2415/LTC2415-1’s conversion is complete
Branch to the loop’s beginning while bit 2 remains
high
BNE CONVEND
*
*
********************
* The SPI data transfer
********************
*
*
TRFLP1LDAA #$0
Load accumulator A with a null byte for SPI transfer
STAASPDR This writes the byte in the SPI data register and starts
the transfer
*
WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s MSB
*
*
and is set to one at the end of an SPI transfer. The branch
will occur while SPIF is a zero.
LDAASPDR Load accumulator A with the current byte of LTC2415/LTC2415-1 data
that was just received
STAA0,X
INX
Transfer the LTC2415/LTC2415-1’s data to memory
Increment the pointer
CPX #DIN4+1
Has the last byte been transferred/exchanged?
BNE TRFLP1If the last byte has not been reached, then proceed to the
next byte for transfer/exchange
*
*
BSETPORTD,Y %00100000 This sets the SS* output bit to a logic high,
de-selecting the LTC2415/LTC2415-1
PULA
PULY
PULX
RTS
Restore the A register
Restore the Y register
Restore the X register
Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1
Conversion Results Over the SPI Serial Interface Shown in Figure 40
2415fa
37
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
Figure 39. Display Graphic
PCB LAYOUT AND FILM
LTC2415CGN
Differential Input 24-Bit ADC
with 2¥ Output Rate
Demo Circuit DC382
www.linear-tech.com
LTC Confidential For Customer Use Only
Silkscreen Top
Top Layer
2415fa
38
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
PCB LAYOUT AND FILM
Bottom Layer
2415fa
39
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2415fa
40
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/15 Reduced external oscillator maximum frequency to 500kHz.
Removed noise histogram plots for 105Hz output rate.
5
6, 7
9
Adjusted output data rate on G27 to maximum of 50 readings/second.
2415fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC2415/LTC2415-1
TYPICAL APPLICATION
D1
BAV74LT1
2
U1
U2
V
JP1
V
JP2
1
1
J1
EXT
CC
CC
LT1460ACN8-2.5
LT1236ACN8-5
R1
JUMPER
JUMPER
V
10Ω
1
3
1
2
6
2
6
2
3
1
V
V
IN
V
V
IN
OUT
GND
OUT
GND
J2
GND
2
+
+
+
+
C1
C2
C3
C4
4
4
10µF
35V
22µF
25V
10µF
35V
100µF
16V
P1
DB9
R2
3Ω
1
6
2
7
3
8
4
9
5
JP3
JUMPER
U3E
U3F
74HC14
74HC14
1
3
R3
51k
10
11
12
13
2
JP4
V
CC
JUMPER
1
3
1
1
J3
CC
V
+
C5
2
BANANA JACK
C6
10µF
35V
1
U3B
74HC14
U3A
74HC14
J4
0.1µF
J5
GND
V
EXT
R4
51k
2
11
CS
4
5
3
6
2
9
1
8
BANANA JACK
V
CC
1
3
14
13
12
16
15
10
J6
+
–
+
REF
F
O
REF
4
5
6
REF
SCK
SDO
GND
GND
GND
U3C
74HC14
U3D
74HC14
BANANA JACK
R5
R6
3k
V
V
+
IN
IN
1
J7
49.9Ω
–
–
U4
REF
LTC2415/
LTC2415-1
1
BANANA JACK
R7
22k
1
J8
IN
3
2
GND GND GND GND
V
+
Q1
MMBT3904LT1
1
7
8
9
BANANA JACK
R8
51k
1
2
1
J9
IN
JP5
JUMPER
V
–
V
CC
BANANA JACK
NOTES:
1
J10
GND
BYPASS CAP
FOR U3
C7
0.1µF
INSTALL JUMBER JP1 AT PIN 1 AND PIN 2
INSTALL JUMBER JP2 AT PIN 1 AND PIN 2
INSTALL JUMBER JP3 AT PIN 1 AND PIN 2
2415 F40
Figure 40. 24-Bit A/D Demo Board Schematic
RELATED PARTS
PART NUMBER
LT1019
DESCRIPTION
COMMENTS
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max Initial Accuracy
80µA Supply Current, 0.5°C Initial Accuracy
LT1025
Micropower Thermocouple Cold Junction Compensator
LTC1043
LTC1050
LT1236A-5
LT1460
Dual Precision Instrumentation Switched Capacitor Building Block Precise Charge, Balanced Switching, Low Power
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
Micropower Series Reference
No External Components 5µV Offset, 1.6µV Noise
P-P
0.05% Max Initial Accuracy, 5ppm/°C Drift
0.075% Max Initial Accuracy, 10ppm/°C Max Drift,
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP
LTC2414/LTC2418 4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs with Differential Inputs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
LTC2411
LTC2413
LTC2420
24-Bit, No Latency ∆Σ ADC with Differential Inputs
24-Bit, No Latency ∆Σ ADC with Differential Inputs in MSOP
24-Bit, No Latency ∆Σ ADC with Differential Inputs
20-Bit, No Latency ∆Σ ADC in SO-8
800nV
Noise, Pin Compatible with LTC2415
Noise, 4ppm INL
RMS
1.45µV
RMS
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
2415fa
LT 0815 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
42
●
●
LINEAR TECHNOLOGY CORPORATION 2001
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2415
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