LTC2436-1 [Linear]
2-Channel Differential Input 16-Bit No Latency DS ADC; 2通道差动输入的16位无延迟DS ADC型号: | LTC2436-1 |
厂家: | Linear |
描述: | 2-Channel Differential Input 16-Bit No Latency DS ADC |
文件: | 总28页 (文件大小:293K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2436-1
2-Channel Differential Input
16-Bit No Latency ∆Σ ADC
U
FEATURES
DESCRIPTIO
■
2-Channel Differential Input with Automatic
The LTC®2436-1 is a 2-channel differential input mi-
cropower 16-bit No Latency ∆ΣTM analog-to-digital con-
verter with an integrated oscillator. It provides 0.5LSB
INL and 800nV RMS noise independent of VREF. The two
differential channels convert alternately with a channel
identification included in the conversion result. It uses
delta-sigma technology and provides single conversion
settling of the digital filter. Through a single pin, the
LTC2436-1 can be configured for better than 87dB input
differential mode rejection at 50Hz and 60Hz ±2%, or it
can be driven by an external oscillator for a user defined
rejection frequency. The internal oscillator requires no
external frequency setting components.
Channel Selection (Ping-Pong)
■
Low Supply Current: 200µA, 4µA in Autosleep
Differential Input and Differential Reference with
■
GND to VCC Common Mode Range
0.12LSB INL, No Missing Codes
■
■
0.16LSB Full-Scale Error and 0.006LSB Offset
■
800nV RMS Noise, Independent of VREF
■
No Latency: Digital Filter Settles in a Single Cycle and
Each Channel Conversion is Accurate
■
Internal Oscillator—No External Components
Required
■
87dB Min, 50Hz and 60Hz Notch Filter
■
Narrow SSOP-16 Package
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from –0.5 • VREF to 0.5 •
VREF. The reference common mode voltage, VREFCM, and
the input common mode voltage, VINCM, may be indepen-
dently set anywhere between GND and VCC. The DC
common mode input rejection is better than 140dB.
■
Single Supply 2.7V to 5.5V Operation
■
Pin Compatible with the 24-Bit LTC2412
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APPLICATIO S
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
The LTC2436-1 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
■
■
■
■
■
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Effective Resolution vs VREF
TYPICAL APPLICATIO
90
80
70
5V REF
1µF
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
60
50
40
30
20
10
1
2
4
14
4.9k
V
F
CC
O
(100mV)
+
+
REF
CH0
100Ω
LTC2436-1
5
3
13
12
11
–
CH0
SCK
SDO
CS
THERMOCOUPLE
3-WIRE
SPI INTERFACE
–
REF
6
7
+
CH1
CH1
0
–
0
4
5
1
2
3
V
(V)
24361 TA02
8, 9, 10, 15, 16
REF
*COMBINES EFFECTS OF PEAK-TO-PEAK NOISE
GND
24361 TA01
16
AND 16-BIT STEP SIZE (V /2
)
REF
24361f
1
LTC2436-1
W W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
ORDER PART NUMBER
Supply Voltage (VCC) to GND.......................–0.3V to 7V
Analog Input Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Reference Input Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2436-1C ............................................ 0°C to 70°C
LTC2436-1I ........................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
V
CC
+
LTC2436-1CGN
LTC2436-1IGN
REF
REF
CH0
CH0
CH1
CH1
–
+
–
+
–
F
O
SCK
SDO
CS
GN PART MARKING
GND
GND
GND
24361
24361I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
●
●
●
16
Bits
REF
CC
REF
IN
–
REF
+
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
= 2.5V, (Note 6)
0.06
0.12
0.30
LSB
LSB
LSB
CC
INCM
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
3
1
CC
INCM
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
0.006
LSB
nV/°C
LSB
CC
+
–
GND ≤ IN = IN ≤ V , (Note 13)
CC
+
–
Offset Error Drift
2.5V ≤ REF ≤ V , REF = GND,
CC
10
+
–
GND ≤ IN = IN ≤ V
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
2.5V ≤ REF ≤ V , REF = GND,
●
●
0.16
0.03
0.16
0.03
3
3
CC
+
+
–
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V /°C
CC
REF
+
+
–
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
LSB
CC
+
+
–
+
+
IN = 0.25 • REF , IN = 0.75 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V /°C
CC
REF
+
+
–
IN = 0.25 • REF , IN = 0.75 • REF
+
–
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V
INCM
0.20
0.20
0.25
3
3
3
LSB
LSB
LSB
CC
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V
CC
INCM
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Output Noise
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND,
0.8
µV
RMS
CC
–
+
GND ≤ IN = IN ≤ V , (Note 13)
CC
24361f
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LTC2436-1
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
●
●
●
●
130
140
dB
CC
–
+
GND ≤ IN = IN ≤ V (Note 5)
CC
+
–
Input Common Mode Rejection
49Hz to 61.2Hz
2.5V ≤ REF ≤ V , REF = GND,
140
87
dB
dB
dB
CC
–
+
GND ≤ IN = IN ≤ V , (Notes 5, 7)
CC
Input Normal Mode Rejection
49Hz to 61.2Hz
(Note 5, 7)
+
–
Reference Common Mode
Rejection DC
2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,
130
140
CC
–
+
V
= 2.5V, IN = IN = GND (Note 5)
REF
+
–
–
+
Power Supply Rejection, DC
REF = 2.5V, REF = GND, IN = IN = GND
120
120
dB
dB
+
–
–
+
Power Supply Rejection,
REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)
Simultaneous 50Hz/60Hz ±2%
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
●
●
●
GND – 0.3
GND – 0.3
V
V
+ 0.3
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3
/2
V
Input Differential Voltage Range
–V /2
REF
V
IN
REF
+
–
(IN – IN )
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
●
●
●
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1
CC
V
Reference Differential Voltage Range
V
REF
CC
+
–
(REF – REF )
+
+
C (IN )
IN Sampling Capacitance
18
18
18
18
1
pF
pF
pF
pF
nA
nA
nA
nA
S
–
–
C (IN )
IN Sampling Capacitance
S
+
+
C (REF )
REF Sampling Capacitance
S
–
–
C (REF )
REF Sampling Capacitance
S
+
+
+
I
I
I
I
(IN )
IN DC Leakage Current
CS = V = 5V, IN = GND
●
●
●
●
–10
–10
–10
–10
10
DC_LEAK
DC_LEAK
DC_LEAK
DC_LEAK
CC
–
–
–
(IN )
IN DC Leakage Current
CS = V = 5V, IN = 5.5V
1
10
10
10
CC
+
+
+
(REF )
REF DC Leakage Current
CS = V = 5V, REF = 5.5V
1
CC
–
–
–
(REF )
REF DC Leakage Current
CS = V = 5V, REF = GND
1
CC
24361f
3
LTC2436-1
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The ● denotes specifications which apply over the full
DIGITAL I PUTS A D DIGITAL OUTPUTS
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
IH
V
IL
V
IH
V
IL
High Level Input Voltage
●
●
●
●
●
●
2.5
2.0
V
V
CC
CS, F
2.7V ≤ V ≤ 3.3V
O
CC
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V
O
CC
High Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 8)
2.5
2.0
V
V
CC
2.7V ≤ V ≤ 3.3V (Note 8)
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V (Note 8)
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
10
µA
µA
pF
pF
V
IN
IN
CS, F
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 8)
10
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 8)
IN
High Level Output Voltage
SDO
I = –800µA
O
●
●
●
●
●
V
V
– 0.5
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO
I = 1.6mA
O
0.4
V
High Level Output Voltage
SCK
I = –800µA (Note 9)
O
– 0.5
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 9)
O
0.4
10
V
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
CC
Conversion Mode
Sleep Mode
Sleep Mode
CS = 0V (Note 14)
●
●
200
4
2
300
13
µA
µA
µA
CS = V (Notes 11, 14)
CC
CS = V , 2.7V ≤ V ≤ 3.3V
CC
CC
(Notes 11, 14)
24361f
4
LTC2436-1
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TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.56
0.25
0.25
143.8
TYP
MAX
2000
390
UNITS
kHz
µs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
●
●
●
EOSC
HEO
390
µs
LEO
F = 0V
●
●
146.7
EOSC
149.6
(in kHz)
ms
ms
CONV
O
External Oscillator (Note 10)
20510/f
f
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
17.5
kHz
kHz
ISCK
f
/8
EOSC
D
Internal SCK Duty Cycle
(Note 9)
(Note 8)
(Note 8)
(Note 8)
●
●
●
●
45
55
%
kHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
2000
ESCK
250
250
1.06
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 19-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
●
●
1.09
1.11
ms
ms
152/f
(in kHz)
EOSC
t
t
External SCK 19-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
(Note 8)
●
●
●
●
●
●
●
●
●
19/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
1
ESCK
0
0
200
200
200
t2
t3
t4
(Note 9)
(Note 8)
0
CS ↓ to SCK ↑
50
t
t
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
220
KQMAX
KQMIN
(Note 5)
15
50
t
t
5
6
50
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 8: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 9: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
V
INCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive
(CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 4: FO pin tied to GND or to an external conversion clock source
with fEOSC = 139,800Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 11: The converter uses the internal oscillator.
FO = 0V.
Note 12: 800nV RMS noise is independent of VREF. Since the noise
performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (VREF/216) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 13: Guaranteed by design and test correlation.
Note 7: FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2%
Note 14: The low sleep mode current is valid only when CS is high.
(external oscillator).
24361f
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LTC2436-1
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PI FU CTIO S
VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
CH0+ (Pin 4): Positive Input for Differential Channel 0.
CH0– (Pin 5): Negative Input for Differential Channel 0.
CH1+ (Pin 6): Positive Input for Differential Channel 1.
CH1– (Pin 7): Negative Input for Differential Channel 1.
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and VCC. Within these limits
the converter bipolar input range (VIN = IN+ – IN–) extends
from–0.5•(VREF)to0.5•(VREF). Outsidethisinputrange
the converter produces unique overrange and underrange
output codes.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to GND (FO = 0V), the
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When FO is driven by an external
clocksignalwithafrequencyfEOSC,theconverterusesthis
signal as its system clock and the digital filter has 87dB
minimum rejection in the range fEOSC/2560 ±14% and
110dB minimum rejection at fEOSC/2560 ±4%.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow and
VCC decoupling. Connect each one of these pins to a ground
planethroughalowimpedanceconnection.Allfivepinsmust
be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
24361f
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LTC2436-1
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FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
F
O
AUTOCALIBRATION
AND CONTROL
(INT/EXT)
+
CH0
CH0
+
–
IN
IN
–
SCK
SDO
CS
DIFFERENTIAL
3RD ORDER
SERIAL
INTERFACE
MUX
∆Σ MODULATOR
+
CH1
CH1
–
+
–
DECIMATING FIR
CH0/CH1
PING-PONG
+
REF
24361 FD
–
REF
Figure 1. Functional Block Diagram
TEST CIRCUITS
V
CC
1.69k
SDO
SDO
C
= 20pF
1.69k
C
= 20pF
LOAD
LOAD
Hi-Z TO V
Hi-Z TO V
OL
OL
OH
OH
V
V
TO V
V
OL
V
OH
TO V
OH
OL
TO Hi-Z
24361 TA04
TO Hi-Z
24361 TA03
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LTC2436-1
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
formed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2436-1 with
additional serial clock pulses. This results in additional
data bits which are always logic HIGH.
Converter Operation Cycle
The LTC2436-1 is a low power, ∆Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2436-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
Whileinthissleepstate,powerconsumptionisreducedby
nearly two orders of magnitude. The conversion result is
heldindefinitelyinastaticshiftregisterwhiletheconverter
is in the sleep state.
Through timing control of the CS and SCK pins, the
LTC2436-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turbthecyclicoperationdescribedabove. Thesemodesof
operation are described in detail in the Serial Interface
Timing Modes section.
Once CS is pulled LOW, the device exits the low power
modeandentersthedataoutputstate. IfCSispulledHIGH
beforethefirstrisingedgeofSCK,thedevicereturnstothe
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2436-1 incorporates a highly accu-
rate on-chip oscillator. This eliminates the need for exter-
nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2436-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.
POWER UP
+
+
–
–
IN = CH0 , IN = CH0
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
SWITCH CHANNEL
Ease of Use
24361 F02
The LTC2436-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
Figure 2. LTC2436-1 State Transition Diagram
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cycle.Thereisaone-to-onecorrespondencebetweenthe
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
remains constant at 800nV RMS (or 4.8µVP-P), while the
quantization is reduced to 1.5µV per LSB. As a result,
lower the reference improves the effective resolution for
low level input voltages.
TheLTC2436-1performsoffsetandfull-scalecalibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
specttotime,supplyvoltagechangeandtemperaturedrift.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0+/CH0– or CH1+/CH1–
input pins extending from GND – 0.3V to VCC + 0.3V.
Outside these limits, the ESD protection devices begin to
turn on and the errors due to input leakage current
increase rapidly. Within these limits, the LTC2436-1 con-
verts the bipolar differential input signal, VIN = IN+ – IN–,
Power-Up Sequence
TheLTC2436-1automaticallyentersaninternalresetstate
when the power supply voltage VCC drops below approxi-
mately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF
=
REF+ – REF–, with the selected channel referred as IN+ and
IN–. Outside this range, the converter indicates the
overrange or the underrange condition using distinct
output codes.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signalwithatypicaldurationof1ms.ThePORsignalclears
all internal registers and selects channel 0. Following the
POR signal, the LTC2436-1 starts a normal conversion
cycleandfollowsthesuccessionofstatesdescribedabove.
ThefirstconversionresultfollowingPORisaccuratewithin
the specifications of the device if the power supply voltage
is restored within the operating range (2.7V to 5.5V) be-
fore the end of the POR time interval.
Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to main-
tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
Current sections. In addition, series resistors will intro-
duceatemperaturedependentoffseterrorduetotheinput
leakage current. A 10nA input leakage current will develop
a1LSBoffseterroronan8kresistorifVREF =5V. Thiserror
has a very strong temperature dependency.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
ficationfortheREF+ andREF– pinscoverstheentirerange
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
Output Data Format
The LTC2436-1 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is deter-
mined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will
significantly improve the converter’s effective resolution,
since the thermal noise (800nV) is well below the quanti-
zationlevelofthedevice(75.6µVfora5Vreference).Atthe
minimum reference (100mV) the thermal noise
The LTC2436-1 serial output data stream is 19 bits long.
The first 3 bits represent status information indicating the
conversion state, selected channel and sign. The next 16
bits are the conversion result, MSB first. The third and
fourth bit together are also used to indicate an underrange
condition(thedifferentialinputvoltageisbelow–FS)oran
overrangecondition(thedifferentialinputvoltageisabove
+FS).
24361f
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Bit 18 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
deviceonceCSispulledLOW.EOCchangesrealtimefrom
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 18 (EOC) can be captured on the first rising
edge of SCK. Bit 17 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 18th SCK and may be latched on
the rising edge of the 19th SCK pulse. On the falling edge
of the 19th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 18) for the next conversion cycle. Table 2 summarizes
the output data format.
Bit17(secondoutputbit)istheselectedchannelindicator.
The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 16 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 15 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 16 also
provides the underrange or overrange indication. If both
Bit 16 and Bit 15 are HIGH, the differential input voltage is
above +FS. If both Bit 16 and Bit 15 are LOW, the
differential input voltage is below –FS.
In order to remain compatible with some SPI
microcontrollers, more than 19 SCK clock pulses may be
applied. As long as these clock edges are complete before
the conversion ends, they will not effect the serial data.
However, switching SCK during a conversion may gener-
ate ground currents in the device leading to extra offset
and noise error sources.
The function of these bits is summarized in Table 1.
Table 1. LTC2436-1 Status Bits
Bit 18 Bit 17 Bit 16 Bit 15
Input Range
EOC CH0/CH1 SIG
MSB
V
≥ 0.5 • V
0
0
0
0
0 or 1
0 or 1
0 or 1
0 or 1
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
IN
REF
–0.5 • V ≤ V < 0V
REF
IN
As long as the voltage on the analog input pins is main-
tainedwithinthe–0.3Vto(VCC +0.3V)absolutemaximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS=0.5•VREF.Fordifferentialinputvoltagesgreaterthan
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
V
< –0.5 • V
IN
REF
Bits 15-0 are the 16-Bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
CS
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 1
BIT 0
LSB
SDO
SCK
CH0/CH1
16
Hi-Z
1
2
3
4
5
17
18
19
SLEEP
DATA OUTPUT
CONVERSION
24361 F03
Figure 3. Output Data Timing
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Table 2. LTC2436-1 Output Data Format
Differential Input Voltage
Bit 18
EOC
Bit 17
CH0/CH1
Bit 16
SIG
Bit 15
MSB
Bit 14
Bit 13
Bit 12
…
Bit 0
V
IN
*
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
IN
REF
+
–
*The differential input voltage V = IN – IN .
IN
+
–
**The differential reference voltage V = REF – REF .
REF
–80
–90
–80
–85
–90
–95
–100
–100
–120
–130
–140
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
48
50
52
54
56
58
60
62
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DEVIATION FROM NOTCH FREQUENCY f
/2560(%)
EOSC
24361 F04
24361 F05
Figure 4. LTC2436-1 Normal Mode
Rejection When Using an Internal Oscillator
Figure 5. LTC2436-1 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hztobedetected.Theexternalclocksignaldutycycle
is not significant as long as the minimum and maximum
Simultaneous Frequency Rejection
The LTC2436-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz as shown in Figure 4. For this simultaneous 50Hz/
60Hz rejection, FO should be connected to GND.
specifications for the high and low periods, tHEO and tLEO
,
are observed.
While operating with an external conversion clock of a
frequencyfEOSC,theLTC2436-1providesbetterthan110dB
normal mode rejection in a frequency range fEOSC/2560
±4%. The normal mode rejection as a function of the input
frequency deviation from fEOSC/2560 is shown in Figure 5.
24361f
When a fundamental rejection frequency different from
therange49Hzto61.2Hzisrequiredorwhentheconverter
mustbesychronizedwithanoutsidesource,theLTC2436-1
canoperatewithanexternalconversionclock.Theconveter
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Whenever an external clock is not present at the FO pin the
converterautomaticallyactivatesitsinternaloscillatorand
enterstheInternalConversionClockmode.TheLTC2436-1
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
notbeaffected.Ifthechangeoccursduringthedataoutput
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2436-1 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internalorexternalSCKmodeisselectedonpower-upand
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW.
The LTC2436-1 transmits the conversion results and
receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
Chip Select Input (CS)
The serial clock signal present on SCK (Pin 13) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
The active LOW chip select, CS (Pin 11), is used to test the
conversionstatusandtoenablethedataoutputtransferas
described in the previous sections.
Table 3. LTC2436-1 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW
Simultaneous 50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s
O
External Oscillator
F = External Oscillator
20510/f
s, Output Data Rate ≤ f
/20510 Readings/s
EOSC
O
EOSC
with Frequency f
kHz
EOSC
(f
EOSC
/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
External Serial Clock with
F = LOW
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.09ms
(19 SCK cycles)
O
F = External Oscillator with
As Long As CS = LOW But Not Longer Than 152/f
ms
EOSC
O
Frequency f
kHz
(19 SCK cycles)
EOSC
As Long As CS = LOW But Not Longer Than 19/f ms
SCK
Frequency f
kHz
(19 SCK cycles)
SCK
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In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2436-1 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
operation. These include internal/external serial clock,
2-or3-wireI/O,singlecycleconversionandautostart.The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW) or an external
oscillator connected to the FO pin. Refer to Table 4 for a
summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 6.
SERIAL INTERFACE TIMING MODES
The serial clock mode is selected on the falling edge of CS.
Toselecttheexternalserialclockmode,theserialclockpin
(SCK) must be LOW during each CS falling edge.
The LTC2436-1’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
Table 4. LTC2436-1 Interface Timing Modes
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
SCK
Configuration
Source
External
External
Internal
Internal
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 6, 7
Figure 8
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
CS ↓
CS ↓
Figures 9, 10
Figure 11
Continuous
Internal
2.7V TO 5.5V
1µF
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
1
14
V
F
CC
O
LTC2436-1
+
2
3
4
5
6
7
REFERENCE
VOLTAGE
REF
REF
13
12
11
–
+
0.1V TO V
SCK
SDO
CS
CC
3-WIRE
SPI INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V TO 0.5V
REF
REF
8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
Hi-Z
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SDO
CH0/CH1
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
24361 F06
TEST EOC
(OPTIONAL)
Figure 6. External Serial Clock, Single Cycle Operation
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SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for abort-
ing an invalid conversion cycle or synchronizing the start
of a conversion.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
2.7V TO 5.5V
1µF
= EXTERNAL CLOCK SOURCE
14
1
V
F
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
CC
O
LTC2436-1
+
2
3
4
5
6
7
REFERENCE
VOLTAGE
REF
REF
13
12
11
–
+
0.1V TO V
SCK
SDO
CS
CC
3-WIRE
SPI INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V
TO 0.5V
REF
REF
8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 5
BIT 4
SDO
CH0/CH1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
SLEEP
TEST EOC (OPTIONAL)
SLEEP
24361 F07
DATA
OUTPUT
Figure 7. External Serial Clock, Reduced Data Output Length
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External Serial Clock, 2-Wire I/O
Internal Serial Clock, Single Cycle Operation
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
externalcontrollerindicatingtheconversionresultisready.
EOC = 1 while the conversion is in progress and EOC = 0
once the conversion ends. On the falling edge of EOC, the
conversion result is loaded into an internal static shift reg-
ister. Data is shifted out the SDO pin on each falling edge
of SCK enabling external circuitry to latch data on the ris-
ingedgeofSCK.EOCcanbelatchedonthefirstrisingedge
of SCK. On the 19th falling edge of SCK, SDO goes HIGH
(EOC = 1) indicating a new conversion has begun.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
WhentestingEOC,iftheconversioniscomplete(EOC=0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
2.7V TO 5.5V
1µF
= EXTERNAL CLOCK SOURCE
14
1
V
F
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
CC
O
LTC2436-1
+
2
3
4
5
6
7
REFERENCE
VOLTAGE
REF
REF
13
12
11
–
+
0.1V TO V
SCK
SDO
CS
CC
2-WIRE
INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V TO 0.5V
REF REF
8, 9, 10, 15, 16
GND
CS
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SDO
CH0/CH1
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
24361 F08
Figure 8. External Serial Clock, CS = 0 Operation (2-Wire)
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V
CC
2.7V TO 5.5V
1µF
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
1
14
V
F
CC
O
10k
LTC2436-1
+
2
REFERENCE
VOLTAGE
0.1V TO V
REF
REF
3
4
5
6
7
13
12
11
–
+
SCK
SDO
CS
CC
3-WIRE
SPI INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V
TO 0.5V
REF
REF
8, 9, 10, 15, 16
GND
<t
EOCtest
CS
TEST EOC
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SDO
CH0/CH1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
24361 F09
TEST EOC
(OPTIONAL)
Figure 9. Internal Serial Clock, Single Cycle Operation
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23µs if the device is using its internal
oscillator (F0 = logic LOW). If FO is driven by an external
oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conver-
sion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin.Thedataoutputcycleconcludes
after the 19th rising edge. Data is shifted out the SDO pin
oneachfallingedgeofSCK. Theinternallygeneratedserial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 19th rising edge of SCK.
After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
Whenever SCK is LOW, the LTC2436-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a
LOW signal, the LTC2436-1’s internal pull-up remains
24361f
16
LTC2436-1
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APPLICATIO S I FOR ATIO
U
2.7V TO 5.5V
V
CC
1µF
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
1
14
V
F
CC
O
10k
LTC2436-1
+
2
3
4
5
6
7
REFERENCE
VOLTAGE
REF
REF
13
12
11
–
+
0.1V TO V
SCK
SDO
CS
CC
3-WIRE
SPI INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V TO 0.5V
REF
REF
8, 9, 10, 15, 16
GND
>t
EOCtest
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
SDO
CH0/CH1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
24361 F10
DATA
OUTPUT
TEST EOC
(OPTIONAL)
Figure 10. Internal Serial Clock, Reduced Data Output Length
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
=0),SCKwillgoLOW.OnceCSgoesHIGH(withinthetime
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately1msafterVCC exceeds2V. Aninternalweak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
24361f
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LTC2436-1
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APPLICATIO S I FOR ATIO
2.7V TO 5.5V
1µF
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
1
14
V
F
CC
O
LTC2436-1
+
2
REFERENCE
VOLTAGE
0.1V TO V
REF
REF
3
4
5
6
7
13
12
11
–
+
SCK
SDO
CS
CC
2-WIRE
INTERFACE
CH0
CH0
CH1
CH1
–
+
–
ANALOG INPUT RANGE
–0.5V TO 0.5V
REF
REF
8, 9, 10, 15, 16
GND
CS
BIT 18
EOC
BIT 17
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SDO
CH0/CH1
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
24361 F11
Figure 11. Internal Serial Clock, Continuous Operation
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 19th rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 19th rising
edge of SCK. After the 19th rising edge, SDO goes HIGH
(EOC=1)indicatinganewconversionisinprogress.SCK
remains HIGH during the conversion.
Digital Signal Levels
The LTC2436-1’s digital interface is easy to use. Its digital
inputs(FO,CSandSCKinExternalSCKmodeofoperation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs.However,someconsiderationsarerequiredtotake
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
inExternalSCKmodeofoperation)iswithinthisrange,the
LTC2436-1 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
PRESERVING THE CONVERTER ACCURACY
TheLTC2436-1isdesignedtoreduceasmuchaspossible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
accuracy capability of this part, some simple precautions
are desirable.
signals to full CMOS levels [VIL < 0.4V and VOH
(VCC – 0.4V)].
>
24361f
18
LTC2436-1
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U
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the
LTC2436-1pinsmayseverelydisturbtheanalogtodigital
conversion process. Undershoot and overshoot can oc-
cur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2436-1.Forreference,onaregularFR-4board,signal
propagation velocity is approximately 183ps/inch for
internal traces and 170ps/inch for surface traces. Thus, a
driver generating a control signal with a minimum transi-
tion time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Such perturbations may occur due to asymmetric capaci-
tivecouplingbetweentheFO signaltraceandtheconverter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formedbytheFO connectiontrace, theterminationandthe
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2436-1 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins
transfering small amounts of charge in the process. A
simplified equivalent circuit is shown in Figure 12, where
IN+ and IN– refer to the selected differential channel and
the unselected channel is omitted for simplicity.
Parallel termination near the LTC2436-1 pin will eliminate
thisproblembutwillincreasethedriverpowerdissipation.
A series resistor between 27Ω and 56Ω placed near the
driver will also eliminate this problem without additional
powerdissipation. Theactualresistorvaluedependsupon
the trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 12), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1LSB accuracy if
the sampling period is at least 11 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
Particular attention must be given to the connection of the
FO signal when the LTC2436-1 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converterinputterminalsmayresultintoaDCoffseterror.
When using the internal oscillator (FO = LOW), the
LTC2436-1’s front-end switched-capacitor network is
clocked at 69900Hz corresponding to a 14.3µs sampling
24361f
19
LTC2436-1
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APPLICATIO S I FOR ATIO
V
CC
I
+
+
REF
R
R
(TYP)
SW
SW
VIN + VINCM − VREFCM
I
I
I IN+
=
=
LEAK
(
)
)
20k
AVG
AVG
0.5• REQ
−VIN + VINCM − VREFCM
0.5• REQ
V
REF
I IN−
(
LEAK
V
V2
CC
1.5• VREF − VINCM + VREFCM
IN
I REF+
=
−
I
+
IN
(
)
(TYP)
20k
AVG
0.5• REQ
V
REF • REQ
I
I
LEAK
V2
−1.5• VREF − VINCM + VREFCM
0.5• REQ
IN
I REF−
=
+
V
+
IN
(
)
C
AVG
V
REF • REQ
EQ
LEAK
18pF
where:
(TYP)
V
CC
VREF = REF+ −REF−
I
–
–
IN
IN
R
R
(TYP)
REF+ +REF−
SW
I
LEAK
LEAK
20k
VREFCM =
2
V
I
V
IN =IN+ −IN−
IN+ −IN−
V
CC
V
INCM
=
I
–
–
2
REF
(TYP)
20k
SW
I
I
LEAK
LEAK
REQ = 3.97MΩ INTERNAL OSCILLATOR 50Hz/60Hz Notch F = LOW
REQ = 0.555• 1012 / fEOSCEXTERNAL OSCILLATOR
(
)
O
24361 F12
V
REF
(
)
SWITCHING FREQUENCY
f
f
= 69.900Hz INTERNAL OSCILLATOR (F = LOW OR HIGH)
SW
SW
O
= 0.5 • f
EXTERNAL OSCILLATOR
EOSC
Figure 12. LTC2436-1 Equivalent Analog Input Circuit
R
SOURCE
period. Thus, for settling errors of less than 1LSB, the
driving source impedance should be chosen such that τ ≤
14.3µs/11 = 1.3µs. When an external oscillator of fre-
quency fEOSC is used, the sampling period is 2/fEOSC and,
+
IN
C
C
PAR
V
+ 0.5V
C
C
INCM
INCM
IN
IN
20pF
LTC2436-1
for a settling error of less than 1LSB, τ ≤ 0.18/fEOSC
.
R
SOURCE
–
IN
24361 F13
PAR
20pF
Input Current
V
– 0.5V
IN
IN
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
theINLperformanceoftheconverter. Figure12showsthe
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
Figure 13. An RC Network at IN+ and IN–
3
C
= 0.01µF
IN
C
= 0.001µF
IN
C
= 100pF
IN
2
1
C
= 0pF
IN
V
= 5V
CC
+
REF = 5V
–
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 13. The CPAR capacitor
includes the LTC2436-1 pin capacitance (5pF typical) plus
thecapacitanceofthetestfixtureusedtoobtaintheresults
shown in Figures 14 and 15. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
REF = GND
+
–
IN = 5V
IN = 2.5V
F
= GND
= 25°C
O
A
T
0
1
10
100
1k
10k
100k
R
(Ω)
SOURCE
24361 F14
Figure 14. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
24361f
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0
20
16
12
8
V
= 5V
V
= 5V
CC
CC
+
+
C
= 1µF, 10µF
REF = 5V
REF = 5V
IN
–
–
REF = GND
REF = GND
+
–
+
–
IN = GND
IN = 3.75V
IN = 2.5V
IN = 1.25V
–1
F
= GND
= 25°C
F
= GND
= 25°C
O
A
O
A
T
T
C
IN
= 0.1µF
C
= 0.01µF
IN
–2
–3
C
= 0.001µF
C
IN
= 0.01µF
IN
4
C
= 100pF
IN
C
= 0pF
IN
0
1
10
100
1k
(Ω)
10k
100k
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
R
SOURCE
SOURCE
24361 F15
24361 F16
Figure 15. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
Figures14and15.Thesemeasuredresultsmaybeslightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small CIN values, the
settling on IN+ and IN– occurs almost independently and
there is little benefit in trying to match the source imped-
ance for the two pins.
C
= 0.01µF
= 0.1µF
IN
–4
–8
C
IN
V
= 5V
CC
–12
–16
–20
+
REF = 5V
–
REF = GND
+
–
IN = 1.25V
IN = 3.75V
F
= GND
= 25°C
C
= 1µF, 10µF
O
A
IN
T
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
WhenFO =LOW(internaloscillatorand50Hz/60Hznotch),
the typical differential input resistance is 2MΩ which will
generate a gain error of approximately 1LSB at full scale
for each 60Ω of source resistance driving IN+ or IN–.
When FO is driven by an external oscillator with a fre-
quency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.28 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN– will
result in 1.11 • 10–7 • fEOSCLSB gain error at full scale. The
effect of the source resistance on the two input pins is
additivewithrespecttothisgainerror. Thetypical+FSand
–FS errors as a function of the sum of the source resis-
tanceseenbyIN+ andIN– forlargevaluesofCIN areshown
in Figures 16 and 17.
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
SOURCE
24361 F17
Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
by Figures 14 and 15. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (CIN
<
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performancewithoutsignificantbenefitsofsignalfiltering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2436-1 can maintain its accuracy while operating with
relative large values of source resistance as shown in
24361f
21
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APPLICATIO S I FOR ATIO
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuitnonzerosourceimpedancecombinedwiththecon-
verter average input current will not degrade the INL
performance,indirectdistortionmayresultfromthemodu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, itisadvisabletocarefullymatchthesourceimped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internaloscillatorand50Hz/60Hznotch), every60Ωmis-
match in source impedance transforms a full-scale com-
mon mode input signal into a differential mode input
signal of 1LSB. When FO is driven by an external oscillator
with a frequency fEOSC, every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 1.11 • 10–7
• fEOSCLSB. Figure 18 shows the typical offset error due to
input common mode voltage for various values of source
resistance imbalance between the IN+ and IN– pins when
large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 15k source resistance will create
a 0LSB typical and 1LSB maximum offset voltage.
8
V
= 5V
CC
+
REF = 5V
A
B
–
REF = GND
IN = IN = V
+
–
Reference Current
INCM
4
0
In a similar fashion, the LTC2436-1 samples the differen-
tialreferencepinsREF+ andREF– transferingsmallamount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gainandINLperformance.Theeffectofthiscurrentcanbe
analyzed in the same two distinct situations.
C
D
E
F
–4
–8
F
= GND
O
A
G
T
= 25°C
R
C
– = 500Ω
SOURCEIN
= 10µF
IN
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
(V)
INCM
Forrelativelysmallvaluesoftheexternalreferencecapaci-
tors(CREF <0.01µF),thevoltageonthesamplingcapacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gainperformancewithoutsignificantbenefitsofreference
filtering and the user is advised to avoid them.
A: ∆R = +400Ω
E: ∆R = –100Ω
IN
IN
B: ∆R = +200Ω
F: ∆R = –200Ω
IN
IN
C: ∆R = +100Ω
G: ∆R = –400Ω
IN
IN
D: ∆R = 0Ω
24361 F18
IN
Figure 18. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
24361f
22
LTC2436-1
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U
Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internal oscillator and 50Hz/60Hz notch), the typical
differential reference resistance is 1.4MΩ which will gen-
erate a gain error of approximately 1LSB full scale for each
40Ω of source resistance driving REF+ or REF–. When FO
is driven by an external oscillator with a frequency fEOSC
(externalconversionclockoperation), thetypicaldifferen-
tial reference resistance is 0.20 • 1012/fEOSCΩ and each
ohm of source resistance drving REF+ or REF– will result
in 1.54 • 10–7 • fEOSCLSB gain error at full scale. The effect
of the source resistance on the two reference pins is
additivewithrespecttothisgainerror. Thetypical+FSand
–FS errors for various combinations of source resistance
seen by the REF+ and REF– pins and external capacitance
C
REF connected to these pins are shown in Figures 19, 20,
21 and 22.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
WhenFO =LOW(internaloscillatorand50Hz/60Hznotch),
every 1000Ω of source resistance driving REF+ or REF–
translates into about 1LSB additional INL error. When FO
is driven by an external oscillator with a frequency fEOSC
,
every 100Ω of source resistance driving REF+ or REF–
3
0
V
= 5V
CC
C
= 0.01µF
REF
+
REF = 5V
–
C
= 0.001µF
REF = GND
REF
C
+
–
IN = 5V
= 100pF
REF
IN = 2.5V
2
1
0
–1
–2
–3
F
= GND
= 25°C
O
A
C = 0pF
REF
T
V
= 5V
CC
C
= 0.01µF
REF
+
–
REF = 5V
REF = GND
+
–
C
= 0.001µF
REF
IN = GND
IN = 2.5V
C
= 100pF
= 0pF
REF
C
F
= GND
O
T
= 25°C
A
REF
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
R
(Ω)
R
(Ω)
SOURCE
SOURCE
24361 F19
2412 F19
Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
30
0
V
= 5V
CC
C
= 0.01µF
REF
+
C
= 1µF, 10µF
REF = 5V
REF
–
REF = GND
22
17
11
6
+
–
6
11
17
22
30
IN = 1.25V
IN = 3.75V
F
= GND
= 25°C
O
A
T
C
= 0.1µF
REF
C
REF
= 0.1µF
V
= 5V
CC
+
REF = 5V
–
REF = GND
+
–
C
= 0.01µF
REF
IN = 3.75V
IN = 1.25V
C
= 1µF, 10µF
REF
F
= GND
= 25°C
O
A
T
0
0
100 200 300 400 500 600 700 800 9001000
(Ω)
0
100 200 300 400 500 600 700 800 9001000
(Ω)
R
R
SOURCE
SOURCE
24361 F22
24361 F21
Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
24361f
23
LTC2436-1
W U U
U
APPLICATIO S I FOR ATIO
translates into about 5.5 • 10–7 • fEOSCLSB additional INL
error. Figure 23 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
Inadditiontothereferencesamplingcharge,thereference
pinsESDprotectiondiodeshaveatemperaturedependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2436-1 can
produce up to 6.8 readings per second. The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2436-1 output data rate can be in-
creased as desired. The duration of the conversion phase
is 20510/fEOSC. If fEOSC = 139,800Hz, the converter be-
havesasiftheinternaloscillatorisusedwithsimultaneous
50Hz/60Hz. There is no significant difference in the
LTC2436-1 performance between these two operation
modes.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
valueovertheentiretemperatureandvoltagerange). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
An increase in fEOSC over the nominal 139,800Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
1
R
= 1000Ω
SOURCE
First,achangeinfEOSC willresultinaproportionalchange
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2436-1’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
0
–1
–0.5–0.4–0.3–0.2–0.1
0
0.1 0.2 0.3 0.4 0.5
V
/V
INDIF REFDIF
V
= 5V
F = GND
O
CC
REF+ = 5V
C
= 10µF
REF
REF– = GND
V
T = 25°C
A
+
–
= 0.5 • (IN + IN ) = 2.5V
24361 F23
INCM
Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
24361f
24
LTC2436-1
W U U
APPLICATIO S I FOR ATIO
U
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
theexternalsourceresistanceupontheLTC2436-1typical
performance can be inferred from Figures 14, 15, 19 and
Third, an increase in the frequency of the external oscilla-
torabove460800Hz(amorethan3×increaseintheoutput
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a pro-
gressive degradation in the converter accuracy and linear-
ity. Typical measured performance curves for output data
rates up to 100 readings per second are shown in Fig-
ures 24, 25, 26, 27, 28 and 29. In order to obtain the
20 in which the horizontal axis is scaled by 139,800/fEOSC
.
420
30
V
= 5V
V
= 5V
CC
CC
+
+
REF = 5V
REF = 5V
–
360
300
240
180
120
60
–
REF = GND
REF = GND
+
–
IN = 3.75V
V
V
F
= 2.5V
INCM
IN = 1.25V
= 0V
IN
F
= EXTERNAL OSCILLATOR
= EXTERNAL OSCILLATOR
O
O
15
T
= 85°C
A
T
A
= 85°C
T
= 25°C
A
T
A
= 25°C
0
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F25
24361 F24
Figure 24. Offset Error vs Output Data Rate and Temperature
Figure 25. +FS Error vs Output Data Rate and Temperature
0
17
16
60
T
= 85°C
A
T
= 25°C
A
120
180
240
300
360
420
T
= 25°C
A
15
14
13
12
T
= 85°C
A
V
= 5V
CC
+
REF = 5V
V
= 5V
CC
–
+
REF = GND
REF = 5V
–
V
V
F
= 2.5V
REF = GND
INCM
+
–
= 0V
IN = 1.25V
IN
= EXTERNAL OSCILLATOR
RESOLUTION = LOG (V /NOISE
IN = 3.75V
O
)
F
O
= EXTERNAL OSCILLATOR
2
REF
RMS
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F26
24361 F27
Figure 26. –FS Error vs Output Data Rate and Temperature
Figure 27. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
24361f
25
LTC2436-1
W U U
U
APPLICATIO S I FOR ATIO
18
16
V
= 5V
CC
+
REF = GND
V
V
= 2.5V
INCM
16
= 0V
IN
T
= 25°C
A
F = EXTERNAL OSCILLATOR
O
T
= 85°C
A
T
= 25°C
A
14
12
10
8
8
V
= 5V
CC
+
REF = 5V
V
= 5V
REF
–
REF = GND
= 2.5V
V
= 2.5V
REF
V
INCM
–2.5V < V < 2.5V
IN
F
O
= EXTERNAL OSCILLATOR
RESOLUTION = LOG (V /INL )
MAX
2
REF
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F28
24361 F29
Figure 28. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 29. Offset Error vs Output
Data Rate and Reference Voltage
highest possible level of accuracy from this converter at
output data rates above 20 readings per second, the user
is advised to maximize the power supply voltage used and
to limit the maximum ambient operating temperature. In
certaincircumstances, areductionofthedifferentialrefer-
ence voltage may be beneficial.
outputcodewillbestableto±1LSBforafixedinput. Asthe
reference is decreased further, the measured noise will
approach 800nVRMS
.
Figure 30 shows two methods of dividing down the
referencevoltagetotheLTC2436-1.Whereabsoluteaccu-
racy is required, a precision divider such as the Vishay
MPM series dividers in a SOT-23 package may be used. A
51:1 divider provides a 98mV reference to the LTC2436-
1 from a 5V source. The resulting ±49mV input range and
1.5µV LSB is suitable for thermocouple and 10mV full-
scale strain gauge measurements.
Increasing Input Resolution by Reducing Reference
Voltage
The resolution of the LTC2436-1 can be increased by
reducing the reference voltage. It is often necessary to
amplify low level signals to increase the voltage resolution
of ADCs that cannot operate with a low reference voltage.
TheLTC2436-1canbeusedwithreferencevoltagesaslow
as100mV,correspondingtoa±50mVinputrangewithfull
16-bit resolution. Reducing the reference voltage is func-
tionally equivalent to amplifying the input signal, however
no amplifier is required.
If high initial accuracy is not critical, a standard 2%
resistor array such as the Panasonic EXB series may be
used. Single package resistor arrays provide better tem-
perature stability than discrete resistors. An array of eight
resistors can be configured as shown to provide a 294mV
reference to the LTC2436-1 from a 5V source. The fully
differentialpropertyoftheLTC2436-1referenceterminals
allow the reference voltage to be taken from four central
resistors in the network connected in parallel, minimizing
drift in the presence of thermal gradients. This is an ideal
reference for medium accuracy sensors such as silicon
micromachined pressure and force sensors. These de-
vicestypicallyhaveaccuraciesontheorderof2%andfull-
scale outputs of 50mV to 200mV.
The LTC2436-1 has a 76µV LSB when used with a 5V
reference, however the thermal noise of the inputs is
800nVRMS and is independent of reference voltage. Thus
reducing the reference voltage will increase the resolution
at the inputs as long as the LSB voltage is significantly
largerthan800nVRMS. A325mVreferencecorrespondsto
a 5µV LSB, which is approximately the peak-to-peak value
of the 800nVRMS input thermal noise. At this point, the
24361f
26
LTC2436-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
24361f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC2436-1
U
TYPICAL APPLICATIO
PANASONIC EXB-2HV202G
+
–
5V
REF
REF
5V
8 × 2k
ARRAY
0.1µF
4.7µF
1
2
3
4
14
F
O
V
CC
+
V
REF
= 294mV
REF
REF
±147mV INPUT RANGE
4.5µV LSB
–
+
5V
CH0
VISHAY MPM1001/5002B
5V
LTC2436-1
HONEYWELL
FSL05N2C
5
13
–
SCK
CH0
500 GRAM
12
11
FORCE SENSOR
SDO
CS
50k
6
7
+
–
+
–
CH1
CH1
REF
THERMOCOUPLE
1k
8, 9, 10, 15, 16
GND
24361 F30
REF
V
REF
= 95.04mV
±49mV INPUT RANGE
1.5µV LSB
Figure 30. Increased Resolution Bridge/Temperature Measurement
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
3ppm/°C Drift, 0.05% Max
Precise Charge, Balanced Switching, Low Power
LT1019
Precision Bandgap Reference, 2.5V, 5V
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
No External Components 5µV Offset, 1.6µV Noise
P-P
LT1236A-5
LT1461
0.05% Max, 5ppm/°C Drift
Micropower Precision LDO Reference
24-Bit, No Latency ∆Σ ADC in SO-8
High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
LTC2404/LTC2408
LTC2410
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
24-Bit, Fully Differential, No Latency ∆Σ ADC
24-Bit, No Latency ∆Σ ADC in MSOP
LTC2411
1.45µV
Noise, 2ppm INL
RMS
LTC2411-1
LTC2412
24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC
2-Channel, 24-Bit, Pin Compatible with LTC2436-1
24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
800nV Noise, 2ppm INL, 3ppm TUE, 200µA
LTC2413
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
LTC2414/LTC2418
LTC2415
8-/16-Channel, 24-Bit No Latency ∆Σ ADC
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
20-Bit, No Latency ∆Σ ADC in SO-8
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
Pin Compatible with the LTC2410
LTC2420
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
4kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2424/LTC2428
LTC2440
4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
High Speed, Low Noise 24-Bit ADC
24361f
LT/TP 0103 2K • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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