LTC2439-1_技术文档

LTC2439-1

8-/16-Channel

16-Bit No Latency ∆Σ^TMADC

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FEATURES

DESCRIPTIO

■

16-Channel Single-Ended or 8-Channel Differential

The LTC^®2439-1 is a 16-channel (8-differential)

micropower 16-bit ∆Σ analog-to-digital converter. It op-

erates from 2.7V to 5.5V and includes an integrated

oscillator,0.12LSBINL and1µVRMSnoise.Itusesdelta-

sigma technology and provides single cycle settling time

for multiplexed applications. Through a single pin, the

LTC2439-1 can be configured for better than 87dB differ-

ential mode rejection at 50Hz and 60Hz ±2%, or it can be

driven by an external oscillator for a user-defined rejec-

tionfrequency.Theinternaloscillatorrequiresnoexternal

frequency setting components.

Inputs

■

Low Supply Current (200µA, 4µA in Autosleep)

■

Rail-to-Rail Differential Input/Reference

16-Bit No Missing Codes

■

1µV RMS Noise, 16-ENOBS Independent of V_REF

■

Very Low Transition Noise: Less Than 0.02LSB

Operates with a Reference as Low as 100mV with

1.5µV LSB Step Size

■

Guaranteed Modulator Stability and Lock-Up

Immunity for Any Input and Reference Conditions

Single Supply 2.7V to 5.5V Operation

Internal Oscillator—No External Components

Required

87dB Min, 50Hz and 60Hz Simultaneous Notch Filter

Pin Compatible with the 24-Bit LTC2418

■

The LTC2439-1 accepts any external differential reference

voltagefrom0.1VtoV_CCforflexibleratiometricandremote

sensing measurement applications. It can be configured

totake8differentialchannelsor16single-endedchannels.

The full-scale bipolar input range is from –0.5V_REFto

0.5V_REF.Thereferencecommonmodevoltage,V_REFCM,and

the input common mode voltage, V_INCM, may be indepen-

dently set between GND and V_CC. The DC common mode

input rejection is better than 140dB.

■

^{28-Lead SSOP P}U^ackage

APPLICATIO S

■

Direct Sensor Digitizer

Weight Scales

Direct Temperature Measurement

Gas Analyzers

Strain Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

■

The LTC2439-1 communicates through a flexible

4-wire digital interface that is compatible with SPI and

MICROWIRE^TMprotocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

■

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TYPICAL APPLICATIO

Minimum Resolvable

Signal vs V_REF

2.7V TO 5.5V

11

90

1µF

9

80

+

REF

V

CC

21 CH0

22 CH1

70

19

F

= EXTERNAL OSCILLATOR

O

60

= 50Hz and 60Hz REJECTION

•

50

20

28 CH7

SDI

SCK

SDO

CS

16-CHANNEL

MUX

18

17

16

1

CH8

40

+

–

DIFFERENTIAL

16-BIT ∆Σ ADC

4-WIRE

SPI INTERFACE

THERMOCOUPLE

•

30

8

CH15

20

10

0

10 COM

–

12 REF

0

4

5

1

2

3

(V)

15

GND

LTC2439-1

V

24361 TA02

REF

*FOR V

= 0.4V RESOLUTION IS LIMITED BY STEP SIZE

REF

241418 TA01a

24391f

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LTC2439-1

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Notes 1, 2)

ORDER PART

NUMBER

TOP VIEW

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (V_CC+ 0.3V)

Reference Input Voltage to GND .. –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

Operating Temperature Range

LTC2439-1C ............................................ 0°C to 70°C

LTC2439-1I ........................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

1

2

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

SDI

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CH8

CH9

LTC2439-1CGN

LTC2439-1IGN

3

CH10

CH11

CH12

CH13

CH14

CH15

4

5

6

7

8

9

V

CC

10

11

12

13

14

F

O

COM

+

SCK

SDO

CS

REF

–

REF

NC

GND

GN PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)

●

16

Bits

REF

CC

REF

IN

REF

+

–

Integral Nonlinearity

4.5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

= 2.5V, (Note 6)

0.06

0.12

0.30

LSB

CC

INCM

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

REF = 2.5V, REF = GND, V

1.25

20

CC

INCM

+

–

= 1.25V, (Notes 6, 15)

INCM

+

–

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

5

µV

nV/°C

LSB

CC

+

–

GND ≤ IN = IN ≤ V , (Notes 12,15)

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

10

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

Negative Full-Scale Error Drift

Total Unadjusted Error

2.5V ≤ REF ≤ V , REF = GND,

●

0.16

0.03

0.16

0.03

1.25

CC

+

–

+

IN = 0.75REF , IN = 0.25 • REF (Note 15)

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V /°C

CC

REF

+

–

+

IN = 0.75REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

LSB

CC

+

–

+

IN = 0.25 • REF , IN = 0.75 • REF (Note 15)

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V /°C

CC

REF

+

–

+

IN = 0.25 • REF , IN = 0.75 • REF

+

–

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

REF = 2.5V, REF = GND, V

= 1.25V

= 2.5V

0.20

0.25

LSB

CC

INCM

+

–

CC

INCM

+

–

= 1.25V, (Note 6)

INCM

+

Output Noise

5V ≤ V ≤ 5.5V, REF = 5V, V – = GND,

1

µV

RMS

CC

REF

–

+

GND ≤ IN = IN ≤ 5V (Note 12)

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LTC2439-1

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CO VERTER CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,

●

130

140

dB

CC

–

+

GND ≤ IN = IN ≤ V (Note 5)

CC

+

–

Input Common Mode Rejection

49Hz to 61.2Hz

2.5V ≤ REF ≤ V , REF = GND,

140

87

dB

CC

–

+

GND ≤ IN = IN ≤ V , (Note 5)

CC

Input Normal Mode Rejection

49Hz to 61.2Hz

(Note 5)

+

–

Reference Common Mode

Rejection DC

2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,

130

140

CC

–

+

V

= 2.5V, IN = IN = GND (Note 5)

REF

+

–

+

Power Supply Rejection, DC

REF = 2.5V, REF = GND, IN = IN = GND

120

dB

+

–

+

Power Supply Rejection,

REF = 2.5V, REF = GND, IN = IN = GND

Simultaneous 50Hz/60Hz ±2%

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A ALOG I PUT A D REFERE CE

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

IN

Absolute/Common Mode IN Voltage

●

GND – 0.3

V

+ 0.3

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3

/2

V

Input Differential Voltage Range

– V /2

V

IN

REF

+

–

(IN – IN )

+

–

+

REF

Absolute/Common Mode REF Voltage

●

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1

CC

V

Reference Differential Voltage Range

V

CC

REF

+

–

(REF – REF )

+

C (IN )

IN Sampling Capacitance

18

1

pF

nA

S

–

C (IN )

IN Sampling Capacitance

S

+

C (REF )

REF Sampling Capacitance

S

–

C (REF )

REF Sampling Capacitance

S

+

I

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = GND

●

–100

100

DC_LEAK

CC

–

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = 5V

1

CC

+

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = 5V

1

CC

–

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = GND

1

CC

Off Channel to On Channel Isolation

(R = 100Ω)

IN

DC

1Hz

f = 15,3600Hz

S

140

dB

t

I

MUX Break-Before-Make Interval

Channel Off Leakage Current

2.7V ≤ V ≤ 5.5V

100

1

ns

OPEN

CC

Channel at V and GND

●

–100

100

nA

S(OFF)

CC

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LTC2439-1

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DIGITAL I PUTS A D DIGITAL OUTPUTS

The ● denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

IH

V

IL

V

IH

V

IL

High Level Input Voltage

●

2.5

2.0

V

CC

CS, F , SDI

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

CS, F , SDI

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 8)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 8)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 8)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 8)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F , SDI

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 8)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F , SDI

O

Digital Input Capacitance

SCK

(Note 8)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 9)

O

– 0.5

V

CC

Low Level Output Voltage

SCK

I = 1.6mA (Note 9)

O

0.4

10

V

I

Hi-Z Output Leakage

SDO

–10

µA

OZ

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POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

2.7

5.5

V

CC

I

CC

Conversion Mode

Sleep Mode

CS = 0V (Note 11)

●

200

4

2

300

15

µA

CS = V (Note 11)

CC

CS = V , 2.7V ≤ V ≤ 3.3V (Note 11, 14)

CC

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LTC2439-1

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TI I G CHARACTERISTICS ^The● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.25

143.8

TYP

MAX

2000

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

390

µs

LEO

F = 0V

●

146.7

EOSC

149.6

(in kHz)

ms

CONV

O

External Oscillator (Note 10)

20510/f

f

Internal SCK Frequency

Internal Oscillator (Note 9)

External Oscillator (Notes 9, 10)

17.5

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 9)

(Note 8)

●

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

External SCK High Period

2000

ESCK

250

1.06

LESCK

ns

HESCK

DOUT_ISCK

Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11)

External Oscillator (Notes 9, 10)

●

1.09

1.11

ms

152/f

(in kHz)

EOSC

t

External SCK 19-Bit Data Output Time (Note 7)

CS ↓ to SDO Low

●

19/f

(in kHz)

ms

ns

DOUT_ESCK

1

ESCK

0

200

t2

t3

t4

CS ↑ to SDO High Z

CS ↓ to SCK ↓

(Note 9)

(Note 8)

0

CS ↓ to SCK ↑

50

t

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

SDI Setup Before SCK↑

SDI Hold After SCK↑

220

50

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

t

(Note 5)

100

7

8

t

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 8: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 9: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output. In this mode of operation the

SCK pin has a total equivalent load capacitance C_LOAD= 20pF.

Note 3: V_CC= 2.7V to 5.5V unless otherwise specified.

V_REF= REF⁺– REF^–, V_REFCM= (REF⁺+ REF^–)/2; V_IN= IN⁺– IN^–,

V_INCM= (IN⁺+ IN^–)/2, IN⁺and IN^–are defined as the selected positive

and negative input respectively.

Note 10: The external oscillator is connected to the F_Opin. The external

oscillator frequency, f_EOSC, is expressed in kHz.

Note 4: F_Opin tied to GND or to V_CCor to external conversion clock

source with f_EOSC= 153600Hz unless otherwise specified.

Note 11: The converter uses the internal oscillator.

F_O= 0V or F_O= V_CC

.

Note 5: Guaranteed by design, not subject to test.

Note 12: 1µV RMS noise is independent of V_REF. Since the noise

performance is limited by the quantization, lowering V_REFimproves the

effective resolution.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a precise analog input voltage. Maximum specifications are limited by

the LSB step size (V_REF/2¹⁶) and the single shot measurement. Typical

specifications are measured from the center of the quantization band.

Note 13: Guaranteed by design and test correlation.

Note 7: F_O= GND (internal oscillator) or f_EOSC= 139800Hz ±2%

Note 14: The low sleep mode current is valid only when CS is high.

(external oscillator).

Note 15: These parameters are guaranteed by design over the full

supply and temperature range. Automated testing proceedures are

limited by the LSB Step Size (V_REF/2¹⁶).

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LTC2439-1

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PI FU CTIO S

CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog

Inputs. May be programmed for single-ended or differen-

tial mode.

is in a high impedance state. During the Conversion and

Sleep periods, this pin is used as the conversion status

output. The conversion status can be observed by pulling

CS LOW.

V_CC(Pin 9): Positive Supply Voltage. Bypass to GND

(Pin 15) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as the digital

outputfortheinternalserialinterfaceclockduringtheData

Output period. In External Serial Clock Operation mode,

SCK is used as the digital input for the external serial

interface clock during the Data Output period. A weak

internal pull-up is automatically activated in Internal Serial

ClockOperationmode.TheSerialClockOperationmodeis

determined by the logic level applied to the SCK pin at

power up or during the most recent falling edge of CS.

COM (Pin 10): The common negative input (IN^–) for all

single-ended multiplexer configurations. The voltage on

Channel 0 to 15 and COM input pins can have any value

between GND – 0.3V and V_CC+ 0.3V. Within these limits,

the two selected inputs (IN⁺and IN^–) provide a bipolar

inputrange(V_IN=IN⁺–IN^–)from–0.5•V_REFto0.5•V_REF

.

Outside this input range, the converter produces unique

overrange and underrange output codes.

F_O(Pin 19): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to GND (F_O= 0V), the

converter uses its internal oscillator and rejects 50Hz and

60Hz simultaneously. When F_Ois driven by an external

clocksignalwithafrequencyf_EOSC,theconverterusesthis

signal as its system clock and the digital filter has 87dB

minimum rejection in the range f_EOSC/2560 ±14% and

110dB minimum rejection at f_EOSC/2560 ±4%.

REF⁺(Pin 11), REF^–(Pin 12): Differential Reference

Input. The voltage on these pins can have any value

between GND and V_CCas long as the positive reference

input, REF⁺, is maintained more positive than the negative

reference input, REF ^–, by at least 0.1V.

GND (Pin 15): Ground. Connect this pin to a ground plane

through a low impedance connection.

CS (Pin 16): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

SDI (Pin 20): Serial Digital Data Input. During the Data

Output period, this pin is used to shift in the multiplexer

address started from the first rising SCK edge. During the

Conversion and Sleep periods, this pin is in the DON’T

CAREstate. However, aHIGHorLOWlogiclevelshouldbe

maintained on SDI in the DON’T CARE mode to avoid an

excessive current in the SDI input buffers.

SDO (Pin 17): Three-State Digital Output. During the Data

Output period, this pin is used as the serial data output.

When the chip select CS is HIGH (CS = V_CC), the SDO pin

NC (Pins 13, 14): Not Internally Connected. Do not con-

nect or connect to ground.

24391f

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LTC2439-1

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FU CTIO AL BLOCK DIAGRA

V

CC

F

AUTOCALIBRATION

AND CONTROL

O

+

–

REF

(INT/EXT)

INTERNAL

OSCILLATOR

GND

CH0

CH1

+

–

+

–

IN

DIFFERENTIAL

3RD ORDER

∆Σ MODULATOR

SDI

SCK

SDO

CS

•

MUX

SERIAL

INTERFACE

CH15

COM

DECIMATING FIR

ADDRESS

24391 F01

Figure 1

TEST CIRCUITS

V

CC

1.69k

SDO

1.69k

C

= 20pF

LOAD

C

= 20pF

LOAD

241418 TC01

241418 TA03

Hi-Z TO V

OH

V

OL

V

OH

TO V

Hi-Z TO V

OL

TO Hi-Z

V

TO V

OH

OL

TO Hi-Z

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

POWER UP

+

–

IN = CH0, IN = CH1

Converter Operation Cycle

The LTC2439-1 is a multichannel, low power, delta-sigma

analog-to-digital converter with an easy-to-use 4-wire se-

rialinterface(seeFigure1).Itsoperationismadeupofthree

states. The converter operating cycle begins with the con-

version,followedbythelowpowersleepstateandendswith

the data input/output (see Figure 2). The 4-wire interface

consistsofserialdatainput(SDI), serialdataoutput(SDO),

serial clock (SCK) and chip select (CS).

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

TRUE

Initially, the LTC2439-1 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

The part remains in the sleep state as long as CS is HIGH.

While in the sleep state, power consumption is reduced by

nearly two orders of magnitude. The conversion result is

heldindefinitelyinastaticshiftregisterwhiletheconverter

is in the sleep state.

DATA OUTPUT

ADDRESS INPUT

24391 F02

Figure 2. LTC2439-1 State Transition Diagram

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LTC2439-1

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APPLICATIO S I FOR ATIO

Once CS is pulled LOW, the device exits the low power

modeandentersthedataoutputstate. IfCSispulledHIGH

beforethefirstrisingedgeofSCK,thedevicereturnstothe

low power sleep mode and the conversion result is still

held in the internal static shift register. If CS remains LOW

after the first rising edge of SCK, the device begins

outputting the conversion result and inputting channel

selection bits. Taking CS high at this point will terminate

the data output state and start a new conversion. The

channel selection control bits are shifted in through SDI

from the first rising edge of SCK and depending on the

control bits, the converter updates its channel selection

immediately and is valid for the next conversion. The

details of channel selection control bits are described in

theInputDataModesection. Theoutputdataisshiftedout

theSDOpinunderthecontroloftheserialclock(SCK).The

output data is updated on the falling edge of SCK allowing

theusertoreliablylatchdataontherisingedgeofSCK(see

Figure 3). The data output state is concluded once 19 bits

are read out of the ADC or when CS is brought HIGH. The

device automatically initiates a new conversion and the

cycle repeats. In order to maintain compatibility with

24-/32-bit data transfers, it is possible to clock the

LTC2439-1withadditionalserialclockpulses.Thisresults

in additional data bits which are always logic HIGH.

Through timing control of the CS and SCK pins, the

LTC2439-1 offers several flexible modes of operation

(internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turbthecyclicoperationdescribedabove. Thesemodesof

operation are described in detail in the Serial Interface

Timing Modes section.

CS

BIT18

EOC

BIT17

(0)

BIT16

SIG

BIT15 BIT14 BIT13 BIT12

MSB B22

BIT11

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

LSB

SDO

SCK

SDI

Hi-Z

CONVERSON RESULT

ODD/

SIGN

(1)

(0)

EN

SGL

A2

A1

A0

DON’T CARE

SLEEP

DATA INPUT/OUTPUT

CONVERSION

24391 F03a

Figure 3a. Input/Output Data Timing

CONVERSION RESULT

N – 1

CONVERSION RESULT

N

CONVERSION RESULT

N + 1

SDO

Hi-Z

SCK

SDI

DON’T CARE

ADDRESS

N

ADDRESS

N + 1

ADDRESS

N + 2

OUTPUT

N

OUTPUT

N – 1

OUTPUT

N + 1

OPERATION

CONVERSION N

CONVERSION N + 1

24391 F03b

Figure 3b. Typical Operation Sequence

24391f

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U

Conversion Clock

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz and

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2439-1 incorporates a highly accu-

rate on-chip oscillator. This eliminates the need for exter-

nal frequency setting components such as crystals or

oscillators. Clocked by the on-chip oscillator, the

LTC2436-1 achieves a minimum of 87dB rejection over

the range 49Hz to 61.2Hz.

Reference Voltage Range

The LTC2439-1 accepts a truly differential external refer-

ence voltage. The absolute/common mode voltage speci-

ficationfortheREF⁺andREF^–pinscoverstheentirerange

from GND to V_CC. For correct converter operation, the

REF⁺pin must always be more positive than the REF^–pin.

The LTC2439-1 can accept a differential reference voltage

from 0.1V to V_CC. The converter output noise is deter-

mined by the thermal noise of the front-end circuits, and

as such, its value in microvolts is nearly constant with

reference voltage. A decrease in reference voltage will

significantly improve the converter’s effective resolution,

since the thermal noise (1µV) is well below the quantiza-

tion level of the device (75.6µV for a 5V reference). At the

minimum reference (100mV) the thermal noise

remains constant at 1µV RMS (or 6µV_P-P), while the

quantization is reduced to 1.5µV per LSB. As a result,

lowering the reference improves the effective resolution

for low level input voltages.

Ease of Use

The LTC2439-1 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle.Thereisaone-to-onecorrespondencebetweenthe

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

TheLTC2439-1performsoffsetandfull-scalecalibrations

ineveryconversioncycle.Thiscalibrationistransparentto

theuserandhasnoeffectonthecyclicoperationdescribed

above. Theadvantageofcontinuouscalibrationisextreme

stabilityofoffsetandfull-scalereadingswithrespecttotime,

supply voltage change and temperature drift.

Input Voltage Range

ThetwoselectedpinsarelabeledIN⁺andIN^–(seeTable1).

Onceselected(eitherdifferentialorsingle-endedmultiplex-

ing mode), the analog input is differential with a common

mode range for the IN⁺and IN^–input pins extending from

GND – 0.3V to V_CC+ 0.3V. Outside these limits, the ESD

protection devices begin to turn on and the errors due to

input leakage current increase rapidly. Within these limits,

the LTC2439-1 converts the bipolar differential input sig-

nal, V_IN= IN⁺– IN^–, from –FS = –0.5 • V_REFto +FS = 0.5

• V_REFwhere V_REF= REF⁺– REF^–. Outside this range the

converter indicates the overrange or the underrange con-

dition using distinct output codes.

Input signals applied to IN⁺and IN^–pins may extend

300mV below ground or above V_CC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN⁺or IN^–pins without affecting the performance

of the device. In the physical layout, it is important to

Power-Up Sequence

TheLTC2439-1automaticallyentersaninternalresetstate

when the power supply voltage V_CCdrops below approxi-

mately 2V. This feature guarantees the integrity of the

conversion result and of the serial interface mode selec-

tion. (See the 3-wire I/O sections in the Serial Interface

Timing Modes section.)

When the V_CCvoltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a typical duration of 1ms. The POR signal

clears all internal registers. Following the POR signal,

the LTC2439-1 starts a normal conversion cycle and

followsthesuccessionofstatesdescribedabove. Thefirst

conversion result following POR is accurate within the

24391f

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APPLICATIO S I FOR ATIO

maintain the parasitic capacitance of the connection be-

tween these series resistors and the corresponding pins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. In addition, series

resistors will introduce a temperature dependent offset

error due to the input leakage current. A 10nA input

leakage current will develop a 1LBS offset error on an 8k

resistor if V_REF= 5V. This error has a very strong tempera-

ture dependency.

Table 1. Channel Selection

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL SIGN

A2 A1 A0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 COM

+

–

+

–

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

IN

+

IN

+

IN

+

IN

+

IN

–

+

IN

–

+

IN

–

+

IN

–

IN

–

IN

–

IN

–

IN

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

*Default at power up

24391f

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U

Input Data Format

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

When the LTC2439-1 is powered up, the default selection

used for the first conversion is IN⁺= CH0 and IN^–= CH1

(Address = 00000). In the data input/output mode follow-

ing the first conversion, a channel selection can be up-

datedusingan8-bitword.TheLTC2439-1serialinputdata

is clocked into the SDI pin on the rising edge of SCK (see

Figure3a).Theinputiscomposedofan8-bitwordwiththe

first 3 bits acting as control bits and the remaining 5 bits

as the channel address bits.

Bit 17 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 16 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bit is LOW.

Bit 15 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 16 also

provides the underrange or overrange indication. If both

Bit 16 and Bit 15 are HIGH, the differential input voltage is

above +FS. If both Bit 16 and Bit 15 are LOW, the

differential input voltage is below –FS.

The first 2 bits are always 10 for proper updating opera-

tion. The third bit is EN. For EN = 1, the following 5 bits are

used to update the input channel selection. For EN = 0,

previous channel selection is kept and the following bits

are ignored. Therefore, the address is updated when the 3

control bits are 101 and kept for 100. Alternatively, the 3

control bits can be all zero to keep the previous address.

This alternation is intended to simplify the SDI interface

allowing the user to simply connect SDI to ground if no

update is needed. Combinations other than 101, 100 and

000 of the 3 control bits should be avoided.

The function of these bits is summarized in Table 2.

Table 2. LTC2439-1 Status Bits

Bit 18 Bit 17 Bit 16 Bit 15

Input Range

EOC

DMY

SIG

MSB

V

≥ 0.5 • V

0

1

0

1

0

IN

REF

0V ≤ V < 0.5 • V

0

1

IN

REF

When update operation is set (101), the following 5 bits

are the channel address. The first bit, SGL, decides if the

differential selection mode (SGL = 0) or the single-ended

selection mode is used (SGL = 1). For SGL = 0, two

adjacent channels can be selected to form a differential

input; for SGL = 1, one of the 16 channels (CH0-CH15) is

selected as the positive input and the COM pin is used as

the negative input. For a given channel selection, the

converter will measure the voltage between the two chan-

nelsindicatedbyIN⁺andIN^–intheselectedrowofTable 1.

–0.5 • V ≤ V < 0V

0

REF

IN

V

< –0.5 • V

0

IN

REF

Bits 15-0 are the 16-Bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 3a. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

register.

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 18 (EOC) can be captured on the first rising

edge of SCK. Bit 17 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 18th SCK and may be latched on

the rising edge of the 19th SCK pulse. On the falling edge

of the 19th SCK pulse, SDO goes HIGH indicating the

Output Data Format

The LTC2439-1 serial output data stream is 19 bits long.

The first 3 bits represent status information indicating the

conversionstate andsign. Thenext16bitsaretheconver-

sion result, MSB first. The third and fourth bit together are

alsousedtoindicateanunderrangecondition(bothbitslow

means the differential input voltage is below –FS) or an

overrange condition (both bits high means the differential

input voltage is above +FS).

Bit 18 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

initiation of a new conversion cycle. This bit serves as EOC

24391f

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(Bit 18) for the next conversion cycle. Table 3 summarizes

canoperatewithanexternalconversionclock.Theconveter

automatically detects the presence of an external clock

signal at the F_Opin and turns off the internal oscillator. The

frequency f_EOSCof the external signal must be at least

2560Hztobedetected.Theexternalclocksignaldutycycle

is not significant as long as the minimum and maximum

the output data format.

In order to remain compatible with some SPI

microcontrollers, more than 19 SCK clock pulses may be

applied. As long as these clock pulses are complete before

the conversion ends, they will not effect the serial data.

However, switching SCK during a conversion may gener-

ate ground currents in the device leading to extra offset

and noise error sources.

specifications for the high and low periods, t_HEOand t_LEO

are observed.

,

While operating with an external conversion clock of a

frequencyf_EOSC,theLTC2439-1providesbetterthan110dB

normal mode rejection in a frequency range f_EOSC/2560

±4%. The normal mode rejection as a function of the input

frequency deviation from f_EOSC/2560 is shown in Figure 5.

Whenever an external clock is not present at the F_Opin the

converterautomaticallyactivatesitsinternaloscillatorand

enterstheInternalConversionClockmode.TheLTC2439-1

operation will not be disturbed if the change of conversion

clocksourceoccursduringthesleepstateorduringthedata

outputstatewhiletheconverterusesanexternalserialclock.

Ifthechangeoccursduringtheconversionstate,theresult

oftheconversioninprogressmaybeoutsidespecifications

but the following conversions will not be affected. If the

change occurs during the data output state and the con-

verterisintheInternalSCKmode,theserialclockdutycycle

maybeaffectedbuttheserialdatastreamwillremainvalid.

As long as the voltage applied to any channel (CH0-CH15,

COM) is maintained within the –0.3V to (V_CC+ 0.3V)

absolutemaximumoperatingrange, aconversionresultis

generated for any differential input voltage V_INfrom

–FS = –0.5 • V_REFto+FS = 0.5 • V_REF. For differential input

voltagesgreaterthan+FS,theconversionresultisclamped

to the value corresponding to the +FS + 1LSB. For differ-

ential input voltages below –FS, the conversion result is

clamped to the value corresponding to –FS – 1LSB.

Simultaneous Frequency Rejection

The LTC2439-1 internal oscillator provides better than

87dB normal mode rejection over the range of 49Hz to

61.2HzasshowninFigure4. Forsimultaneous50Hz/60Hz

rejection using the internal oscillator, F_Oshould be con-

nected to GND.

Table 4 summarizes the duration of each state and the

achievable output data rate as a function of F_O.

When a fundamental rejection frequency different from

therange49Hzto61.2Hzisrequiredorwhentheconverter

mustbesychronizedwithanoutsidesource,theLTC2439-1

–80

–85

–80

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–100

–120

–130

–140

–12

–8

–4

0

4

8

12

48

50

52

54

56

58

60

62

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

DEVIATION FROM NOTCH FREQUENCY f

/2560(%)

EOSC

24391 F04a

24361 F04b

Figure 5. LTC2439-1 Normal Mode Rejection When

Using an External Oscillator of Frequency f_EOSC

Figure 4. LTC2439-1 Normal Mode Rejection

When Using an Internal Oscillator

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Table 3. LTC2439-1 Output Data Format

Differential Input Voltage

Bit 18

EOC

Bit 17

DMY

Bit 16

SIG

Bit 15

MSB

Bit 14

Bit 13

Bit 12

…

Bit 0

V

IN

*

V * ≥ 0.5 • V **

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

…

0

1

0

1

0

1

0

1

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

REF

0.25 • V ** – 1LSB

REF

0

–1LSB

–0.25 • V **

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

REF

V * < –0.5 • V **

0

IN

REF

+

–

+

–

*The differential input voltage V = IN – IN .

**The differential reference voltage V = REF – REF .

IN

REF

Table 4. LTC2439-1 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

Simultaneous 50Hz/60Hz Rejection

147ms, Output Data Rate ≤ 6.8 Readings/s

O

External Oscillator

F = External Oscillator

O

20510/f s, Output Data Rate ≤ f /20510 Readings/s

EOSC

with Frequency f

kHz

EOSC

(f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock

External Serial Clock with

F = LOW

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.09ms

(19 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 152/f

ms

EOSC

O

Frequency f

kHz

(19 SCK cycles)

EOSC

As Long As CS = LOW But Not Longer Than 19/f ms

SCK

Frequency f

kHz

(19 SCK cycles)

SCK

SERIAL INTERFACE PINS

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2439-1 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

InternalorExternalSCKmodeisselectedonpower-upand

thenreselectedeverytimeaHIGH-to-LOWtransitionisde-

tected at the CS pin. If SCK is HIGH or floating at power-

uporduringthistransition,theconverterenterstheinternal

SCK mode. If SCK is LOW at power-up or during this tran-

sition, the converter enters the external SCK mode.

The LTC2439-1 transmits the conversion results and re-

ceives the start of conversion command through a syn-

chronous4-wireinterface.Duringtheconversionandsleep

states, this interface can be used to assess the converter

status and during the data I/O state it is used to read the

conversion result and write in channel selection bits.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 18) is used to

synchronizethedatatransfer.Eachbitofdataisshiftedout

the SDO pin on the falling edge of the serial clock and each

input bit is shifted in the SDI pin on the rising edge of the

serial clock.

Serial Data Input (SDI)

Theserialdatainputpin,SDI(Pin20),isusedtoshiftinthe

channelcontrolbitsduringthedataoutputstatetoprepare

the channel selection for the following conversion.

24391f

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When CS (Pin 16) is HIGH or the converter is in the con-

version state, the SDI input is ignored and may be driven

HIGH or LOW. When CS goes LOW and the conversion is

complete, SDO goes low and then SDI starts to shift in bits

on the rising edge of SCK.

Finally, CS can be used to control the free-running mode

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by F_O.

SERIAL INTERFACE TIMING MODES

Serial Data Output (SDO)

The LTC2439-1’s 4-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

3- or 4-wire I/O, single cycle conversion. The following

sections describe each of these serial interface timing

modes in detail. In all these cases, the converter can use

the internal oscillator (F_O= LOW) or an external oscillator

connected to the F_Opin. Refer to Table 6 for a summary.

The serial data output pin, SDO (Pin 17), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 16) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase, theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 6.

Chip Select Input (CS)

The serial clock mode is selected on the falling edge of CS.

Toselecttheexternalserialclockmode,theserialclockpin

(SCK) must be LOW during each CS falling edge.

The active LOW chip select, CS (Pin 16), is used to test the

conversion status and to enable the data input/output

transfer as described in the previous sections.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the conversion is complete. If CS is HIGH, the device

automatically enters the low power sleep state once the

conversion is complete.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2439-1 will abort any serial data

transfer in progress and start a new conversion cycle

anytime a LOW-to-HIGH transition is detected at the CS

pin after the converter has entered the data input/output

state (i.e., after the first rising edge of SCK occurs with

CS = LOW). If the device has not finished loading the last

input bit (A0 of SDI) by the time CS pulled HIGH, the

address information is discarded and the previous ad-

dress is kept.

Whenthedeviceisinthesleepstate,itsconversionresult

is held in an internal static shift register. The device

remainsinthesleepstateuntilthefirstrisingedgeofSCK

Table 6. LTC2439-1 Interface Timing Modes

Conversion

Cycle

Data

Output

Control

Connection

and

SCK

Configuration

Source

External

Internal

Control

Waveforms

External SCK, Single Cycle Conversion

External SCK, 3-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 6, 7

Figure 8

Internal SCK, Single Cycle Conversion

Internal SCK, 3-Wire I/O, Continuous Conversion

CS ↓

Figures 9, 10

Figure 11

Continuous

Internal

24391f

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2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

9

20

V

CC

F

O

LTC2439-1

+

11

19

18

REFERENCE

VOLTAGE

0.1V TO V

REF

SDI

12

21

28

1

–

SCK

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

SDO

CS

16

ANALOG

INPUTS

CH8

•

8

TEST EOC

CH15

(OPTIONAL)

15

10

COM

GND

CS

TEST EOC

BIT 0

BIT 18

EOC

BIT 17

(0)

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 6

SDO

LBS

Hi-Z

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

DATA OUTPUT

A0

CONVERSION

24391 F05

SLEEP

Figure 6. External Serial Clock, Single Cycle Operation

is seen while CS is LOW. The input data is then shifted in

via the SDI pin on the rising edge of SCK (including the

first rising edge) and the output data is shifted out of the

SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 19th rising edge of SCK. On the 19th falling edge of

SCK, thedevicebeginsanewconversion. SDOgoesHIGH

(EOC = 1) indicating a conversion is in progress.

ous address is kept. This is useful for aborting an invalid

conversioncycleorsynchronizingthestartofaconversion.

External Serial Clock, 3-Wire I/O

This timing mode utilizes a 3-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 8. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

typically 1ms after V_CCexceeds approximately 2V. The

level applied to SCK at this time determines if SCK is

internal or external. SCK must be driven LOW prior to the

endofPORinordertoentertheexternalserialclocktiming

mode.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CSHIGHanytimebetweenthefirstrisingedgeandthe19th

falling edge of SCK, see Figure 7. On the rising edge of CS,

the device aborts the data output state and immediately

initiates a new conversion. If the device has not finished

loading the last input bit A0 of SDI by the time CS is pulled

HIGH, the address information is discarded and the previ-

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion ends. On the falling edge of

EOC, the conversion result is loaded into an internal static

24391f

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shift register. The input data is then shifted in via the SDI

pin on the rising edge of SCK (including the first rising

edge) and the output data is shifted out of the SDO pin on

each falling edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 19th falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun.

2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

20

9

V

CC

F

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

O

LTC2439-1

+

11

12

21

28

1

19

18

REFERENCE

VOLTAGE

REF

SDI

–

SCK

0.1V TO V

CC

4-WIRE

SPI INTERFACE

CH0

•

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

TEST EOC

CH15

(OPTIONAL)

15

10

COM

GND

CS

TEST EOC

BIT 0

EOC

BIT 18

EOC

BIT 17

“O”

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 5

BIT 4

SDO

Hi-Z

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

SLEEP

DATA OUTPUT

CONVERSION

24391 F06

DATA

OUTPUT

SLEEP

Figure 7. External Serial Clock, Reduced Data Output Length

2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

9

20

V

F

CC

O

LTC2439-1

+

11

12

21

28

1

19

18

REFERENCE

VOLTAGE

REF

SDI

–

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

CH0

•

17

CH7

SDO

CS

16

ANALOG

INPUTS

CH8

•

8

CH15

15

10

COM

GND

CS

BIT 18

EOC

BIT 17

“O”

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 6

BIT 0

LSB

SDO

SCK

(EXTERNAL)

ODD/

SIGN

SDI

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

DATA OUTPUT

A0

CONVERSION

24391 F07

Figure 8. External Serial Clock, CS = 0 Operation

24391f

16

LTC2439-1

W U U

APPLICATIO S I FOR ATIO

U

Internal Serial Clock, Single Cycle Operation

edge of SCK. In the internal SCK timing mode, SCK goes

HIGHandthedevicebeginsoutputtingdataattimet_EOCtest

after the falling edge of CS (if EOC = 0) or t_EOCtestafter EOC

goes LOW (if CS is LOW during the falling edge of EOC).

Thevalueoft_EOCtestis23µsifthedeviceisusingitsinternal

oscillator (F_O= logic LOW or HIGH). If F_Ois driven by an

external oscillator of frequency f_EOSC, then t_EOCtestis

3.6/f_EOSC. If CS is pulled HIGH before time t_EOCtest, the

device returns to the sleep state and the conversion result

is held in the internal static shift register.

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 9.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

If CS remains LOW longer than t_EOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data I/O cycle concludes

after the 19th rising edge. The input data is then shifted in

viatheSDIpinontherisingedgeofSCK(includingthefirst

rising edge) and the output data is shifted out of the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

EOC can be latched on the first rising edge of SCK and the

last bit of the conversion result on the 19th rising edge of

SCK. Afterthe19thrisingedge, SDOgoesHIGH(EOC=1),

SCK stays HIGH and a new conversion starts.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the conversion is complete.

WhentestingEOC,iftheconversioniscomplete(EOC= 0),

the device will exit the low power mode during the EOC

test. In order to allow the device to return to the low power

sleep state, CS must be pulled HIGH before the first rising

2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

20

9

V

F

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

CC

O

V

CC

LTC2439-1

+

11

12

21

28

1

19

18

REFERENCE

VOLTAGE

10k

REF

SDI

–

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

17

CH7

SDO

CS

16

ANALOG

INPUTS

CH8

•

8

CH15

15

10

COM

GND

TEST EOC

<t

EOCtest

CS

TEST EOC

BIT 18

EOC

BIT 17

“O”

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 6

BIT 0

LSB

SDO

Hi-Z

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

DATA OUTPUT

CONVERSION

24391 F08

SLEEP

Figure 9. Internal Serial Clock, Single Cycle Operation

24391f

17

LTC2439-1

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U

APPLICATIO S I FOR ATIO

However, certain applications may require an external

driveronSCK.IfthisdrivergoesHi-ZafteroutputtingaLOW

signal,theLTC2439-1’sinternalpull-upremainsdisabled.

Hence, SCK remains LOW. On the next falling edge of CS,

the device is switched to the external SCK timing mode.

By adding an external 10k pull-up resistor to SCK, this pin

goes HIGH once the external driver goes Hi-Z. On the next

CS falling edge, the device will remain in the internal SCK

timing mode.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 19th rising edge of

SCK, see Figure 10. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. If the device has not finished loading the

last input bit (A0 of SDI) by the time CS is pulled HIGH, the

address information is discarded and the previous ad-

dress is still kept. This is useful for aborting an invalid

conversion cycle, or synchronizing the start of a conver-

sion. If CS is pulled HIGH while the converter is driving

SCK LOW, the internal pull-up is not available to restore

SCK to a logic HIGH state. This will cause the device to exit

the internal serial clock mode on the next falling edge of

CS. This can be avoided by adding an external 10k pull-up

resistor to the SCK pin or by never pulling CS HIGH when

SCK is LOW.

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

period defined above as t_EOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

internal pull-up may not be adequate to return SCK to a

HIGHlevelbeforeCSgoeslowagain. Thisisnotaconcern

under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

Whenever SCK is LOW, the LTC2439-1’s internal pull-up

at pin SCK is disabled. Normally, SCK is not externally

driven if the device is in the internal SCK timing mode.

2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

20

9

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

V

F

CC

O

V

CC

LTC2439-1

+

11

12

21

28

1

19

18

REFERENCE

VOLTAGE

10k

REF

SDI

–

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

17

CH7

CH8

SDO

CS

16

ANALOG

INPUTS

•

8

CH15

COM

TEST EOC

(OPTIONAL)

15

10

GND

>t

<t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 18

EOC

BIT 17

“O”

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 4

SDO

Hi-Z

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

CONVERSION

(1)

(0)

EN

SGL

A2

A1

A0

SLEEP

DATA OUTPUT

DATA

OUTPUT

24391 F09

SLEEP

Figure 10. Internal Serial Clock, Reduced Data Output Length

24391f

18

LTC2439-1

W U U

APPLICATIO S I FOR ATIO

U

Internal Serial Clock, 3-Wire I/O,

Continuous Conversion

then immediately begins outputting data. The data input/

output cycle begins on the first rising edge of SCK and

ends after the 19th rising edge. The input data is then

shifted in via the SDI pin on the rising edge of SCK

(including the first rising edge) and the output data is

shifted out of the SDO pin on each falling edge of SCK.

The internally generated serial clock is output to the SCK

pin. Thissignalmaybeusedtoshifttheconversionresult

into external circuitry. EOC can be latched on the first

risingedgeofSCKandthelastbitoftheconversionresult

can be latched on the 19th rising edge of SCK. After the

19th rising edge, SDO goes HIGH (EOC = 1) indicating a

newconversionisinprogress.SCKremainsHIGHduring

the conversion.

This timing mode uses a 3-wire interface. The conversion

resultisshiftedoutofthedevicebyaninternallygenerated

serialclock(SCK)signal, seeFigure11. CSmaybeperma-

nently tied to ground, simplifying the user interface or

isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately1msafterV_CCexceeds2V. Aninternalweak

pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

PRESERVING THE CONVERTER ACCURACY

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

The LTC2439-1 is designed to reduce as much as

possible the conversion result sensitivity to device

decoupling, PCB layout, antialiasing circuits, line fre-

quency perturbations and so on. Nevertheless, in order to

preserve the accuracy capability of this part, some simple

precautions are desirable.

2.7V TO 5.5V

1µF

= EXTERNAL CLOCK SOURCE

20

9

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

V

F

CC

O

LTC2439-1

11

19

18

+

–

REFERENCE

REF

SDI

VOLTAGE

12

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

21

28

1

CH0

•

17

CH7

SDO

CS

16

ANALOG

INPUTS

CH8

•

8

CH15

15

10

COM

GND

CS

BIT 18

EOC

BIT 17

“O”

BIT 16

SIG

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 6

BIT 0

LSB

SDO

SCK

(INTERNAL)

ODD/

SIGN

SDI

DON’T CARE

CONVERSION

DON’T CARE

(1)

(0)

EN

SGL

A2

A1

A0

DATA OUTPUT

CONVERSION

24391 F10

Figure 11. Internal Serial Clock, CS = 0 Continuous Operation

24391f

19

LTC2439-1

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U

APPLICATIO S I FOR ATIO

Digital Signal Levels

problem without additional power dissipation. The actual

resistor value depends upon the trace impedance and

connection topology.

The LTC2439-1’s digital interface is easy to use. Its digital

inputs (SDI, F_O, CS and SCK in External SCK mode of

operation)acceptstandardTTL/CMOSlogiclevelsandthe

internalhysteresisreceiverscantolerateedgeratesasslow

as 100µs. However, some considerations are required to

take advantage of the accuracy and low supply current of

this converter.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The differential input and refer-

ence architecture reduce substantially the converter’s

sensitivity to ground currents.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

Particular attention must be given to the connection of the

F_Osignal when the LTC2439-1 is used with an external

conversion clock. This clock is active during the conver-

sion time and the normal mode rejection provided by the

internal digital filter is not very high at this frequency. A

normal mode signal of this frequency at the converter

reference terminals may result into DC gain and INL

errors. A normal mode signal of this frequency at the

converterinputterminalsmayresultintoaDCoffseterror.

Such perturbations may occur due to asymmetric capaci-

tivecouplingbetweentheF_Osignaltraceandtheconverter

input and/or reference connection traces. An immediate

solution is to maintain maximum possible separation

between the F_Osignal trace and the input/reference sig-

nals. When the F_Osignal is parallel terminated near the

converter, substantial AC current is flowing in the loop

formedbytheF_Oconnectiontrace, theterminationandthe

ground return path. Thus, perturbation signals may be

inductively coupled into the converter input and/or refer-

ence. In this situation, the user must reduce to a minimum

the loop area for the F_Osignal as well as the loop area for

the differential input and reference connections.

While a digital input signal is in the range 0.5V to

(V_CC– 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (SDI, F_O, CS and

SCK in External SCK mode of operation) is within this

range, the power supply current may increase even if the

signal in question is at a valid logic level. For micropower

operation, it is recommended to drive all digital input

signals to full CMOS levels [V_IL< 0.4V and

V_OH> (V_CC– 0.4V)].

During the conversion period, the undershoot and/or

overshoot of a fast digital signal connected to the pins

may severely disturb the analog to digital conversion

process.Undershootandovershootcanoccurbecauseof

the impedance mismatch at the converter pin when the

transition time of an external control signal is less than

twice the propagation delay from the driver to LTC2439-

1. For reference, on a regular FR-4 board, signal propaga-

tion velocity is approximately 183ps/inch for internal

traces and 170ps/inch for surface traces. Thus, a driver

generating a control signal with a minimum transition

time of 1ns must be connected to the converter pin

through a trace shorter than 2.5 inches. This problem

becomes particularly difficult when shared control lines

are used and multiple reflections may occur. The solution

is to carefully terminate all transmission lines close to

their characteristic impedance.

Driving the Input and Reference

The input and reference pins of the LTC2439-1 converter

are directly connected to a network of sampling capaci-

tors. Depending upon the relation between the differential

input voltage and the differential reference voltage, these

capacitorsareswitchingbetweenthesefourpinstransfer-

ring small amounts of charge in the process. A simplified

equivalent circuit is shown in Figure 12.

Parallel termination near the LTC2439-1 pin will eliminate

thisproblembutwillincreasethedriverpowerdissipation.

A series resistor between 27Ω and 56Ω placed near the

driver or near the LTC2439-1 pin will also eliminate this

For a simple approximation, the source impedance R_S

driving an analog input pin (IN⁺, IN^–, REF⁺or REF^–) can be

considered to form, together with R_SWand C_EQ(see

24391f

20

LTC2439-1

W U U

APPLICATIO S I FOR ATIO

U

Figure 12), a first order passive network with a time

constant τ = (R_S+ R_SW) • C_EQ. The converter is able to

sample the input signal with better than 1LSB accuracy if

the sampling period is at least 11 times greater than the

input circuit time constant τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

frequency f_EOSCis used, the sampling period is 2/f_EOSC

and, for a settling error of less than 1LSB, τ ≤ 0.18/f_EOSC

.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

theINLperformanceoftheconverter. Figure12showsthe

mathematical expressions for the average bias currents

flowing through the IN⁺and IN^–pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

When using the internal oscillator (F_O= LOW), the

LTC2439-1’s front-end switched-capacitor network is

clocked at 69900Hz corresponding to a 14.3µs sampling

period. Thus, for settling errors of less than 1LSB, the

driving source impedance should be chosen such that

τ ≤ 14.3µs/11 = 1.3µs. When an external oscillator of

V + V_INCM− V_REFCM

IN

I IN⁺

=

V

(

)

CC

AVG

0.5• R_EQ

I

+

REF

R

(TYP)

SW

I

LEAK

−V + V_INCM− V_REFCM

IN

I IN⁻

20k

(

V

REF

0.5• R_EQ

V²

1.5• V_REF− V_INCM+ V_REFCM

IN

I REF⁺

=

−

V

CC

(

)

I

IN

+

AVG

0.5• R_EQ

V_REF• R_EQ

(TYP)

20k

SW

I

LEAK

V²

−1.5• V_REF− V_INCM+ V_REFCM

0.5• R_EQ

IN

I REF⁻

=

V

+

IN

(

)

C

EQ

AVG

V

_REF• R_EQ

18pF

where:

(TYP)

V

CC

I

–

V_REF= REF⁺−REF⁻

IN

R

(TYP)

20k

SW

I

LEAK

REF⁺+ REF⁻

V

IN

V_REFCM

=

2

V

_IN= IN⁺−IN⁻

CC

V

I

–

REF

(TYP)

20k

SW

IN⁺− IN⁻

I

LEAK

V

INCM

=

24391 F11

V

REF

2

R_EQ= 3.97MΩ INTERNAL OSCILLATOR 50Hz/60Hz Notch F_O= LOW

(

)

R_EQ= 0.555• 10¹²/f_EOSCEXTERNAL OSCILLATOR

SWITCHING FREQUENCY

(

)

f

= 69900Hz INTERNAL OSCILLATOR (F = LOW)

SW

O

= 0.5 • f

EXTERNAL OSCILLATOR

EOSC

Figure 12. LTC2439-1 Equivalent Analog Input Circuit

24391f

21

LTC2439-1

W U U

U

APPLICATIO S I FOR ATIO

R

SOURCE

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 13. The C_PARcapacitor

includes the LTC2439-1 pin capacitance (5pF typical) plus

thecapacitanceofthetestfixtureusedtoobtaintheresults

shown in Figures 14 and 15. A careful implementation can

bring the total input capacitance (C_IN+ C_PAR) closer to 5pF

thus achieving better performance than the one predicted

by Figures 14 and 15. For simplicity, two distinct situa-

tions can be considered.

+

IN

C

PAR

V

+ 0.5V

C

INCM

IN

20pF

LTC2439-1

SOURCE

–

IN

24361 F13

PAR

20pF

– 0.5V

INCM

IN

Figure 13. An RC Network at IN⁺and IN^–

For relatively small values of input capacitance (C_IN

<

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

for C_INwill deteriorate the converter offset and gain

performancewithoutsignificantbenefitsofsignalfiltering

and the user is advised to avoid them. Nevertheless, when

small values of C_INare unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the

LTC2439-1 can maintain its accuracy while operating with

relative large values of source resistance as shown in

Figures14and15.Thesemeasuredresultsmaybeslightly

different from the first order approximation suggested

earlier because they include the effect of the actual second

order input network together with the nonlinear settling

process of the input amplifiers. For small C_INvalues, the

settling on IN⁺and IN^–occurs almost independently and

there is little benefit in trying to match the source imped-

ance for the two pins.

3

C

= 0.01µF

IN

C

= 0.001µF

IN

C

= 100pF

IN

2

1

C

= 0pF

IN

V

= 5V

REF = 5V

CC

+

–

REF = GND

+

–

IN = 5V

IN = 2.5V

F

= GND

O

A

T

= 25°C

0

1

10

100

1k

(Ω)

10k

100k

R

SOURCE

24361 F14

Figure 14. +FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

0

V

= 5V

CC

+

REF = 5V

Larger values of input capacitors (C_IN> 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

WhenF_O=LOW(internaloscillatorand50Hz/60Hznotch),

the typical differential input resistance is 2MΩ which will

generate a gain error of approximately 1LSB at full scale

for each 60Ω of source resistance driving IN⁺or IN^–.

When F_Ois driven by an external oscillator with a fre-

quency f_EOSC(external conversion clock operation), the

typical differential input resistance is 0.28 • 10¹²/f_EOSCΩ

–

REF = GND

+

–

IN = GND

IN = 2.5V

–1

–2

–3

F

T

= GND

O

= 25°C

A

C

= 0.01µF

IN

C

= 0.001µF

IN

C

IN

= 100pF

C

IN

= 0pF

1

10

100

1k

10k

100k

R

(Ω)

SOURCE

24361 F15

Figure 15. –FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

24391f

22

LTC2439-1

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APPLICATIO S I FOR ATIO

U

20

16

12

8

and each ohm of source resistance driving IN⁺or IN^–will

result in 1.11 • 10^–7• f_EOSCLSB gain error at full scale. The

effect of the source resistance on the two input pins is

additivewithrespecttothisgainerror. Thetypical+FSand

–FS errors as a function of the sum of the source resis-

tanceseenbyIN⁺andIN^–forlargevaluesofC_INareshown

in Figures 16 and 17.

V

= 5V

CC

+

C

= 1µF, 10µF

REF = 5V

IN

–

REF = GND

+

–

IN = 3.75V

IN = 1.25V

F

= GND

= 25°C

O

A

T

C

= 0.1µF

IN

C

IN

= 0.01µF

4

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

IN⁺and IN^–and with the difference between the input and

reference common mode voltages. While the input drive

circuitnonzerosourceimpedancecombinedwiththecon-

verter average input current will not degrade the INL

performance,indirectdistortionmayresultfromthemodu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large C_INcapacitor

values, itisadvisabletocarefullymatchthesourceimped-

ance seen by the IN⁺and IN^–pins. When F_O= LOW

(internaloscillatorand50Hz/60Hznotch), every60Ωmis-

match in source impedance transforms a full-scale com-

mon mode input signal into a differential mode input

signal of 1LSB. When F_Ois driven by an external oscillator

with a frequency f_EOSC, every 1Ω mismatch in source

impedance transforms a full-scale common mode input

signal into a differential mode input signal of 1.11 • 10^–7

• f_EOSCLSB. Figure 18 shows the typical offset error due to

input common mode voltage for various values of source

resistance imbalance between the IN⁺and IN^–pins when

large C_INvalues are used.

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

24361 F16

Figure 16. +FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

0

C

IN

= 0.01µF

–4

–8

C

IN

= 0.1µF

V

= 5V

CC

–12

–16

–20

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

F

T

= GND

= 25°C

C

IN

= 1µF, 10µF

O

A

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

24361 F17

Figure 17. –FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

8

V

= 5V

CC

+

REF = 5V

A

B

–

REF = GND

IN = IN = V

+

–

INCM

4

0

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

C

D

E

F

–4

–8

F

= GND

O

A

G

T

= 25°C

R

C

– = 500Ω

SOURCEIN

= 10µF

IN

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Themagnitudeofthedynamicinputcurrentdependsupon

thesizeoftheverystableinternalsamplingcapacitorsand

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

andpowersupplyrangeistypicallybetterthan0.5%.Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN⁺and

V

INCM

(V)

A: ∆R = +400Ω

E: ∆R = –100Ω

IN

B: ∆R = +200Ω

F: ∆R = –200Ω

IN

C: ∆R = +100Ω

G: ∆R = –400Ω

IN

D: ∆R = 0Ω

24361 F18

Figure 18. Offset Error vs Common Mode Voltage

(V_INCM= IN⁺= IN^–) and Input Source Resistance

Imbalance (∆R_IN= R_SOURCEIN+ – R_SOURCEIN–) for

Large C_INValues (C_IN≥ 1µF)

24391f

23

LTC2439-1

W U U

U

APPLICATIO S I FOR ATIO

IN^–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

and the external source resistance will see a quasi con-

stant reference differential impedance. When F_O= LOW

(internal oscillator and 50Hz/60Hz notch), the typical

differential reference resistance is 1.4MΩ which will gen-

erate a gain error of approximately 1LSB full scale for each

40Ω of source resistance driving REF⁺or REF^–. When F_O

is driven by an external oscillator with a frequency f_EOSC

(externalconversionclockoperation), thetypicaldifferen-

tial reference resistance is 0.20 • 10¹²/f_EOSCΩ and each

ohm of source resistance drving REF⁺or REF^–will result

in 1.54 • 10^–7• f_EOSCLSB gain error at full scale. The effect

of the source resistance on the two reference pins is

additivewithrespecttothisgainerror. Thetypical+FSand

–FS errors for various combinations of source resistance

seen by the REF⁺and REF^–pins and external capacitance

C_REFconnected to these pins are shown in Figures 19, 20,

21 and 22.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

in a small offset shift. A 15k source resistance will create

a 0LSB typical and 1LSB maximum offset voltage.

Reference Current

In a similar fashion, the LTC2439-1 samples the differen-

tialreferencepinsREF⁺andREF^–transferingsmallamount

of charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gainandINLperformance.Theeffectofthiscurrentcanbe

analyzed in the same two distinct situations.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

WhenF_O=LOW(internaloscillatorand50Hz/60Hznotch),

every 1000Ω of source resistance driving REF⁺or REF^–

translates into about 1LSB additional INL error. When F_O

Forrelativelysmallvaluesoftheexternalreferencecapaci-

tors(C_REF<0.01µF),thevoltageonthesamplingcapacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for C_REFwill deteriorate the converter offset and

gainperformancewithoutsignificantbenefitsofreference

filtering and the user is advised to avoid them.

is driven by an external oscillator with a frequency f_EOSC

,

every 100Ω of source resistance driving REF⁺or REF^–

translates into about 5.5 • 10^–7• f_EOSCLSB additional INL

error. Figure 23 shows the typical INL error due to the

source resistance driving the REF⁺or REF^–pins when

large C_REFvalues are used. The effect of the source

resistance on the two reference pins is additive with

respect to this INL error. In general, matching of source

Larger values of reference capacitors (C_REF> 0.01µF) may

be required as reference filters in certain configurations.

Suchcapacitorswillaveragethereferencesamplingcharge

3

0

V

= 5V

C

= 0.01µF

CC

REF

+

REF = 5V

–

C

= 0.001µF

REF

REF = GND

+

–

IN = 5V

C

REF

= 100pF

IN = 2.5V

2

1

0

–1

–2

–3

F

= GND

= 25°C

O

A

C

= 0pF

REF

T

V

= 5V

CC

C

= 0.01µF

REF

+

–

REF = 5V

REF = GND

+

–

C

REF

= 0.001µF

IN = GND

IN = 2.5V

C

= 100pF

REF

F

= GND

O

T = 25°C

A

C

= 0pF

REF

1

10

100

1k

10k

100k

1

10

100

R

1k

(Ω)

10k

100k

R

(Ω)

SOURCE

2412 F19

24361 F19

Figure 20. –FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

Figure 19. +FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

24391f

24

LTC2439-1

W U U

U

APPLICATIO S I FOR ATIO

0

30

22

17

11

6

C

REF

= 0.01µF

V

= 5V

CC

+

C

= 1µF, 10µF

REF = 5V

REF

–

REF = GND

6

+

–

IN = 1.25V

IN = 3.75V

F

= GND

O

11

17

22

30

T

= 25°C

A

C

REF

= 0.1µF

C

REF

= 0.1µF

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 3.75V

C

= 0.01µF

REF

IN = 1.25V

C

REF

= 1µF, 10µF

F

= GND

= 25°C

O

A

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

R

SOURCE

24361 F21

24361 F22

Figure 21. +FS Error vs R_SOURCEat REF⁺and REF^–(Large C_REF

)

Figure 22. –FS Error vs R_SOURCEat REF⁺and REF^–(Large C_REF

)

1

current gain error will be insignificant (about 1% of its

valueovertheentiretemperatureandvoltagerange). Even

for the most stringent applications a one-time calibration

operation may be sufficient.

R

= 1000Ω

SOURCE

Inadditiontothereferencesamplingcharge,thereference

pinsESDprotectiondiodeshaveatemperaturedependent

leakage current. This leakage current, nominally 1nA

(±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05µV typical and 0.5µV maxi-

mum full-scale error.

0

–1

–0.5–0.4–0.3–0.2–0.1

0

0.1 0.2 0.3 0.4 0.5

V

/V

INDIF REFDIF

Output Data Rate

V

= 5V

F

C

T

= GND

CC

O

REF+ = 5V

= 10µF

REF

REF– = GND

= 25°C

24361 F23

A

When using its internal oscillator, the LTC2439-1 can

produce up to 6.8 readings per second. The actual output

data rate will depend upon the length of the sleep and data

output phases which are controlled by the user and which

can be made insignificantly short. When operated with an

external conversion clock (F_Oconnected to an external

oscillator), the LTC2439-1 output data rate can be in-

creased as desired. The duration of the conversion phase

is 20510/f_EOSC. If f_EOSC= 139,800Hz, the converter be-

havesasiftheinternaloscillatorisusedwithsimultaneous

50Hz/60Hz. There is no significant difference in the

LTC2439-1 performance between these two operation

modes.

+

–

V

INCM

= 0.5 • (IN + IN ) = 2.5V

Figure 23. INL vs Differential Input Voltage (V_IN= IN⁺– IN^–)

and Reference Source Resistance (R_SOURCEat REF⁺and REF^–

for Large C_REFValues (C_REF≥ 1µF)

impedance for the REF⁺and REF^–pins does not help the

gain or the INL error. The user is thus advised to minimize

the combined source impedance driving the REF⁺and

REF^–pins rather than to try to match it.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors

(50ppm/°C) are used for the external source impedance

seen by REF⁺and REF^–, the expected drift of the dynamic

An increase in f_EOSCover the nominal 139,800Hz will

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

24391f

25

LTC2439-1

W U U

U

APPLICATIO S I FOR ATIO

First,achangeinf_EOSCwillresultinaproportionalchange

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line

frequency. In many applications, the subsequent perfor-

mance degradation can be substantially reduced by rely-

ing upon the LTC2439-1’s exceptional common mode

rejection and by carefully eliminating common mode to

differential mode conversion sources in the input circuit.

The user should avoid single-ended input filters and

should maintain a very high degree of matching and

symmetry in the circuits driving the IN⁺and IN^–pins.

amplify low level signals to increase the voltage resolution

of ADCs that cannot operate with a low reference voltage.

TheLTC2439-1canbeusedwithreferencevoltagesaslow

as100mV,correspondingtoa±50mVinputrangewithfull

16-bit resolution. Reducing the reference voltage is func-

tionally equivalent to amplifying the input signal, however

no amplifier is required.

The LTC2439-1 has a 76µV LSB when used with a 5V

reference, however the thermal noise of the inputs is

1µV_RMSand is independent of reference voltage. Thus

reducing the reference voltage will increase the resolution

at the inputs as long as the LSB voltage is significantly

larger than 1µV_RMS. A 325mV reference corresponds to a

5µV LSB, which is approximately the peak-to-peak value

ofthe1µV_RMSinputthermalnoise.Atthispoint,theoutput

code will be stable to ±1LSB for a fixed input. As the

reference is decreased further, the measured noise will

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

input and/or reference capacitors (C_IN, C_REF) are used, the

previous section provides formulae for evaluating the

effect of the source resistance upon the converter perfor-

mance for any value of f_EOSC. If small external input and/

or reference capacitors (C_IN, C_REF) are used, the effect of

theexternalsourceresistanceupontheLTC2439-1typical

performance can be inferred from Figures 14, 15, 19 and

approach 1µV_RMS

.

Figure 30 shows two methods of dividing down the

referencevoltagetotheLTC2439-1.Whereabsoluteaccu-

racy is required, a precision divider such as the Vishay

MPM series dividers in a SOT-23 package may be used. A

51:1 divider provides a 98mV reference to the LTC2439-1

from a 5V source. The resulting ±49mV input range and

1.5µV LSB is suitable for thermocouple and 10mV full-

scale strain gauge measurements.

20 in which the horizontal axis is scaled by 139,800/f_EOSC

.

Third, an increase in the frequency of the external oscilla-

torabove460800Hz(amorethan3×increaseintheoutput

data rate) will start to decrease the effectiveness of the

internal autocalibration circuits. This will result in a pro-

gressive degradation in the converter accuracy and linear-

ity. Typical measured performance curves for output data

rates up to 100 readings per second are shown in Fig-

ures 24, 25, 26, 27, 28 and 29. In order to obtain the

highest possible level of accuracy from this converter at

output data rates above 20 readings per second, the user

is advised to maximize the power supply voltage used and

to limit the maximum ambient operating temperature. In

certaincircumstances, areductionofthedifferentialrefer-

ence voltage may be beneficial.

If high initial accuracy is not critical, a standard 2%

resistor array such as the Panasonic EXB series may be

used. Single package resistor arrays provide better tem-

perature stability than discrete resistors. An array of eight

resistors can be configured as shown to provide a 294mV

reference to the LTC2439-1 from a 5V source. The fully

differentialpropertyoftheLTC2439-1referenceterminals

allow the reference voltage to be taken from four central

resistors in the network connected in parallel, minimizing

drift in the presence of thermal gradients. This is an ideal

reference for medium accuracy sensors such as silicon

micromachined pressure and force sensors. These de-

vicestypicallyhaveaccuraciesontheorderof2%andfull-

scale outputs of 50mV to 200mV.

Increasing Input Resolution by Reducing Reference

Voltage

The resolution of the LTC2439-1 can be increased by

reducing the reference voltage. It is often necessary to

24391f

26

LTC2439-1

W U U

APPLICATIO S I FOR ATIO

U

420

360

300

240

180

120

60

30

0

60

V

= 5V

CC

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

T

A

= 85°C

IN = 3.75V

V

O

= 2.5V

= 0V

= EXTERNAL OSCILLATOR

INCM

IN

IN = 1.25V

120

180

240

300

360

420

T

= 25°C

F

= EXTERNAL OSCILLATOR

A

O

F

15

T

= 85°C

A

T

A

= 85°C

V

= 5V

CC

+

REF = 5V

–

T

= 25°C

A

REF = GND

T

A

= 25°C

+

–

IN = 1.25V

IN = 3.75V

F

O

= EXTERNAL OSCILLATOR

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

24361 F25

24361 F24

24361 F26

Figure 24. Offset Error vs Output

Data Rate and Temperature

Figure 25. +FS Error vs Output

Data Rate and Temperature

Figure 26. –FS Error vs Output

Data Rate and Temperature

17

18

16

14

12

10

8

16

V

= 5V

CC

+

REF = GND

V

= 2.5V

= 0V

INCM

IN

16

15

14

13

12

T

= 25°C

A

T

= 25°C

A

F = EXTERNAL OSCILLATOR

O

T

= 85°C

A

T

= 25°C

A

8

T

= 85°C

A

V

= 5V

V

= 5V

REF = 5V

REF = GND

= 2.5V

–2.5V < V < 2.5V

CC

+

–

REF = 5V

V

= 5V

REF

–

REF = GND

V

REF

= 2.5V

V

F

= 2.5V

= 0V

V

INCM

IN

O

INCM

IN

= EXTERNAL OSCILLATOR

RESOLUTION = LOG (V /NOISE

F

O

= EXTERNAL OSCILLATOR

RESOLUTION = LOG (V /INL )

MAX

)

2

REF

RMS

2

REF

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

24361 F27

24361 F28

24361 F29

Figure 28. Resolution (INL_MAX≤ 1LSB)

vs Output Data Rate and Temperature

Figure 27. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Temperature

Figure 29. Offset Error vs Output

Data Rate and Reference Voltage

U

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 ±.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 TYP

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

.015 ± .004

(0.38 ± 0.10)

1. CONTROLLING DIMENSION: INCHES

.053 – .069

(1.351 – 1.748)

.004 – .009

(0.102 – 0.249)

× 45°

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

.0075 – .0098

(0.191 – 0.249)

0° – 8° TYP

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

.016 – .050

(0.406 – 1.270)

.008 – .012

(0.203 – 0.305)

.0250

(0.635)

BSC

GN28 (SSOP) 0502

24391f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC2439-1

U

TYPICAL APPLICATIO

PANASONIC EXB-2HV202G

5V

+

–

REF

5V

8 × 2k

ARRAY

0.1µF

4.7µF

9

11

12

21

19

F

O

V

CC

+

V

REF

= 294mV

REF

±147mV INPUT RANGE

4.5µV LSB

20

–

SD1

5V

CH0

VISHAY MPM1001/5002B

5V

LTC2439-1

HONEYWELL

FSL05N2C

22

18

17

16

SCK

SDO

CS

CH1

500 GRAM

FORCE SENSOR

50k

8

10

15

+

–

CH15

CH10

GND

REF

THERMOCOUPLE

1k

24391 F30

REF

V

REF

= 95.04mV

±49mV INPUT RANGE

1.5µV LSB

Figure 30. Increased Resolution Bridge/Temperature Measurement

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1043

Dual Precision Instrumentation Switched Capacitor

Building Block

Precise, Charge Balanced Switching, Low Power

LT1236A-5

LT1461

Precision Bandgap Reference, 5V

0.05% Max, 5ppm/°C Drift

Micropower Precision LDO Reference

24-Bit, No Latency ∆Σ ADC in SO-8

High Accuracy 0.04% Max, 3ppm/°C Max Drift

LTC2400

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

LTC2401/LTC2402

LTC2404/LTC2408

LTC2410

1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

24-Bit, Fully Differential, No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC in MSOP

LTC2411

1.45µV

Noise, 2ppm INL

RMS

LTC2411-1

LTC2412

24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC

2-Channel, 24-Bit, Pin Compatible with LTC2439-1

24-Bit, No Latency ∆Σ ADC

0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411

800nV Noise, 2ppm INL, 3ppm TUE, 200µA

LTC2413

Simultaneous 50Hz/60Hz Rejection, 800nV

Noise

RMS

LTC2414/LTC2418

LTC2415

8-/16-Channel, 24-Bit No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate

20-Bit, No Latency ∆Σ ADC in SO-8

0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

Pin Compatible with the LTC2410

LTC2420

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

Low Noise, 16-Bits at ±50mV Input Range

LTC2424/LTC2428

LTC2433-1

LTC2436-1

LTC2440

4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs

Differential Single Channel 16-Bit ∆Σ ADC

2-Channel Differential 16-Bit ∆Σ ADC

Low Noise, 16-Bits at ±50mV Input Range

High Speed, Low Noise 24-Bit ADC

4kHz Output Rate, 200nV Noise, 24.6 ENOBs

4kHz MUX Rate, 200nV Noise

LTC2444/45/48/49

8-/16-Channel High Speed, Low Noise 24-Bit ADC

24391f

LT/TP 0404 1K • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LTC2439-1
厂家：	Linear
描述：	8-/16-Channel 16-Bit No Latency Delta-Sigma ADC 8位/ 16通道16位无延迟增量累加ADC
文件：	总28页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2439-1 [Linear]

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