LTC2440IGNPBF_技术文档

LTC2452

Ultra-Tiny, Differential, 16-Bit

ΔΣ ADC with SPI Interface

FEATURES

DESCRIPTION

The LTC^®2452 is an ultra-tiny, fully differential, 16-bit,

analog-to-digital converter. The LTC2452 uses a single

2.7V to 5.5V supply and communicates through an SPI

n

V

Differential Input Range

CC

n

16-Bit Resolution (Including Sign), No Missing

Codes

2LSB Offset Error

4LSB Full-Scale Error

60 Conversions Per Second

Single Conversion Settling Time for Multiplexed

Applications

Single-Cycle Operation with Auto Shutdown

800µA Supply Current

0.2µA Sleep Current

n

interface. The ADC is available in an 8-pin, 3mm × 2mm

DFNpackageorTSOT-23package.Itincludesanintegrated

oscillator that does not require any external components.

It uses a delta-sigma modulator as a converter core and

has no latency for multiplexed applications. The LTC2452

includesaproprietaryinputsamplingschemethatreduces

the average input sampling current several orders of

magnitude when compared to conventional delta-sigma

converters. Additionally, due to its architecture, there is

negligible current leakage between the input pins.

n

Internal Oscillator—No External Components

Required

n

SPI Interface

The LTC2452 can sample at 60 conversions per second,

andduetotheverylargeoversamplingratio,hasextremely

relaxed antialiasing requirements. The LTC2452 includes

continuous internal offset and full-scale calibration algo-

rithmswhicharetransparenttotheuser,ensuringaccuracy

over time and over the operating temperature range. The

converterhasanexternalREFpinandthedifferentialinput

Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages

APPLICATIONS

n

System Monitoring

n

Environmental Monitoring

n

Direct Temperature Measurements

voltage range can extend up to V

.

REF

n

Instrumentation

n

Industrial Process Control

Following a single conversion, the LTC2452 can automati-

cally enter a sleep mode and reduce its supply current to

less than 0.2µA. If the user reads the ADC once a second,

the LTC2452 consumes an average of less than 50µW

from a 2.7V supply.

n

Data Acquisition

n

Embedded ADC Upgrades

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No

Latency ΔΣ is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242,

7088280, 7164378.

Integral Nonlinearity, V_CC= 3V

TYPICAL APPLICATION

3

2.7V TO 5.5V

10µF

2

1

0.1µF

REF

V

CC

+

–

IN

T

A

= –45°C, 25°C, 90°C

CS

10k

R

SCK

SDO

0

–1

–2

–3

3-WIRE SPI

INTERFACE

LTC2452

GND

IN

0.1µF

2452 TA01a

–3

–2

–1

0

1

2

3

DIFFERENTIAL INPUT VOLTAGE (V)

2452 TA01b

2452fc

1

LTC2452

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Storage Temperature Range................... –65°C to 150°C

Operating Temperature Range

CC

+

–

Analog Input Voltage (V , V ).. –0.3V to (V + 0.3V)

IN

CC

Reference Voltage (V ) .............. –0.3V to (V + 0.3V)

LTC2452C ................................................ 0°C to 70°C

LTC2452I.............................................. –40°C to 85°C

REF

CC

Digital Voltage (V , V , V ).. –0.3V to (V + 0.3V)

SDO SCK CS

CC

PIN CONFIGURATION

TOP VIEW

SCK

GND

REF

1

2

3

4

8

7

6

5

SDO

SCK 1

GND 2

REF 3

8 SDO

CS

7 CS

9

+

IN

+

6 IN

–

V

CC

IN

V

CC

4

5 IN

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

C/I GRADE T = 125°C, θ = 140°C/W

DD8 PACKAGE

8-LEAD (3mm × 2mm) PLASTIC DFN

C/I GRADE T = 125°C, θ = 76°C/W

JMAX

JA

JMAX

JA

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI)

LTC2452CDDB#TRMPBF

LTC2452IDDB#TRMPBF

LTC2452CTS8#TRMPBF

LTC2452ITS8#TRMPBF

TAPE AND REEL

PART MARKING*

LDNJ

LTDPK

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

–40°C to 85°C

0°C to 70°C

LTC2452CDDB#TRPBF

LTC2452IDDB#TRPBF

LTC2452CTS8#TRPBF

LTC2452ITS8#TRPBF

8-Lead Plastic (3mm × 2mm) DFN

8-Lead Plastic TSOT-23

–40°C to 85°C

TRM = 500 pieces. *Temperature grades are identiﬁed by a label on the shipping container.

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

(Note 3)

MIN

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Nonlinearity

Offset Error

16

(Note 4)

1

10

LSB

2

LSB

Offset Error Drift

Gain Error

0.02

0.01

0.02

2.2

80

LSB/°C

l

0.02 % of FS

LSB/°C

Gain Error Drift

Transition Noise

µV

RMS

Power Supply Rejection DC

dB

2452fc

2

LTC2452

The l denotes the speciﬁcations which apply over the full

ANALOG INPUTS AND REFERENCES

operating temperature range, otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

V

+

l

V

C

Positive Input Voltage Range

Negative Input Voltage Range

Reference Voltage Range

Overrange + Underrange Voltage, IN

V

IN

CC

–

0

V

2.5

V

REF

+

–

+

–

+ V

V

= 5V, V = 2.5V (See Figure 3)

31

LSB

pF

OR

IN

UR

REF

IN

–

+

Overrange + Underrange Voltage, IN–

= 5V, V = 2.5V (See Figure 3)

UR

REF

IN

+

–

IN , IN Sampling Capacitance

0.35

+

l

+

I

IN DC Leakage Current

V

IN

V

IN

= GND (Note 10)

–10

1

10

nA

DC_LEAK(IN )

= V (Note 10)

CC

–

l

–

I

IN DC Leakage Current

V

IN

V

IN

= GND (Note 10)

–10

1

10

nA

DC_LEAK(IN )

= V (Note 10)

CC

l

I

REF DC Leakage Current

V

REF

= 3V (Note 10)

–10

1

10

nA

DC_LEAK(REF)

Input Sampling Current (Note 5)

50

CONV

The l denotes the speciﬁcations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

CC

Supply Voltage

2.7

5.5

V

I

CC

Supply Current

Conversion

Sleep

l

CS = GND (Note 6)

800

0.2

1200

0.6

µA

CS = V (Note 6)

CC

The l denotes the speciﬁcations which apply over the full

DIGITAL INPUTS AND DIGITAL OUTPUTS

operating temperature range,otherwise speciﬁcations are at T_A= 25°C. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

– 0.3

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

IH

IL

CC

V

0.3

10

V

I

IN

–10

µA

pF

V

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

10

IN

l

I = –800µA

O

V

– 0.5

CC

OH

OL

I = 1.6mA

O

0.4

10

V

I

OZ

–10

µA

2452fc

3

LTC2452

TIMING CHARACTERISTICS _{The l denotes the speciﬁcations which apply over the full operating temperature}

range,otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

23

UNITS

ms

MHz

ns

l

t

f

t

Conversion Time

13

16.6

CONV

SCK

lSCK

hSCK

1

SCK Frequency Range

SCK Low Period

2

250

0

SCK High Period

ns

CS Falling Edge to SDO Low Z

CS Rising Edge to SDO High Z

CS Falling Edge to SCK Falling Edge

SCK Falling Edge to SDO Valid

(Notes 7, 8)

100

ns

0

ns

2

100

0

ns

3

(Note 7)

100

ns

KQ

Note 5: CS = V . A positive current is ﬂowing into the DUT pin.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

CC

Note 6: SCK = V or GND. SDO is high impedance.

CC

Note 7: See Figure 4.

Note 8: See Figure 5.

Note 9: Input sampling current is the average input current drawn from the

input sampling network while the LTC2452 is actively sampling the input.

Note 10: A positive current is ﬂowing into the DUT pin.

Note 2. All voltage values are with respect to GND. V = 2.7V to 5.5V

CC

unless otherwise speciﬁed.

V

= V /2, FS = V

REF REF

REFCM

+

–

+

–

= V – V , –V ≤ V ≤ V ; V

= (V + V )/2.

IN IN

IN

REF

IN

REF INCM

Note 3. Guaranteed by design, not subject to test.

Note 4. Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

Guaranteed by design and test correlation.

(T_A= 25°C, unless otherwise noted)

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity, V_CC= 5V

Integral Nonlinearity, V_CC= 3V

Maximum INL vs Temperature

3

2

3

2

3

2

T

= 90°C

A

1

V

= V

= 5V, 4.1V, 3V

REF

CC

T

= –45°C, 25°C, 90°C

A

0

T

= –45°C, 25°C

A

–1

–2

–3

–1

–2

–3

–1

–2

–3

–2

–1

0

1

2

3

–5 –4 –3 –2 –1

0

1

2

3

4

5

–50

–25

0

25

50

75

100

DIFFERENTIAL INPUT VOLTAGE (V)

TEMPERATURE (°C)

2452 G02

2452 G01

2452 G03

2452fc

4

LTC2452

TYPICAL PERFORMANCE CHARACTERISTICS (T_A= 25°C, unless otherwise noted)

Offset Error vs Temperature

Gain Error vs Temperature

Transition Noise vs Temperature

5

4

5

4

10

9

8

7

6

5

4

3

2

1

0

V

= V

REF

= 3V

CC

3

2

V

= V

= 4.1V

REF

CC

1

V

= V

= 5V

REF

CC

0

V

= V

= 5V

REF

CC

V

= 5V

= 3V

–1

–2

–3

–4

–5

–1

–2

–3

–4

–5

CC

V

= V

= 4.1V

REF

CC

50

V

= V

= 3V

REF

CC

–50

–25

0

25

75

100

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

2452 G04

2452 G05

2452 G06

Conversion Mode Power Supply

Current vs Temperature

Sleep Mode Power Supply

Current vs Temperature

Average Power Dissipation

vs Temperature, V_CC= 3V

10000

1000

100

10

900

800

700

600

500

400

300

200

100

0

250

200

150

100

50

V

= 5V

= 3V

25Hz OUTPUT SAMPLE RATE

10Hz OUTPUT SAMPLE RATE

CC

V

= 5V

CC

V

= 4.1V

CC

V

CC

V

= 4.1V

CC

1Hz OUTPUT SAMPLE RATE

V

= 3V

CC

0

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

2452 G09

2452 G07

2452 G08

Power Supply Rejection

vs Frequency at V_CC

Conversion Time vs Temperature

21

20

19

18

17

16

15

14

0

–20

–40

V

= 5V, 4.1V, 3V

CC

–60

–80

–100

–120

–50

–25

0

25

50

75

100

1

10 100 1k 10k 100k 1M 10M

FREQUENCY AT V (Hz)

TEMPERATURE (°C)

CC

2452 G11

2452 G10

2452fc

5

LTC2452

PIN FUNCTIONS

–

+

SCK(Pin1):SerialClockInput.SCKsynchronizestheserial

data output. While digital data is available (the ADC is not

in CONVERT state) and CS is LOW (ADC is not in SLEEP

state) a new data bit is produced at the SDO output pin

following every falling edge applied to the SCK pin.

IN (Pin 5), IN (Pin 6): Differential Analog Input.

CS (Pin 7): Chip Select (Active LOW) Digital Input. A

LOW on this pin enables the SDO digital output. A HIGH

on this pin places the SDO output pin in a high imped-

ance state.

GND (Pin 2): Ground. Connect to a ground plane through

a low impedance connection.

SDO (Pin 8): Three-State Serial Data Output. SDO is used

for serial data output during the DATA OUTPUT state and

can be used to monitor the conversion status.

REF(Pin3):ReferenceInput. ThevoltageonREFcanhave

any value between 2.5V and V . The reference voltage

CC

Exposed Pad (Pin 9): Ground. Must be soldered to PCB

ground. For prototyping purposes, this pad may remain

ﬂoating.

sets the full-scale range.

V

(Pin 4): Positive Supply Voltage. Bypass to GND

CC

(Pin 2) with a 10µF capacitor in parallel with a low-se-

ries-inductance 0.1µF capacitor located as close to the

LTC2452 as possible.

BLOCK DIAGRAM

3

4

REF

V

CC

CS

7

8

1

SPI

INTERFACE

+

SDO

SCK

IN

16-BIT ΔΣ

A/D CONVERTER

6

5

DECIMATING

SINC FILTER

–

IN

16-BIT ΔΣ

A/D CONVERTER

INTERNAL

OSCILLATOR

GND

2, 9

2452 BD

Figure 1. Functional Block Diagram

APPLICATIONS INFORMATION

CONVERTER OPERATION

The operating cycle begins with the CONVERT state, is

followed by the SLEEP state, and ends with the DATA OUT-

PUT state (see Figure 2). The 3-wire interface consists of

serial data output (SDO), serial clock input (SCK), and the

active low chip select input (CS).

Converter Operation Cycle

The LTC2452 is a low power, fully differential, delta-sigma

analog-to-digital converter with a simple 3-wire SPI in-

terface (see Figure 1). Its operation is composed of three

successive states: CONVERT, SLEEP and DATA OUTPUT.

TheCONVERTstatedurationisdeterminedbytheLTC2452

conversion time (nominally 16.6 milliseconds). Once

2452fc

6

LTC2452

APPLICATIONS INFORMATION

POWER-ON RESET

corresponds to the last completed conversion. A new bit

of data appears at the SDO pin following each falling edge

detected at the SCK input pin and appears from MSB to

LSB. The user can reliably latch this data on every rising

edge of the external serial clock signal driving the SCK

pin (see Figure 3).

CONVERT

SLEEP

The DATA OUTPUT state concludes in one of two different

ways.First,theDATAOUTPUTstateoperationiscompleted

once all 16 data bits have been shifted out and the clock

SCK = LOW

NO

AND

CS = LOW?

th

then goes low. This corresponds to the 16 falling edge

of SCK. Second, the DATA OUTPUT state can be aborted

at any time by a LOW-to-HIGH transition on the CS input.

Following either one of these two actions, the LTC2452

will enter the CONVERT state and initiate a new conver-

sion cycle.

YES

DATA OUTPUT

16TH FALLING

NO

YES

EDGE OF SCK

OR

Power-Up Sequence

2452 F02

CS = HIGH?

When the power supply voltage (V ) applied to the con-

CC

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

Figure 2. LTC2452 State Transition Diagram

When V rises above this critical threshold, the converter

started, this operation can not be aborted except by a low

CC

generates an internal power-on reset (POR) signal for

approximately 0.5ms. The POR signal clears all internal

registers. Following the POR signal, the LTC2452 starts a

conversioncycleandfollowsthesuccessionofstatesshown

in Figure 2. The ﬁrst conversion result following POR is

accurate within the speciﬁcations of the device if the power

power supply condition (V < 2.1V) which generates an

CC

internal power-on reset signal.

After the completion of a conversion, the LTC2452 enters

the SLEEP state and remains there until both the chip

select and serial clock inputs are low (CS = SCK = LOW).

Followingthiscondition,theADCtransitionsintotheDATA

OUTPUT state.

supply voltage V is restored within the operating range

CC

(2.7V to 5.5V) before the end of the POR time interval.

While in the SLEEP state, whenever the chip select input

is pulled high (CS = HIGH), the LTC2452’s power supply

currentisreducedtolessthan200nA.Whenthechipselect

input is pulled low (CS = LOW), and SCK is maintained

at a HIGH logic level, the LTC2452 will return to a normal

power consumption level. During the SLEEP state, the

result of the last conversion is held indeﬁnitely in a static

register.

Ease of Use

TheLTC2452dataoutputhasnolatency,ﬁltersettlingdelay

orredundantresultsassociatedwiththeconversioncycle.

Thereisaone-to-onecorrespondencebetweentheconver-

sion and the output data. Therefore, multiplexing multiple

analog input voltages requires no special actions.

The LTC2452 performs offset calibrations every conver-

sion. This calibration is transparent to the user and has no

effect upon the cyclic operation described previously. The

advantage of continuous calibration is stability of the ADC

performance with respect to time and temperature.

Upon entering the DATA OUTPUT state, SDO outputs the

sign (D15) of the conversion result. During this state,

the ADC shifts the conversion result serially through the

SDO output pin under the control of the SCK input pin.

There is no latency in generating this data and the result

2452fc

7

LTC2452

APPLICATIONS INFORMATION

20

16

12

8

TheLTC2452includesaproprietaryinputsamplingscheme

that reduces the average input current by several orders

of magnitude when compared to traditional delta-sigma

architectures. This allows external ﬁlter networks to in-

terface directly to the LTC2452. Since the average input

sampling current is 50nA, an external RC lowpass ﬁlter

using 1kΩ and 0.1µF results in <1LSB additional error.

Additionally, there is negligible leakage current between

4

0

–4

–8

–12

–16

–20

SIGNALS

BELOW

GND

+

–

IN and IN .

–0.001 –0.005

0

V

0.005 0.001 0.0015

+

/V

IN REF

Reference Voltage Range

2452 F03

Figure 3. Output Code vs V_IN⁺with V_IN^–= 0

The LTC2453 reference input range is 2.5V to V . For the

CC

simplest operation, REF can be shorted to V .

CC

The total amount of overrange and underrange capability

is typically 31LSB for a given device. The 31LSB total

is distributed between the overrange and underrange

capability. For example, if the underrange capability is

8LSB,theoverrangecapabilityistypically31–8=23LSB.

Input Voltage Range

AsmentionedintheOutputDataFormatsection,theoutput

code is given as 32768•V /V + 32768. For V ≥ V ,

IN REF

IN

REF

the output code is clamped at 65535 (all ones). For V ≤

IN

Output Data Format

–V , the output code is clamped at 0 (all zeroes).

REF

The LTC2452 generates a 16-bit direct binary encoded

result. It is provided as a 16-bit serial stream through the

SDO output pin under the control of the SCK input pin

(see Figure 4).

The LTC2452 includes a proprietary system that can,

typically, digitize each input 8LSB above V and below

REF

GND, if the differential input is within V . As an ex-

REF

ample (Figure 3), if the user desires to measure a signal

–

+

–

slightly below ground, the user could set V = GND,

Letting V = (V

– V ), the output code is given

IN

+

and V = 5V. If V = GND, the output code would be

as 32768•V /V

+ 32768. The ﬁrst bit output by the

REF

IN

IN REF

+

–

approximately 32768. If V = GND – 8LSB = –1.22 mV,

the output code would be approximately 32760.

LTC2452, D15, is the MSB, which is 1 for V ≥ V and

IN

+

–

0 for V < V . This bit is followed by successively less

IN

signiﬁcant bits (D14, D13...) until the LSB is output by the

LTC2452. Table 1 shows some example output codes.

Table 1. LTC2452 Output Data Format

DIFFERENTIAL INPUT

D15

(MSB)

D14

D13 D12...D2 D1

D0

CORRESPONDING

+

–

VOLTAGE V – V

(LSB) DECIMAL VALUE

IN

≥V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

65535

65534

49152

49151

32768

32767

16384

16383

0

REF

V

– 1LSB

REF

0.5•V

REF

0.5•V – 1LSB

REF

0

–1LSB

–0.5•V

REF

–0.5•V – 1LSB

REF

≤ –V

2452fc

8

LTC2452

APPLICATIONS INFORMATION

t

3

t

2

t

1

CS

D

15

D

11

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

0

14

13

12

10

1

MSB

LSB

SDO

SCK

2452 F04

t

hSCK

KQ

lSCK

Figure 4. Data Output Timing

t

2

1

CS

SDO

SCK = HIGH

CONVERT

SLEEP

2452 F05

Figure 5. Conversion Status Monitoring Mode

During the data output operation the CS input pin must

be pulled low (CS = LOW). The data output process starts

with the most signiﬁcant bit of the result being present

at the SDO output pin (SDO = D15) once CS goes low.

A new data bit appears at the SDO output pin after each

falling edge detected at the SCK input pin. The output

data can be reliably latched by the user using the rising

edge of SCK.

indication of a completed conversion cycle. An example

of such a sequence is shown in Figure 5.

Conversion status monitoring, while possible, is not re-

quiredforLTC2452asitsconversiontimeisﬁxedandequal

at approximately 16.6ms (23ms maximum). Therefore,

externaltimingcanbeusedtodeterminethecompletionofa

conversion cycle.

SERIAL INTERFACE

Conversion Status Monitor

The LTC2452 transmits the conversion result and receives

the start of conversion command through a synchronous

3-wire interface. This interface can be used during the

CONVERT and SLEEP states to assess the conversion

status and during the DATA OUTPUT state to read the

conversion result, and to trigger a new conversion.

For certain applications, the user may wish to monitor

the LTC2452 conversion status. This can be achieved

by holding SCK HIGH during the conversion cycle. In

this condition, whenever the CS input pin is pulled low

(CS = LOW), the SDO output pin will provide an indication

of the conversion status. SDO = HIGH is an indication of

a conversion cycle in progress while SDO = LOW is an

2452fc

9

LTC2452

APPLICATIONS INFORMATION

Serial Interface Operation Modes

Serial Clock Idle-High (CPOL = 1) Examples

The modes of operation can be summarized as follows:

In Figure 6, following a conversion cycle the LTC2452

automatically enters the low power sleep mode. The user

can monitor the conversion status at convenient intervals

using CS and SDO.

1) The LTC2452 functions with SCK idle high (commonly

known as CPOL = 1) or idle low (commonly known as

CPOL = 0).

Pulling CS LOW while SCK is HIGH tests whether or not

the chip is in the CONVERT state. While in the CONVERT

state, SDO is HIGH while CS is LOW. In the SLEEP state,

SDO is LOW while CS is LOW. These tests are not required

operationalstepsbutmaybeusefulforsomeapplications.

2) After the 16th bit is read, the user can choose one of

two ways to begin a new conversion. First, one can

pull CS high (CS = ↑). Second, one can use a high-low

transition on SCK (SCK = ↓).

3) At any time during the Data Output state, pulling CS

high (CS = ↑) causes the part to leave the I/O state,

abort the output and begin a new conversion.

Whenthedataisavailable, theuserapplies16clockcycles

to transfer the result. The CS rising edge is then used to

initiate a new conversion.

4) When SCK = HIGH, it is possible to monitor the conver-

sion status by pulling CS low and watching for SDO to

go low. This feature is available only in the idle-high

(CPOL = 1) mode.

The operation example of Figure 7 is identical to that of

Figure 6, except the new conversion cycle is triggered by

the falling edge of the serial clock (SCK). A 17th clock

pulse is used to trigger a new conversion cycle.

CS

SD0

D

12

D

1

D

0

15

14

13

2

SCK

clk

1

clk

2

clk

3

clk

4

clk

15

clk

16

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F06

Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.

The Rising Edge of CS Starts a New Conversion

CS

SD0

SCK

D

1

D

2

D

0

15

14

13

12

1

clk

4

clk

15

clk

16

clk

17

2

3

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F07

Figure 7. Idle-High (CPOL = 1) Clock Operation Example.

A 17th Clock Pulse is Used to Trigger a New Conversion Cycle

2452fc

10

LTC2452

APPLICATIONS INFORMATION

CS

SD0

D

15

D

14

D

13

D

12

D

2

D

1

D

0

SCK

clk

1

clk

2

clk

3

clk clk

clk

15

clk

16

4

14

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F08

Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion

CS

SD0

D

12

D

0

15

14

13

2

1

SCK

clk

1

clk

2

clk

3

clk

4

clk

14

clk

15

clk

16

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F09

Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion

Serial Clock Idle-Low (CPOL = 0) Examples

Examples of Aborting Cycle using CS

In Figure 8, following a conversion cycle the LTC2452

automatically enters the low-power sleep state. The user

determines data availability (and the end of conversion)

based upon external timing. The user then pulls CS low

(CS = ↓) and uses 16 clock cycles to transfer the result.

Followingthe16thrisingedgeoftheclock,CSispulledhigh

(CS = ↑), which triggers a new conversion.

For some applications, the user may wish to abort the I/O

cycle and begin a new conversion. If the LTC2452 is in

the data output state, a CS rising edge clears the remain-

ing data bits from the output registers, aborts the output

cycle and triggers a new conversion. Figure 10 shows

an example of aborting an I/O with idle-high (CPOL = 1)

and Figure 11 shows an example of aborting an I/O with

idle-low (CPOL = 0).

ThetimingdiagraminFigure9isidenticaltothatofFigure 8,

except in this case a new conversion is triggered by SCK.

The 16th SCK falling edge triggers a new conversion cycle

and the CS signal is subsequently pulled high.

A new conversion cycle can be triggered using the CS

signal without having to generate any serial clock pulses

as shown in Figure 12. If SCK is maintained at a low logic

level, after the end of a conversion cycle, a new conver-

2452fc

11

LTC2452

APPLICATIONS INFORMATION

CS

SD0

SCK

D

15

D

13

14

clk

1

clk

2

clk

3

clk

4

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F10

Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example

CS

SD0

D

13

15

14

SCK

clk

1

clk

2

clk

3

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F11

Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example

CS

SD0

D

15

SCK = LOW

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F12

Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example

2452fc

12

LTC2452

APPLICATIONS INFORMATION

sion operation can be triggered by pulling CS low and

then high. When CS is pulled low (CS = LOW), SDO will

output the sign (D15) of the result of the just completed

conversion. While a low logic level is maintained at SCK

pin and CS is subsequently pulled high (CS = HIGH) the

remaining 15 bits of the result (D14:D0) are discarded

and a new conversion cycle starts.

Figure 13 shows a 2-wire operation sequence which uses

anidle-high(CPOL=1)serialclocksignal. Theconversion

status can be monitored at the SDO output. Following a

conversion cycle, the ADC enters SLEEP state and the

SDO output transitions from HIGH to LOW. Subsequently

16 clock pulses are applied to the SCK input in order

to serially shift the 16 bit result. Finally, the 17th clock

pulse is applied to the SCK input in order to trigger a new

conversion cycle.

Following the aborted I/O, additional clock pulses in the

CONVERT state are acceptable, but excessive signal tran-

sitions on SCK can potentially create noise on the ADC

during the conversion, and thus may negatively inﬂuence

the conversion accuracy.

Figure 14 shows a 2-wire operation sequence which uses

an idle-low (CPOL = 0) serial clock signal. The conversion

status cannot be monitored at the SDO output. Following

a conversion cycle, the LTC2452 bypasses the SLEEP

state and immediately enters the DATA OUTPUT state. At

this moment the SDO pin outputs the sign (D15) of the

conversion result. The user must use external timing in

order to determine the end of conversion and result avail-

ability. Subsequently 16 clock pulses are applied to SCK

in order to serially shift the 16-bit result. The 16th clock

falling edge triggers a new conversion cycle.

2-Wire Operation

The2-wireoperationmodes,whilereducingthenumberof

requiredcontrolsignals,shouldbeusedonlyiftheLTC2452

low power sleep capability is not required. In addition the

option to abort serial data transfers is no longer available.

Hardwire CS to GND for 2-wire operation.

CS = LOW

D

14

D

0

15

13

12

2

1

SD0

SCK

clk

1

clk

2

clk

3

clk

4

clk

15

clk

16

clk

17

CONVERT

SLEEP

DATA OUTPUT

CONVERT

2452 F13

Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example

CS = LOW

SD0

D

15

D

13

D

12

D

2

D

1

D

0

14

SCK

clk

1

clk

2

clk

3

clk clk

clk

15

clk

16

4

14

CONVERT

DATA OUTPUT

CONVERT

2452 F14

Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example

2452fc

13

LTC2452

APPLICATIONS INFORMATION

PRESERVING THE CONVERTER ACCURACY

these two decoupling capacitors, and returning to the

converter GND pin. The area encompassed by this circuit

path, as well as the path length, should be minimized.

TheLTC2452isdesignedtominimizetheconversionresult’s

sensitivity to device decoupling, PCB layout, antialiasing

circuits, line and frequency perturbations. Nevertheless,

in order to preserve the high accuracy capability of this

part, some simple precautions are desirable.

Furthermore, as shown in Figure 15, GND is used as the

negative reference voltage. It is thus important to keep the

GND line quiet and connect GND through a low-imped-

ance trace.

Digital Signal Levels

Very low impedance ground and power planes, and star

DuetothenatureofCMOSlogic,itisadvisabletokeepinput

connections at both V and GND pins, are preferable.

CC

digital signals near GND or V . Voltages in the range of

The V pin should have two distinct connections: the

CC

0.5V to V – 0.5V may result in additional current leakage

ﬁrst to the decoupling capacitors described above, and

the second to the ground return for the power supply

voltage source.

CC

from the part. Undershoot and overshoot should also be

minimized, particularly while the chip is converting. It is

thus beneﬁcial to keep edge rates of about 10ns and limit

overshoot and undershoot to less than 0.3V.

Driving REF

Noisy external circuitry can potentially impact the output

under 2-wire operation. In particular, it is possible to get

the LTC2452 into an unknown state if an SCK pulse is

missed or noise triggers an extra SCK pulse. In this situ-

ation, it is impossible to distinguish SDO = 1 (indicating

conversion in progress) from valid “1” data bits. As such,

CPOL = 1 is recommended for the 2-wire mode. The user

should look for SDO = 0 before reading data, and look

for SDO = 1 after reading data. If SDO does not return a

“0” within the maximum conversion time (or return a “1”

after a full data read), generate 16 SCK pulses to force a

new conversion.

A simpliﬁed equivalent circuit for REF is shown in Figure

15. Like all other A/D converters, the LTC2452 is only

as accurate as the reference it is using. Therefore, it is

important to keep the reference line quiet by careful low

and high frequency decoupling.

V

CC

R

SW

15k

I

LEAK

(TYP)

REF

LEAK

R

SW

15k

I

LEAK

(TYP)

Driving V and GND

+

CC

IN

LEAK

InrelationtotheV andGNDpins,the LTC2452combines

CC

internalhighfrequencydecouplingwithdampingelements,

which reduce the ADC performance sensitivity to PCB

layout and external components. Nevertheless, the very

highaccuracyofthisconverterisbestpreservedbycareful

low and high frequency power supply decoupling.

C

EQ

R

SW

0.35pF

(TYP)

15k

I

LEAK

(TYP)

–

IN

LEAK

A 0.1µF, high quality, ceramic capacitor in parallel with a

10µF ceramic capacitor should be connected between the

R

SW

15k

I

LEAK

(TYP)

2452 F15

V

CC

and GND pins, as close as possible to the package.

GND

The 0.1µF capacitor should be placed closest to the ADC

package. It is also desirable to avoid any via in the circuit

LEAK

path, starting from the converter V pin, passing through

CC

Figure 15. LTC2452 Analog Input/Reference Equivalent Circuit

2452fc

14

LTC2452

APPLICATIONS INFORMATION

The LT6660 reference is an ideal match for driving the

LTC2452’s REF pin. The LTC6660 is available in a 2mm

× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.

Therearesomeimmediatetrade-offsinR andC without

S IN

needing a full circuit analysis. Increasing R and C can

S

IN

give the following beneﬁts:

1) DuetotheLTC2452’sinputsamplingalgorithm,theinput

A 0.1µF, high quality, ceramic capacitor in parallel with a

10µF ceramic capacitor should be connected between the

REFandGNDpins,ascloseaspossibletothepackage.The

0.1µF capacitor should be placed closest to the ADC.

+

–

current drawn by either V or V over a conversion

IN

cycle is typically 50nA. A high R • C attenuates the

S

IN

high frequency components of the input current, and

R values up to 1k result in <1LSB error.

S

+

–

Driving V and V

IN

2) The bandwidth from V is reduced at the input pins

SIG

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 16. The input signal V is

+

–

(IN , IN ). This bandwidth reduction isolates the ADC

from high frequency signals, and as such provides

simple antialiasing and input noise reduction.

SIG

+

–

connected to the ADC input pins (IN and IN ) through an

equivalentsourceresistanceR .Thisresistorincludesboth

S

the actual generator source resistance and any additional

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

optional resistors connected to the input pins. Optional

input capacitors C are also connected to the ADC input

IN

4) A large C gives a better AC ground at the input pins,

IN

pins. This capacitor is placed in parallel with the ADC

helping reduce reﬂections back to the signal source.

input parasitic capacitance C . Depending on the PCB

PAR

5) Increasing R protects the ADC by limiting the current

layout, C

has typical values between 2pF and 15pF. In

S

PAR

during an outside-the-rails fault condition.

addition, the equivalent circuit of Figure 16 includes the

converter equivalent internal resistor R and sampling

SW

There is a limit to how large R • C should be for a given

S

IN

capacitor C .

EQ

application. Increasing R beyond a given point increases

S

the voltage drop across R due to the input current,

S

to the point that signiﬁcant measurement errors exist.

V

CC

R

SW

Additionally, forsomeapplications, increasingtheR • C

S

IN

15k

I

LEAK

R

S

(TYP)

product too much may unacceptably attenuate the signal

+

IN

at frequencies of interest.

I

LEAK

+

C

IN

EQ

SIG

I

CONV

–

0.35pF

(TYP)

C

PAR

For most applications, it is desirable to implement C as

IN

a high-quality 0.1µF ceramic capacitor and R ≤ 1k. This

S

CC

R

SW

capacitor should be located as close as possible to the

15k

I

LEAK

R

S

(TYP)

actualV packagepin.Furthermore,theareaencompassed

IN

–

IN

by this circuit path, as well as the path length, should be

LEAK

–

+

C

IN

SIG

EQ

I

CONV

–

minimized.

0.35pF

(TYP)

C

PAR

2452 F16

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split R and place series

S

Figure 16. LTC2452 Input Drive Equivalent Circuit

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

2452fc

15

LTC2452

APPLICATIONS INFORMATION

Figure 17 shows the measured LTC2452 INL vs Input

Finally, if the recommended choice for C is unacceptable

IN

Voltage as a function of R value with an input capacitor

fortheuser’sspeciﬁcapplication,analternatestrategyisto

S

C = 0.1µF.

IN

eliminateC andminimizeC andR .Inpracticalterms,

IN PAR S

thisconﬁgurationcorrespondstoalowimpedancesensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

Insomecases,R canbeincreasedabovetheseguidelines.

S

The input current is zero when the ADC is either in sleep

or I/O modes. Thus, if the time constant of the input RC

circuit t = R • C , is of the same order of magnitude or

S

IN

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

on. The resultant INL vs V is shown in Figure 18. The

IN

measurements of Figure 18 include a capacitor C

cor-

PAR

respondingtoaminimumsizedlayoutpadandaminimum

width input trace of about 1 inch length.

These considerations need to be balanced out by the input

signal bandwidth. The 3dB bandwidth ≈ 1/(2pR C ).

S IN

10

C

V

A

= 0.1µF

= 5V

C

V

A

= 0

IN

CC

= 25°C

IN

CC

8

6

8

6

= 5V

T

= 25°C

R

S

= 10k

4

R

S

= 10k

2

R

S

= 2k

R

S

= 0

0

R

S

= 0

R = 1k, 2k

S

R

S

= 1k

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

–5 –4 –3 –2 –1

0

1

2

3

4

5

–5 –4 –3 –2 –1

0

1

2

3

4

5

DIFFERENTIAL INPUT VOLTAGE (V)

2452 F18

2452 F17

Figure 17. Measured INL vs Input Voltage,

C_IN= 0.1µF, V_CC= 5V, T_A= 25°C

Figure 18. Measured INL vs Input Voltage,

_IN= 0, V_CC= 5V, T_A= 25°C

C

2452fc

16

LTC2452

APPLICATIONS INFORMATION

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

bit, regardless of the value of the other input voltage. If

both of the input voltages are within their transition noise

bands, the output can ﬂuctuate 2 bits.

1

TheLTC2452includesasinc typedigitalﬁlterwiththeﬁrst

notch located at f = 60Hz. As such, the 3dB input signal

Forasimplesystemnoiseanalysis,theV drivecircuitcan

0

IN

bandwidthis26.54Hz.ThecalculatedLTC2452inputsignal

attenuation vs frequency over a wide frequency range is

shown in Figure 19. The calculated LTC2452 input signal

attenuation vs frequency at low frequencies is shown in

be modeled as a single-pole equivalent circuit character-

ized by a pole location f and a noise spectral density n .

i

If the converter has an unlimited bandwidth, or at least a

bandwidth substantially larger than f , then the total noise

i

Figure 20. The converter noise level is about 2.2µV

contribution of the external drive circuit would be:

RMS

and can be modeled by a white noise source connected

V_n= n_ip /2• f_i

at the input of a noise-free converter.

On a related note, the LTC2452 uses two separate A/D

converters to digitize the positive and negative inputs.

Then, the total system noise level can be estimated as

2

the square root of the sum of (V ) and the square of the

n

2

Each of these A/D converters has 2.2µV

transition

RMS

LTC2452 noise ﬂoor (~2.2µV ).

noise. If one of the input voltages is within this small

transition noise band, then the output will ﬂuctuate one

0

–20

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–40

–60

–80

–100

0

5.0

7.5

1.00 1.25 1.50

0

60 120 180 240 300 360 420 480 540 600

INPUT SIGNAL FREQUENCY (Hz)

2452 F20

2.5

INPUT SIGNAL FREQUENCY (MHz)

2452 F19

Figure 19. LTC2452 Input Signal Attentuation vs Frequency

Figure 20. LTC2452 Input Signal Attenuation

vs Frequency (Low Frequencies)

2452fc

17

LTC2452

TYPICAL APPLICATION

JP1

+5V

EXT

+

U2

V

1

2

3

LT6660HCDC-5

V

3

1

CC

IN

OUT

V

CC

1µF

1k

GND GND

1µF

GND

2

4

+

REF

+

V

V V

CC

0.1µF

1µF

1

2

10V

5V

CONTROLLER

SCK SDO

CS

3

+

4

TO

U1*

REF

V

1k

6

4

7

5

CC

6

5

CS

SCK/SCL

MOSI/SDA

MISO/SDO

GND GND GND

7

1

+

IN

CS

LTC2452

0.1µF

SCK

1k

–

8

IN

SDO

–

REF

GND

9

0.1µF

2

3

8

13

2452 TA02

2452fc

18

LTC2452

PACKAGE DESCRIPTION

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702 Rev B)

0.61 0.05

(2 SIDES)

0.70 0.05

2.55 0.05

1.15 0.05

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

2.20 0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115

0.40 0.10

3.00 0.10

(2 SIDES)

TYP

5

R = 0.05

8

TYP

2.00 0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

PIN 1

R = 0.20 OR

(SEE NOTE 6)

0.25 × 45°

0.56 0.05

(2 SIDES)

CHAMFER

4

1

(DDB8) DFN 0905 REV B

0.25 0.05

0.75 0.05

0.200 REF

0.50 BSC

2.15 0.05

(2 SIDES)

0 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

2452fc

19

LTC2452

PACKAGE DESCRIPTION

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

2.90 BSC

(NOTE 4)

0.40

MAX

0.65

REF

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

TS8 TSOT-23 0710 REV A

0.09 – 0.20

(NOTE 3)

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

2452fc

20

LTC2452

REVISION HISTORY ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

03/10 Updated Analog Inputs and References section

Added text to Input Voltage Range section

3

8

2452fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

21

LTC2452

RELATED PARTS

PART NUMBER

LT1236A-5

LT1461

DESCRIPTION

COMMENTS

Precision Bandgap Reference, 5V

Micropower Series Reference, 2.5V

Micropower Precision Reference in TSOT-23-6 Package

0.05% Max, 5ppm/°C Drift

0.04% Max, 3ppm/°C Drift

LT1790

60µA Max Supply Current, 10ppm/°C Max Drift, 1.25V, 2.048V,

2.5V, 3V, 3.3V, 4.096V and 5V Options

LTC1860/LTC1861

12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP

850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC

LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP

LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC

LTC2440

LTC2480

200nV

Noise, 4kHz Output Rate, 15ppm INL

24-Bit No Latency ΔΣ™ADC

RMS

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

Noise,

16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

Temp. Sensor, SPI

RMS

LTC2481

LTC2482

LTC2483

LTC2484

LTC2485

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

2

Temp. Sensor, I C

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, SPI

2

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, I C

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

24-Bit, Differential Input, No Latency ΔΣ ADC, SPI with

Temp. Sensor

2

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

24-Bit, Differential Input, No Latency ΔΣ ADC, I C with

Temp. Sensor

LTC6241

LT6660

Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp

550nV Noise, 125µV Offset Max

P-P

Micropower References in 2mm × 2mm DFN Package,

2.5V, 3V, 3.3V, 5V

20ppm/°C max drift, 0.2% Max

LTC2450

LTC2450-1

LTC2451

LTC2453

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI

2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,

30Hz Output Rate

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI

2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

60Hz Output Rate

2

Easy-to-Use, Ultra-Tiny 16-Bit ADC, I C

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package, Programmable 30Hz/60Hz Output Rates

2

Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I C

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

2452fc

LT 0311 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

22

l

 LINEAR TECHNOLOGY CORPORATION 2008

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2440IGNPBF
厂家：	Linear
描述：	暂无描述
文件：	总22页 (文件大小：501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2440IGNPBF [Linear]

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