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LTC2442IG#TR [Linear]

LTC2442 - 24-Bit High Speed 4-Channel Delta Sigma ADC with Integrated Amplifier; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C;
LTC2442IG#TR
型号： LTC2442IG#TR
厂家： Linear    Linear
描述：

LTC2442 - 24-Bit High Speed 4-Channel Delta Sigma ADC with Integrated Amplifier; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C

光电二极管 转换器
文件： 总32页 (文件大小：377K)
中文：  中文翻译
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LTC2442  
24-Bit High Speed  
4-Channel ΔΣ ADC  
with Integrated Amplifier  
U
DESCRIPTIO  
FEATURES  
The LTC®2442 is an ultra high precision, variable speed,  
24-bit ΔΣTM ADC with integrated amplifier. The amplifier  
can be configured as a buffer for easy input drive of high  
impedance sensors. 1 part-per-million (ppm) linearity is  
achievable when the amplifier is configured in unity gain.  
External resistors can be used to set a gain for increased  
resolution of low level input signals. The positive and  
■
1ppm Linearity with No Missing Codes  
■
Integrated Amplifier for Direct Sensor Digitization  
■
2 Differential or 4 Single-Ended Input Channels  
■
Up to 8kHz Output Rate  
■
Up to 4kHz Multiplexing Rate  
■
Selectable Speed/Resolution  
2µV  
Noise at 1.76kHz Output Rate  
RMS  
RMS  
220nV  
Noise at 13.8Hz Output Rate with  
negative amplifier supply pins may be tied directly to V  
CC  
Simultaneous 50Hz/60Hz Rejection  
(4.5V to 5.5V) and GND or biased above V and below  
CC  
■
Guaranteed Modulator Stability and Lock-Up  
Immunity for any Input and Reference Conditions  
GND for rail-to-rail input signals.  
The proprietary ΔΣ architecture ensures stable DC ac-  
curacy through continuous transparent calibration. Ten  
■
■
<5µV Offset (4.5V < V < 5.5V, –40°C to 85°C)  
CC  
Differential Input and Differential Reference with GND  
speed/resolution combinations from 6.9Hz/220nV  
to  
RMS  
to V Common Mode Range  
CC  
3.5kHz/25µV  
can be selected with no latency or shift  
RMS  
■
No Latency Mode, Each Conversion is Accurate Even  
in DC accuracy. Additionally, a 2X speed mode can be  
selected enabling output rates up to 7kHz (8kHz with an  
external oscillator) with one cycle latency.  
After a New Channel is Selected  
■
■
Internal Oscillator—No External Components  
36-Lead SSOP PUackage  
Any combination of single-ended (up to 4 inputs) or dif-  
ferential (up to 2 inputs) can be selected with a common  
APPLICATIO S  
mode input range from ground to V . While operating in  
CC  
■
Auto Ranging 6-Digit DVMs  
the 1X speed mode the first conversion following a new  
■
High Speed Multiplexing  
speed/resolution or channel selection is valid.  
■
Weight Scales  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
No Latency ∆Σ is a trademark of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
■
Direct Temperature Measurement  
■
High Speed Data Acquisition  
Protected by U.S. Patents including 6140950, 6169506, 6411242, 6639526.  
U
TYPICAL APPLICATIO  
High Precision Data Acquisition System  
LTC2442 Integral Non-Linearity  
5
V
V
V
V
V
= 2.048V  
0.1µF  
INCM  
REF  
4
3
= 4.096V  
= 5V  
CC  
4.5V TO 15V 4.5V TO 5.5V  
+
= 5V  
–
= EXTERNAL OSCILLATOR  
= 0V  
2
+
+
= INTERNAL OSCILLATOR  
V
REF  
V
V
CC  
F
O
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE)  
1
CH0  
–
+
SDI  
SCK  
SDO  
CS  
0
CH1  
HIGH Z  
2-CHANNEL  
DIFFERENTIAL/  
4-CHANNEL  
SINGLE ENDED  
VARIABLE SPEED/  
RESOLUTION  
DIFFERENTIAL  
24-BIT ∆Σ ADC  
4-WIRE  
SPI INTERFACE  
–1  
–2  
–3  
–4  
–5  
CH2 AUTO-CAL  
+
–
CH3  
COM  
–
–
V
V
REF  
GND  
LTC2442  
2442 TA01  
–2.048  
–1.024  
0
1.024  
2.048  
–15V TO 0V  
V
DIFFERENTIAL (V)  
0.1µF  
IN  
2442 TA02  
2442f  
1
LTC2442  
W W U W  
U
W
U
ABSOLUTE AXI U RATI GS  
PACKAGE/ORDER I FOR ATIO  
(Notes 1, 2)  
TOP VIEW  
Supply Voltage (V ) to GND....................... –0.3V to 6V  
CC  
1
2
SDO  
CS  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
SCK  
BUSY  
EXT  
Analog Input Pins Voltage  
to GND......................................–0.3V to (V + 0.3V)  
CC  
3
F
O
Reference Input Pins Voltage  
4
SDI  
DGND  
AGND  
CH0  
to GND......................................–0.3V to (V + 0.3V)  
CC  
CC  
CC  
5
GND  
Digital Input Voltage to GND .........–0.3V to (V + 0.3V)  
–
6
REF  
REF  
Digital Output Voltage to GND.......–0.3V to (V + 0.3V)  
+
7
CH1  
Operating Temperature Range  
8
V
CH2  
CC  
LTC2442CG.................................................. 0°C to 70°C  
LTC2442IG............................................... –40°C to 85°C  
Storage Temperature Range................... –65°C to 150°C  
Lead Temperature (Soldering, 10 sec) .................. 300°C  
9
COM  
MUXOUTA  
MUXOUTB  
+INA  
V–  
CH3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
ADCINB  
ADCINA  
OUTA  
–INA  
NC  
+
–
Amplifier Supply Voltage (V to V ) ..........................36V  
NC  
NC  
NC  
V+  
NC  
NC  
OUTB  
–INB  
+INB  
G PACKAGE  
36-LEAD PLASTIC SSOP  
= 125°C, θ = 160°C/W  
T
JMAX  
JA  
ORDER PART NUMBER  
PART MARKING  
LTC2442CG  
LTC2442IG  
LTC2442CG  
LTC2442IG  
Order Options Tape and Reel: Add #TR  
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF  
Lead Free Part Marking: http://www.linear.com/leadfree/  
Consult LTC Marketing for parts specified with wider operating temperature ranges.  
ELECTRICAL CHARACTERISTICS The  
●
denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4, 15)  
A
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
●
Resolution (No Missing Codes)  
Integral Nonlinearity  
0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V (Note 5)  
24  
Bits  
REF  
CC  
REF  
IN  
REF  
+
+
–
●
●
V
V
= 5V, REF = 5V, REF = GND, V  
= 2.5V (Note 6, 14)  
INCM  
2
2
1
10  
7
ppm of V  
CC  
CC  
INCM  
REF  
REF  
REF  
–
= 5V, REF = 2.5V, REF = GND, V  
= 1.25V (Note 6, 14)  
ppm of V  
ppm of V  
+
–
REF = 4.096V, REF = GND, V  
= 2.048V (Note 6, 14)  
INCM  
+
+
–
●
Offset Error  
2.5V ≤ REF ≤ V , REF = GND,  
2.5  
5
µV  
CC  
–
GND ≤ SEL = SEL ≤ V (Note 12)  
CC  
+
+
–
Offset Error Drift  
2.5V ≤ REF ≤ V , REF = GND,  
20  
nV/°C  
CC  
–
GND ≤ SEL = SEL ≤ V  
CC  
+
+
–
+
–
●
●
Positive Full-Scale Error  
Positive Full-Scale Error Drift  
REF = 5V, REF = GND, SEL = 3.75V, SEL = 1.25V  
10  
10  
50  
50  
ppm of V  
REF  
REF  
–
+
–
REF = 2.5V, REF = GND, SEL = 1.875V, SEL = 0.625V  
ppm of V  
+
–
2.5V ≤ REF ≤ V , REF = GND,  
0.2  
ppm of V /°C  
CC  
REF  
+
+
–
+
SEL = 0.75 • REF , SEL = 0.25 • REF  
2442f  
2
LTC2442  
ELECTRICAL CHARACTERISTICS The  
●
denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4, 15)  
A
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
+
+
–
+
–
●
●
Negative Full-Scale Error  
REF = 5V, REF = GND, SEL = 1.25V, SEL = 3.75V  
10  
10  
50  
50  
ppm of V  
REF  
REF  
–
+
–
REF = 2.5V, REF = GND, SEL = 0.625V, SEL = 1.875V  
ppm of V  
+
–
–
Negative Full-Scale Error Drift  
Total Unadjusted Error  
2.5V ≤ REF ≤ V , REF = GND,  
0.2  
ppm of V /°C  
REF  
CC  
+
+
+
SEL = 0.25 • REF , SEL = 0.75 • REF  
+
–
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V  
= 1.25V (Note 6)  
= 2.5V (Note 6)  
INCM  
12  
12  
12  
ppm of V  
ppm of V  
ppm of V  
CC  
INCM  
REF  
REF  
REF  
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V  
CC  
+
–
REF = 2.5V, REF = GND, V  
= 1.25V (Note 6)  
INCM  
+
–
–
Input Common Mode Rejection DC  
2.5V ≤ REF ≤ V , REF = GND,  
120  
dB  
CC  
+
GND ≤ SEL = SEL ≤ V  
CC  
U
U
U
U
A ALOG I PUT A D REFERE CE  
The  
●
denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 15)  
A
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
+
+
+
●
●
●
SEL  
Absolute/Common Mode SEL Voltage  
SEL is the Positive Selected  
GND – 0.3  
V
V
+ 0.3  
V
CC  
Input Channel, see Table 3  
–
–
–
SEL  
Absolute/Common Mode SEL Voltage  
SEL is the Negative Selected  
GND – 0.3  
+ 0.3  
/2  
V
V
CC  
Input Channel, see Table 3  
V
IN  
Input Differential Voltage Range  
–V /2  
REF  
V
REF  
+
–
(SEL – SEL )  
+
–
+
●
●
●
REF  
REF  
Absolute/Common Mode REF Voltage  
0.1  
GND  
0.1  
V
V
V
V
CC  
–
Absolute/Common Mode REF Voltage  
V
– 0.1  
CC  
V
Reference Differential Voltage Range  
V
REF  
CC  
+
–
(REF – REF )  
C
C
C
C
ADCINA Sampling Capacitance  
ADCINB Sampling Capacitance  
2
2
2
2
1
pF  
pF  
pF  
pF  
nA  
S(ADCINA)  
S(ADCINB)  
+
+
REF Sampling Capacitance  
S(REF )  
–
–
REF Sampling Capacitance  
S(REF )  
+
–
+
–
●
I
Leakage Current, Inputs and Reference CS = V , SEL = GND, SEL =  
–15  
15  
DC_LEAK(SEL , SEL ,  
REF+, REF–)  
CC  
+
–
GND, REF = 5V, REF = GND  
t
MUX Break-Before-Make  
MUX Off Isolation  
50  
ns  
OPEN  
QIRR  
V
IN  
= 2V DC to 1.8MHz  
120  
dB  
P-P  
2442f  
3
LTC2442  
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS  
The  
●
denotes the specifications which apply over the  
full operating temperature range, otherwise specifications are at T = 25°C. (Note 3)  
A
SYMBOL  
PARAMETER  
CONDITIONS  
4.5V ≤ V ≤ 5.5V  
MIN  
TYP  
MAX  
UNITS  
●
●
●
●
●
●
V
V
V
V
High Level Input Voltage  
2.5  
V
IH  
IL  
IH  
IL  
CC  
CS, F , EXT, SDI  
O
Low Level Input Voltage  
4.5V ≤ V ≤ 5.5V  
0.8  
V
V
CC  
CS, F , EXT, SDI  
O
High Level Input Voltage  
SCK  
4.5V ≤ V ≤ 5.5V (Note 8)  
2.5  
CC  
Low Level Input Voltage  
SCK  
4.5V ≤ V ≤ 5.5V (Note 8)  
0.8  
10  
10  
V
CC  
I
I
Digital Input Current  
0V ≤ V ≤ V  
CC  
–10  
–10  
µA  
µA  
pF  
pF  
V
IN  
IN  
CS, F , EXT, SDI  
O
Digital Input Current  
SCK  
0V ≤ V ≤ V (Note 8)  
IN  
IN  
CC  
C
C
V
V
V
V
Digital Input Capacitance  
10  
10  
IN  
CS, F , EXT, SDI  
O
Digital Input Capacitance  
SCK  
(Note 8)  
IN  
●
●
●
●
●
High Level Output Voltage  
SDO, BUSY  
I = –800µA  
O
V
V
– 0.5  
OH  
OL  
OH  
OL  
CC  
CC  
Low Level Output Voltage  
SDO, BUSY  
I = 1.6µA  
O
0.4  
V
High Level Output Voltage  
SCK  
I = –800µA (Note 9)  
O
– 0.5  
V
Low Level Output Voltage  
SCK  
I = 1.6µA (Note 9)  
O
0.4  
10  
V
I
Hi-Z Output Leakage  
SDO  
–10  
µA  
OZ  
W U  
POWER REQUIRE E TS  
The  
●
denotes the specifications which apply over the full operating temperature  
range, otherwise specifications are at T = 25°C. (Notes 3)  
A
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
4.5  
TYP  
MAX  
5.5  
15  
UNITS  
●
●
●
●
V
V
V
Supply Voltage  
V
V
CC  
+
Amplifier Positive Supply  
Amplifier Negative Supply  
Supply Current  
4.5  
–
–15  
0
V
I
Amplifiers and ADC  
10  
13  
mA  
CC  
2442f  
4
LTC2442  
W U  
TI I G CHARACTERISTICS  
The  
●
denotes the specifications which apply over the full operating temperature  
range, otherwise specifications are at T = 25°C. (Note 3)  
A
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
0.1  
25  
TYP  
MAX  
20  
UNITS  
MHz  
ns  
●
●
●
f
t
t
t
External Oscillator Frequency Range  
External Oscillator High Period  
External Oscillator Low Period  
Conversion Time  
EOSC  
HEO  
10000  
10000  
25  
ns  
LEO  
●
●
OSR = 256 (SDI = 0)  
OSR = 32768 (SDI = 1)  
0.99  
126  
1.13  
145  
1.33  
170  
ms  
ms  
CONV  
●
●
External Oscillator (Notes 10, 13)  
40 • OSR + 170  
EOSC  
ms  
f
(KHz)  
f
Internal SCK Frequency  
Internal Oscillator (Note 9)  
External Oscillator (Notes 9, 10)  
0.8  
45  
0.9  
EOSC  
1
MHz  
Hz  
ISCK  
f
/10  
●
●
●
●
D
Internal SCK Duty Cycle  
(Note 9)  
(Note 8)  
(Note 8)  
(Note 8)  
55  
20  
%
MHz  
ns  
ISCK  
f
External SCK Frequency Range  
External SCK Low Period  
ESCK  
fLESCK  
25  
25  
t
t
External SCK High Period  
ns  
HESCK  
●
●
Internal SCK 32-Bit Data Output Time  
Internal Oscillator (Notes 9, 11)  
External Oscillator (Notes 9, 10)  
30.9  
35.3  
41.6  
µs  
s
DOUT_ISCK  
320/f  
EOSC  
●
●
●
t
t
t
t
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time  
CS ↓ to SDO Low Z  
(Note 8)  
32/f  
s
ns  
ns  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DOUT_ESCK  
ESCK  
(Note 12)  
(Note 12)  
(Note 9)  
0
0
25  
25  
1
CS ↑ to SDO High Z  
CS ↓ to SCK ↓  
2
5
3
●
●
●
●
●
●
●
CS ↓ to SCK ↑  
(Note 8, 12)  
25  
4
SCK ↓ to SDO Valid  
SDO Hold After SCK ↓  
SCK Setup Before CS ↓  
SCK Hold After CS ↓  
SDI Setup Before SCK ↑  
SDI Hold After SCK ↑  
25  
50  
KQMAX  
(Note 5)  
15  
50  
KQMIN  
5
6
7
8
(Note 5)  
(Note 5)  
10  
10  
Note 1: Absolute Maximum Ratings are those values beyond which the life  
of a device may be impaired.  
Note 9: The converter is in internal SCK mode of operation such that the  
SCK pin is used as a digital output. In this mode of operation, the SCK pin  
has a total equivalent load capacitance of C  
= 20pF.  
Note 2: All voltage values are with respect to GND.  
LOAD  
Note 10: The external oscillator is connected to the F pin. The external  
Note 3: V = 4.5V to 5.5V unless otherwise specified.  
O
CC  
+
–
+
–
oscillator frequency, f  
, is expressed in Hz.  
EOSC  
V
V
= REF – REF , V  
= (REF + REF )/2;  
= (SEL + SEL )/2.  
REF  
REFCM  
+
–
+
–
= SEL – SEL , V  
Note 11: The converter uses the internal oscillator. F = 0V.  
IN  
INCM  
O
Note 4: F pin tied to GND or to external conversion clock source with  
Note 12: Guaranteed by design and test correlation.  
Note 13: There is an internal reset that adds an additional 1µs (typ) to the  
conversion time.  
O
f
= 10MHz unless otherwise specified.  
EOSC  
Note 5: Guaranteed by design, not subject to test.  
Note 6: Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual endpoints of the transfer curve.  
The deviation is measured from the center of the quantization band.  
Note 14: In order to achieve optimum linearity, the amplifier power  
+
positive supply input (V ) must exceed the maximum input voltage level by  
–
2V or greater. The negative amplifier power supply input (V ) must be at  
least 200mV below the minimum input voltage level.  
Note 7: The converter uses the internal oscillator.  
Note 15: Amplifiers are externally compensated with 0.1µF.  
Note 8: The converter is in external SCK mode of operation such that the  
SCK pin is used as a digital input. The frequency of the clock signal driving  
SCK during the data output is f  
and is expressed in Hz.  
ESCK  
2442f  
5
LTC2442  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Integral Non-Linearity  
vs Temperature  
Integral Non-Linearity  
vs Temperature  
Integral Non-Linearity  
5
4
10  
8
10  
8
V
V
V
F
= 5V  
V
V
V
F
= 5V  
= 5V  
V
V
V
V
V
= 2.048V  
CC  
CC  
REF  
INCM  
REF  
= 2.5V  
= 4.096V  
REF  
–40°C  
CM = 1.25  
CM = 1.25  
= 5V  
IN  
IN  
CC  
3
6
6
+
= GND  
= GND  
= 5V  
O
O
–40°C  
+
+
–
V
= 7V  
V
= 7V  
= 0V  
2
4
4
–
–
V
= –2V  
V
= –2V  
1
2
2
0
0
0
–1  
–2  
–3  
–4  
–5  
–2  
–4  
–6  
–8  
–10  
–2  
–4  
–6  
–8  
–10  
25°C  
90°C  
25°C  
90°C  
–2.048  
–1.024  
0
1.024  
2.048  
–1.25 –0.75  
–0.25  
INPUT VOLTAGE (V)  
0.25  
0.75  
1.25  
–2.5  
–1.5  
1.5  
–0.5  
0.5  
INPUT VOLTAGE (V)  
2.5  
V
DIFFERENTIAL (V)  
IN  
2442 TA02  
2442 G02  
2442 G03  
INL vs Op Amp Positive Supply  
INL vs Op Amp Negative Supply  
+
–
Voltage (V )  
Voltage (V )  
Offset Error vs Supply Voltage  
10  
8
5.0  
2.5  
10  
8
V
V
F
= 5V  
V
V
F
= 5V  
V
V
V
= 2.5V  
OSR = 32768  
CC  
CC  
REF  
REF  
REF  
+
–
+
= 5.5  
= GND  
= 5V  
= GND  
= GND  
= 5V  
= 2.5V  
F
= GND  
O
–
= GND  
T
= 25°C  
O
O
A
6
6
+
–
V
V
V
V
SEL = SEL = GND  
REF  
IN  
REF  
IN  
CM = 2.5V  
CM = 2.5V  
4
4
2
2
0
0
0
–
–2  
–4  
–6  
–8  
–10  
V
= –2V  
–2  
–4  
–6  
–8  
–10  
+
V
= 5.5V  
–
+
V
= –1V  
0.5  
V
= 5.25V  
–
V
= 0V  
–2.5  
+
V
= 5V  
–5.0  
–2.5  
–1.5  
–0.5  
V
1.5  
2.5  
4.5  
4.7  
5.1  
(V)  
5.3  
4.9  
V
CC  
5.5  
–2.5  
–1.5  
–0.5  
V
0.5  
(V)  
1.5  
2.5  
(V)  
IN  
IN  
2442 G05  
2442 G06  
2442 G04  
Offset Error vs Common Mode  
Input Voltage  
Offset Error vs Conversion Rate  
Offset Error vs Temperature  
5.0  
2.5  
5.0  
2.5  
0
5.0  
2.5  
+
–
+
–
V
V
V
V
= 5V  
= 5V  
SEL = SEL = GND  
V
V
V
V
= 5V  
= 5V  
SEL = SEL = V  
OSR = 32768  
CC  
CC  
INCM  
F
= GND  
= 25°C  
= 5V  
REF  
REF  
REF  
O
REF  
REF  
REF  
+
–
+
–
= 5V  
= GND  
T
= 5V  
= GND  
F
= GND  
A
O
+
V
V
T
= 25°C  
A
–
= –2V  
V
= 5V  
CC  
V
= 5.5V  
V
= 4.5V  
CC  
CC  
0
0
V
V
V
V
= 4.5V  
V
= 5.5V, 5V  
CC  
CC  
= 2.5V  
V
V
V
= 5V  
REF  
REF  
REF  
REF  
REF  
REF  
+
–
+
+
–
+
= 2.5V  
= 5V  
–2.5  
–2.5  
–5.0  
–2.5  
–5.0  
= GND  
= GND  
–
–
SEL = SEL = GND SEL = SEL = GND  
OSR = 256  
OSR = 256  
F
= GND  
F
= GND  
O
O
–5.0  
0
500 1000 1500 2000 2500 3000 3500  
CONVERSION RATE (Hz)  
–55  
5
35  
65  
95  
125  
–25  
0
1
2
V
3
4
5
TEMPERATURE (°C)  
(V)  
INCM  
2442 G07  
2442 G09  
2442 G08  
2442f  
6
LTC2442  
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ADCINA (Pin 11): ADC Input. Must tie to the amplifier  
SCK(Pin1):BidirectionalDigitalClockPin.Ininternalserial  
clock operation mode, SCK is used as a digital output for  
the internal serial interface clock during the data output  
period. In the external serial clock operation mode, SCK  
is used as the digital input for the external serial interface  
clock during the data output period. The serial clock op-  
eration mode is determined by the logic level applied to  
EXT (Pin 3).  
output, OUTA (Pin 12).  
OUTA (Pin 12): Amplifier A output. Must be compensated  
with 0.1µF or greater capacitor. Drives the ADCINA ADC  
input (Pin 11).  
–INA (Pin 13): Amplifier A negative Input. By shorting this  
pin to OUTA (Pin 12) the amplifier becomes a buffer with  
unity gain. Alternatively, an external resistor network may  
be added here for gains greater than 1.  
BUSY (Pin 2): Conversion in Progress Indicator. This pin  
is HIGH while the conversion is in progress and goes LOW  
indicating the conversion is complete and data is ready.  
It remains LOW during the sleep and data output states.  
At the conclusion of the data output state, it goes HIGH  
indicating a new conversion has begun.  
NC (Pins 14, 15, 16, 20, 22, 23): No Connect. These pins  
should be left floating or tied to Ground.  
OUTB (Pin 17): Amplifier B Output. Must be compensated  
with 0.1µF or greater capacitor. Drives the ADCINB ADC  
input (Pin 10).  
EXT (Pin 3): Internal/External SCK Selection Pin. This  
pin is used to select internal or external SCK for output-  
ting/inputting data. If EXT is tied low, the device is in the  
external SCK mode and data is shifted out of the device  
under the control of a user applied serial clock. If EXT is  
tied high, the internal serial clock mode is selected. The  
device generates its own SCK signal and outputs this on  
the SCK pin. A framing signal BUSY (Pin 2) goes low  
indicating data is being output.  
–INB (Pin 18): Amplifier B negative Input. By shorting this  
pin to OUTB (Pin 17) the amplifier becomes a buffer with  
unity gain. Alternatively, an external resistor network may  
be added here for gains greater than 1.  
+INB (Pin 19): Amplifier B positive Input. Must tie to the  
Multiplexer output MUXOUTB (Pin 26).  
+
V (Pin 21): Amplifier positive supply voltage input. May  
tie to V or an external supply voltage up to 15V. Bypass  
CC  
GND (Pins 4, 5, 32): Ground. Multiple ground pins inter-  
to GND with 1µF capacitor.  
nally connected for optimum ground current flow and V  
CC  
–
V (Pin 24): Amplifier Negative supply voltage input. May  
decoupling. Connect each one of these pins to a common  
groundplanethroughalowimpedanceconnection.Allthree  
pins must be connected to ground for proper operation.  
tie to GND or an external supply voltage as low as –15V.  
Bypass to GND with a 1µF capacitor.  
+INA (Pin 25): Amplifier A positive Input. Must tie to the  
CH0 to CH3 (Pins 6, 7, 8, 9): Analog Inputs. May be  
programmed for single-ended or differential mode. (See  
Table 3)  
Multiplexer output MUXOUTA (Pin 27).  
MUXOUTB (Pin 26): Multiplexer Output. Must tie to +INB  
amplifier input (Pin 19).  
ANCINB (Pin 10): ADC Input. Must tie to the amplifier  
output, OUTB (Pin 17).  
2442f  
7
LTC2442  
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MUXOUTA (Pin 27): Multiplexer Output. Must tie to +INA  
the device under control of the serial clock (SCK) during  
the data output cycle. The first conversion following a new  
channel/speed is valid.  
amplifier input (Pin 25).  
–
COM (Pin 28): The common negative input (SEL ) for all  
single ended multiplexer configurations. The voltage on  
CH0-CH3 and COM pins can have any value between GND  
F (Pin 34): Frequency Control Pin. Digital input that con-  
0
trols the internal conversion clock. When F is connected  
0
–0.3V to V +0.3V. Within these limits, the two selected  
to V or GND, the converter uses its internal oscillator  
CC  
CC  
+
–
inputs (SEL and SEL ) provide a bipolar input range (V  
= SEL – SEL ) from –0.5 • V  
runningat9MHz. Theconversionrateisdeterminedbythe  
IN  
+
–
to 0.5 • V . Outside  
selected OSR such that t  
(ms) = 40 • OSR + 170/f  
REF  
REF  
CONV OSC  
thisinputrange,theconverterproducesuniqueover-range  
and under-range output codes.  
(kHz). The first digital filter null is located at 8/t  
, 7kHz  
CONV  
at OSR = 256 and 55Hz (Simultaneous 50Hz/60Hz at OSR  
= 32768. This pin may be driven with a maximum external  
clock of 10.24MHz resulting in a maximum 8kHz output  
rate (OSR = 64, 2X mode).  
V
(Pin29):PositiveSupplyVoltage. BypasstoGNDwith  
CC  
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic  
capacitor as close to the part as possible.  
CS (Pin 35): Active Low Chip Select. A LOW on this pin  
enables the SDO digital output and wakes up the ADC.  
Following each conversion the ADC automatically enters  
the sleep mode and remains in this state as long as CS is  
HIGH. A LOW-to-HIGH transition on CS during the Data  
Output aborts the data transfer and starts a new conver-  
sion.  
+
–
REF (Pin30),REF (Pin31):DifferentialReferenceInput.  
ThevoltageonthesepinscanhaveanyvaluebetweenGND  
+
and V as long as the reference positive input, REF , is  
CC  
maintainedmorepositivethanthenegativereferenceinput,  
–
REF , by at least 0.1V. Bypass to GND with 0.1µF Ceramic  
capacitor as close to the part as possible.  
SDI (Pin 33): Serial Data Input. This pin is used to select  
the speed, 1X or 2X mode, resolution and input channel  
for the next conversion cycle. At initial power up, the de-  
fault mode of operation is CH0-CH1, OSR of 256 and 1X  
mode. The serial data input contains an enable bit which  
determines if a new channel/speed is selected. If this bit is  
low the following conversion remains at the same speed  
and selected channel. The serial data input is applied to  
SDO (Pin 36): Three-State Digital Output. During the data  
output period, this pin is used as serial data output. When  
the chip select CS is HIGH (CS = V ) the SDO pin is in  
CC  
a high impedance state. During the conversion and sleep  
periods, this pin is used as the conversion status output.  
TheconversionstatuscanbeobservedbypullingCSLOW.  
This signal is HIGH while the conversion is in progress  
and goes LOW once the conversion is complete.  
2442f  
8
LTC2442  
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FU CTIO AL BLOCK DIAGRA  
INTERNAL  
OSCILLATOR  
+
–
+
–
V
CC  
MUXOUTB +INB –INB  
OUTB ADCINB  
REF  
REF  
V
V
AUTOCALIBRATION  
AND CONTROL  
GND  
F
O
–
AMPB  
AMPA  
CH0  
CH1  
CH2  
CH3  
COM  
BUSY  
+
+
–
IN  
IN  
DIFFERENTIAL  
3RD ORDER  
∆Σ MODULATOR  
SDI  
SCK  
SDO  
CS  
MUX  
SERIAL  
INTERFACE  
+
–
DECIMATING FIR  
ADDRESS  
EXT  
2442 F01  
MUXOUTA +INA –INA  
OUTA ADCINA  
Figure 1. Functional Block Diagram  
V
CC  
TEST CIRCUITS  
1.69k  
C
SDO  
SDO  
= 20pF  
1.69k  
C
= 20pF  
LOAD  
LOAD  
Hi-Z TO V  
Hi-Z TO V  
OL  
OH  
OH  
V
V
TO V  
OL  
V
V
TO V  
OH  
OL  
OL  
OH  
TO Hi-Z  
TO Hi-Z  
2442 TA04  
2442 TA03  
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APPLICATIO S I FOR ATIO  
CONVERTER OPERATION  
Converter Operation Cycle  
POWER UP  
IN =CH0, IN =CH1  
OSR=256,1X MODE  
+
–
The LTC2442 is a multi-channel, high speed, ΔΣ analog-  
to-digital converter with an easy to use 3- or 4-wire serial  
interface (see Figure 1). Its operation is made up of three  
states. The converter operating cycle begins with the con-  
version, followed by the sleep state and ends with the data  
output/input (see Figure 2). The 4-wire interface consists  
of serial data input (SDI), serial data output (SDO), serial  
clock (SCK) and chip select (CS). The interface, timing,  
operation cycle and data out format is compatible with  
Linear’s entire family of ΔΣ converters.  
CONVERT  
SLEEP  
CS = LOW  
AND  
SCK  
Initially, the LTC2442 performs a conversion. Once the  
conversion is complete, the device enters the sleep state.  
The part remains in the sleep state as long as CS is HIGH.  
The conversion result is held indefinitely in a static shift  
register while the converter is in the sleep state.  
CHANNEL SELECT  
SPEED SELECT  
DATA OUTPUT  
2442 F02  
Figure 2. LTC2442 State Transition Diagram  
2442f  
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Once CS is pulled LOW, the device begins outputting the  
conversion result. There is no latency in the conversion  
result while operating in the 1X mode. The data output  
corresponds to the conversion just performed. This result  
is shifted out on the serial data out pin (SDO) under the  
control of the serial clock (SCK). Data is updated on the  
falling edge of SCK allowing the user to reliably latch  
data on the rising edge of SCK (see Figure 3). The data  
output state is concluded once 32 bits are read out of the  
ADC or when CS is brought HIGH. In either scenario, the  
device automatically initiates a new conversion and the  
cycle repeats.  
The LTC2442 performs offset and full-scale calibrations  
every conversion cycle. This calibration is transparent to  
theuserandhasnoeffectonthecyclicoperationdescribed  
above. Theadvantageofcontinuouscalibrationisextreme  
stability of offset and full-scale readings with respect to  
time, supply voltage change and temperature drift.  
Power-Up Sequence  
The LTC2442 automatically enters an internal reset state  
when the power supply voltage V drops below ap-  
CC  
proximately 2.2V. This feature guarantees the integrity  
of the conversion result and of the serial interface mode  
selection.  
Through timing control of the CS, SCK and EXT pins,  
the LTC2442 offers several flexible modes of operation  
(internal or external SCK). These various modes do not  
require programming configuration registers; moreover,  
they do not disturb the cyclic operation described above.  
These modes of operation are described in detail in the  
Serial Interface Timing Modes section.  
When the V voltage rises above this critical threshold,  
CC  
the converter creates an internal power-on-reset (POR)  
signal with a duration of approximately 0.5ms. The POR  
signal clears all internal registers. The conversion im-  
mediately following a POR is performed on the input  
+
–
channel SEL = CH0, SEL = CH1 at an OSR = 256 in the  
1X mode. Following the POR signal, the LTC2442 starts  
a normal conversion cycle and follows the succession of  
states described above. The first conversion result fol-  
lowing POR is accurate within the specifications of the  
device if the power supply voltage is restored within the  
operating range (4.5V to 5.5V) before the end of the POR  
time interval.  
Ease of Use  
TheLTC2442dataoutputhasnolatency,filtersettlingdelay  
or redundant data associated with the conversion cycle  
while operating in the 1X mode. There is a one-to-one cor-  
respondence between the conversion and the output data.  
Therefore, multiplexing multiple analog voltages is easy.  
Speed/resolution adjustments may be made seamlessly  
between two conversions without settling errors.  
CS  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
32  
SCK  
SDI  
1
0
EN  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
EOC “0” SIG MSB  
SGL  
ODD  
A2  
A1  
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
BIT 0  
Hi-Z  
Hi-Z  
SDO  
LSB  
BUSY  
2442 F03  
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing  
2442f  
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Reference Voltage Range  
Bit 31 (first output bit) is the end of conversion (EOC)  
indicator. This bit is available at the SDO pin during the  
conversion and sleep states whenever the CS pin is LOW.  
This bit is HIGH during the conversion and goes LOW  
when the conversion is complete.  
The LTC2442 ΔΣ converter accepts a truly differential  
external reference voltage. The absolute/common mode  
+
–
voltage specification for the REF and REF pins covers  
the entire range from GND to V . For correct converter  
CC  
+
operation, the REF pin must always be more positive  
Bit 30 (second output bit) is a dummy bit (DMY) and is  
always LOW.  
–
than the REF pin.  
The LTC2442 can accept a differential reference voltage  
Bit 29 (third output bit) is the conversion result sign  
from0.1VtoV .Theconverteroutputnoiseisdetermined  
indicator (SIG). If V is >0, this bit is HIGH. If V is <0,  
CC  
IN IN  
by the thermal noise of the front-end circuits, and as such,  
its value in microvolts is nearly constant with reference  
voltage. A decrease in reference voltage will not signifi-  
cantly improve the converter’s effective resolution. On the  
other hand, a reduced reference voltage will improve the  
converter’s overall INL performance.  
this bit is LOW.  
Bit28(fourthoutputbit)isthemostsignificantbit(MSB)of  
the result. This bit in conjunction with Bit 29 also provides  
the underrange or overrange indication. If both Bit 29 and  
Bit 28 are HIGH, the differential input voltage is above +FS.  
If both Bit 29 and Bit 28 are LOW, the differential input  
voltage is below –FS.  
Input Voltage Range  
The function of these bits is summarized in Table 1.  
Theanaloginputistrulydifferentialwithanabsolute/com-  
mon mode range for the CH0-CH3 and COM input pins  
Table 1. LTC2442 Status Bits  
extending from GND – 0.3V to V + 0.3V. Outside these  
Input Range  
Bit 31  
EOC  
Bit 30  
DMY  
Bit 29  
SIG  
Bit 28  
MSB  
CC  
limits, the ESD protection devices begin to turn on and the  
errorsduetoinputleakagecurrentincreaserapidly.Within  
these limits, the LTC2442 converts the bipolar differential  
V
≥ 0.5 • V  
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
IN  
REF  
0V ≤ V < 0.5 • V  
IN  
REF  
+
–
input signal, V = SEL – SEL , from –FS = –0.5 • V  
–0.5 • V ≤ V < 0V  
IN  
REF  
REF  
IN  
+
–
to +FS = 0.5 • V  
where V  
= REF – REF . Outside  
REF  
REF  
V
< –0.5 • V  
IN  
REF  
this range, the converter indicates the overrange or the  
Bits 28-5 are the 24-bit conversion result MSB first.  
Bit 5 is the least significant bit (LSB).  
underrange condition using distinct output codes.  
Output Data Format  
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0  
may be included in averaging or discarded without loss  
of resolution.  
The LTC2442 serial output data stream is 32 bits long.  
The first three bits represent status information indicating  
the sign and conversion state. The next 24 bits are the  
conversion result, MSB first. The remaining five bits are  
sub LSBs beyond the 24-bit level that may be included in  
averaging or discarded without loss of resolution. In the  
caseofultrahighresolutionmodes, morethan24effective  
bitsofperformancearepossible(seeTable4).Underthese  
conditions, subLSBsareincludedintheconversionresult  
and represent useful information beyond the 24-bit level.  
The third and fourth bit together are also used to indicate  
an underrange condition (the differential input voltage  
is below –FS) or an overrange condition (the differential  
input voltage is above +FS).  
Data is shifted out of the SDO pin under control of the  
serial clock (SCK), see Figure 3. Whenever CS is HIGH,  
SDO remains high impedance and SCK is ignored.  
In order to shift the conversion result out of the device,  
CS must first be driven LOW. EOC is seen at the SDO pin  
of the device once CS is pulled LOW. EOC changes real  
time from HIGH to LOW at the completion of a conversion.  
This signal may be used as an interrupt for an external  
microcontroller. Bit 31 (EOC) can be captured on the first  
rising edge of SCK. Bit 30 is shifted out of the device on  
2442f  
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APPLICATIO S I FOR ATIO  
the first falling edge of SCK. The final data bit (Bit 0) is  
shifted out on the falling edge of the 31st SCK and may  
be latched on the rising edge of the 32nd SCK pulse. On  
the falling edge of the 32nd SCK pulse, SDO goes HIGH  
indicating the initiation of a new conversion cycle. This  
bit serves as EOC (Bit 31) for the next conversion cycle.  
Table 2 summarizes the output data format.  
Serial Clock Input/Output (SCK)  
The serial clock signal present on SCK (Pin 1) is used to  
synchronize the data transfer. Each bit of data is shifted  
out the SDO pin on the falling edge of the serial clock.  
In the Internal SCK mode of operation, the SCK pin is an  
output and the LTC2442 creates its own serial clock. In  
the External SCK mode of operation, the SCK pin is used  
as input. The internal or external SCK mode is selected  
by tying EXT (Pin 3) LOW for external SCK and HIGH for  
internal SCK.  
+
–
As long as the voltage on the SEL and SEL pins is main-  
tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum  
CC  
operating range, a conversion result is generated for any  
differential input voltage V from –FS = –0.5 • V  
to  
IN  
REF  
+FS = 0.5 • V . For differential input voltages greater  
REF  
Serial Data Output (SDO)  
than +FS, the conversion result is clamped to the value  
corresponding to the +FS + 1LSB. For differential input  
voltages below –FS, the conversion result is clamped to  
the value corresponding to –FS – 1LSB.  
The serial data output pin, SDO (Pin 36), provides the  
result of the last conversion as a serial bit stream (MSB  
first) during the data output state. In addition, the SDO  
pin is used as an end of conversion indicator during the  
conversion and sleep states.  
Serial Interface Pins  
When CS (Pin 35) is HIGH, the SDO driver is switched  
to a high impedance state. This allows sharing the serial  
interface with other devices. If CS is LOW during the  
convert or sleep state, SDO will output EOC. If CS is LOW  
duringtheconversionphase, theEOCbitappearsHIGHon  
the SDO pin. Once the conversion is complete, EOC goes  
LOW. The device remains in the sleep state until the first  
rising edge of SCK occurs while CS = LOW.  
TheLTC2442transmitstheconversionresultandreceives  
the start of conversion command through a synchronous  
3- or 4-wire interface. During the conversion and sleep  
states, this interface can be used to access the converter  
status and during the data output state it is used to read  
the conversion result and program the speed, resolution  
and input channel.  
Table 2. LTC2442 Output Data Format  
Differential Input Voltage  
V *  
Bit 31  
EOC  
Bit 30  
DMY  
Bit 29  
SIG  
Bit 28  
MSB  
Bit 27  
Bit 26  
Bit 25  
...  
Bit 0  
IN  
V * ≥ 0.5 • V **  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
1
0
1
0
1
0
1
0
1
IN  
REF  
0.5 • V ** –1LSB  
REF  
0.25 • V **  
REF  
0.25 • V ** –1LSB  
REF  
0
–1LSB  
–0.25 • V **  
REF  
–0.25 • V ** –1LSB  
REF  
–0.5 • V **  
REF  
V * < –0.5 • V **  
0
1
IN  
REF  
+
–
+
–
*The differential input voltage V = SEL – SEL . **The differential reference voltage V = REF – REF .  
IN  
REF  
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Table 3. Channel Selection  
MUX ADDRESS  
CHANNEL SELECTION  
CH2  
SGL  
0
ODD/SIGN  
A2  
0
A1  
0
A0  
0
CH0  
CH1  
CH3  
COM  
+
–
0
0
1
1
0
0
1
1
SEL  
SEL  
SEL  
SEL  
+
–
+
0
0
0
1
SEL  
SEL  
SEL  
–
+
+
0
0
0
0
SEL  
–
0
0
0
1
SEL  
–
1
0
0
0
SEL  
+
–
1
0
0
1
SEL  
SEL  
+
–
1
0
0
0
SEL  
SEL  
+
–
1
0
0
1
SEL  
SEL  
Table 4. Speed/Resolution Selection  
CONVERSION RATE  
OSR3  
OSR2  
OSR1  
OSR0  
TWOX  
RMS  
NOISE  
ENOB  
OSR  
LATENCY  
INTERNAL EXTERNAL  
9MHZ  
Clock  
10.24MHz  
Clock  
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Keep Previous Speed/Resolution  
3.52kHz  
1.76kHz  
879Hz  
4kHz  
2kHz  
23µV  
36µV  
17.7  
20.4  
21.2  
21.6  
22  
64  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
128  
1kHz  
2.1µV  
1.5µV  
1.2µV  
840nV  
630nV  
430nV  
305nV  
220nV  
256  
439Hz  
500Hz  
512  
220Hz  
250Hz  
1024  
2048  
4096  
8192  
16384  
32768  
110Hz  
125Hz  
22.5  
22.9  
23.5  
24  
55Hz  
62.5Hz  
31.25Hz  
15.625Hz  
7.8125Hz  
27.5Hz  
13.73Hz  
6.875Hz  
24.4  
Keep Previous Speed/Resolution  
7.03kHz  
3.52kHz  
1.76kHz  
879Hz  
8kHz  
4kHz  
23µV  
3.6µV  
2.1µV  
1.5µV  
1.2µV  
840nV  
630nV  
430nV  
305nV  
220nV  
17.7  
20.4  
21.2  
21.6  
22  
64  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
1 cycle  
128  
2kHz  
256  
1kHz  
512  
439Hz  
500Hz  
250Hz  
125Hz  
62.5Hz  
31.25Hz  
15.625Hz  
1024  
2048  
4096  
8192  
16384  
32768  
220Hz  
22.5  
22.9  
23.5  
24  
110Hz  
55Hz  
27.5Hz  
13.73Hz  
24.4  
2442f  
13  
LTC2442  
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APPLICATIO S I FOR ATIO  
Chip Select Input (CS)  
If the first three bits shifted into the device are 101, then  
the following five bits select the input channel for the fol-  
lowing conversion (see Tables 3 and 4). The next five bits  
select the speed/resolution and mode 1X (no Latency) 2X  
(doubleoutputratewithoneconversionlatency),seeTable  
4. If these five bits are set to all 0’s, the previous speed  
remains selected for the next conversion. This is useful  
in applications requiring a fixed output rate/resolution but  
need to change the input channel.  
The active LOW chip select, CS (Pin 35), is used to test the  
conversion status and to enable the data output transfer  
as described in the previous sections.  
In addition, the CS signal can be used to trigger a new  
conversion cycle before the entire serial data transfer has  
been completed. The LTC2442 will abort any serial data  
transfer in progress and start a new conversion cycle  
anytime a LOW-to-HIGH transition is detected at the CS  
pin after the converter has entered the data output state.  
When an update operation is initiated the first three bits  
are 101. The following five bits are the channel address.  
The first bit, SGL, determines if the input selection is dif-  
ferential (SGL = 0) or single-ended (SGL = 1). For SGL =  
0, two adjacent channels can be selected to form a dif-  
ferential input. For SGL = 1, one of 4 channels is selected  
as the positive input. The negative input is COM for all  
single ended operations. The next 4-bits (ODD, A2, A1,  
A0) determine which channel is selected and its polarity,  
(see Table 3). In order to remain software compatible with  
LTCs other multi-channel ΔΣ ADCs, A2 and A1 are unused  
and should be set low.  
Serial Data Input (SDI)  
The serial data input (SDI, Pin 33) is used to select the  
speed/resolution and input channel of the LTC2442. SDI is  
programmedbyaserialinputdatastreamunderthecontrol  
of SCK during the data output cycle, see Figure 3.  
Initially, after powering up, the device performs a conver-  
+
–
sion with SEL = CH0, SEL = CH1, OSR = 256 (output rate  
nominally 879Hz), and 1X speedup mode (no Latency).  
Once this first conversion is complete, the device enters  
the sleep state and is ready to output the conversion  
result and receive the serial data input stream program-  
ming the speed/resolution and input channel for the next  
conversion. At the conclusion of each conversion cycle,  
the device enters this state.  
Speed Multiplier Mode  
In addition to selecting the speed/resolution, a speed  
multiplier mode is used to double the output rate while  
maintaining the selected resolution. The last bit of the  
5-bit speed/resolution control word (TWOX, see Table 4)  
determines if the output rate is 1X (no speed increase) or  
2X (double the selected speed).  
In order to change the speed/resolution or input channel,  
the first three bits shifted into the device are 101. This is  
compatible with the programming sequence of all LTC  
multichannel differential input ΔΣ ADCs. If the sequence  
is set to 000 or 100, the following input data is ignored  
(don’t care) and the previously selected speed/resolution  
and channel remain valid for the next conversion. Combi-  
nations other than 101, 100, and 000 of the three control  
bits should be avoided.  
While operating in the 1X mode, the device combines two  
internal conversions for each conversion result in order  
to remove the ADC offset. Every conversion cycle, the  
offset and offset drift are transparently calibrated greatly  
simplifying the user interface. The resulting conversion  
resulthasnolatency.Thefirstconversionfollowinganewly  
2442f  
14  
LTC2442  
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APPLICATIO S I FOR ATIO  
selected speed/resolution and input channel is valid. This  
is identical to the operation of the LTC2440 and LTC2444  
through LTC2449.  
While operating in the 1X mode, if a new input channel  
is selected the multiplexer is switched on the falling edge  
of the 14th SCK (once the complete data input word is  
programmed). The remaining data output sequence time  
can be used to allow the external amplifier to settle.  
While operating in the 2X mode, the device performs a  
running average of the last two conversion results. This  
automatically removes the offset and drift of the device  
while increasing the output rate by 2X. The resolution  
(noise) remains the same. If a new channel is selected,  
the conversion result is valid for all conversions after the  
firstconversion(onecyclelatency).Ifanewspeed/resolu-  
tion is selected, the first conversion result is valid but the  
resolution (noise) is a function of the running average.  
All subsequent conversion results are valid. If the mode  
is changed from either 1X to 2X or 2X to 1X without  
changing the resolution or channel, the first conversion  
result is valid.  
BUSY  
The BUSY output (Pin 2) is used to monitor the state of  
conversion, data output and sleep cycle. While the part is  
converting, the BUSY pin is HIGH. Once the conversion  
is complete, BUSY goes LOW indicating the conversion  
is complete and data out is ready. The part now enters the  
sleep state. BUSY remains LOW while data is shifted out of  
the device and SDI is shifted into the device. It goes HIGH  
at the conclusion of the data input/output cycle indicating  
anewconversionhasbegun. Thisrisingedgemaybeused  
to flag the completion of the data read cycle.  
The 2X mode can also be used to increase the settling  
time of the amplifier between readings. While operating  
in the 2X mode, the multiplexer output (input to the buf-  
fer/amplifier) is switched at the end of each conversion  
cycle. Prior to concluding the data out/in cycle, the analog  
multiplexer output is switched. This occurs at the end of  
the conversion cycle (just prior to the data output cycle)  
for auto calibration. The time required to read the con-  
version enables more settling time for the amplifier. The  
offset/offsetdriftoftheamplifierisautomaticallyremoved  
by the converter’s auto calibration sequence for both the  
1X and 2X speed modes.  
Serial Interface Timing Modes  
TheLTC2442’s3-or4-wireinterfaceisSPIandMICROWIRE  
compatible. This interface offers several flexible modes of  
operation. These include internal/external serial clock, 3-  
or 4-wire I/O, single cycle conversion and autostart. The  
following sections describe each of these serial interface  
timing modes in detail. In all these cases, the converter  
can use the internal oscillator (F = LOW) or an external  
O
oscillator connected to the F pin. Refer to Table 5 for a  
O
summary.  
Table 5. Interface Timing Modes  
Configuration  
SCK Source  
External  
External  
Internal  
Conversion Cycle Control  
Data Output Control  
CS and SCK  
SCK  
Connection and Waveforms  
Figures 4, 5  
External SCK, Single Cycle Conversion  
External SCK, 2-Wire I/O  
CS and SCK  
SCK  
Figure 6  
Internal SCK, Single Cycle Conversion  
CS ↓  
CS ↓  
Figures 7, 8  
Internal SCK, 2-Wire I/O, Continuous  
Conversion  
Internal  
Continuous  
Internal  
Figure 9  
2442f  
15  
LTC2442  
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APPLICATIO S I FOR ATIO  
External Serial Clock, Single Cycle Operation  
(SPI/MICROWIRE Compatible)  
When the device is in the sleep state (EOC = 0), its conver-  
sion result is held in an internal static shift register. The  
device remains in the sleep state until the first rising edge  
of SCK is seen. Data is shifted out the SDO pin on each  
falling edge of SCK. This enables external circuitry to latch  
the output on the rising edge of SCK. EOC can be latched  
on the first rising edge of SCK and the last bit of the con-  
version result can be latched on the 32nd rising edge of  
SCK. On the 32nd falling edge of SCK, the device begins  
a new conversion. SDO goes HIGH (EOC = 1) and BUSY  
goes HIGH indicating a conversion is in progress.  
This timing mode uses an external serial clock to shift out  
theconversionresultandaCSsignaltomonitorandcontrol  
the state of the conversion cycle, see Figure 4.  
The serial clock mode is selected by the EXT pin. To select  
the external serial clock mode, EXT must be tied low.  
The serial data output pin (SDO) is Hi-Z as long as CS is  
HIGH. At any time during the conversion cycle, CS may be  
pulled LOW in order to monitor the state of the converter.  
While CS is pulled LOW, EOC is output to the SDO pin.  
EOC = 1 (BUSY = 1) while a conversion is in progress  
and EOC = 0 (BUSY = 0) if the device is in the sleep state.  
Independent of CS, the device automatically enters the  
sleep state once the conversion is complete.  
At the conclusion of the data cycle, CS may remain LOW  
and EOC monitored as an end-of-conversion interrupt.  
Alternatively, CS may be driven HIGH setting SDO to Hi-Z  
and BUSY monitored for the completion of a conversion.  
4.5V TO 5.5V  
V
TO 15V  
CC  
1µF  
1µF  
21  
29  
+
V
CC  
V
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
REF  
REF  
EXT  
SDI  
33  
1
0.1V TO V  
CC  
SCK  
SDO  
CS  
6
7
4-WIRE  
SPI INTERFACE  
CH0  
CH1  
CH2  
CH3  
COM  
36  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
34  
2
F
O
28  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
0.1µF  
CS  
TEST EOC  
TEST EOC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
32  
SCK  
(EXTERNAL)  
SDI  
1
0
EN  
SGL  
ODD  
0
0
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
EOC “0” SIG MSB  
BIT 0  
LSB  
Hi-Z  
Hi-Z  
SDO  
BUSY  
CONVERSION  
SLEEP  
DATA OUTPUT  
CONVERSION  
2442 F04  
Figure 4. External Serial Clock, Single Cycle Operation  
2442f  
16  
LTC2442  
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APPLICATIO S I FOR ATIO  
As described above, CS may be pulled LOW at any time in  
order to monitor the conversion status on the SDO pin.  
sequence is aborted prior to the 13th rising edge of SCK,  
the new input data is ignored, and the previously selected  
speed/resolutionandchannelareusedforthenextconver-  
sion cycle. This is useful for systems not requiring all 32  
bits of output data, aborting an invalid conversion cycle or  
synchronizing the start of a conversion. If a new channel  
is being programmed, the rising edge of CS must come  
after the 14th falling edge of SCK in order to store the  
data input sequence.  
Typically, CS remains LOW during the data output state.  
However, the data output state may be aborted by pull-  
ing CS HIGH anytime between the fifth falling edge and  
the 32nd falling edge of SCK, see Figure 5. On the rising  
edge of CS, the device aborts the data output state and  
immediately initiates a new conversion. Thirteen serial  
input data bits are required in order to properly program  
the speed/resolution and input channel. If the data output  
4.5V TO 5.5V  
V
TO 15V  
CC  
1µF  
1µF  
21  
29  
+
V
CC  
V
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
REF  
REF  
EXT  
SDI  
33  
0.1V TO V  
CC  
1
SCK  
SDO  
CS  
6
7
4-WIRE  
CH0  
CH1  
CH2  
CH3  
COM  
36  
SPI INTERFACE  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
34  
2
F
O
28  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
CS  
TEST EOC  
1
5
1
2
3
4
5
6
SCK  
(EXTERNAL)  
SDI  
DON'T CARE  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25  
EOC “0” SIG MSB  
DON'T CARE  
DON'T CARE  
Hi-Z  
Hi-Z  
SDO  
BUSY  
SLEEP  
DATA OUTPUT  
DATA OUTPUT  
CONVERSION  
CONVERSION  
CONVERSION  
SLEEP  
2442 F05  
Figure 5. External Serial Clock, Reduced Output Data Length  
2442f  
17  
LTC2442  
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APPLICATIO S I FOR ATIO  
External Serial Clock, 2-Wire I/O  
controller indicating the conversion result is ready. EOC =  
1 (BUSY = 1) while the conversion is in progress and EOC  
= 0 (BUSY = 0) once the conversion enters the sleep state.  
On the falling edge of EOC/BUSY, the conversion result  
is loaded into an internal static shift register. The device  
remains in the sleep state until the first rising edge of SCK.  
Data is shifted out the SDO pin on each falling edge of SCK  
enabling external circuitry to latch data on the rising edge  
of SCK. EOC can be latched on the first rising edge of SCK.  
On the 32nd falling edge of SCK, SDO and BUSY go HIGH  
(EOC = 1) indicating a new conversion has begun.  
This timing mode utilizes a 2-wire serial I/O interface.  
The conversion result is shifted out of the device by an  
externally generated serial clock (SCK) signal, see Figure  
6. CS may be permanently tied to ground, simplifying the  
user interface or isolation barrier. The external serial clock  
mode is selected by tying EXT LOW.  
Since CS is tied LOW, the end-of-conversion (EOC) can  
be continuously monitored at the SDO pin during the  
convert and sleep states. Conversely, BUSY (Pin 2) may  
be used to monitor the status of the conversion cycle.  
EOC or BUSY may be used as an interrupt to an external  
4.5V TO 5.5V  
V
TO 15V  
CC  
1µF  
1µF  
21  
29  
+
V
CC  
V
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
REF  
REF  
EXT  
SDI  
33  
0.1V TO V  
CC  
1
3-WIRE  
SCK  
SDO  
CS  
6
7
SPI INTERFACE  
CH0  
CH1  
CH2  
CH3  
COM  
36  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
34  
2
F
O
28  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
0.1µF  
CS  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
32  
SCK  
(EXTERNAL)  
DON'T CARE  
1
0
EN  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
EOC “0” SIG MSB  
SGL  
ODD  
0
0
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
DON'T CARE  
BIT 0  
SDI  
LSB  
SDO  
BUSY  
CONVERSION  
2442 F06  
DATA OUTPUT  
CONVERSION  
SLEEP  
Figure 6. External Serial Clock, CS = 0 Operation (2-Wire)  
2442f  
18  
LTC2442  
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APPLICATIO S I FOR ATIO  
Internal Serial Clock, Single Cycle Operation  
conversion and goes LOW at the conclusion. It remains  
LOW until the result is read from the device.  
This timing mode uses an internal serial clock to shift out  
theconversionresultandaCSsignaltomonitorandcontrol  
the state of the conversion cycle, see Figure 7.  
When testing EOC, if the conversion is complete (EOC =  
0), the device will exit the sleep state and enter the data  
output state if CS remains LOW. In order to prevent the  
device from exiting the sleep state, CS must be pulled  
HIGH before the first rising edge of SCK. In the internal  
SCK timing mode, SCK goes HIGH and the device begins  
In order to select the internal serial clock timing mode,  
the EXT pin must be tied HIGH.  
The serial data output pin (SDO) is Hi-Z as long as CS is  
HIGH. At any time during the conversion cycle, CS may be  
pulled LOW in order to monitor the state of the converter.  
Once CS is pulled LOW, SCK goes LOW and EOC is output  
to the SDO pin. EOC = 1 while a conversion is in progress  
and EOC = 0 if the device is in the sleep state. Alterna-  
tively, BUSY (Pin 2) may be used to monitor the status  
of the conversion in progress. BUSY is HIGH during the  
outputting data at time t  
after the falling edge of CS  
after EOC goes LOW (if CS is LOW  
EOCtest  
(if EOC = 0) or t  
EOCtest  
during the falling edge of EOC). The value of t  
is  
EOCtest  
, the device  
500ns. If CS is pulled HIGH before time t  
EOCtest  
remains in the sleep state. The conversion result is held  
in the internal static shift register.  
4.5V TO 5.5V  
V
TO 15V  
CC  
1µF  
1µF  
21  
29  
+
V
CC  
V
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
V
REF  
REF  
EXT  
SDI  
CC  
33  
1
0.1V TO V  
CC  
SCK  
SDO  
CS  
4-WIRE  
SPI INTERFACE  
6
7
CH0  
CH1  
CH2  
CH3  
COM  
36  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
34  
2
F
O
28  
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
0.1µF  
<t  
EOC(TEST)  
CS  
SCK  
SDI  
TEST EOC  
TEST EOC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
32  
1
0
EN  
SGL  
ODD  
0
0
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
DON'T CARE  
DON'T CARE  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
EOC “0” SIG MSB  
BIT 0  
LSB  
Hi-Z  
Hi-Z  
SDO  
BUSY  
SLEEP  
DATA OUTPUT  
CONVERSION  
CONVERSION  
2442 F07  
Figure 7. Internal Serial Clock, Single Cycle Operation  
2442f  
19  
LTC2442  
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APPLICATIO S I FOR ATIO  
If CS remains LOW longer than t  
, the first rising  
EOCtest  
CS HIGH anytime between the first and 32nd rising edge  
of SCK, see Figure 8. On the rising edge of CS, the device  
abortsthedataoutputstateandimmediatelyinitiatesanew  
conversion. This is useful for systems not requiring all 32  
bits of output data, aborting an invalid conversion cycle,  
or synchronizing the start of a conversion. Thirteen serial  
input data bits are required in order to properly program  
the speed/resolution and input channel. If the data output  
sequence is aborted prior to the 13th rising edge of SCK,  
the new input data is ignored, and the previously selected  
speed/resolution and channel are used for the next con-  
version cycle. If a new channel is being programmed, the  
rising edge of CS must come after the 14th falling edge of  
SCK in order to store the data input sequence.  
edge of SCK will occur and the conversion result is serially  
shifted out of the SDO pin. The data output cycle begins  
on this first rising edge of SCK and concludes after the  
32nd rising edge. Data is shifted out the SDO pin on each  
falling edge of SCK. The internally generated serial clock  
is output to the SCK pin. This signal may be used to shift  
the conversion result into external circuitry. EOC can be  
latched on the first rising edge of SCK and the last bit of  
the conversion result on the 32nd rising edge of SCK.  
After the 32nd rising edge, SDO goes HIGH (EOC = 1),  
SCK stays HIGH and a new conversion starts.  
Typically, CS remains LOW during the data output state.  
However, the data output state may be aborted by pulling  
4.5V TO 5.5V  
V
CC  
TO 15V  
1µF  
1µF  
21  
29  
+
V
V
CC  
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
REF  
REF  
V
CC  
EXT  
SDI  
33  
1
0.1V TO V  
CC  
SCK  
SDO  
CS  
6
7
4-WIRE  
SPI INTERFACE  
CH0  
CH1  
CH2  
CH3  
COM  
36  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
34  
2
F
28  
O
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
0.1µF  
CS  
1
1
2
0
3
4
5
6
0
7
8
9
10  
11  
12  
13  
14  
15  
32  
SCK  
DON'T CARE  
EN  
SGL  
ODD  
0
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
DON'T CARE  
SDI  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
BIT 0  
EOC  
“0”  
SIG  
MSB  
SDO  
BUSY  
DATA OUTPUT  
CONVERSION  
2442 F08  
CONVERSION  
SLEEP  
Figure 8. Internal Serial Clock, Reduced Data Output Length  
2442f  
20  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
device has entered the sleep state. The part remains in  
the sleep state a minimum amount of time (≈500ns) then  
immediately begins outputting data. The data output cycle  
begins on the first rising edge of SCK and ends after the  
32nd rising edge. Data is shifted out the SDO pin on each  
falling edge of SCK. The internally generated serial clock  
is output to the SCK pin. This signal may be used to shift  
the conversion result into external circuitry. EOC can be  
latched on the first rising edge of SCK and the last bit of  
the conversion result can be latched on the 32nd rising  
edge of SCK. After the 32nd rising edge, SDO goes HIGH  
(EOC = 1) indicating a new conversion is in progress. SCK  
remains HIGH during the conversion.  
Internal Serial Clock, 3-Wire I/O, Continuous  
Conversion  
This timing mode uses a 3-wire, all output (SCK and SDO)  
interface. Theconversionresultisshiftedoutofthedevice  
by an internally generated serial clock (SCK) signal, see  
Figure9.CSmaybepermanentlytiedtoground,simplifying  
the user interface or isolation barrier. The internal serial  
clock mode is selected by tying EXT HIGH.  
During the conversion, the SCK and the serial data output  
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the  
conversion is complete, SCK, BUSY and SDO go LOW  
(EOC = 0) indicating the conversion has finished and the  
4.5V TO 5.5V  
V
TO 15V  
CC  
1µF  
1µF  
21  
29  
+
V
V
CC  
LTC2442  
30  
31  
3
+
–
REFERENCE  
VOLTAGE  
REF  
REF  
V
CC  
EXT  
SDI  
33  
1
0.1V TO V  
CC  
3-WIRE  
SPI INTERFACE  
SCK  
SDO  
CS  
6
7
CH0  
CH1  
CH2  
CH3  
COM  
36  
35  
8
ANALOG  
INPUTS  
9
= EXTERNAL OSCILLATOR  
34  
2
F
O
28  
= INTERNAL OSCILLATOR  
(SIMULTANEOUS 50Hz/60Hz  
REJECTION AT 6.9Hz OUTPUT RATE  
BUSY  
12  
13  
11  
OUTA  
–INA  
27  
25  
MUXOUTA  
+INA  
ADCINA  
26  
19  
24  
0.1µF  
MUXOUTB  
+INB  
17  
18  
10  
OUTB  
–INB  
–
–15V TO GND  
V
4, 5, 32  
GND  
ADCINB  
0.1µF  
CS  
1
1
2
0
3
4
5
6
0
7
8
9
10  
11  
12  
13  
14  
15  
32  
SCK  
DON'T CARE  
EN  
SGL  
ODD  
0
A0  
OSR3 OSR2 OSR1 OSR0 TWOX  
DON'T CARE  
SDI  
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19  
BIT 0  
EOC  
“0”  
SIG  
MSB  
SDO  
BUSY  
DATA OUTPUT  
CONVERSION  
2442 F09  
CONVERSION  
SLEEP  
Figure 9. Internal Serial Clock, Continuous Operation  
2442f  
21  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
Normal Mode Rejection and Antialiasing  
Table 6. OSR vs Notch Frequency (f ) (with Internal Oscillator  
N
Running at 9MHz)  
One of the advantages delta-sigma ADCs offer over  
conventional ADCs is on-chip digital filtering. Combined  
with a large oversampling ratio, the LTC2442 significantly  
simplifies antialiasing filter requirements.  
OSR  
NOTCH (f )  
N
64  
28.13kHz  
14.06kHz  
7.03kHz  
3.52kHz  
1.76kHz  
879Hz  
128  
256  
The LTC2442’s speed/resolution is determined by the  
oversample ratio (OSR) of the on-chip digital filter. The  
OSR ranges from 64 for 3.5kHz output rate to 32,768 for  
6.9Hz (in No Latency mode) output rate. The value of OSR  
512  
1024  
2048  
4096  
439Hz  
and the sample rate f determine the filter characteristics  
S
8192  
220Hz  
of the device. The first NULL of the digital filter is at f  
N
16384  
32768*  
110Hz  
and multiples of f where f = f /OSR, see Figure 10 and  
N
N
S
55Hz  
Table 6. The rejection at the frequency f 14% is better  
N
* Simultaneous 50/60Hz rejection  
than 80dB, see Figure 11.  
0
–80  
–90  
4
SINC ENVELOPE  
–20  
–40  
–100  
–110  
–120  
–130  
–140  
–60  
–80  
–100  
–120  
–140  
60  
120  
240  
57 59  
0
180  
47 49 51 53 55  
61 63  
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)  
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)  
2442 F10  
2442 F11  
Figure 10. Normal Mode Rejection (Internal Oscillator)  
Figure 11. Normal Mode Rejection (Internal Oscillator)  
2442f  
22  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
If F is grounded, f is set by the on-chip oscillator at  
1.8MHz 5% (over supply and temperature variations). At  
an OSR of 32,768, the first NULL is at f = 55Hz and the  
no latency output rate is f /8 = 6.9Hz. At the maximum  
OSR,thenoiseperformanceofthedeviceis220nV  
clock applied to F . Combining a large OSR with a reduced  
O
O
S
sample rate leads to notch frequencies f near DC while  
N
maintaining simple antialiasing requirements. A 100kHz  
N
clock applied to F results in a NULL at 0.6Hz plus all  
N
O
with  
harmonics up to 20kHz, see Figure 13. This is useful in  
applications requiring digitalization of the DC component  
of a noisy input signal and eliminates the need of placing  
a 0.6Hz filter in front of the ADC.  
RMS  
better than 80dB rejection of 50Hz 2% and 60Hz 2%.  
Since the OSR is large (32,768) the wide band rejection  
is extremely large and the antialiasing requirements are  
simple. The first multiple of f occurs at 55Hz • 32,768 =  
S
Anexternaloscillatoroperatingfrom100kHzto20MHzcan  
be implemented using the LTC1799 (resistor set SOT-23  
oscillator), see Figure 14. By floating pin 4 (DIV) of the  
LTC1799, the output oscillator frequency is:  
1.8MHz, see Figure 12.  
The first NULL becomes f = 7.03kHz with an OSR of 256  
N
(anoutputrateof879Hz)andF grounded.WhiletheNULL  
O
has shifted, the sample rate remains constant. As a result  
of constant modulator sampling rate, the linearity, offset  
and full-scale performance remains unchanged as does  
⎛
⎞
10k  
fOSC =10MHz •  
⎜
⎟
10 •R  
⎝
⎠
SET  
the first multiple of f .  
S
The normal mode rejection characteristic shown in  
Figure 13isachievedbyapplyingtheoutputoftheLTC1799  
(with R = 100k) to the F pin on the LTC2442 with OSR  
The sample rate f and NULL f , may also be adjusted by  
S
N
driving the F pin with an external oscillator. The sample  
O
SET  
= 32,768.  
O
rate is f = f  
/5, where f is the frequency of the  
S
EOSC  
EOSC  
0
–20  
–40  
–60  
–80  
0
–20  
–40  
–60  
1.8MHz  
–80  
–100  
–120  
–140  
–100  
–120  
–140  
REJECTION > 120dB  
1000000  
2000000  
0
2
4
6
8
10  
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)  
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)  
2442 F12  
2442 F13  
Figure 12. Normal Mode Rejection (Internal Oscillator)  
Figure 13. Normal Mode Rejection (Internal Oscillator at 90kHz)  
2442f  
23  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
Input Bandwidth and Frequency Rejection  
First Notch Frequency  
4
4
The combined effect of the internal SINC digital filter and  
ThisisthefirstnotchintheSINC portionofthedigitalfilter  
anddependsonthefoclockfrequencyandtheoversample  
ratio. Rejection at this frequency and its multiples (up to  
the modulator sample rate of 1.8MHz) exceeds 120dB.  
This is 8 times the maximum conversion rate.  
the digital and analog autocalibration circuits determines  
theLTC2442inputbandwidthandrejectioncharacteristics.  
The digital filter’s response can be adjusted by setting the  
oversample ratio (OSR) through the SPI interface or by  
supplying an external conversion clock to the f pin.  
O
Effective Noise Bandwidth  
Table 7 lists the properties of the LTC2442 with various  
combinations of oversample ratio and clock frequency.  
Understanding these properties is the key to fine tuning  
the characteristics of the LTC2442 to the application.  
TheLTC2442hasextremelygoodinputnoiserejectionfrom  
the first notch frequency all the way out to the modulator  
sample rate (typically 1.8MHz). Effective noise bandwidth  
is a measure of how the ADC will reject wideband input  
noise up to the modulator sample rate  
Maximum Conversion Rate  
The maximum conversion rate is the fastest possible rate  
at which conversions can be performed.  
Table 7  
Over-  
sample  
Ratio  
*RMS  
Noise  
ENOB  
= 5V)  
Maximum  
Conversion Rate  
First Notch  
Frequency  
Effective  
Noise BW  
–3dB  
point (Hz)  
(V  
REF  
Internal  
External  
Internal  
External  
Internal  
External  
Internal  
External  
(OSR)  
9MHz clock  
3515.6  
1757.8  
878.9  
439.5  
219.7  
109.9  
54.9  
f
0
9MHz clock  
28125  
14062.5  
7031.3  
3515.6  
1757.8  
878.9  
f
0
9MHz clock  
3148  
1574  
787  
f
0
9MHz clock  
1696  
848  
f
0
64  
128  
23µV  
3.6µV  
2.1µV  
1.5µV  
1.2µV  
840nV  
630nV  
430nV  
305nV  
220nV  
17.7  
f /2560  
f /320  
f /5710  
f /5310  
0
0
0
0
20.4  
21.2  
21.6  
22  
f /5120  
0
f /640  
0
f /2860  
0
f /10600  
0
256  
f /10240  
0
f /1280  
0
f /1140  
0
424  
f /21200  
0
512  
f /20480  
0
f /2560  
0
394  
f /2280  
0
212  
f /42500  
0
1024  
2048  
4096  
8192  
16384  
32768  
f /40960  
0
f /5120  
0
197  
f /4570  
0
106  
f /84900  
0
22.5  
22.4  
23.5  
24  
f /81920  
0
f /1020  
0
98.4  
f /9140  
0
53  
f /170000  
0
f /163840  
0
439.5  
f /2050  
0
49.2  
f /18300  
0
26.5  
13.2  
6.6  
f /340000  
0
27.5  
f /327680  
0
219.7  
f /4100  
0
24.6  
f /36600  
0
f /679000  
0
13.7  
f /655360  
0
109.9  
f /8190  
0
12.4  
f /73100  
0
f /1358000  
0
24.4  
6.9  
f /1310720  
0
54.9  
f /16380  
0
6.2  
f /146300  
0
3.3  
f /2717000  
0
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 64 include effects  
from internal modulator quantization noise.  
4.5V TO 5.5V  
1µF  
29  
2
V
BUSY  
CC  
LTC2442  
REF  
LTC1799  
OUT  
R
SET  
30  
31  
6
34  
1
+
+
REFERENCE  
VOLTAGE  
F
O
V
–
0.1µF  
REF  
SCK  
SDO  
CS  
0.1V TO V  
CC  
36  
35  
3-WIRE  
ANALOG INPUT  
CH0  
GND  
SET  
SPI INTERFACE  
–0.5V  
TO  
REF  
REF  
0.5V  
7
CH1  
•
•
•
4,5,32  
3
EXT  
GND  
DIV  
NC  
2442 F14  
Figure 14. Simple External Clock Source  
2442f  
24  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
Optimizing Linearity  
thelinearityimprovesto19-Bits(2ppm).Ifthereferenceis  
reduced to 4.096V and the input common mode is V /2  
REF  
Whiletheintegratedop-amphasrail-to-railinputrange, in  
order to achieve parts-per-million linearity performance,  
the input range and op-amp supply voltages must be con-  
sidered. Input levels within 1.25V of the upper op-amp rail  
(2.048V) the linearity performance improves to better  
+
–
than 1ppm with V tied to V and V tied to ground, see  
CC  
Figure16. Inputsignalsneargroundrequireabout100mV  
headroomontheop-amppowersupplyinordertoachieve  
1ppm INL, see Figure 17. Optimal linearity is achieved  
by driving the input differentially. As seen in Figure 18, a  
single ended input (the negative input is tied to ground)  
yields 18-bits ( 4ppm) linearity performance. In this case  
+
(V ) begin to degrade the performance. For example (see  
+
Figure 15) while operating with V = 5.1V and absolute  
input voltages (V CM + V DIFF) up to 3.75V (V CM =  
IN  
IN  
IN  
2.5Vand–2.5V<V DIFF<2.5V), thelinearityisdegraded  
IN  
+
to about 17-bits. Once V is increased to 5.25V or greater  
–
V is 100mV below ground.  
10  
4
V
V
V
= 5V  
V
V
V
= 4.096V  
REF  
CC  
REF  
= 5V  
= 5V  
8
6
CC  
INCM  
3
2
= 2.5V  
= 2.048V  
INCM  
4
+
–
V
> 5.25, V = 0, –1, –2  
1
2
0
0
+
–
V
= 5V, V = 0V  
–2  
–4  
–6  
–8  
–10  
–1  
–2  
–3  
–4  
+
–
V
= 5.1V, V = 0  
+
–
V
= 5, V = 0  
+
–
V
= 5, V = –2  
0.5  
1
1.5  
2
2.5  
–2.048 –1.536 –1.024 –0.512  
0
0.512  
1.024 1.536 2.048  
–2.5 –2 –1.5 –1 –0.5  
0
DIFFERENTIAL V (V)  
DIFFERENTIAL V (V)  
IN  
IN  
2442 F15  
2442 F16  
Figure 16. Linearity vs V  
Figure 15. INL vs Op-Amp Supply Voltage  
IN  
5
4
2
V
V
V
V
V
= 5V  
= 5V  
INCM  
= 5V  
= –100mV  
V
V
V
V
V
V
= 5V  
= 5V  
IN  
= 0V  
= 5V  
= –100mV  
CC  
REF  
CC  
REF  
1.5  
1
+
= 0.625V  
= V  
IN  
+
–
3
–
IN  
+
2
–
0.5  
1
0
0
–1  
–2  
–3  
–4  
–5  
–0.5  
–1  
–1.5  
–2  
–0.75  
–0.25  
0.75  
–1.25  
1.25  
0.25  
0
0.5  
1
1.5  
2
2.5  
+
–
DIFFERENTIAL INPUT (V)  
SINGLE ENDED SEL , SEL = 0V FIXED  
2442 F17  
2442 F18  
Figure 17. Linearity Near Ground  
Figure 18. Single-Ended Linearity  
2442f  
25  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
Input Bias Current  
The LTC2442 breaks new ground in high impedance input  
ΔΣ ADCs. The input buffer is optimized to make driving  
the ADC as easy as possible, while overcoming many of  
the limitations typical of integrated buffers.  
The 10nA typical bias current of the buffers results in less  
than 1ppm (5µV) error for source resistance imbalances  
of less than 500Ω. Matching the resistance at the inputs  
cancels much of the error due to amplifier bias current.  
For source resistances up to 50k, 1% resistors are ad-  
equate.Figure20showsproperinputresistancematching  
for a precision voltage divider on the CH2-3 inputs. The  
resistance seen by CH2 is the parallel combination of 30k  
and 10k or 7.5k. A 1%, 7.5k resistor at CH3 balances the  
resistance of the divider output.  
Convenient +5V to –5V/+9V DC-DC Converter  
If either of the signal inputs must include ground and  
V , then the amplifier will require both a positive supply  
CC  
greater than the maximum input voltage and a negative  
supply. Figure 19 shows how to derive both –5V and +9V  
from a single 5V supply using an LTC1983, allowing the  
ADC inputs to extend as much as 300mV below ground  
While the two input buffers will have slightly different  
bias currents, the autozero process applies the bias cur-  
rent from each buffer to both of the inputs for half of the  
conversion time, so the offset is equal to the average  
of the two bias currents multiplied by the mismatch in  
source resistance.  
and above V . For inputs that include ground but do  
CC  
not go within 1.5V of V , then C4, C5, C6 and D1 can  
CC  
be eliminated and the amplifier positive supply can be  
connected to V .  
CC  
5V  
LTC1983ES6-5  
1
6
3
2
5
4
V
V
–5V  
OUT  
CC  
SHDN  
GND  
C2  
4.7µF  
C1  
4.7µF  
+
–
C
C
C3  
2.2µF  
C4  
2.2µF  
C5  
2.2µF  
D1  
BAT54S  
9V  
C6  
4.7µF  
2442 F19  
Figure 19. LTC1983 with Another Charge  
Pump Stacked onto V to Give 9V  
CC  
2442f  
26  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
Low Power Operation  
instrumentation amplifier or simple op-amp level shift  
circuit. Rather than shift the analog input, the LTC2442  
can run on 2.5V supplies so that ground is centered in  
the input range. This is equivalent to a perfect analog  
level shift with no degradation in accuracy. The digital  
signals are shifted from 0 to 5V logic to 2.5V logic by a  
very inexpensive 74HC4053 analog switch and the data  
from the LTC2442 is shifted back to 0 to 5V logic by a  
MMBT3904 transistor.  
The integrated buffers have a supply current of 1mA total,  
greatly reducing the total power consumption when the  
ADC is operated at a low duty cycle. The typical approach  
to driving a ΔΣ ADC is to use a high bandwidth ampli-  
fier that settles very quickly in response to the sampling  
process at the ADC input. The LTC2442 approach is to use  
an accurate, low bandwidth amplifier that requires a load  
capacitor for compensation. This capacitor also serves as  
a charge reservoir during the sampling process, so the  
disturbance at the ADC input is minimal. The amplifier  
only supplies the average sampling current that the ADC  
draws, which is on the order of 50µA.  
Onbothinputs,precisionresistornetworksscaletheinput  
signal from 10V to 2.5V. CH0-1 is driven truly differen-  
tially for maximum linearity, typically better than 3ppm,  
however3resistorsandanLTC2050HVautozeroamplifier  
arerequired.The8.88kΩoutputresistorbalancestheoffset  
associatedwiththeLTC2442’sbiascurrent.Theresistance  
seen by CH0 is 4.44k and the offset at CH0 is also inverted  
and appears at the output of the LTC2050HV.  
Scaling for Higher Input Voltages  
TheLTC2442isideallysuitedforapplicationswithlow-level,  
differential signal with a common mode approximately  
equal to mid-supply, such as strain gages and silicon  
micromachinedsensors.Otherapplicationsrequirescaling  
a high voltage signal to the range of the ADC.  
CH2toCH3isdrivensingle-ended,withCH3tiedtoground.  
Thisdegradeslinearityslightly,butitiseasiertoimplement  
than a true differential drive. In this case the resistance at  
CH3 should be equal to the resistance at CH2 or 7.5k. This  
circuit is also suitable for signals that are always positive,  
with the LTC2442 operating on a single 5V supply.  
Figure 20 shows how to properly scale a bipolar, ground-  
referred input voltage to drive the LTC2442. First, the  
input must be level shifted so that it never exceeds the  
LTC2442 supply rails. This is commonly done with an  
2442f  
27  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
+
REF  
2
6
V
IN1  
5V  
IN  
OUT  
LT1236N  
U3  
4.7k  
C15  
5
GND  
TRIM  
1k  
R20  
0.1  
C13  
0.1  
C8  
4
–2.5V  
2.5V  
5V  
29  
21  
+
R1  
40k  
5k  
R3  
5k  
R4  
V
V
CC  
+
REF  
–2.5V  
30  
35  
+
REF  
REF  
CS  
5V  
31  
6
1
–
LTC2442  
U1  
SCK  
SD0  
6
36  
33  
3
4
R5  
8.88k  
CH0  
+
1
7
CH1  
SDI  
U2  
8
9
2
CH2  
BUSY  
–
5
34  
3
2
CH3  
F
O
28  
LTC2050HV  
–5V  
–2.5V  
COM  
ADCINB  
ADCINA  
OUTA  
–INA  
OUTB  
–INB  
EXT  
10  
11  
12  
13  
17  
18  
27  
26  
MUOUTA  
MUXOUTB  
V
IN2  
30k  
R6  
R9  
10k  
R10  
7.5k  
C14  
0.1k  
C10  
0.1k  
25  
19  
+INA  
+INB  
–
GND GND GND  
32  
V
4
5
24  
74HC4053  
U4  
–5V  
0.1  
C9  
–2.5V  
12  
13  
2
14  
15  
4
0.1  
–2.5V  
2.5V  
X0  
X1  
Y0  
Y1  
Z0  
X
Y
Z
C17  
5k  
R21  
1
5V  
5
SDO  
3
Z1  
1.8k  
R22  
6
MMBT3904  
INH  
11  
10  
9
A
B
C
V
SDI  
CS  
5V  
CC  
V
–2.5  
EE  
GND  
SCK  
Figure 20. Scaling Inputs for 10V Range  
2442f  
28  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
nd  
Details of the Conversion and Autozero Process  
32 falling clock edge. Halfway through the conversion  
(approximately 73ms later) the multiplexer switches the  
CH0 input to +INB and the CH1 input to +INA. The digital  
filter subtracts the two half-conversions, which removes  
the offset of the amplifiers and converter.  
The LTC2442 performs automatic offset cancellation for  
each conversion. This is accomplished by taking the aver-  
age of two “half-conversions” with the inputs applied in  
opposite polarity. Figure 21 shows a conversion on CH0 to  
CH1 differential at OSR of 32768, in 1x mode. This chan-  
nel is selected by sending the appropriate configuration  
word to the LTC2442 through the SPI interface. On the  
At the end of a conversion, the multiplexer assumes that  
the next conversion will be on the same channel and  
switches back to the opposite polarity on the channel just  
converted. This gives extra settling time when convert-  
ing on one channel continuously. If a different channel is  
th  
13 falling clock edge, the CH0 input is applied to +INA  
through the multiplexer and CH1 is connected to +INB.  
The outputs of the amplifiers slew during the remainder  
of the data I/O state and the conversion begins on the  
th  
programmed, the multiplexer will switch again on the 13  
falling clock edge.  
2V/DIV  
5V/DIV  
OUTB  
OUTA  
BUSY  
SCK  
CS  
20ms/DIV  
Figure 21. Amplifier Outputs and CS, SCK, BUSY During a Conversion  
on CH0-1, OSR32768. V = 2.5V, V = 2.5V  
INDIFF  
CM  
2442f  
29  
LTC2442  
U
W U U  
APPLICATIO S I FOR ATIO  
The amplifiers take approximately 50µs to settle for a  
full-scale input voltage. This does not affect accuracy in  
either 2x mode or 1x mode for OSR values between 256  
to 32768. However, the amplifier settling time will cause  
a gain error in 1x mode for OSR values between 64 to  
256. This is because the mid-conversion slew time is a  
significant portion of the total conversion time. Figure 22  
shows the details of a conversion in 1x mode, OSR128,  
beginslewingandhavereachedthecorrectvoltagebefore  
the conversion begins. Midway through the conversion,  
the multiplexer reverses the inputs. Figure 23 shows  
operation in 2x mode. After the first half-conversion  
is done, the multiplexer reverses. Waiting 50µs before  
beginning the next half-conversion allows the amplifiers  
to settle fully. 2x mode is recommended for OSR values  
between 64 and 128 because the amplifiers have time to  
settle between half conversions. If only the 1x data rate  
is required, ignore every other sample.  
with a full-scale input voltage applied (V = 2.5V, V  
=
IN  
CM  
2.5V). The previously selected channel had both inputs  
th  
grounded. On the 13 falling clock edge, the amplifiers  
1V/DIV  
5V/DIV  
OUTB  
BUSY  
SCK  
CS  
200µs/DIV  
Figure 22. Details of Conversion in 1x Mode, OSR128 (OUTA and OUTB Superimposed)  
1V/DIV  
OUTB  
BUSY  
SCK  
CS  
5V/DIV  
200µs/DIV  
Figure 23. Details of Conversion in 2x Mode, OSR128 (OUTA and OUTB Superimposed)  
2442f  
30  
LTC2442  
U
PACKAGE DESCRIPTIO  
G Package  
36-Lead Plastic SSOP (5.3mm)  
(Reference LTC DWG # 05-08-1640)  
12.50 – 13.10*  
(.492 – .516)  
1.25 0.12  
5.3 – 5.7  
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19  
7.8 – 8.2  
7.40 – 8.20  
(.291 – .323)  
0.42 0.03  
0.65 BSC  
5
7
8
RECOMMENDED SOLDER PAD LAYOUT  
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18  
2.0  
(.079)  
MAX  
5.00 – 5.60**  
(.197 – .221)  
0° – 8°  
0.65  
(.0256)  
BSC  
0.09 – 0.25  
(.0035 – .010)  
0.55 – 0.95  
(.022 – .037)  
0.05  
0.22 – 0.38  
(.009 – .015)  
TYP  
(.002)  
NOTE:  
MIN  
1. CONTROLLING DIMENSION: MILLIMETERS  
G36 SSOP 0204  
MILLIMETERS  
2. DIMENSIONS ARE IN  
(INCHES)  
3. DRAWING NOT TO SCALE  
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED .152mm (.006") PER SIDE  
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD  
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE  
2442f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
31  
LTC2442  
U
TYPICAL APPLICATIO  
Scaling Inputs for 10V Range  
+
REF  
2
6
5
V
IN1  
5V  
IN  
OUT  
LT1236N  
U3  
4.7k  
C15  
GND  
TRIM  
1k  
R20  
0.1  
C13  
0.1  
C8  
4
–2.5V  
2.5V  
5V  
29  
21  
+
R1  
40k  
5k  
R3  
5k  
R4  
V
V
CC  
+
REF  
–2.5V  
30  
35  
+
REF  
REF  
CS  
5V  
31  
6
1
–
LTC2442  
U1  
SCK  
SD0  
6
36  
33  
3
4
R5  
8.88k  
CH0  
+
1
5
7
CH1  
SDI  
U2  
8
9
2
CH2  
BUSY  
–
34  
3
2
CH3  
F
O
28  
LTC2050HV  
–5V  
–2.5V  
COM  
ADCINB  
ADCINA  
OUTA  
–INA  
OUTB  
–INB  
EXT  
10  
11  
12  
13  
17  
18  
27  
26  
MUOUTA  
MUXOUTB  
V
IN2  
30k  
R6  
R9  
10k  
R10  
7.5k  
C14  
0.1k  
C10  
0.1k  
25  
19  
+INA  
+INB  
–
GND GND GND  
32  
V
4
5
24  
74HC4053  
U4  
–5V  
0.1  
C9  
–2.5V  
12  
13  
2
14  
15  
4
0.1  
–2.5V  
2.5V  
X0  
X1  
Y0  
Y1  
Z0  
X
Y
Z
C17  
5k  
R21  
1
5V  
5
SDO  
3
Z1  
1.8k  
R22  
6
MMBT3904  
INH  
11  
10  
9
A
B
C
V
SDI  
CS  
5V  
CC  
V
–2.5V  
EE  
GND  
SCK  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
80µA Supply Current, 0.5°C Initial Accuracy  
Precise Charge, Balanced Switching, Low Power  
LT1025  
Micropower Thermocouple Cold Junction Compensator  
LTC1043  
Dual Precision Instrumentation Switched Capacitor Building  
Block  
LTC2050  
LT1236A-5  
LT1461  
Precision Chopper Stabilized Op Amp  
Precision Bandgap Reference, 5V  
Micropower Series Reference, 2.5V  
Ultraprecise 16-Bit SoftSpanTM DAC  
Resistor Set SOT-23 Oscillator  
100mA Charge Pump  
No External Components 3µV Offset, 1.5µV Noise  
P-P  
0.05% Max, 5ppm/°C Drift  
0.04% Max, 3ppm/°C Max Drift  
Six Programmable Output Ranges  
Single Resistor Frequency Set  
5V to Regulated –5V Conversion  
LT1592  
LTC1799  
LTC1983  
LTC2053  
LTC2440  
Rail-to-Rail Instrumentation Amplifier  
10µV Offset with 50nV/°C Drift, 2.5µV Noise 0.01Hz to 10Hz  
P-P  
1-Channel, Differential Input, High Speed/Low Noise,  
24-Bit, No Latency ΔΣ ADC  
2µV  
Noise at 880Hz, 200nV  
Noise at 6.9Hz,  
RMS  
RMS  
0.0005% INL, Up to 3.5kHz Output Rate  
2442f  
LT 1105 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
32  
●
●
© LINEAR TECHNOLOGY CORPORATION 2005  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  

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