LTC2444IUHF [Linear]
24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution; 24位高速8位/ 16通道ADC,带有可选速度/分辨率型号: | LTC2444IUHF |
厂家: | Linear |
描述: | 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution |
文件: | 总28页 (文件大小:258K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2444/LTC2445/
LTC2448/LTC2449
24-Bit High Speed
8-/16-Channel ∆Σ ADCs with
Selectable Speed/Resolution
U
FEATURES
DESCRIPTIO
The LTC®2444/LTC2445/LTC2448/LTC2449 are 8-/16-
channel (4-/8-differential) high speed 24-bit No Latency
∆ΣTM ADCs. They use a proprietary delta-sigma architec-
ture enabling variable speed/resolution. Through a simple
4-wire serial interface, ten speed/resolution combinations
6.9Hz/280nVRMS to 3.5kHz/25µVRMS (4kHz with external
oscillator) can be selected with no latency between con-
version results or shift in DC accuracy (offset, full-scale,
linearity, drift). Additionally, a 2X speed mode can be
selected enabling output rates up to 7kHz (8kHz if an
external oscillator is used) with one cycle latency.
■
Up to 8 Differential or 16 Single-Ended Input
Channels
■
Up to 8kHz Output Rate
■
Up to 4kHz Multiplexing Rate
■
Selectable Speed/Resolution
■
2µVRMS Noise at 1.76kHz Output Rate
■
200nVRMS Noise at 13.8Hz Output Rate with
Simultaneous 50/60Hz Rejection
■
Guaranteed Modulator Stability and Lock-Up
Immunity for any Input and Reference Conditions
■
0.0005% INL, No Missing Codes
■
Autosleep Enables 20µA Operation at 6.9Hz
■
<5µV Offset (4.5V < VCC < 5.5V, –40°C to 85°C)
Any combination of single-ended or differential inputs can
beselectedwithacommonmodeinputrangefromground
to VCC, independent of VREF. While operating in the 1X
speed mode the first conversion following a new speed,
resolution, or channel selection is valid. Since there is no
settling time between conversions, all 8 differential chan-
nels can be scanned at a rate of 500Hz. At the conclusion
of each conversion, the converter is internally reset elimi-
nating any memory effects between successive conver-
sions and assuring stability of the high order delta-sigma
modulator.
■
Differential Input and Differential Reference with
GND to VCC Common Mode Range
■
No Latency Mode, Each Conversion is Accurate Even
After a New Channel is Selected
■
Internal Oscillator—No External Components
■
LTC2445/LTC2449 Include MUXOUT/ADCIN for
External Buffering or Gain
■
Tiny QFN 5mm xU7mm Package
APPLICATIO S
■
High Speed Multiplexing
■
Weight Scales
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
■
Auto Ranging 6-Digit DVMs
■
Direct Temperature Measurement
■
High Speed Data Acquisition
U
TYPICAL APPLICATIO
LTC2444/LTC2448
Simple 24-Bit Variable Speed Data Acquisition System
Speed vs RMS Noise
4.5V TO 5.5V
100
10
1
V
V
V
= 5V
CC
= 5V
IN
REF
1µF
+
–
= V = 0V
IN
+
REF
V
2X SPEED MODE
CC
CH0
CH1
= EXTERNAL OSCILLATOR
NO LATENCY MODE
= INTERNAL OSCILLATOR
F
O
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE)
•
•
•
2.8µV AT 880Hz
CH7
CH8
SDI
SCK
SDO
CS
16-CHANNEL
MUX
VARIABLE SPEED/
RESOLUTION
DIFFERENTIAL
24-BIT ∆Σ ADC
280nV AT 6.9Hz
(50/60Hz REJECTION)
+
–
4-WIRE
SPI INTERFACE
THERMOCOUPLE
•
•
•
CH15
COM
0.1
–
REF
1
10
100
1000
10000
CONVERSION RATE (Hz)
GND
LTC2448
2440 TA02
2444 TA01
sn2444589 2444589fs
1
LTC2444/LTC2445/
LTC2448/LTC2449
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) to GND.......................–0.3V to 6V
Analog Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
Operating Temperature Range
LTC2444C/LTC2445C/
LTC2448C/LTC2449C .............................. 0°C to 70°C
LTC2444I/LTC2445I/
to GND.................................... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
LTC2448I/LTC2449I ........................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
38 37 36 35 34 33 32
38 37 36 35 34 33 32
LTC2445CUHF
LTC2445IUHF
LTC2444CUHF
LTC2444IUHF
GND
BUSY
EXT
1
2
3
4
5
6
7
8
9
31 GND
GND
BUSY
EXT
1
2
3
4
5
6
7
8
9
31 GND
–
–
30 REF
30 REF
+
+
REF
29
28
REF
29
28
GND
GND
GND
COM
NC
V
CC
GND
GND
GND
COM
NC
V
CC
27 MUXOUTN
26 ADCINN
25 ADCINP
24 MUXOUTP
23 NC
27 NC
26 NC
25 NC
24 NC
23 NC
CH0
CH0
QFN PART MARKING*
2444
QFN PART MARKING*
2445
CH1 10
NC 11
NC 12
22 CH7
CH1 10
NC 11
NC 12
22 CH7
21 CH6
21 CH6
20
NC
20
NC
13 14 15 16 17 18 19
UHF PACKAGE
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
TJMAX = 125°C, θJA = 34°C/W
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
38 37 36 35 34 33 32
38 37 36 35 34 33 32
LTC2448CUHF
LTC2448IUHF
GND
BUSY
EXT
1
2
3
4
5
6
7
8
9
31 GND
LTC2449CUHF
LTC2449IUHF
GND
BUSY
EXT
1
2
3
4
5
6
7
8
9
31 GND
–
–
30 REF
30 REF
+
+
REF
29
28
REF
29
28
GND
GND
GND
COM
CH0
V
CC
GND
GND
GND
COM
CH0
V
CC
27 NC
26 NC
25 NC
24 NC
27 MUXOUTN
26 ADCINN
25 ADCINP
24 MUXOUTP
23 CH15
CH1
23 CH15
22 CH14
21 CH13
CH1
CH2 10
CH3 11
CH4 12
QFN PART MARKING*
2448
CH2 10
CH3 11
CH4 12
22 CH14
QFN PART MARKING*
2449
21 CH13
20
CH12
20
CH12
13 14 15 16 17 18 19
UHF PACKAGE
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
TJMAX = 125°C, θJA = 34°C/W
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
sn2444589 2444589fs
2
LTC2444/LTC2445/
LTC2448/LTC2449
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
●
●
24
Bits
REF
CC
REF
IN
REF
+
–
V
= 5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
5
3
15
5
ppm of V
ppm of V
CC
INCM
REF
REF
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
●
2.5
µV
CC
+
–
GND ≤ IN = IN ≤ V (Note 12)
CC
+
–
Offset Error Drift
2.5V ≤ REF ≤ V , REF = GND,
20
nV/°C
CC
+
–
GND ≤ IN = IN ≤ V
CC
+
–
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
REF = 5V, REF = GND, IN = 3.75V, IN = 1.25V
●
●
10
10
50
50
ppm of V
ppm of V
REF
REF
+
–
+
–
REF = 2.5V, REF = GND, IN = 1.875V, IN = 0.625V
+
–
2.5V ≤ REF ≤ V , REF = GND,
IN = 0.75REF , IN = 0.25 • REF
0.2
ppm of V /°C
REF
CC
+
+
–
+
+
–
+
–
REF = 5V, REF = GND, IN = 1.25V, IN = 3.75V
●
●
10
10
50
50
ppm of V
ppm of V
REF
REF
+
–
+
–
REF = 2.5V, REF = GND, IN = 0.625V, IN = 1.875V
+
–
2.5V ≤ REF ≤ V , REF = GND,
IN = 0.25 • REF , IN = 0.75 • REF
0.2
ppm of V /°C
REF
CC
+
+
–
+
+
–
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V
15
15
15
ppm of V
ppm of V
ppm of V
CC
INCM
REF
REF
REF
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V
CC
INCM
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
120
dB
CC
–
+
GND ≤ IN = IN ≤ V
CC
U
U
U
U
A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
●
●
●
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
V
Input Differential Voltage Range
–V /2
REF
V
IN
REF
+
–
(IN – IN )
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
●
●
●
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
V
Reference Differential Voltage Range
V
CC
REF
+
–
(REF – REF )
+
C
C
C
C
IN Sampling Capacitance
2
2
2
2
1
pF
pF
pF
pF
nA
S(IN+)
–
IN Sampling Capacitance
S(IN–)
+
REF Sampling Capacitance
S(REF+)
–
REF Sampling Capacitance
S(REF–)
+
–
I
Leakage Current, Inputs and Reference
CS = V , IN = GND, IN = GND,
●
–15
15
DC_LEAK(IN+, IN–,
CC
+
–
REF = 5V, REF = GND
REF+, REF–)
I
Average Input/Reference Current
During Sampling
Varies, See Applications Section
nA
SAMPLE(IN+, IN–,
REF+, REF–)
t
MUX Break-Before-Make
MUX Off Isolation
50
ns
OPEN
QIRR
V
= 2V DC to 1.8MHz
120
dB
IN
P-P
sn2444589 2444589fs
3
LTC2444/LTC2445/
LTC2448/LTC2449
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
4.5V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
V
V
V
High Level Input Voltage
●
●
●
●
●
●
2.5
V
IH
IL
IH
IL
CC
CS, F
O
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
V
V
CC
O
High Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
2.5
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
0.8
10
10
V
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
µA
µA
pF
pF
V
IN
IN
CS, F , EXT, SOI
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 8)
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 8)
IN
High Level Output Voltage
SDO, BUSY
I = –800µA
O
●
●
●
●
●
V
V
– 0.5V
– 0.5V
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO, BUSY
I = 1.6mA
O
0.4V
V
High Level Output Voltage
SCK
I = –800µA (Note 9)
O
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 9)
O
0.4V
10
V
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
W U
POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
●
4.5
5.5
V
CC
I
CC
Conversion Mode
Sleep Mode
CS = 0V (Note 7)
●
●
8
8
11
30
mA
µA
CS = V (Note 7)
CC
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.1
25
TYP
MAX
20
UNITS
MHz
ns
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
●
●
●
EOSC
HEO
10000
10000
25
ns
LEO
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
●
●
0.99
126
1.13
145
1.33
170
ms
ms
CONV
40 • OSR +170
External Oscillator (Notes 10, 13)
●
●
ms
f
(kHz)
EOSC
0.9
/10
f
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
0.8
1
MHz
Hz
ISCK
f
EOSC
sn2444589 2444589fs
4
LTC2444/LTC2445/
LTC2448/LTC2449
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
(Note 9)
MIN
TYP
MAX
55
UNITS
%
D
ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
●
●
●
●
45
f
t
t
t
(Note 8)
20
MHz
ns
ESCK
(Note 8)
25
25
LESCK
(Note 8)
ns
HESCK
DOUT_ISCK
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
●
●
41.6
35.3
30.9
µs
s
320/f
EOSC
t
t
t
t
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
(Note 8)
●
●
●
32/f
s
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
(Note 12)
(Note 12)
(Note 9)
0
0
25
25
1
CS ↑ to SDO High Z
CS ↓ to SCK ↓
2
5
3
CS ↓ to SCK ↑
(Notes 8, 12)
●
●
●
●
●
●
●
25
4
SCK ↓ to SDO Valid
25
50
KQMAX
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
SDI Setup Before SCK ↑
SDI Hold After SCK ↑
(Note 5)
15
50
KQMIN
5
6
7
8
(Note 5)
(Note 5)
10
10
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 7: The converter uses the internal oscillator.
of the device may be impaired.
Note 8: The converter is in external SCK mode of operation such that the
Note 2: All voltage values are with respect to GND.
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
and is expressed in Hz.
ESCK
Note 3: V = 4.5V to 5.5V unless otherwise specified.
CC
+
–
+
–
V
V
= REF – REF , V
= (REF + REF )/2;
Note 9: The converter is in internal SCK mode of operation such that the
REF
IN
REFCM
+
–
+
–
= IN – IN , V
= (IN + IN )/2.
SCK pin is used as a digital output. In this mode of operation, the SCK pin
INCM
has a total equivalent load capacitance of C
= 20pF.
LOAD
Note 4: F pin tied to GND or to external conversion clock source with
O
f
= 10MHz unless otherwise specified.
Note 10: The external oscillator is connected to the F pin. The external
O
EOSC
oscillator frequency, f
, is expressed in Hz.
EOSC
Note 5: Guaranteed by design, not subject to test.
Note 11: The converter uses the internal oscillator. F = 0V.
O
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1µs (typ) to the
conversion time.
U
U
U
PI FU CTIO S
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All 7 pins must be connected to
ground for proper operation.
EXT (Pin 3): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0-CH15 and COM pins can have any value between
sn2444589 2444589fs
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
5
LTC2444/LTC2445/
LTC2448/LTC2449
U
U
U
PI FU CTIO S
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN =IN+–IN–)from–0.5•VREF to0.5•VREF. Outsidethis
input range, the converter produces unique over-range
and under-range output codes.
defaultmodeofoperationisCH0-CH1,OSRof256,and1X
mode. The serial data input contains an enable bit which
determines if a new channel/speed is selected. If this bit is
low the following conversion remains at the same speed
andselectedchannel. Theserialdatainputisappliedtothe
device under control of the serial clock (SCK) during the
data output cycle. The first conversion following a new
channel/speed is valid.
CH0 to CH15 (Pins 8-23): LTC2448/LTC2449 Analog
Inputs. May be programmed for single-ended or differen-
tial mode.
FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock. When FO is con-
nected to VCC or GND, the converter uses its internal
oscillator running at 9MHz. The conversion rate is deter-
mined by the selected OSR such that tCONV (ms) = 40 •
OSR + 170/fOSC (kHz). The first digital filter null is located
at8/tCONV,7kHzatOSR=256and55Hz(Simultaneous50/
60Hz) at OSR = 32768. This pin may be driven with a
maximum external clock of 10.24MHz resulting in a maxi-
mum 8kHz output rate (OSR = 64, 2X Mode).
CH0toCH7(Pins9,10,13,14,17,18,21,22):LTC2444/
LTC2445 Analog Inputs. May be programmed for single-
ended or differential mode.
NC (Pins 8, 11, 12, 15, 16, 19, 20, 23): LTC2444/
LTC2445 No Connect/Channel Isolation Shield. May be
left floating or tied to any voltage 0 to VCC in order to
provide isolation for pairs of differential input channels.
NC (Pins 24, 25, 26, 27): LTC2444/LTC2448 No Connect.
These pins can either be tied to ground or left floating.
CS (Pin 36): Active Low Chip Select. A LOW on this pin
enables the SDO ditital output and wakes up the ADC.
Following each conversion the ADC automatically enters
thesleepmodeandremainsinthislowpowerstateaslong
asCSisHIGH. ALOW-to-HIGHtransitiononCSduringthe
Data Output aborts the data transfer and starts a new
conversion.
MUXOUTP (Pin 24): LTC2445/LTC2449 Positive Multi-
plexerOutput. Usedtodrivetheinputtoanexternalbuffer/
amplifier.
ADCINP (Pin 25): LTC2445/LTC2449 Positive ADC Input.
Tie to output of buffer/amplifier driven by MUXOUTP.
ADCINN(Pin26):LTC2445/LTC2449NegativeADCInput.
Tie to output of buffer/amplifier driven by MUXOUTN.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS
LOW. This signal is HIGH while the conversion is in
progress and goes LOW once the conversion is complete.
MUXOUTN (Pin 27): LTC2445/LTC2449 Negative Multi-
plexerOutput. Usedtodrivetheinputtoanexternalbuffer/
amplifier.
VCC (Pin28):PositiveSupplyVoltage. BypasstoGNDwith
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 29), REF– (Pin 30): Differential Reference
Input. The voltage on these pins can have any value
between GND and VCC as long as the reference positive
input, REF+, is maintained more positive than the negative
reference input, REF+, by at least 0.1V.
SCK (Pin 38): Bidirectional Digital Clock Pin. In internal
serialclockoperationmode,SCKisusedasadigitaloutput
fortheinternalserialinterfaceclockduringthedataoutput
period. In the external serial clock operation mode, SCK is
used as the digital input for the external serial interface
clock during the data output period. The serial clock
operation mode is determined by the logic level applied to
the EXT pin.
SDI (Pin 34): Serial Data Input. This pin is used to select
the speed, 1X or 2X mode, resolution, and input channel,
for the next conversion cycle. At initial power up, the
sn2444589 2444589fs
6
LTC2444/LTC2445/
LTC2448/LTC2449
U
U
W
FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
F
AUTOCALIBRATION
AND CONTROL
O
(INT/EXT)
+
–
REF
REF
CH0
CH1
+
–
+
–
IN
IN
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
SDI
•
•
•
MUX
SCK
SDO
CS
SERIAL
INTERFACE
CH15
COM
DECIMATING FIR
ADDRESS
2444 F01
Figure 1. Functional Block Diagram
V
TEST CIRCUITS
CC
1.69k
SDO
SDO
C
= 20pF
1.69k
C
LOAD
= 20pF
LOAD
Hi-Z TO V
Hi-Z TO V
OL
OL
OH
OH
V
V
TO V
V
TO V
OH
OL
OL
OH
TO Hi-Z
2440 TA04
V
TO Hi-Z
2440 TA03
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
POWER UP
IN =CH0, IN =CH1
OSR=256,1X MODE
+
–
Converter Operation Cycle
CONVERT
SLEEP
The LTC2444/LTC2445/LTC2448/LTC2449 are multi-
channel, high speed, delta-sigma analog-to-digital con-
verterswithaneasytouse3-or4-wireserialinterface(see
Figure 1). Their operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output/input (see Figure 2). The 4-wire interface
consists of serial data input (SDI), serial data output
(SDO), serial clock (SCK) and chip select (CS). The inter-
face, timing, operation cycle and data out format is com-
patible with Linear’s entire family of ∆Σconverters.
CS = LOW
AND
SCK
CHANNEL SELECT
SPEED SELECT
DATA OUTPUT
2444 F02
Figure 2. LTC2444/LTC2445/LTC2448/LTC2449
State Transition Diagram
sn2444589 2444589fs
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LTC2444/LTC2445/
LTC2448/LTC2449
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APPLICATIO S I FOR ATIO
Power-Up Sequence
Initially, the LTC2444/LTC2445/LTC2448/LTC2449 per-
form a conversion. Once the conversion is complete, the
device enters the sleep state. While in this sleep state,
power consumption is reduced below 10µA. The part
remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
TheLTC2444/LTC2445/LTC2448/LTC2449automatically
enter an internal reset state when the power supply
voltage VCC drops below approximately 2.2V. This fea-
ture guarantees the integrity of the conversion result and
of the serial interface mode selection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. The conversion imme-
diately following a POR is performed on the input channel
IN+ = CH0, IN– = CH1 at an OSR = 256 in the 1X mode.
FollowingthePORsignal,theLTC2444/LTC2445/LTC2448/
LTC2449 start a normal conversion cycle and follow the
succession of states described above. The first conver-
sion result following POR is accurate within the specifica-
tions of the device if the power supply voltage is restored
within the operating range (4.5V to 5.5V) before the end of
the POR time interval.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
resultwhileoperatinginthe1xmode. Thedataoutputcor-
responds to the conversion just performed. This result is
shifted out on the serial data out pin (SDO) under the con-
trol of the serial clock (SCK). Data is updated on the falling
edge of SCK allowing the user to reliably latch data on the
rising edge of SCK (see Figure 3). The data output state is
concludedonce32bitsarereadoutoftheADCorwhenCS
is brought HIGH. The device automatically initiates a new
conversion and the cycle repeats.
Through timing control of the CS, SCK and EXT pins, the
LTC2444/LTC2445/LTC2448/LTC2449 offer several flex-
ible modes of operation (internal or external SCK). These
variousmodesdonotrequireprogrammingconfiguration
registers; moreover, they do not disturb the cyclic opera-
tion described above. These modes of operation are
described in detail in the Serial Interface Timing Modes
section.
Reference Voltage Range
These converters accept a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
ficationfortheREF+ andREF– pinscoverstheentirerange
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2444/LTC2445/LTC2448/LTC2449 can accept a
differential reference voltage from 0.1V to VCC. The con-
verter output noise is determined by the thermal noise of
the front-end circuits, and as such, its value in microvolts
is nearly constant with reference voltage. A decrease in
reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a
reduced reference voltage will improve the converter’s
Ease of Use
The LTC2444/LTC2445/LTC2448/LTC2449 data output
has no latency, filter settling delay or redundant data
associated with the conversion cycle while operating in
the 1X mode. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy. Speed/
resolution adjustments may be made seamlessly be- overall INL performance.
tween two conversions without settling errors.
Input Voltage Range
The LTC2444/LTC2445/LTC2448/LTC2449 perform off-
The analog input is truly differential with an absolute/
setandfull-scalecalibrationseveryconversioncycle. This
calibration is transparent to the user and has no effect on
the cyclic operation described above. The advantage of
continuous calibration is extreme stability of offset and
full-scale readings with respect to time, supply voltage
change and temperature drift.
common mode range for the CH0-CH15 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2444/LTC2445/
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LTC2444/LTC2445/
LTC2448/LTC2449
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APPLICATIO S I FOR ATIO
LTC2448/LTC2449 convert the bipolar differential input
signal, VIN = IN+ – IN– (where IN+ and IN– are the selected
inputchannels),from–FS=–0.5•VREF to+FS=0.5•VREF
where VREF = REF+ – REF–. Outside this range, the con-
verterindicatestheoverrangeortheunderrangecondition
using distinct output codes.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
MUXOUT/ADCIN
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
There are two differences between the LTC2444/LTC2448
and the LTC2445/LTC2449. The first is the RMS noise
performance. For a given OSR, the LTC2445/LTC2449
noise level is approximately √2 times lower (0.5 effective
bits)than that of the LTC2444/LTC2448.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The second difference is the LTC2445/LTC2449 includes
MUXOUT/ADCINpins.Thesepinsenableanexternalbuffer
or gain block to be inserted between the output of the
multiplexer and the input to the ADC. Since the buffer is
driven by the output of the multiplexer, only one circuit is
required for all 16 input channels. Additionally, the trans-
parentcalibrationfeatureoftheLTC244Xfamilyautomati-
cally removes the offset errors of the external buffer.
The function of these bits is summarized in Table 1.
Table 1. LTC2444/LTC2445/LTC2448/LTC2449 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
Input Range
EOC
DMY
SIG MSB
In order to achieve optimum performance, the MUXOUT
and ADCIN pins should not be shorted together. In appli-
cationswheretheMUXOUTandADCINneedtobeshorted
together, the LTC2444/LTC2448 should be used because
the MUXOUT and ADCIN are internally connected for
optimum performance.
V
≥ 0.5 • V
0
0
0
0
0
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
0
IN
REF
–0.5 • V ≤ V < 0V
0
REF
IN
V
< –0.5 • V
0
IN
REF
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Output Data Format
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
The LTC2444/LTC2445/LTC2448/LTC2449 serial output
datastreamis32bitslong. Thefirst3bitsrepresentstatus
information indicating the sign and conversion state. The
next 24 bits are the conversion result, MSB first. The
remaining 5 bits are sub LSBs beyond the 24-bit level that
may be included in averaging or discarded without loss of
resolution. In the case of ultrahigh resolution modes,
more than 24 effective bits of performance are possible
(see Table 5). Under these conditions, sub LSBs are
included in the conversion result and represent useful
information beyond the 24-bit level. The third and fourth
bit together are also used to indicate an underrange
condition(thedifferentialinputvoltageisbelow–FS)oran
overrangecondition(thedifferentialinputvoltageisabove
+FS).
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
deviceonceCSispulledLOW.EOCchangesrealtimefrom
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
risingedgeofSCK. Bit30isshiftedoutofthedeviceonthe
sn2444589 2444589fs
9
LTC2444/LTC2445/
LTC2448/LTC2449
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APPLICATIO S I FOR ATIO
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
SCK
SDI
1
0
EN
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
EOC “0” SIG MSB
SGL
ODD
A2
A1
A0
OSR3 OSR2 OSR1 OSR0 TWOX
BIT 0
Hi-Z
Hi-Z
SDO
LSB
BUSY
2444 F04
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
SERIAL INTERFACE PINS
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edgeofthe32ndSCKpulse,SDOgoesHIGHindicatingthe
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
AslongasthevoltageontheIN+ andIN– pinsismaintained
within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS=0.5•VREF.Fordifferentialinputvoltagesgreaterthan
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
The LTC2444/LTC2445/LTC2448/LTC2449 transmit the
conversion results and receive the start of conversion
command through a synchronous 3- or 4-wire interface.
Duringtheconversionandsleepstates, thisinterfacecan
be used to assess the converter status and during the
data output state it is used to read the conversion result
and program the speed, resolution and input channel.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 38) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
outputandtheLTC2444/LTC2445/LTC2448/LTC2449cre-
ate their own serial clock. In the External SCK mode of
operation, the SCK pin is used as input. The internal or
Table 2. LTC2444/LTC2445/LTC2448/LTC2449 Output Data Format
Differential Input Voltage
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
V
IN
*
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
1
1
IN
REF
+
–
+
–
*The differential input voltage V = IN – IN . **The differential reference voltage V = REF – REF .
IN
REF
sn2444589 2444589fs
10
LTC2444/LTC2445/
LTC2448/LTC2449
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APPLICATIO S I FOR ATIO
U
external SCK mode is selected by tying EXT (Pin 3) LOW
for external SCK and HIGH for internal SCK.
nominally 880Hz), and 1X speedup mode (no Latency).
Once this first conversion is complete, the device enters
the sleep state and is ready to output the conversion result
and receive the serial data input stream programming the
speed/resolution and input channel for the next conver-
sion. At the conclusion of each conversion cycle, the
device enters this state.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
In order to change the speed/resolution or input channel,
the first 3 bits shifted into the device are 101. This is
compatible with the programming sequence of the
LTC2414/LTC2418. If the sequence is set to 000 or 100,
the following input data is ignored (don’t care) and the
previously selected speed/resolution and channel remain
valid for the next conversion. Combinations other than
101, 100, and 000 of the 3 control bits should be avoided.
When CS (Pin 36) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel for the following
conversion (see Tables 3 and 4). The next 5 bits select the
speed/resolution and mode 1X (no Latency) 2X (double
output rate with one conversion latency), see Table 5. If
these 5 bits are set to all 0’s, the previous speed remains
selected for the next conversion. This is useful in applica-
tions requiring a fixed output rate/resolution but need to
changetheinputchannel.Inthiscase,thetimingandinput
sequence is compatible with the LTC2414/LTC2418.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversionstatusandtoenablethedataoutputtransferas
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2444/LTC2445/LTC2448/
LTC2449willabortanyserialdatatransferinprogressand
start a new conversion cycle anytime a LOW-to-HIGH
transition is detected at the CS pin after the converter has
entered the data output state.
When an update operation is initiated (the first 3 bits are
101) the first 5 bits are the channel address. The first
bit, SGL, determines if the input selection is differential
(SGL = 0) or single-ended (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels (LTC2444/LTC2445)
or one of 16 channels (LTC2448/LTC2449) is selected as
the positive input. The negative input is COM for all single
ended operations. The remaining 4 bits (ODD, A2, A1, A0)
determine which channel is selected. The LTC2448/
LTC2449 use all 4 bits to select one of 16 different input
channels (see table 3) while in the case of the LTC2444/
LTC2445, A2 is always 0, and the remaining 3 bits select
one of 8 different input channels (see Table 4).
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution and input channel of the LTC2444/
LTC2445/LTC2448/LTC2449. SDI is programmed by a
serial input data stream under the control of SCK during
the data output cycle, see Figure 3.
Initially, after powering up, the device performs a conver-
sion with IN+ = CH0, IN– = CH1, OSR = 256 (output rate
sn2444589 2444589fs
11
LTC2444/LTC2445/
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Table 3. Channel Selection for the LTC2448/LTC2449
MUX ADDRESS
CHANNEL SELECTION
ODD/
SGL SIGN
A2 A1 A0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 COM
+
–
+
–
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IN
IN
+
–
+
–
IN
IN
+
–
+
–
IN
IN
+
–
+
–
IN
IN
+
–
+
–
IN
IN
+
–
IN
IN
IN
IN
+
–
IN
IN
IN
IN
+
–
IN
IN
IN
IN
+
IN
IN
+
IN
IN
+
IN
IN
+
IN
IN
+
IN
IN
–
+
IN
–
+
IN
–
+
IN
–
IN
IN
–
IN
IN
–
IN
IN
–
IN
IN
–
IN
IN
+
–
IN
+
–
IN
+
–
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
*Default at power up
sn2444589 2444589fs
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LTC2444/LTC2445/
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Table 4. Channel Selection for the LTC2444/LTC2445 (Bit A2 Should Always Be 0)
MUX ADDRESS
CHANNEL SELECTION
ODD/
SGL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SIGN A2 A1 A0
0
1
2
3
4
5
6
IN
IN
IN
7
IN
IN
COM
+
–
+
–
+
*
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IN
IN
+
–
+
–
IN
IN
+
–
+
–
IN
IN
+
–
+
–
+
IN
IN
IN
+
IN
IN
IN
+
IN
IN
IN
–
IN
–
IN
–
IN
–
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
+
–
IN
IN
*Default at power up
sn2444589 2444589fs
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Table 5. LTC2444/LTC2445/LTC2448/LTC2449 Speed/Resolution Selection
CONVERSION RATE
OSR3 OSR2 OSR1 OSR0 TWOX INTERNAL EXTERNAL NOISE
RMS
RMS
NOISE
ENOB
ENOB
OSR
LATENCY
9MHz
Clock
10.24MHz LTC2444/ LTC2445/ LTC2444/ LTC2445/
Clock
LTC2448 LTC2449 LTC2448 LTC2449
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Keep Previous Speed/Resolution
3.52kHz
1.76kHz
880Hz
440Hz
220Hz
110Hz
55Hz
4kHz
2kHz
1kHz
500Hz
250Hz
125Hz
62.5Hz
31.25Hz
23µV
4.4µV
2.8µV
2µV
1.4µV
1.1µV
720nV
530nV
23µV
3.5µV
2µV
1.4µV
1µV
750nV
510nV
375nV
250nV
200nV
17
17
64
128
256
none
none
none
none
none
none
none
none
none
none
20.1
20.8
21.3
21.8
22.1
22.7
23.2
23.8
24.1
20.1
21.3
21.8
22.4
22.9
23.4
24
512
1024
2048
4096
8192
16384
32768
27.5Hz
13.75Hz 15.625Hz 350nV
6.875Hz 7.8125Hz 280nV
24.4
24.6
Keep Previous Speed/Resolution
7.04kHz
3.52kHz
1.76kHz
880Hz
440Hz
220Hz
110Hz
55Hz
8kHz
4kHz
2kHz
23µV
4.4µV
2.8µV
2µV
1.4µV
1.1µV
720nV
530nV
350nV
23µV
3.5µV
2µV
1.4µV
1µV
750nV
510nV
375nV
250nV
200nV
17
17
64
128
256
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
1 cycle
20.1
20.8
21.3
21.8
22.1
22.7
23.2
23.8
24.1
20.1
21.3
21.8
22.4
22.9
23.4
24
1kHz
512
500Hz
250Hz
125Hz
62.5Hz
31.25Hz
1024
2048
4096
8192
16384
32768
27.5Hz
24.4
24.6
13.75Hz 15.625Hz 280nV
sn2444589 2444589fs
14
LTC2444/LTC2445/
LTC2448/LTC2449
W U U
APPLICATIO S I FOR ATIO
U
Speed Multiplier Mode
the end of the conversion cycle (just prior to the data
output cycle) for auto calibration. The time required to
read the conversion enables more settling time for the
external buffer/amplifier. The offset/offset drift of the
external amplifier is automatically removed by the
converter’s auto calibration sequence for both the 1X and
2X speed modes.
In addition to selecting the speed/resolution, a speed
multiplier mode is used to double the output rate while
maintainingtheselectedresolution.Thelastbitofthe5-bit
speed/resolution control word (TWOX, see Table 5) deter-
mines if the output rate is 1X (no speed increase) or 2X
(double the selected speed).
While operating in the 1X mode, if a new input channel is
selected the multiplexer is switched on the falling edge of
the 14th SCK (once the complete data input word is
programmed). The remaining data output sequence time
can be used to allow the external buffer/amplifier to settle.
While operating in the 1X mode, the device combines two
internal conversions for each conversion result in order to
remove the ADC offset. Every conversion cycle, the offset
and offset drift are transparently calibrated greatly simpli-
fying the user interface. The resulting conversion result
has no latency. The first conversion following a newly
selected speed/resolution and input channel is valid. This
is identical to the operation of the LTC2440, LTC2414 and
LTC2418.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device and SDI is shifted into the device.
It goes HIGH at the conclusion of the data input/output
cycle indicating a new conversion has begun. This rising
edge may be used to flag the completion of the data read
cycle.
While operating in the 2X mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2X. The resolution
(noise) remains the same. If a new channel is selected, the
conversion result is valid for all conversions after the first
conversion (one cycle latency). If a new speed/resolution
is selected, the first conversion result is valid but the
resolution (noise) is a function of the running average. All
subsequent conversion results are valid. If the mode is
changedfromeither1Xto2Xor2Xto1Xwithoutchanging
the resolution or channel, the first conversion result is
valid.
SERIAL INTERFACE TIMING MODES
The LTC2444/LTC2445/LTC2448/LTC2449’s 3- or 4-wire
interface is SPI and MICROWIRE compatible. This inter-
face offers several flexible modes of operation. These in-
clude internal/external serial clock, 3- or 4-wire I/O, single
cycle conversion and autostart. The following sections
describe each of these serial interface timing modes in
detail. Inallthesecases, theconvertercanusetheinternal
oscillator (FO = LOW) or an external oscillator connected
to the FO pin. Refer to Table 6 for a summary.
If an external buffer/amplifier circuit is used for the
LTC2445/LTC2449, the 2X mode can be used to increase
the settling time of the amplifier between readings. While
operating in the 2X mode, the multiplexer output (input to
theexternalbuffer/amplifier)isswitchedattheendofeach
conversioncycle.Priortoconcludingthedataout/incycle,
the analog multiplexer output is switched. This occurs at
Table 6. LTC2444/LTC2445/LTC2448/LTC2449 Interface Timing Modes
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
SCK
Configuration
Source
External
External
Internal
Internal
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 4, 5
Figure 6
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
CS ↓
CS ↓
Figures 7, 8
Continuous
Internal
Figure 9
sn2444589 2444589fs
15
LTC2444/LTC2445/
LTC2448/LTC2449
W U U
U
APPLICATIO S I FOR ATIO
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen. Data isshifted out the SDO pin
oneachfallingedgeofSCK.Thisenablesexternalcircuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 (BUSY = 1) while a conversion is in progress and
EOC = 0 (BUSY = 0) if the device is in the sleep state.
IndependentofCS,thedeviceautomaticallyentersthelow
power sleep state once the conversion is complete.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
2.7V TO 5.5V
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
F
O
CC
LTC2448
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
CH8
SDO
CS
36
ANALOG
INPUTS
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
CS
TEST EOC
TEST EOC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
1
0
EN
SGL
ODD
A2
A1
A0
OSR3 OSR2 OSR1 OSR0 TWOX
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
EOC “0” SIG MSB
BIT 0
LSB
Hi-Z
Hi-Z
SDO
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2444 F05
Figure 4. External Serial Clock, Single Cycle Operation
sn2444589 2444589fs
16
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next con-
version cycle. This is useful for systems not requiring all
32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion. If a new
channelisbeingprogrammed,therisingedgeofCSmust
come after the 14th falling edge of SCK in order to store
the data input sequence.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. Thirteen serial input
data bits are required in order to properly program the
speed/resolution and input channel. If the data output
2.7V TO 5.5V
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
CC
F
O
LTC2448
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
CH8
SDO
CS
36
ANALOG
INPUTS
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
CS
TEST EOC
1
5
1
2
3
4
5
6
SCK
(EXTERNAL)
SDI
DON'T CARE
DON'T CARE
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25
EOC “0” SIG MSB
Hi-Z
Hi-Z
SDO
BUSY
SLEEP
DATA OUTPUT
DATA OUTPUT
CONVERSION
CONVERSION
CONVERSION
SLEEP
2444 F06
Figure 5. External Serial Clock, Reduced Output Data Length
sn2444589 2444589fs
17
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
External Serial Clock, 2-Wire I/O
indicating the conversion result is ready. EOC = 1
(BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 6. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. Conversely, BUSY (Pin 2) may be used
tomonitorthestatusoftheconversioncycle.EOCorBUSY
may be used as an interrupt to an external controller
2.7V TO 5.5V
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
F
O
CC
LTC2448
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
CH8
SDO
CS
36
ANALOG
INPUTS
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
SCK
(EXTERNAL)
DON'T CARE
1
0
EN
SGL
ODD
A2
A1
A0
OSR3 OSR2 OSR1 OSR0 TWOX
DON'T CARE
BIT 0
SDI
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
EOC “0” SIG MSB
LSB
SDO
BUSY
CONVERSION
2444 F07
DATA OUTPUT
CONVERSION
SLEEP
Figure 6. External Serial Clock, CS = 0 Operation (2-Wire)
sn2444589 2444589fs
18
LTC2444/LTC2445/
LTC2448/LTC2449
W U U
APPLICATIO S I FOR ATIO
U
Internal Serial Clock, Single Cycle Operation
sionandgoesLOWattheconclusion.ItremainsLOWuntil
the result is read from the device.
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 7.
WhentestingEOC,iftheconversioniscomplete(EOC=0),
thedevicewillexitthesleepstateandenterthedataoutput
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is
500ns. If CS is pulled HIGH before time tEOCtest, the device
remains in the sleep state. The conversion result is held in
the internal static shift register.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 2) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
2.7V TO 5.5V
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
CC
F
O
LTC2448
1µF
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
SDO
CS
36
ANALOG
INPUTS
CH8
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
<t
EOC(TEST)
CS
SCK
SDI
TEST EOC
TEST EOC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
1
0
EN
SGL
ODD
A2
A1
A0
OSR3 OSR2 OSR1 OSR0 TWOX
DON'T CARE
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
EOC “0” SIG MSB
BIT 0
LSB
Hi-Z
Hi-Z
SDO
BUSY
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2444 F08
Figure 7. Internal Serial Clock, Single Cycle Operation
sn2444589 2444589fs
19
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edgeofSCK.Theinternallygeneratedserialclockisoutput
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latchedonthefirstrisingedgeofSCKandthelastbitofthe
conversionresultonthe32ndrisingedgeofSCK. Afterthe
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
of SCK, see Figure 8. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. Thirteen
serial input data bits are required in order to properly
program the speed/resolution and input channel. If the
data output sequence is aborted prior to the 13th rising
edge of SCK, the new input data is ignored, and the
previouslyselectedspeed/resolutionandchannelareused
for the next conversion cycle. If a new channel is being
programmed, the rising edge of CS must come after the
14th falling edge of SCK in order to store the data input
sequence.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
2.7V TO 5.5V
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
F
O
CC
LTC2448
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
CH8
SDO
CS
36
ANALOG
INPUTS
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
<t
1
<t
EOC(TEST)
EOC(TEST)
CS
TEST EOC
5
1
2
3
4
5
6
SCK
SDI
DON'T CARE
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25
EOC “0” SIG MSB
DON'T CARE
Hi-Z
Hi-Z
SDO
BUSY
SLEEP
DATA OUTPUT
DATA OUTPUT
CONVERSION
CONVERSION
CONVERSION
SLEEP
2444 F09
Figure 8. Internal Serial Clock, Reduced Data Output Length
sn2444589 2444589fs
20
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
device has entered the low power sleep state. The part
remains in the sleep state a minimum amount of time
(≈500ns) then immediately begins outputting data. The
dataoutputcyclebeginsonthefirstrisingedgeofSCKand
endsafterthe32ndrisingedge.DataisshiftedouttheSDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH(EOC=1)indicatinganewconversionisinprogress.
SCK remains HIGH during the conversion.
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplify-
ing the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
2.7V TO 5.5V
1µF
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
28
35
V
CC
F
O
LTC2448
29
30
8
34
38
+
–
REFERENCE
VOLTAGE
REF
REF
SDI
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
CH0
•
•
•
•
•
•
15
16
23
7
37
CH7
SDO
CS
36
ANALOG
INPUTS
CH8
•
•
•
•
•
•
2
CH15
BUSY
GND
1,4,5,6,31,32,33
COM
CS
1
1
2
0
3
4
5
6
7
8
9
10
11
12
13
14
32
SCK
DON'T CARE
EN
SGL
ODD
A2
A1
A0
OSR3 OSR2 OSR1 OSR0 TWOX
DON'T CARE
BIT 0
SDI
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
EOC
“0”
SIG
MSB
LSB
SDO
BUSY
DATA OUTPUT
CONVERSION
2444 F10
CONVERSION
SLEEP
Figure 9. Internal Serial Clock, Continuous Operation
sn2444589 2444589fs
21
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
Table 7. OSR vs Notch Frequency (fN) (with Internal Oscillator
Running at 9MHz)
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2444/LTC2445/
LTC2448/LTC2449 significantly simplify antialiasing filter
requirements.
OSR
NOTCH (f )
N
64
28.16kHz
14.08kHz
7.04kHz
3.52kHz
1.76kHz
880Hz
128
256
512
TheLTC2444/LTC2445/LTC2448/LTC2449’sspeed/reso-
lution is determined by the over sample ratio (OSR) of the
on-chip digital filter. The OSR ranges from 64 for 3.5kHz
output rate to 32,768 for 6.9Hz (in No Latency mode)
output rate. The value of OSR and the sample rate fS
determine the filter characteristics of the device. The first
NULL of the digital filter is at fN and multiples of fN where
fN = fS/OSR, see Figure 10 and Table 7. The rejection at the
frequency fN ±14% is better than 80dB, see Figure 11.
1024
2048
4096
440Hz
8192
16384
220Hz
110Hz
32768*
55Hz
*Simultaneous 50/60Hz rejection
–80
–90
0
4
SINC ENVELOPE
–20
–40
–100
–110
–120
–130
–140
–60
–80
–100
–120
–140
57 59
47 49 51 53 55
61 63
60
120
240
0
180
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F12
2440 F11
Figure 10. LTC2444/LTC2445/LTC2448/LTC2449
Normal Mode Rejection (Internal Oscillator)
Figure 11. LTC2444/LTC2445/LTC2448/LTC2449
Normal Mode Rejection (Internal Oscillator)
sn2444589 2444589fs
22
LTC2444/LTC2445/
LTC2448/LTC2449
W U U
APPLICATIO S I FOR ATIO
U
If FO is grounded, fS is set by the on-chip oscillator at
1.8MHz ±5%(oversupplyandtemperaturevariations). At
an OSR of 32,768, the first NULL is at fN = 55Hz and the no
latency output rate is fN/8 = 6.9Hz. At the maximum OSR,
thenoiseperformanceofthedeviceis280nVRMS(LTC2444/
LTC2448)and200nVRMS (LTC2445/LTC2449)withbetter
than80dBrejectionof50Hz±2%and60Hz±2%.Sincethe
OSR is large (32,768) the wide band rejection is extremely
large and the antialiasing requirements are simple. The
first multiple of fS occurs at 55Hz • 32,768 = 1.8MHz, see
Figure 12.
clock applied to FO. Combining a large OSR with a reduced
sample rate leads to notch frequencies fN near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to FO results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 13. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 16. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
The first NULL becomes fN = 7.04kHz with an OSR of 256
(an output rate of 880Hz) and FO grounded. While the
NULL has shifted, the sample rate remains constant. As a
result of constant modulator sampling rate, the linearity,
offset and full-scale performance remains unchanged as
does the first multiple of fS.
⎛
10k
⎞
fOSC = 10MHz •
⎜
⎟
⎝10•RSET
⎠
The normal mode rejection characteristic shown in
Figure 13isachievedbyapplyingtheoutputoftheLTC1799
(withRSET =100k)totheFO pinontheLTC2444/LTC2445/
LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).
The sample rate fS and NULL fN, may also be adjusted by
driving the FO pin with an external oscillator. The sample
rate is fS = fEOSC/5, where fEOSC is the frequency of the
0
–20
–40
0
–20
–40
–60
–60
1.8MHz
–80
–80
–100
–100
–120
–140
REJECTION > 120dB
–120
–140
1000000
2000000
0
2
4
6
10
0
8
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
1440 F13
2440 F14
Figure 12. LTC2444/LTC2445/LTC2448/LTC2449
Normal Mode Rejection (Internal Oscillator)
Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (External Oscillator at 90kHz)
sn2444589 2444589fs
23
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
Reduced Power Operation
Average Input Current
The LTC2444/LTC2448 switch the input and reference to
a 2pF capacitor at a frequency of 1.8MHz. A simplified
equivalent circuit is shown in Figure 15. The sample
capacitor for the LTC2445/LTC2449 is 4pF, and its aver-
age input current is externally buffered from the input
source.
In addition to adjusting the speed/resolution of the
LTC2444/LTC2445/LTC2448/LTC2449, the speed/reso-
lution/power dissipation may also be adjusted using the
automatic sleep mode. During the conversion cycle, the
LTC2444/LTC2445/LTC2448/LTC2449 draw 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8µA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 14.
The average input and reference currents can be ex-
pressed in terms of the equivalent input resistance of the
sample capacitor, where: Req = 1/(fSW • Ceq)
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
V
CC
I
+
+
REF
R
(TYP)
SW
SW
I
I
LEAK
500Ω
V
REF
LEAK
V
CC
I +
IN
R
(TYP)
500Ω
I
I
LEAK
C
EQ
5pF
V +
IN
(TYP)
LEAK
MUX
(C = 2pF
EQ
SAMPLE CAP
+ PARASITICS)
V
CC
I
–
–
IN
R
SW
(TYP)
I
LEAK
500Ω
V
IN
I
LEAK
MUX
V
CC
I
–
–
REF
R
SW
(TYP)
I
I
LEAK
500Ω
2440 F16
V
REF
LEAK
SWITCHING FREQUENCY
f
f
= 1.8MHz INTERNAL OSCILLATOR
EOSC
SW
SW
= f
/5 EXTERNAL OSCILLATOR
Figure 15. LTC2444/LTC2448 Input Structure
CONVERTER
STATE
SLEEP
CONVERT
SLEEP
CONVERT
SLEEP
DATA
OUT
DATA
OUT
CS
SUPPLY
CURRENT
8µA
8mA
8µA
8mA
8µA
2440 F15
Figure 14. Reduced Power Timing Mode
sn2444589 2444589fs
24
LTC2444/LTC2445/
LTC2448/LTC2449
U
W U U
APPLICATIO S I FOR ATIO
First Notch Frequency
Input Bandwidth and Frequency Rejection
This is the first notch in the SINC4 portion of the digital
filter and depends on the fo clock frequency and the
oversample ratio. Rejection at this frequency and its
multiples (up to the modulator sample rate of 1.8MHz)
exceeds 120dB. This is 8 times the maximum conversion
rate.
The combined effect of the internal SINC4 digital filter and
the digital and analog autocalibration circuits determines
the LTC2444/LTC2445/LTC2448/LTC2449 input band-
width and rejection characteristics. The digital filter’s
response can be adjusted by setting the oversample ratio
(OSR) through the SPI interface or by supplying an exter-
nal conversion clock to the fo pin.
Effective Noise Bandwidth
Table 8 lists the properties of the LTC2444/LTC2445/
LTC2448/LTC2449 with various combinations of
oversample ratio and clock frequency. Understanding
these properties is the key to fine tuning the characteris-
tics of the LTC2444/LTC2445/LTC2448/LTC2449 to the
application.
TheLTC2444/LTC2445/LTC2448/LTC2449hasextremely
good input noise rejection from the first notch frequency
all the way out to the modulator sample rate (typically
1.8MHz). Effective noise bandwidth is a measure of how
the ADC will reject wideband input noise up to the modu-
lator sample rate. The example on the following page
shows how the noise rejection of the LTC2444/LTC2445/
LTC2448/LTC2449 reduces the effective noise of an am-
plifier driving its input.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
Table 8
Over-
*RMS
*RMS
Noise
ENOB
(V = 5V)
Maximum
First Notch
Frequency
Effective
–3dB
sample Noise
Conversion Rate
Noise BW
point (Hz)
REF
Ratio LTC2444/ LTC2445/ LTC2444/ LTC2445/
(OSR) LTC2448 LTC2449 LTC2449 LTC2449 9MHz clock
Internal
External
Internal External
Internal
External
Internal
External
f
9MHz clock
28125
14062.5
7031.3
3515.6
1757.8
878.9
f
9MHz clock
3148
1574
787
f
9MHz clock
1696
848 f /10600
o
f
o
o
o
o
64
23µV
4.5µV
2.8µV
2µV
23µV
3.5µV
2µV
17
17
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
f /2560
f /320
f /5710
f /5310
o
o
o
o
128
20.1
20.8
21.3
21.8
22.1
22.7
23.2
23.8
24.1
20
f /5120
o
f /640
f /2860
o
o
256
21.3
21.8
22.4
22.9
23.4
24
f /10240
o
f /1280
f /1140
o
424
f /21200
o
o
512
1.4µV
1µV
f /20480
o
f /2560
394
f /2280
o
212
f /42500
o
o
1024
2048
4096
8192
1.4µV
1.1µV
720nV
530nV
f /40960
o
f /5120
197
f /4570
o
106
f /84900
o
o
750nV
510nV
375nV
250nV
200nV
f /81920
o
f /1020
98.4
f /9140
o
53
f /170000
o
o
f /163840
o
439.5
f /2050
o
49.2
f /18300
o
26.5
13.2
6.6
f /340000
o
27.5
f /327680
o
219.7
f /4100
o
24.6
f /36600
o
f /679000
o
16384 350nV
32768 280nV
24.4
24.6
13.7
f /655360
o
109.9
f /8190
o
12.4
f /73100
o
f /1358000
o
6.9
f /1310720
o
54.9
f /16380
o
6.2
f /146300
o
3.3
f /2717000
o
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantization
noise.
sn2444589 2444589fs
25
LTC2444/LTC2445/
LTC2448/LTC2449
W U U
U
APPLICATIO S I FOR ATIO
Example:
Automatic Offset Calibration of External
Buffers/Amplifiers
If an amplifier (e.g. LT1219) driving the input of an
LTC2444/LTC2445/LTC2448/LTC2449 has wideband
noise of 33nV/√Hz, band-limited to 1.8MHz, the total
noise entering the ADC input is:
The LTC2445/LTC2449 enable an external amplifier to be
inserted between the multiplexer output and the ADC
input. This enables one external buffer/amplifier circuit to
be shared between all 17 analog inputs (16 single-ended
or8differential). TheLTC2445/LTC2449performaninter-
nal offset calibration every conversion cycle in order to
remove the offset and drift of the ADC. This calibration is
performed through a combination of front end switching
and digital processing. Since the external amplifier is
placedbetweenthemultiplexerandtheADC,itisinsidethe
correctionloop. Thisresultsinautomaticoffsetcorrection
and offset drift removal of the external amplifier.
33nV/√Hz • √1.8MHz = 44.3µV.
When the ADC digitizes the input, its digital filter filters out
the wideband noise from the input signal. The noise
reduction depends on the oversample ratio which defines
the effective bandwidth of the digital filter.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifier noise to:
33nV/√Hz • √787Hz = 0.93µV.
The total noise is the RMS sum of this noise with the 2µV
noise of the ADC at OSR=256.
The LT1368 is an excellent amplifier for this function. It
has rail-to-rail inputs and outputs, and it operates on a
single 5V supply. Its open-loop gain is 1M and its input
bias current is 10nA. It also requires at least a 0.1µF load
capacitor for compensation. It is this feature that sets it
apart from other amplifiers—the load capacitor attenu-
atessamplingglitchesfromtheLTC2445/LTC2449ADCIN
terminals, allowing it to achieve full performance of the
ADC with high impedance at the multiplexer inputs.
√(0.93µV)2 + (2uV)2 = 2.2µV.
Increasing the oversample ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifier noise to:
33nV/√Hz • √6.2Hz = 82nV.
ThetotalnoiseistheRMSsumofthisnoisewiththe200nV
noise of the ADC at OSR = 32768.
Another benefit of the LT1368 is that it can be powered
fromsuppliesequaltoorgreaterthan thatoftheADC.This
can allow the inputs to span the entire absolute maximum
of GND – 0.3V to VCC + 0.3V. Using a positive supply of
7.5V to 10V and a negative supply of –2.5 to –5V gives the
amplifier plenty of headroom over the LTC2445/LTC2449
input range.
√(82nV)2 + (200nV)2 = 216nV.
In this way, the digital filter with its variable oversampling
ratio can greatly reduce the effects of external noise
sources.
4.5V TO 5.5V
1µF
28
2
V
BUSY
CC
LTC2448
REF
LTC1799
OUT
R
SET
29
30
8
35
38
37
36
+
+
REFERENCE
VOLTAGE
F
O
V
–
0.1µF
REF
SCK
SDO
CS
0.1V TO V
CC
3-WIRE
ANALOG INPUT
CH0
GND
SET
SPI INTERFACE
–0.5V
TO
REF
REF
9
CH1
0.5V
•
•
•
1,4,5,6,31,32,33
3
EXT
GND
DIV
NC
24448 F17
Figure 16. Simple External Clock Source
sn2444589 2444589fs
26
LTC2444/LTC2445/
LTC2448/LTC2449
U
PACKAGE DESCRIPTIO
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.20 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.20 ± 0.05 (2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
3.15 ± 0.10
0.435 0.18
(2 SIDES)
0.75 ± 0.05
5.00 ± 0.10
(2 SIDES)
37 38
0.18
0.00 – 0.05
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
0.23
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.40 ± 0.10
0.200 REF 0.25 ± 0.05
R = 0.115
TYP
(UH) QFN 0303
0.50 BSC
0.200 REF
0.75 ± 0.05
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
sn2444589 2444589fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
27
LTC2444/LTC2445/
LTC2448/LTC2449
U
TYPICAL APPLICATIO
External Buffers Provide High Impedance Inputs
and Amplifier Offsets are Cancelled
SDI
SCK
SDO
CS
LTC2449
CH0-CH15/
COM
HIGH
17
SPEED
MUX
∆Σ ADC
2
3
–
1
1/2 LT1368
0.22µF
+
(EXTERNAL AMPLIFIERS)
5V
6
8
–
7
1/2 LT1368
5
0.22µF
+
4
2444589 TA05
0V
RELATED PARTS
PART NUMBER
LT1025
DESCRIPTION
COMMENTS
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
No External Components 5µV Offset, 1.6µV Noise
P-P
LT1236A-5
LT1461
0.05% Max, 5ppm/°C Drift
Micropower Series Reference, 2.5V
Ultraprecise 16-Bit SoftSpanTM DAC
0.04% Max, 3ppm/°C Max Drift
Six Programmable Output Ranges
±1LSB DNL, 600µA, Internal Reference, SO-8
Single Resistor Frequency Set
LTC1592
LTC1655
16-Bit Rail-to-Rail Micropower DAC
LTC1799
Resistor Set SOT-23 Oscillator
LTC2053
Rail-to-Rail Instrumentation Amplifier
2-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC
1-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC
10µV Offset with 50nV/°C Drift, 2.5µV Noise 0.01Hz to 10Hz
P-P
LTC2412
0.16ppm Noise, 2ppm INL, 200µA
LTC2415
0.23ppm Noise, 2ppm INL, 2X Speed Up
LTC2414/LTC2418
LTC2430/LTC2431
LTC2436-1
LTC2440
4-/8-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 200µA
1-Channel, Differential Input, 20-Bit, No Latency ∆Σ ADC
2-Channel, Differential Input, 16-Bit, No Latency ∆Σ ADC
0.56ppm Noise, 3ppm INL, 200µA
800nV Noise, 0.12LBS INL, 0.006LBS Offset, 200µA
RMS
1-Channel, Differential Input, High Speed/Low Noise,
24-Bit, No Latency ∆Σ ADC
2µV
Noise at 880Hz, 200nV
Noise at 6.9Hz,
RMS
RMS
0.0005% INL, Up to 3.5kHz Output Rate
SoftSpan is a trademark of Linear Technology Corporation.
sn2444589 2444589fs
LT/TP 0304 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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