LTC2462_技术文档

LTC2460/LTC2462

Ultra-Tiny, 16-Bit ΔΣ ADCs

with 10ppm/°C Max

Precision Reference

DESCRIPTION

FEATURES

The LTC^®2460/LTC2462 are ultra tiny, 16-Bit analog-to-

digital converters with an integrated precision reference.

They use a single 2.7V to 5.5V supply and communicate

through an SPI Interface. The LTC2460 is single-ended

with a 0V to V_REFinput range and the LTC2462 is dif-

ferential with a V_REFinput range. Both ADC’s include

a 1.25V integrated reference with 2ppm/°C drift per-

formance and 0.1% initial accuracy. The converters are

available in a 12-pin DFN 3mm × 3mm package or an

MSOP-12 package. They include an integrated oscillator

and perform conversions with no latency for multiplexed

applications. TheLTC2460/LTC2462includeaproprietary

input sampling scheme that reduces the average input

current several orders of magnitude when compared to

conventional delta sigma converters.

n

16-Bit Resolution, No Missing Codes

n

Internal Reference, High Accuracy 10ppm/°C (Max)

n

Single-Ended (LTC2460) or Differential (LTC2462)

n

2LSB Offset Error

0.01% Gain Error

60 Conversions Per Second

n

Single Conversion Settling Time for Multiplexed

Applications

n

Single-Cycle Operation with Auto Shutdown

n

1.5mA Supply Current

2μA (Max) Sleep Current

n

Internal Oscillator—No External Components

Required

SPI Interface

Ultra-Tiny 12-Lead 3mm × 3mm DFN and MSOP

Packages

n

Following a single conversion, the LTC2460/LTC2462

automatically power down the converter and can also be

conﬁgured to power down the reference. When both the

ADC and reference are powered down, the supply current

is reduced to 200nA.

APPLICATIONS

n

System Monitoring

n

Environmental Monitoring

n

Direct Temperature Measurements

The LTC2460/LTC2462 can sample at 60 conversions per

second, and due to the very large oversampling ratio,

have extremely relaxed antialiasing requirements. Both

includecontinuousinternaloffsetandfullscalecalibration

algorithmswhicharetransparenttotheuser, ensuringac-

curacy over time and the operating temperature range.

n

Instrumentation

n

Industrial Process Control

n

Data Acquisition

n

Embedded ADC Upgrades

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.

TYPICAL APPLICATION

V_REFvs Temperature

1.2520

2.7V TO 5.5V

1.2515

1.2510

1.2505

1.2500

1.2495

1.2490

1.2485

1.2480

0.1μF

COMP

0.1μF

10μF

0.1μF

10k

REFOUT

V

CC

+

–

IN

SCK

10k

SPI

INTERFACE

LTC2462

SDO

IN

CS

0.1μF

–

REF

GND

R

24602 TA01a

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24602 TA01b

24602f

1

LTC2460/LTC2462

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Storage Temperature Range................... –65°C to 150°C

Operating Temperature Range

CC

Analog Input Voltage

+

–

(IN , IN , IN, REF ,

LTC2460C/LTC2462C ............................... 0°C to 70°C

LTC2460I/LTC2462I.............................. –40°C to 85°C

COMP, REFOUT)............................ –0.3V to (V + 0.3V)

CC

Digital Voltage

(V , V , V , V )................. –0.3V to (V + 0.3V)

SDI SDO SCK CS

CC

PIN CONFIGURATION

LTC2462

TOP VIEW

1

2

3

4

5

6

V

12

CC

REFOUT

COMP

CS

1

2

3

4

5

6

REFOUT

COMP

CS

12 V

CC

11 GND

–

11 GND

IN

10

9

–

10 IN

+

SDI

SCK

SDO

9

8

7

IN

–

REF

8

REF

GND

SCK

7

GND

SDO

MS PACKAGE

DD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC DFN

= 125°C, θ = 43°C/W

12-LEAD PLASTIC MSOP

T

= 125°C, θ = 120°C/W

T

JMAX

JA

JMAX

JA

EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL

LTC2460

TOP VIEW

1

2

3

4

5

6

12

V

CC

REFOUT

COMP

CS

1

2

3

4

5

6

REFOUT

COMP

CS

12 V

CC

11 GND

10 GND

11 GND

GND

IN

10

9

SDI

SCK

SDO

9

8

7

IN

REF

GND

–

REF

8

SCK

7

GND

SDO

MS PACKAGE

DD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC DFN

= 125°C, θ = 43°C/W

12-LEAD PLASTIC MSOP

T

= 125°C, θ = 120°C/W

T

JMAX

JA

JMAX

JA

EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL

ORDER INFORMATION

LEAD FREE FINISH

LTC2460CDD#PBF

LTC2460IDD#PBF

LTC2460CMS#PBF

LTC2460IMS#PBF

LTC2462CDD#PBF

LTC2462IDD#PBF

LTC2462CMS#PBF

LTC2462IMS#PBF

TAPE AND REEL

PART MARKING*

LFDQ

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2460CDD#TRPBF

LTC2460IDD#TRPBF

LTC2460CMS#TRPBF

LTC2460IMS#TRPBF

LTC2462CDD#TRPBF

LTC2462IDD#TRPBF

LTC2462CMS#TRPBF

LTC2462IMS#TRPBF

12-Lead Plastic (3mm × 3mm) DFN

12-Lead Plastic MSOP-12

LFDQ

–40°C to 85°C

0°C to 70°C

2460

12-Lead Plastic MSOP-12

–40°C to 85°C

0°C to 70°C

LDXM

2462

12-Lead Plastic (3mm × 3mm) DFN

12-Lead Plastic MSOP-12

–40°C to 85°C

0°C to 70°C

2462

12-Lead Plastic MSOP-12

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

24602f

2

LTC2460/LTC2462

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

(Note 3)

MIN

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Nonlinearity

Offset Error

16

(Note 4)

1

10

LSB

2

LSB

Offset Error Drift

Gain Error

0.02

0.01

LSB/°C

l

Includes Contributions of ADC and Internal Reference

0.25 % of FS

Gain Error Drift

Includes Contributions of ADC and Internal Reference

C-Grade

I-Grade

l

2

5

10

ppm/°C

Transition Noise

2.2

80

μV

RMS

Power Supply Rejection DC

dB

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

ANALOG INPUTS

speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

LTC2462

MIN

0

TYP

MAX

UNITS

V

+

l

V

C

Positive Input Voltage Range

Negative Input Voltage Range

Input Voltage Range

V

REF

V

REF

V

REF

IN

–

LTC2462

0

V

LTC2460

0

V

+

–

+

–

+

–

, V

UR

, V

UR

Overrange/Underrange Voltage, IN

V

IN

V

IN

= 0.625V (See Figure 3)

8

LSB

pF

OR

IN

+

Overrange/Underrange Voltage, IN–

+

–

IN , IN , IN Sampling Capacitance

0.35

+

–

l

+

–

I

IN , IN DC Leakage Current (LTC2462)

IN DC Leakage Current (LTC2460)

V

= GND (Note 8)

–10

1

10

nA

DC_LEAK(IN , IN , IN)

IN

= V (Note 8)

CC

–

l

–

IN DC Leakage Current

V

= GND (Note 8)

–10

1

10

nA

DC_LEAK(IN )

IN

= V (Note 8)

CC

Input Sampling Current (Note 5)

Reference Output Voltage

50

nA

V

CONV

l

V

1.247

1.25

1.253

10

REF

Reference Voltage Coefﬁcient

(Note 11)

C-Grade

I-Grade

2

5

ppm/°C

Reference Line Regulation

2.7V ≤ V ≤ 5.5V

–90

dB

mA

CC

l

Reference Short Circuit Current

COMP Pin Short Circuit Current

Reference Load Regulation

Reference Output Noise Density

V

CC

V

CC

= 5.5, Forcing Output to GND

35

200

μA

2.7V ≤ V ≤ 5.5V, I

= 100ꢀA Sourcing

= 0.1ꢀF, At f = 1kHz

3.5

30

mV/mA

nV/√Hz

CC

OUT

C = 0.1ꢀF, C

COMP REFOUT

The l denotes the speciﬁcations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

2.7

5.5

V

CC

I

Supply Current

Conversion

Nap

CC

l

1.5

800

0.2

2.5

1500

2

mA

μA

Sleep

24602f

3

LTC2460/LTC2462

The l denotes the speciﬁcations which apply over the full

DIGITAL INPUTS AND DIGITAL OUTPUTS

operating temperature range,otherwise speciﬁcations are at T_A= 25°C. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

– 0.3

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

IH

IL

CC

0.3

10

V

I

IN

–10

μA

pF

V

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

10

IN

l

I = –800μA

O

– 0.5

CC

OH

OL

I = 1.6mA

O

0.4

10

V

I

OZ

–10

μA

TIMING CHARACTERISTICS _{The l denotes the speciﬁcations which apply over the full operating temperature}

range,otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

23

UNITS

ms

MHz

ns

l

t

f

t

Conversion Time

13

16.6

CONV

SCK

lSCK

hSCK

1

SCK Frequency Range

SCK Low Period

2

250

0

SCK High Period

ns

CS Falling Edge to SDO Low Z

CS Rising Edge to SDO High Z

CS Falling Edge to SCK Falling Edge

SCK Falling Edge to SDO Valid

SDI Setup Before SCK↑

SDI Hold After SCK↑

(Notes 7, 8)

100

ns

0

ns

2

100

0

ns

3

(Note 7)

(Note 3)

100

ns

KQ

4

100

ns

5

Guaranteed by design and test correlation.

Note 5: CS = V . A positive current is ﬂowing into the DUT pin.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

CC

Note 6: SCK = V or GND. SDO is high impedance.

CC

Note 7: See Figure 4.

Note 8: See Figure 5.

Note 9: Input sampling current is the average input current drawn from the

input sampling network while the LTC2460/LTC2462 is actively sampling

the input.

Note 10: A positive current is ﬂowing into the DUT pin.

Note 11: Temperature coefﬁcient is calculated by dividing the maximum

Note 2. All voltage values are with respect to GND. V = 2.7V to 5.5V

CC

unless otherwise speciﬁed.

V

= V /2, FS = V

REF REF

REFCM

+

–

+

–

= V – V , –V ≤ V ≤ V ; V

= (V + V )/2.

IN IN

IN

REF

IN

REF INCM

Note 3. Guaranteed by design, not subject to test.

Note 4. Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

change in output voltage by the speciﬁed temperature range.

24602f

4

LTC2460/LTC2462

TYPICAL PERFORMANCE CHARACTERISTICS (T_A= 25°C, unless otherwise noted)

Integral Nonlinearity

Maximum INL vs Temperature

3

2

3

2

3

2

V

= 5.5V, 4.1V, 2.7V

V

= 5.5V

V

= 2.7V

CC

T

A

= –45°C, 25°C, 90°C

T = –45°C, 25°C, 90°C

A

1

0

–1

–2

–3

–1

–2

–3

–1

–2

–3

–1.25

–0.75

–0.25

0.25

0.75

1.25

–1.25

–0.75

–0.25

0.25

0.75

1.25

–55 –35 –15

5

25 45 65 85 105 125

DIFFERENTIAL INPUT VOLTAGE (V)

TEMPERATURE (°C)

24602 G03

24602 G01

24602 G02

Offset Error vs Temperature

ADC Gain Error vs Temperature

Transition Noise vs Temperature

25

20

15

10

5

10

9

8

7

6

5

4

3

2

1

0

5

4

V

= 5.5V

CC

V

= 5.5V

CC

3

2

V

= 4.1V

CC

1

V

= 2.7V

0

CC

–1

–2

–3

–4

–5

V

= 4.1V

= 2.7V

CC

V

= 2.7V

= 5.5V

30

CC

V

CC

0

–50

–25

0

25

50

75

100

–50 –30 –10 10

50

70

90

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24602 G05

24602 G06

24602 G04

Conversion Mode Power Supply

Current vs Temperature

Sleep Mode Power Supply

Current vs Temperature

V

_REFvs Temperature

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

350

300

250

200

150

100

50

1.2508

1.2507

1.2506

1.2505

1.2504

1.2503

1.2502

V

= 5.5V

CC

V

= 5.5V

CC

V

= 4.1V

CC

V

= 2.7V

V

= 4.1V

CC

V

= 2.7V

30

CC

0

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

50

70

90

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24602 G07

24602 G08

24602 G09

24602f

5

LTC2460/LTC2462

TYPICAL PERFORMANCE CHARACTERISTICS (T_A= 25°C, unless otherwise noted)

Power Supply Rejection

vs Frequency at V_CC

Conversion Time vs Temperature

V_REFvs V_CC

0

–20

21

20

19

18

17

16

15

14

1.24892

1.24891

1.24890

1.24889

1.24888

1.24887

1.24886

1.24885

1.24884

T

= 25°C

A

–40

V

= 5V, 4.1V, 3V

CC

–60

–80

–100

–120

1

10 100 1k 10k 100k 1M 10M

–50

–25

0

25

50

75

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(V)

FREQUENCY AT V (Hz)

CC

TEMPERATURE (°C)

V

CC

24602 G10

24602 G11

24602 G12

PIN FUNCTIONS

REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,

this voltage sets the fullscale input range of the ADC. For

noise and reference stability connect to a 0.1μF capacitor

tied to GND. This capacitor value must be less than or

equal to the capacitor tied to the reference compensation

pin (COMP). REFOUT cannot be overdriven by an external

reference. For applications that require an input range

greater than 0V to 1.25V, please refer to the LTC2450/

LTC2452.

SDO (Pin 6): Three-State Serial Data Output. SDO is used

forserialdataoutputduringtheDATAINPUT/OUTPUTstate

and can be used to monitor the conversion status.

GND (Pins 7, 11): Ground. Connect directly to the ground

plane through a low impedance connection.

–

REF (Pin 8): Negative Reference Input to the ADC. The

voltage on this pin sets the zero input to the ADC. This

pin should tie directly to ground or the ground sense of

the input sensor.

COMP (Pin 2): Internal Reference Compensation Pin. For

low noise and reference stability, tie a 0.1ꢀF capacitor to

GND.

+

IN (LTC2462), IN (LTC2460) (Pin 9): Positive input volt-

age for the LTC2462 differential device. ADC input for the

LTC2460 single-ended device.

CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW

on this pin enables the SDO output. A HIGH on this pin

places the SDO output pin in a high impedance state and

any inputs on SDI and SCK will be ignored.

–

IN (LTC2462), GND (LTC2460) (Pin 10): Negative input

voltage for the LTC2462 differential device. GND for the

LTC2460 single-ended device.

V

(Pin 12): Positive Supply Voltage. Bypass to GND

SDI (Pin 4): Serial Data Input Pin. This pin is used to

program the sleep mode and 30Hz/60Hz output rate

(LTC2460).

CC

with a 10ꢀF capacitor in parallel with a low-series-induc-

tance 0.1ꢀF capacitor located as close to the device as

possible.

SCK (Pin 5): Serial Clock Input. SCK synchronizes the

serial data input/output. Once the conversion is complete,

a new data bit is produced at the SDO pin following each

SCK falling edge. Data is shifted into the SDI pin on each

rising edge of SCK.

Exposed Pad (Pin 13 – DFN Package): Ground. Connect

directly to the ground plane through a low impedance

connection.

24602f

6

LTC2460/LTC2462

BLOCK DIAGRAM

1

2

12

REFOUT

COMP

V

CC

3

CS

INTERNAL

REFERENCE

5

$3 A/D

CONVERTER

SPI

INTERFACE

SCK

9

+

IN

6

4

SDO

SDI

(IN)

DECIMATING

SINC FILTER

–

$3 A/D

CONVERTER

10

–

IN

INTERNAL

OSCILLATOR

(GND)

–

REF

GND

7,11,13 (DD PACKAGE)

8

24602 BD

( ) PARENTHESIS INDICATE LTC2460

Figure 1. Functional Block Diagram

APPLICATIONS INFORMATION

CONVERTER OPERATION

POWER-ON RESET

CONVERT

Converter Operation Cycle

The LTC2460/LTC2462 are low power, delta sigma, ana-

log to digital converters with a simple SPI interface (see

Figure 1). The LTC2462 has a fully differential input while

the LTC2460 is single-ended. Both are pin and software

compatible. Their operation is composed of three distinct

states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT.

The operation begins with the CONVERT state (see Fig-

ure 2).Oncetheconversionisﬁnished,theconverterauto-

matically powers down (NAP) or under user control, both

the converter and reference are powered down (SLEEP).

The conversion result is held in a static register while the

device is in this state. The cycle concludes with the DATA

INPUT/OUTPUTstate. Onceall16-bitsarereadoranabort

is initiated the device begins a new conversion.

SLEEP/NAP

NO

CS = LOW?

YES

DATA INPUT/OUTPUT

16TH FALLING

EDGE OF SCK

OR

NO

YES

24602 F02

CS = HIGH?

TheCONVERTstatedurationisdeterminedbytheLTC2460/

LTC2462 conversion time (nominally 16.6 milliseconds).

Oncestarted, thisoperationcannotbeabortedexceptbya

Figure 2. LTC2460/LTC2462 State Transition Diagram

low power supply condition (V < 2.1V) which generates

CC

While in the SLEEP/NAP state, when chip select input is

HIGH (CS = HIGH), the LTC2460/LTC2462’s converters

are powered down. This reduces the supply current by

approximately 50%. While in the Nap state the reference

remainspoweredup.Inordertopowerdownthereference

in addition to the converter, the user can select the SLEEP

an internal power-on reset signal.

Afterthecompletionofaconversion,theLTC2460/LTC2462

enters the SLEEP/NAP state and remains there until the

chip select is LOW (CS = LOW). Following this condition,

the ADC transitions into the DATA INPUT/OUTPUT state.

24602f

7

LTC2460/LTC2462

APPLICATIONS INFORMATION

mode during the DATA INPUT/OUTPUT state. Once the

next conversion is complete, the SLEEP state is entered

and power is reduced to less than 2ꢀA. The reference is

powered up once CS is brought low. The reference startup

timeis12ms(ifthereferenceandcompensationcapacitor

values are both 0.1ꢀF).

cycle. If SLP = 1, the reference powers down following

the next conversion cycle. The remaining 12 SDI input

bits are ignored (don’t care).

SDI may also be tied directly to GND or V in order to

DD

simplify the user interface. In the case of the LTC2460,

the 60Hz output rate is selected if SDI is tied low and

Upon entering the DATA INPUT/OUTPUT state, SDO

outputs the sign (D15) of the conversion result. During

this state, the ADC shifts the conversion result serially

through the SDO output pin under the control of the SCK

input pin. There is no latency in generating this data and

the result corresponds to the last completed conversion.

A new bit of data appears at the SDO pin following each

falling edge detected at the SCK input pin and appears

from MSB to LSB. The user can reliably latch this data

on every rising edge of the external serial clock signal

driving the SCK pin.

the 30Hz output rate is selected if SDI is tied to V . The

DD

LTC2462 output rate is always 60Hz independent of SDI

or SPD. The reference sleep mode is disabled for both

the LTC2460 and LTC2462 if SDI is tied to GND or V .

DD

The DATA INPUT/OUTPUT state concludes in one of two

differentways.First,theDATAINPUT/OUTPUTstateopera-

tion is completed once all 16 data bits have been shifted

out and the clock then goes low. This corresponds to the

th

16 falling edge of SCK. Second, the DATA INPUT/OUT-

PUT state can be aborted at any time by a LOW-to-HIGH

transition on the CS input. Following either one of these

twoactions,theLTC2460/LTC2462willentertheCONVERT

state and initiate a new conversion cycle.

During the DATA INPUT/OUTPUT state, the LTC2460/

LTC2462 can be programmed to SLEEP or NAP (default)

followingthenextconversioncycle.Dataisshiftedintothe

device through the SDI pin on the rising edge of SCK. The

input word is 4 bits. If the ﬁrst bit EN1 = 1 and the second

bit EN2 = 0 the device is enabled for programming. The

following two bits (SPD and SLP) will be written into the

device. SPD(onlyusedfortheLTC2460)toselectthe60Hz

output rate, no offset calibration mode (SPD = 0, default).

Set SPD = 1 for 30Hz mode with offset calibration. SPD

is ignored for the LTC2462. The next bit (SLP) enables

the sleep or nap mode. If SLP = 0 (default) the reference

remains powered up at the end of the next conversion

Power-Up Sequence

When the power supply voltage (V ) applied to the con-

CC

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

WhenV risesabovethiscriticalthreshold, theconverter

CC

generates an internal power-on reset (POR) signal for

approximately 0.5ms. The POR signal clears all internal

registers.FollowingthePORsignal,theLTC2460/LTC2462

startaconversioncycleandfollowthesuccessionofstates

shown in Figure 2. The reference startup time following a

20

16

12

8

POR is 12ms (C

= C

= 0.1ꢀF). The ﬁrst conver-

COMP

REFOUT

sion following powerup will be invalid since the reference

voltage has not completely settled. The ﬁrst conversion

following power up can be discarded using the data abort

command or simply read and ignored. The following con-

versions are accurate to the device speciﬁcations.

4

0

–4

SIGNALS

–8

BELOW

GND

–12

–16

–20

Ease of Use

The LTC2460/LTC2462 data output has no latency, ﬁlter

settling delay or redundant results associated with the

conversion cycle. There is a one-to-one correspondence

–0.001 –0.005

0

V

0.005 0.001 0.0015

+

/V

IN REF

24602 F03

Figure 3. Output Code vs V_IN⁺with V_IN^–= 0 (LTC2462)

between the conversion and the output data. Therefore,

24602f

8

LTC2460/LTC2462

APPLICATIONS INFORMATION

multiplexing multiple analog input voltages requires no

special actions.

Input Voltage Range (LTC2462)

AsmentionedintheOutputDataFormatsection,theoutput

+

–

The LTC2460/LTC2462 perform offset calibrations every

conversion. This calibration is transparent to the user

and has no effect upon the cyclic operation described

previously. The advantage of continuous calibration is

stability of the ADC performance with respect to time and

temperature.

code is given as 32768 • (V – V )/V + 32768. For

IN

REF

+

–

(V – V ) ≥ V , the output code is clamped at 65535

(all ones). For (V – V ) ≤ –V , the output code is

IN

REF

IN

+

–

IN

REF

clamped at 0 (all zeroes).

The LTC2462 includes a proprietary architecture that

can, typically, digitize each input up to 8 LSBs above V

REF

TheLTC2460/LTC2462includeaproprietaryinputsampling

scheme that reduces the average input current by several

orders of magnitude when compared to traditional delta-

sigma architectures. This allows external ﬁlter networks

to interface directly to the LTC2460/LTC2462. Since the

average input sampling current is 50nA, an external RC

lowpass ﬁlter using 1kΩ and 0.1μF results in <1LSB

additional error. Additionally, there is negligible leakage

and below GND, if the differential input is within V

.

REF

As an example (Figure 3), if the user desires to measure

–

a signal slightly below ground, the user could set V

IN

+

= GND, and V = 1.25V. If V = GND, the output code

would be approximately 32768. If V = GND – 8LSB =

REF

IN

+

IN

–0.305mV,theoutputcodewouldbeapproximately32760.

For applications that require an input range greater than

1.25V, please refer to the LTC2452.

+

–

current between IN and IN .

Output Data Format

Input Voltage Range (LTC2460)

The LTC2460/LTC2462 generates a 16-bit direct binary

encoded result. It is provided as a 16-bit serial stream

through the SDO output pin under the control of the SCK

input pin (see Figure 4).

Ignoring offset and full-scale errors, the LTC2460 will

theoretically output an “all zero” digital result when the

input is at ground (a zero scale input) and an “all one”

digital result when the input is at V (V

= 1.25V).

The LTC2462 (differential input) output code is given by

REF REFOUT

+

–

In an under-range condition, for all input voltages below

zeroscale,theconverterwillgeneratetheoutputcode0.In

an over-range condition, for all input voltages greater than

32768 • (V – V )/V

+ 32768. The ﬁrst bit output

IN

REF

+

by the LTC2462, D15, is the MSB, which is 1 for V

≥

IN

–

+

–

V

and 0 for V < V . This bit is followed by succes-

IN

IN IN

V

, the converter will generate the output code 65535.

sively less signiﬁcant bits (D14, D13, …) until the LSB is

REF

For applications that require an input range greater than

output by the LTC2462, see Table 1.

0V to 1.25V, please refer to the LTC2450.

t

3

t

2

t

1

CS

D

7

D

6

D

3

D

1

D

0

15

14

13

12

11

10

9

8

5

4

2

MSB

LSB

SDO

SCK

t

hSCK

KQ

lSCK

EN1

EN2

SPD* SLP

DON’T CARE

SDI

24602 F04

t

5

t

6

*SPD IS A DON’T CARE BIT FOR THE LTC2462

Figure 4. Data Input/Output Timing

24602f

9

LTC2460/LTC2462

APPLICATIONS INFORMATION

Table 1. LTC2460/LTC2462 Output Data Format

SINGLE ENDED INPUT V

(LTC2460)

DIFFERENTIAL INPUT VOLTAGE

D15

(MSB)

D14

D13

D12...D2

D1

D0

(LSB)

CORRESPONDING

DECIMAL VALUE

IN

+

–

V

– V (LTC2462)

IN

≥V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

65535

65534

49152

49151

32768

32767

16384

16383

0

REF

V

– 1LSB

V

– 1LSB

REF

0.75 • V

0.5 • V

REF

0.75 • V – 1LSB

0.5 • V – 1LSB

REF

0.5 • V

0

REF

0.5 • V – 1LSB

–1LSB

REF

0.25 • V

–0.5 • V

REF

0.25 • V – 1LSB

–0.5 • V – 1LSB

REF

0

≤ –V

REF

The LTC2460 (single-ended input) output code is a direct

binary encoded result, see Table 1.

the next conversion is complete. It will remain powered

down until CS is pulled low. The reference startup time is

approximately 12ms. In order to ensure a stable reference

for the following conversions, either the data input/output

time should be delayed 12ms after CS goes low or the

ﬁrst conversion following a reference start up should be

discarded. If SDI is tied HIGH (LTC2460 operating in 30Hz

mode) the SLP mode is disabled.

During the data output operation the CS input pin must

be pulled low (CS = LOW). The data output process starts

with the most signiﬁcant bit of the result being present at

the SDO output pin (SDO = D15) once CS goes low. A new

data bit appears at the SDO output pin after each falling

edge detected at the SCK input pin. The output data can

be reliably latched on the rising edge of SCK.

Conversion Status Monitor

Data Input Format

For certain applications, the user may wish to monitor the

LTC2460/LTC2462conversionstatus.Thiscanbeachieved

by holding SCK HIGH during the conversion cycle. In

this condition, whenever the CS input pin is pulled low

(CS = LOW), the SDO output pin will provide an indication

of the conversion status. SDO = HIGH is an indication of

a conversion cycle in progress while SDO = LOW is an

indication of a completed conversion cycle. An example

of such a sequence is shown in Figure 5.

The data input word is 4 bits long and consists of two

enable bits (EN1 and EN2) and two programming bits

(SPD and SLP). EN1 is applied to the ﬁrst rising edge of

SCK after the conversion is complete. Programming is

enabled by setting EN1 = 1 and EN2 = 0.

The speed bit (SPD) is only used by the LTC2460. In the

default mode, SPD = 0, the output rate is 60Hz and con-

tinuousbackgroundoffsetcalibrationisnotperformed. By

changing the SPD bit to 1, background offset calibration is

performed and the output rate is reduced to 30Hz. Alterna-

Conversion status monitoring, while possible, is not re-

quired for the LTC2460/LTC2462 as its conversion time is

ﬁxed and typically 16.6ms (23ms maximum). Therefore,

externaltimingcanbeusedtodeterminethecompletionofa

conversion cycle.

tively, SDI can be tied directly to ground (SPD = 0) or V

CC

(SPD = 1), eliminating the need to program the device. The

LTC2462 data output rate is always 60Hz and background

offset calibration is performed (SPD = don’t care).

SERIAL INTERFACE

The sleep bit (SLP) is used to power down the on chip

reference. In the default mode, the reference remains

powered up even when the ADC is powered down. If the

SLP bit is set HIGH, the reference will power down after

The LTC2460/LTC2462 transmit the conversion result

and receive the start of conversion command through

a synchronous 2-, 3- or 4-wire interface. This interface

24602f

10

LTC2460/LTC2462

APPLICATIONS INFORMATION

t

1

t

2

CS

SDO

SDI = LOW

SCK = HIGH

CONVERT

NAP

24602 F05

Figure 5. Conversion Status Monitoring Mode

can be used during the CONVERT and SLEEP states to

assess the conversion status and during the DATA OUT-

PUT state to read the conversion result, and to trigger a

new conversion.

4) When SCK = HIGH, it is possible to monitor the conver-

sion status by pulling CS low and watching for SDO to

go low. This feature is available only in the idle-high

(CPOL = 1) mode.

Serial Interface Operation Modes

Serial Clock Idle-High (CPOL = 1) Examples

The modes of operation can be summarized as follows:

In Figure 6, following a conversion cycle the LTC2460/

LTC2462 automatically enter the NAP mode with the ADC

powereddown.TheADC’sreferencewillpowerdownifthe

SLPbitwassethighpriortothejustcompletedconversion

and CS is HIGH. Once CS goes low, the device powers up.

The user can monitor the conversion status at convenient

intervals using CS and SDO.

1) The LTC2460/LTC2462 function with SCK idle high

(commonly known as CPOL = 1) or idle low (commonly

known as CPOL = 0).

2) After the 16th bit is read, a new conversion is started

if CS is pulled high or SCK is pulled low.

3) At any time during the Data Output state, pulling CS

high causes the part to leave the I/O state, abort the

output and begin a new conversion.

Pulling CS LOW while SCK is HIGH tests whether

or not the chip is in the CONVERT state. While in

the CONVERT state, SDO is HIGH while CS is LOW.

Once the conversion is complete, SDO is LOW

CS

D

15

D

14

D

13

D

12

D

2

D

1

D

0

SD0

SCK

clk

1

clk

2

clk

3

clk

4

clk

15

clk

16

EN1

EN2

SPD

SLP

DATA OUTPUT

SDI

CONVERT

NAP

CONVERT

24602 F06

Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.

The Rising Edge of CS Starts a New Conversion

24602f

11

LTC2460/LTC2462

APPLICATIONS INFORMATION

while CS is LOW. These tests are not required op-

erational steps but may be useful for some applications.

ThetimingdiagraminFigure9isidenticaltothatofFigure 8,

except in this case a new conversion is triggered by SCK.

The 16th SCK falling edge triggers a new conversion cycle

and the CS signal is subsequently pulled high.

Whenthedataisavailable, theuserapplies16clockcycles

to transfer the result. The CS rising edge is then used to

initiate a new conversion.

Examples of Aborting Cycle using CS

The operation example of Figure 7 is identical to that of

Figure 6, except the new conversion cycle is triggered by

the falling edge of the serial clock (SCK).

For some applications, the user may wish to abort the I/O

cycleandbeginanewconversion.IftheLTC2460/LTC2462

are in the data output state, a CS rising edge clears the

remainingdatabitsfromtheoutputregister,abortstheout-

put cycle and triggers a new conversion. Figure 10 shows

an example of aborting an I/O with idle-high (CPOL = 1)

and Figure 11 shows an example of aborting an I/O with

idle-low (CPOL = 0).

Serial Clock Idle-Low (CPOL = 0) Examples

In Figure 8, following a conversion cycle the LTC2460/

LTC2462 automatically enters the NAP state. The device

reference will power down if the SLP bit was set high

prior to the just completed conversion and CS is HIGH.

Once CS goes low, the reference powers up. The user

determines data availability (and the end of conversion)

based upon external timing. The user then pulls CS low

(CS = ↓) and uses 16 clock cycles to transfer the result.

Followingthe16thrisingedgeoftheclock,CSispulledhigh

(CS = ↑), which triggers a new conversion.

A new conversion cycle can be triggered using the CS

signal without having to generate any serial clock pulses

as shown in Figure 12. If SCK is maintained at a low logic

level, after the end of a conversion cycle, a new conver-

sion operation can be triggered by pulling CS low and

then high. When CS is pulled low (CS = LOW), SDO will

CS

D

14

D

12

D

2

D

1

D

0

15

13

SD0

SCK

clk

3

clk

17

1

2

4

15

16

EN1

EN2

SPD

SLP

DATA OUTPUT

SDI

CONVERT

NAP

CONVERT

24602 F07

Figure 7. Idle-High (CPOL = 1) Clock Operation Example.

A 17th Clock Pulse is Used to Trigger a New Conversion Cycle

CS

D

13

D

12

D

1

D

0

15

14

2

SD0

SCK

clk

1

clk

clk clk

clk

16

2

3

4

14

15

EN1

EN2

SPD

SLP

DATA OUTPUT

SDI

CONVERT

NAP

CONVERT

24602 F08

Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion

24602f

12

LTC2460/LTC2462

APPLICATIONS INFORMATION

CS

D

1

D

0

15

14

13

12

2

SD0

SCK

clk

2

clk

3

clk

16

1

4

14

15

EN1

EN2

SPD

SLP

DATA OUTPUT

SDI

CONVERT

NAP

CONVERT

24602 F09

Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion

CS

D

13

15

14

SD0

SCK

clk

4

1

2

3

EN1

EN2

SPD

SLP

SDI

CONVERT

NAP

DATA OUTPUT

CONVERT

24602 F10

Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example

CS

D

13

15

14

SD0

SCK

clk

1

clk

3

2

EN1

EN2

SPD

SLP

SDI

CONVERT

NAP

DATA OUTPUT

CONVERT

24602 F11

Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example

CS

D

15

SD0

SDI = DON’T CARE

SCK = LOW

CONVERT

NAP

DATA OUTPUT

CONVERT

24602 F12

Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example

24602f

13

LTC2460/LTC2462

APPLICATIONS INFORMATION

output the sign (D15) of the result of the just completed

conversion. While a low logic level is maintained at SCK

pin and CS is subsequently pulled high (CS = HIGH) the

remaining 15 bits of the result (D14:D0) are discarded

and a new conversion cycle starts.

Figure 13 shows a 2-wire operation sequence which uses

anidle-high(CPOL=1)serialclocksignal. Theconversion

status can be monitored at the SDO output. Following a

conversion cycle, the ADC enters the data output state

and the SDO output transitions from HIGH to LOW. Sub-

sequently 16 clock pulses are applied to the SCK input in

order to serially shift the 16 bit result. Finally, the 17th

clock pulse is applied to the SCK input in order to trigger

a new conversion cycle.

Following the aborted I/O, additional clock pulses in the

CONVERT state are acceptable, but excessive signal tran-

sitions on SCK can potentially create noise on the ADC

during the conversion, and thus may negatively inﬂuence

the conversion accuracy.

Figure 14 shows a 2-wire operation sequence which uses

an idle-low (CPOL = 0) serial clock signal. The conversion

status cannot be monitored at the SDO output. Following

aconversioncycle,theLTC2460/LTC2462enterstheDATA

OUTPUT state. At this moment the SDO pin outputs the

sign (D15) of the conversion result. The user must use

externaltiminginordertodeterminetheendofconversion

and result availability. Subsequently 16 clock pulses are

applied to SCK in order to serially shift the 16-bit result.

The 16th clock falling edge triggers a new conversion

cycle. For the LTC2460 tie SDI LOW for 60Hz output rate

and HIGH for 30Hz output rate.

2-Wire Operation

The 2-wire operation modes, while reducing the number

of required control signals, should be used only if the

LTC2460/LTC2462 low power sleep capability is not re-

quired. In addition the option to abort serial data transfers

is no longer available. Hardwire CS to GND for 2-wire

operation. For the LTC2460, tie SDI LOW for 60Hz output

rate and HIGH for 30Hz output rate, for the LTC2462 tie

SDI low.

CS = LOW

D

4

D

0

15

14

13

12

2

1

SD0

SCK

clk

17

1

2

3

15

16

CONVERT

DATA OUTPUT

CONVERT

SDI = 0 OR 1

24602 F13

Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example

CS = LOW

SD0

D

14

D

2

D

0

15

13

12

1

SCK

clk

2

clk

clk clk

clk

15

clk

16

1

3

4

14

CONVERT

DATA OUTPUT

CONVERT

SDI = 0 OR 1

24602 F14

Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example

24602f

14

LTC2460/LTC2462

APPLICATIONS INFORMATION

PRESERVING THE CONVERTER ACCURACY

passing through these two decoupling capacitors, and

returningtotheconverterGNDpin.Theareaencompassed

by this circuit path, as well as the path length, should be

minimized.

TheLTC2460/LTC2462aredesignedtominimizetheconver-

sion result’s sensitivity to device decoupling, PCB layout,

antialiasingcircuits,lineandfrequencyperturbations.Nev-

ertheless, inordertopreservethehighaccuracycapability

of this part, some simple precautions are desirable.

–

As shown in Figure 15, REF is used as the negative refer-

ence voltage input to the ADC. This pin can be tied directly

to ground or kelvined to sensor ground. In the case where

–

Digital Signal Levels

REF is used as a sense input, it should be bypassed to

ground with a 0.1ꢀF ceramic capacitor in parallel with a

10ꢀF low ESR ceramic capacitor.

DuetothenatureofCMOSlogic,itisadvisabletokeepinput

digital signals near GND or V . Voltages in the range of

CC

0.5V to V – 0.5V may result in additional current leakage

CC

Very low impedance ground and power planes, and star

from the part. Undershoot and overshoot should also be

minimized, particularly while the chip is converting. It is

thus beneﬁcial to keep edge rates of about 10ns and limit

overshoot and undershoot to less than 0.3V.

connections at both V and GND pins, are preferable.

CC

The V pin should have two distinct connections: the

CC

ﬁrst to the decoupling capacitors described above, and

the second to the ground return for the power supply

voltage source.

Noisy external circuitry can potentially impact the output

under 2-wire operation. In particular, it is possible to get

the LTC2460/LTC2462 into an unknown state if an SCK

pulse is missed or noise triggers an extra SCK pulse.

In this situation, it is impossible to distinguish SDO = 1

(indicating conversion in progress) from valid “1” data

bits. As such, CPOL = 1 is recommended for the 2-wire

mode. The user should look for SDO = 0 before reading

data, and look for SDO = 1 after reading data. If SDO does

not return a “0” within the maximum conversion time (or

return a “1” after a full data read), generate 16 SCK pulses

to force a new conversion.

REFOUT and COMP

The on chip 1.25V reference is internally tied to the

converter’s reference input and is output to the REFOUT

INTERNAL

V

CC

REFERENCE

R

SW

15k

I

LEAK

(TYP)

REFOUT

R

SW

15k

Driving V and GND

I

LEAK

CC

(TYP)

+

IN

InrelationtotheV andGNDpins, the LTC2460/LTC2462

CC

LEAK

combinesinternalhighfrequencydecouplingwithdamping

elements, which reduce the ADC performance sensitivity

to PCB layout and external components. Nevertheless,

the very high accuracy of this converter is best pre-

served by careful low and high frequency power supply

decoupling.

C

EQ

R

SW

0.35pF

(TYP)

15k

I

LEAK

(TYP)

–

IN

LEAK

A 0.1μF, high quality, ceramic capacitor in parallel with

a 10μF low ESR ceramic capacitor should be connected

R

SW

15k

I

LEAK

(TYP)

24602 F15

–

REF

between the V and GND pins, as close as possible to the

CC

LEAK

package. The 0.1μF capacitor should be placed closest

to the ADC package. It is also desirable to avoid any via

in the circuit path, starting from the converter V pin,

Figure 15. LTC2460/LTC2462 Analog Input/Reference

Equivalent Circuit

CC

24602f

15

LTC2460/LTC2462

APPLICATIONS INFORMATION

pin. A 0.1ꢀF capacitor should be placed on the REFOUT

pin.Itispossibletoreducethiscapacitor,butthetransition

noise increases. A 0.1ꢀF capacitor should also be placed

on the COMP pin. This pin is tied to an internal point in the

referenceandisusedforstability.Inorderforthereference

to remain stable the capacitor placed on the COMP pin

must be greater than or equal to the capacitor tied to the

REFOUT pin. The REFOUT pin cannot be overridden by an

external voltage. If a reference voltage greater than 1.25V

is required, the LTC2450/LTC2452 should be used.

input parasitic capacitance C . Depending on the PCB

PAR

layout, C

has typical values between 2pF and 15pF. In

PAR

addition, the equivalent circuit of Figure 16 includes the

converter equivalent internal resistor R and sampling

SW

capacitor C .

EQ

V

CC

IN

R

SW

(LTC2460)

15k

I

LEAK

R

S

(TYP)

+

IN

(LTC2462)

I

LEAK

+

C

IN

EQ

SIG

I

CONV

–

0.35pF

(TYP)

C

PAR

DependingonthesizeofthecapacitorstiedtotheREFOUT

and COMP pins, the internal reference has a correspond-

ing start up time. This start up time is typically 12ms

when 0.1ꢀF capacitors are used. At initial power up, the

ﬁrst conversion result can be aborted or ignored. At the

completion of this ﬁrst conversion, the reference has

settled and all subsequent conversions are valid.

V

CC

R

SW

15k

I

LEAK

R

S

(TYP)

–

IN

(LTC2462)

LEAK

–

+

C

IN

C

SIG

EQ

CONV

–

0.35pF

(TYP)

C

PAR

24602 F16

Figure 16. LTC2460/LTC2462 Input Drive Equivalent Circuit

If the reference is put to sleep (program SLP = 1 and

CS = 1) the reference is powered down after the next

conversion. This conversion result is valid. On CS falling

edge, the reference is powered up. In order to ensure the

reference output has settled before the next conversion,

the power up time can be extended by delaying the data

read 12ms after the falling edge of CS. Once all 16 bits

are read from the device or CS is brought HIGH, the next

conversion automatically begins. In the default operation,

the reference remains powered up at the conclusion of the

conversion cycle.

Therearesomeimmediatetrade-offsinR andC without

S

IN

needing a full circuit analysis. Increasing R and C can

S

IN

give the following beneﬁts:

1) DuetotheLTC2460/LTC2462’sinputsamplingalgorithm,

+

–

the input current drawn by either V or V over a

IN

conversion cycle is typically 50nA. A high R • C at-

S

IN

tenuates the high frequency components of the input

current, and R values up to 1k result in <1LSB error.

S

2) The bandwidth from V is reduced at the input pins

SIG

+

–

(IN , IN or IN). This bandwidth reduction isolates the

ADCfromhighfrequencysignals, andassuchprovides

simple antialiasing and input noise reduction.

+

–

Driving V and V

IN

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 16. The input signal V is

SIG

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

+

–

connected to the ADC input pins (IN and IN ) through an

equivalentsourceresistanceR .Thisresistorincludesboth

S

4) A large C gives a better AC ground at the input pins,

the actual generator source resistance and any additional

IN

helping reduce reﬂections back to the signal source.

optional resistors connected to the input pins. Optional

input capacitors C are also connected to the ADC input

IN

5) Increasing R protects the ADC by limiting the current

S

pins. This capacitor is placed in parallel with the ADC

during an outside-the-rails fault condition.

24602f

16

LTC2460/LTC2462

APPLICATIONS INFORMATION

There is a limit to how large R • C should be for a given

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

S

IN

application. Increasing R beyond a given point increases

S

the voltage drop across R due to the input current,

on. The resultant INL vs V is shown in Figure 18. The

S

IN

to the point that signiﬁcant measurement errors exist.

measurements of Figure 18 include a capacitor C

cor-

PAR

Additionally, forsomeapplications, increasingtheR •C

respondingtoaminimumsizedlayoutpadandaminimum

width input trace of about 1 inch length.

S

IN

product too much may unacceptably attenuate the signal

at frequencies of interest.

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

For most applications, it is desirable to implement C as

IN

a high-quality 0.1μF ceramic capacitor and R ≤ 1k. This

S

1

The LTC2460/LTC2462 include a sinc type digital ﬁlter

capacitor should be located as close as possible to the

with the ﬁrst notch located at f = 60Hz. As such, the

actualV packagepin.Furthermore,theareaencompassed

0

IN

3dB input signal bandwidth is 26.54Hz. The calculated

LTC2460/LTC2462 input signal attenuation vs frequency

over a wide frequency range is shown in Figure 19. The

calculated LTC2460/LTC2462 input signal attenuation vs

frequency at low frequencies is shown in Figure 20. The

by this circuit path, as well as the path length, should be

minimized.

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split R and place series

S

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

converter noise level is about 2.2μV

and can be mod-

RMS

eled by a white noise source connected at the input of a

noise-free converter.

Figure 17 shows the measured LTC2462 INL vs Input

On a related note, the LTC2462 uses two separate A/D

converters to digitize the positive and negative inputs.

Voltage as a function of R value with an input capacitor

S

C = 0.1μF.

IN

Each of these A/D converters has 2.2μV

transition

RMS

Insomecases,R canbeincreasedabovetheseguidelines.

noise. If one of the input voltages is within this small

transition noise band, then the output will ﬂuctuate one

bit, regardless of the value of the other input voltage. If

both of the input voltages are within their transition noise

bands, the output can ﬂuctuate 2 bits.

S

The input current is zero when the ADC is either in sleep

or I/O modes. Thus, if the time constant of the input RC

circuit τ = R • C , is of the same order of magnitude or

S

IN

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

Forasimplesystemnoiseanalysis,theV drivecircuitcan

IN

be modeled as a single-pole equivalent circuit character-

These considerations need to be balanced out by the input

ized by a pole location f and a noise spectral density n .

i

signal bandwidth. The 3dB bandwidth ≈ 1/(2πR C ).

If the converter has an unlimited bandwidth, or at least a

S IN

bandwidth substantially larger than f , then the total noise

i

Finally, if the recommended choice for C is unacceptable

IN

contribution of the external drive circuit would be:

fortheuser’sspeciﬁcapplication,analternatestrategyisto

eliminateC andminimizeC andR .Inpracticalterms,

IN

PAR

S

V_n= n_iπ /2• f_i

thisconﬁgurationcorrespondstoalowimpedancesensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

Then, the total system noise level can be estimated as

2

the square root of the sum of (V ) and the square of the

n

2

LTC2460/LTC2462 noise ﬂoor (~2.2μV ).

24602f

17

LTC2460/LTC2462

APPLICATIONS INFORMATION

3

2

C

V

T

= 0.1μF

= 5V

C

V

T

= 0

IN

CC

= 25°C

IN

CC

A

= 5V

= 25°C

2

1

A

R

= 10k

R = 10k

S

1

R

= 1k

S

R

S

= 0k

0

R

= 0k

R

= 1k

S

–1

–2

–3

–1

–2

–3

–1.25

–0.75

–0.25

0.25

0.75

1.25

–1.25

–0.75

–0.25

0.25

0.75

1.25

DIFFERENTIAL INPUT VOLTAGE (V)

24602 F17

24602 F18

Figure 17. Measured INL vs Input Voltage

Figure 18. Measured INL vs Input Voltage

0

–20

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–40

–60

–80

–100

0

5.0

7.5

1.00 1.25 1.50

2.5

0

60 120 180 240 300 360 420 480 540 600

INPUT SIGNAL FREQUENCY (Hz)

INPUT SIGNAL FREQUENCY (MHz)

24602 F19

24602 F20

Figure 19. LTC2462 Input Signal Attentuation vs Frequency

Figure 20. LTC2462 Input Signal Attenuation

vs Frequency (Low Frequencies)

24602f

18

LTC2460/LTC2462

PACKAGE DESCRIPTION

DD Package

12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

R = 0.115

0.40 0.10

TYP

7

12

0.70 0.05

2.38 0.10

1.65 0.10

2.38 0.05

1.65 0.05

3.50 0.05

2.10 0.05

3.00 0.10

(4 SIDES)

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.20 OR

0.25 s 45°

CHAMFER

PIN 1

TOP MARK

(SEE NOTE 6)

6

1

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.45 BSC

2.25 REF

(DD12) DFN 0106 REV A

2.25 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev Ø)

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.889 p 0.127

(.035 p .005)

0.406 p 0.076

(.016 p .003)

REF

12 11 10 9 8 7

DETAIL “A”

0o – 6o TYP

3.00 p 0.102

(.118 p .004)

(NOTE 4)

5.23

4.90 p 0.152

(.193 p .006)

0.254

(.010)

3.20 – 3.45

(.206)

(.126 – .136)

MIN

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1

2 3 4 5 6

0.65

(.0256)

BSC

0.42 p 0.038

(.0165 p .0015)

TYP

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

RECOMMENDED SOLDER PAD LAYOUT

0.22 – 0.38

(.009 – .015)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MS12) 1107 REV Ø

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

24602f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC2460/LTC2462

TYPICAL APPLICATION

10μF

+

V

CC

V

CC

0.1μF

1μF

1

2

10V

5V

SCK SDO

CS

μC

1

12

U1*

6

4

7

5

CS

3

5

REFOUT

V

1k

CC

CS

10

9

+

–

SCK/SCL

MOSI/SDA

MISO/SDO

IN

SCK

LTC2462

0.1μF

1k

6

4

SDO

SDI

–

IN

GND GND GND

–

COMP REF GND

0.1μF

3

8

13

2

8

7, 11

0.1μF

24602 TA02

RELATED PARTS

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DESCRIPTION

COMMENTS

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RMS

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LTC2481

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LTC2484

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Easy-Drive Input Current Cancellation, 600nV

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Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp

550nV Noise, 125μV Offset Max

P-P

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input

Range

2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,

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LTC2450-1

LTC2451

LTC2452

LTC2453

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input

Range

2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

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2

Easy-to-Use, Ultra-Tiny 16-Bit ADC, I C, 0V to 5.5V Input

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Package, Programmable 30Hz/60Hz Output Rates

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2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

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2

Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I C, 5.5V

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

Input Range

No Latency ΔΣ is a trademark of Linear Technology Corporation.

24602f

LT 0409 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2462
厂家：	Linear
描述：	Ultra-Tiny, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference 超纤巧， 16位ΔΣ ADC，具有10ppm的/ ° C（最大值）精密基准
文件：	总20页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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