LTC2481CDD#PBF [Linear]
LTC2481 - 16-Bit Delta Sigma ADC with Easy Drive Input Current Cancellation and I<sup>2</sup>C Interface; Package: DFN; Pins: 10; Temperature Range: 0°C to 70°C;
| 型号： | LTC2481CDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2481 - 16-Bit Delta Sigma ADC with Easy Drive Input Current Cancellation and I<sup>2</sup>C Interface; Package: DFN; Pins: 10; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总40页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2481
16-Bit ∆Σ ADC with Easy Drive
Input Current Cancellation
2
and I C Interface
FeaTures
DescripTion
®
™
™
n
Easy Drive Technology Enables Rail-to-Rail Inputs
TheLTC 2481combinesa16-bitplussignNoLatency∆Σ
with Zero Differential Input Current
analog-to-digital converter with patented Easy Drive
2
n
Directly Digitizes High Impedance Sensors with
technologyandI Cdigitalinterface.Thepatentedsampling
Full Accuracy
Programmable Gain from 1 to 256
scheme eliminates dynamic input current errors and the
shortcomings of on-chip buffering through automatic
cancellation of differential input current. This allows large
externalsourceimpedancesandinputsignals,withrail-to-
rail input range to be directly digitized while maintaining
exceptional DC accuracy.
n
n
GND to V Input/Reference Common Mode Range
CC
2
n
2-Wire I C Interface
n
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
n
2ppm (0.25LSB) INL, No Missing Codes
The LTC2481 includes on-chip programmable gain and
an oscillator. The LTC2481 can be configured through an
n
1ppm Offset and 15ppm Full-Scale Error
n
Selectable 2x Speed Mode
2
I C interface to provide a programmable gain from 1 to
n
No Latency: Digital Filter Settles in a Single Cycle
256 in 8 steps, to digitize an external signal or internal
temperaturesensor, rejectlinefrequencies(50Hz, 60Hzor
simultaneous 50Hz/60Hz) as well as a 2x speed-up mode.
n
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
n
n
Six Addresses Available and One Global Address for
The LTC2481 allows a wide common mode input range
Synchronization
n
(0V to V ) independent of the reference voltage. The
Available in a Tiny (3mm × 3mm) 10-Lead DFN Package
CC
reference can be as low as 100mV or can be tied directly
applicaTions
to V . The LTC2481 includes an on-chip trimmed oscil-
CC
n
lator eliminating the need for external crystals or oscil-
lators. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
Direct Sensor Digitizer
n
Weight Scales
n
Direct Temperature Measurement
n
Strain Gauge Transducers
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents Pending.
Instrumentation
n
Industrial Process Control
n
DVMs and Meters
Typical applicaTion
+FS Error vs RSOURCE at IN+ and IN–
80
V
V
V
V
= 5V
CC
V
CC
= 5V
REF
60
40
20
+
= 3.75V
= 1.25V
IN
–
IN
1µF
0.1µF
f
= GND
O
T
= 25°C
A
SCL
SDA
+
10k
2-WIRE
I C INTERFACE
I
= 0
REF
LTC2481
GND
V
C
= 1µF
IN
DIFF
CC
+
2
V
0
IN
SENSE
CA0/f
CA1
–20
0
6 ADDRESSES
–
V
IN
–
–40
–60
–80
REF
10k
2481 TA01a
0.1µF
1
10
100
10k
100k
1k
(Ω)
2481 TA01b
R
SOURCE
2481fd
1
For more information www.linear.com/LTC2481
LTC2481
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltage (V ) to GND...................... –0.3V to 6V
CC
+
Analog Input Voltage to GND ....... –0.3V to (V + 0.3V)
REF
1
2
3
4
5
10 CA0/f
0
CC
V
9
8
7
6
CA1
GND
SDA
SCL
CC
–
Reference Input Voltage to GND .. –0.3V to (V + 0.3V)
CC
11
REF
IN
Digital Input Voltage to GND ....... –0.3V to (V + 0.3V)
CC
+
–
Digital Output Voltage to GND...... –0.3V to (V + 0.3V)
CC
IN
Operating Temperature Range
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
LTC2481C.................................................... 0°C to 70°C
LTC2481I .................................................–40°C to 85°C
LTC2481H .............................................. –40°C to 125°C
Storage Temperature Range ................. –65°C to 125°C
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2481CDD#PBF
LTC2481IDD#PBF
LTC2481HDD#PBF
TAPE AND REEL
PART MARKING*
LBPV
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2481CDD#TRPBF
LTC2481IDD#TRPBF
LTC2481HDD#TRPBF
0°C to 70°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
LBPV
–40°C to 85°C
–40°C to 125°C
LBPV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics (norMal speeD) The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
l
l
Resolution (No Missing Codes)
Integral Nonlinearity
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V = 5V, V
= 2.5V (Note 6)
2
1
10
ppm of V
CC
REF
IN(CM)
REF
REF
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
ppm of V
CC
REF
IN(CM)
–
+
l
l
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 13)
0.5
10
2.5
µV
REF
CC
CC
CC
+
–
Offset Error Drift
Positive Full-Scale Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
nV/°C
REF
CC
+
+
–
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
REF
REF
CC
REF
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
ppm
REF
CC
REF
REF
REF
REF
+
–
Positive Full-Scale Error Drift
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
0.1
ppm of V /°C
REF
REF
CC
REF
–
–
+
+
l
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
REF
REF
CC
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
ppm
REF
CC
REF
REF
–
+
Negative Full-Scale Error Drift
Total Unadjusted Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
REF CC REF REF
ppm of V /°C
REF
5V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
15
15
15
ppm of V
ppm of V
ppm of V
CC
REF
IN(CM)
REF
REF
REF
5V ≤ V ≤ 5.5V, V = 5V, V = 2.5V (Note 6)
CC
CC
REF
REF
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
IN(CM)
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 12)
0.6
µV
RMS
CC
REF
CC
Internal PTAT Signal
Programmable Gain
T = 27°C
390
1
450
256
mV
A
l
See Table 2a
2481fd
2
For more information www.linear.com/LTC2481
LTC2481
elecTrical characTerisTics (2x speeD)
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS
Resolution (No Missing Codes) 0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
l
l
16
Bits
REF
CC
IN
Integral Nonlinearity
5V ≤ V ≤ 5.5V, V = 5V, V
= 2.5V (Note 6)
2
1
10
2
ppm of V
REF
CC
REF
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
l
l
l
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 13)
0.5
mV
REF
CC
CC
CC
+
–
Offset Error Drift
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
100
nV/°C
REF
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Output Noise
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
25
ppm of V
REF
REF
CC
REF
REF
REF
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of V /°C
REF
REF
CC
REF
–
+
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
ppm of V
REF
REF
CC
REF
–
+
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of V /°C
REF
REF
CC
REF
–
+
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V
0.84
µV
RMS
CC
REF
CC
l
Programmable Gain
See Table 2b
1
128
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
MIN
140
140
TYP
MAX
UNITS
dB
–
+
l
l
Input Common Mode Rejection DC
REF
CC
CC
–
+
Input Common Mode Rejection
50Hz 2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
dB
REF
CC
CC
–
+
l
Input Common Mode Rejection
60Hz 2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
140
dB
REF
CC
CC
–
–
+
+
l
l
Input Normal Mode Rejection
50Hz 2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 7)
110
104
120
120
dB
dB
REF
CC
CC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (H-Grade)
REF
CC
CC
–
–
+
+
l
l
Input Normal Mode Rejection
60Hz 2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 8)
110
104
dB
dB
REF
CC
CC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (H-Grade)
REF
CC
CC
–
+
l
Input Normal Mode Rejection
50Hz/60Hz 2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 9)
87
dB
REF
CC
CC
–
+
l
Reference Common Mode Rejection DC 2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
120
140
120
120
120
dB
dB
dB
dB
REF
CC
CC
–
+
Power Supply Rejection DC
V
V
V
= 2.5V, IN = IN = GND
REF
REF
REF
–
+
Power Supply Rejection, 50Hz 2%
Power Supply Rejection, 60Hz 2%
= 2.5V, IN = IN = GND (Notes 7, 9)
–
+
= 2.5V, IN = IN = GND (Notes 8, 9)
analog inpuT anD reFerence The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
+
–
l
l
l
l
FS
Full Scale of the Differential Input (IN – IN )
0.5V /GAIN
REF
16
LSB
Least Significant Bit of the Output Code
FS/2
+
–
V
V
Input Differential Voltage Range (IN – IN )
–FS
0.1
+FS
V
V
IN
+
–
Reference Voltage Range (REF – REF )
V
CC
REF
+
+
C (IN )
IN Sampling Capacitance
11
pF
S
2481fd
3
For more information www.linear.com/LTC2481
LTC2481
analog inpuT anD reFerence The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
11
11
1
MAX
UNITS
pF
–
–
C (IN )
IN Sampling Capacitance
S
C (V
)
V
Sampling Capacitance
pF
S
REF
DC_LEAK
DC_LEAK
REF
+
+
+
l
l
l
I
I
I
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
–10
–10
10
10
nA
–
–
–
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
1
nA
+
–
(V
)
REF , REF DC Leakage Current
Sleep Mode, V = V
CC
–100
1
100
nA
DC_LEAK REF
REF
i2c DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.7V
TYP
MAX
UNITS
l
l
l
l
l
V
V
V
V
High Level Input Voltage
V
V
IH
CC
Low Level Input Voltage
0.3V
CC
IL
Low Level Input Voltage for Address Pin
High Level Input Voltage for Address Pins
0.05V
V
IL(CA1)
CC
0.95V
V
IH(CA0/f0,CA1)
CC
R
R
R
Resistance from CA0/f , CA1 to V to Set
Chip Address Bit to 1
10
10
kΩ
INH
INL
INF
0
CC
l
l
l
Resistance from CA1 to GND to Set Chip
Address Bit to 0
kΩ
Resistance from CA0/f , CA1 to V or
GND to Set Chip Address Bit to Float
2
MΩ
0
CC
I
Digital Input Current
–10
10
µA
V
I
V
V
Hysteresis of Schmitt Trigger Inputs
Low Level Output Voltage SDA
(Note 5)
I = 3mA
0.05V
HYS
OL
CC
l
l
l
l
l
l
l
0.4
250
50
1
V
t
t
I
Output Fall Time from V
to V
Bus Load C 10pF to 400pF (Note 14)
20+0.1C
ns
ns
µA
pF
pF
pF
OF
IHMIN
ILMAX
B
B
Input Spike Suppression
Input Leakage
SP
IN
0.1V ≤ V ≤ V
CC
CC
IN
C
C
C
Capacitance for Each I/O Pin
10
I
Capacitance Load for Each Bus Line
400
10
B
External Capacitive Load On-Chip Address
CAX
Pins (CA0/f ,CA1) for Valid Float
0
l
l
V
V
High Level CA0/f External Oscillator
2.7V ≤ V < 5.5V
V – 0.5V
CC
V
V
IH(EXT,OSC)
0
CC
Low Level CA0/f External Oscillator
2.7V ≤ V < 5.5V
0.5
IL(EXT,OSC)
0
CC
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Supply Voltage
Supply Current
2.7
5.5
V
CC
l
l
l
I
Conversion Mode (Note 11)
Sleep Mode (Note 11)
H-Grade
160
1
250
2
20
µA
µA
µA
CC
2481fd
4
For more information www.linear.com/LTC2481
LTC2481
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
10
TYP
MAX
1000
100
UNITS
kHz
µs
l
l
l
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
EOSC
HEO
0.125
0.125
100
µs
LEO
l
l
l
l
l
l
l
50Hz Mode
50Hz Mode (H-Grade)
60Hz Mode
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator (Note 10)
157.2
157.2
131.0
131.0
144.1
144.1
160.3
160.3
133.6
133.6
146.9
146.9
163.5
165.1
136.3
137.6
149.9
151.0
ms
ms
ms
ms
ms
ms
ms
CONV_1
41036/f
EOSC
l
l
l
l
l
l
l
t
Conversion Time for 2x Speed Mode
50Hz Mode
78.7
65.6
72.2
80.3
66.9
73.6
81.9
82.7
68.2
68.9
75.1
75.6
ms
ms
ms
ms
ms
ms
ms
CONV_2
50Hz Mode (H-Grade)
60Hz Mode
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator (Note 10)
20556/f
EOSC
i2c TiMing characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15)
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock Pin
HIGH Period of the SCL Clock Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
0.6
HD(SDA)
LOW
1.3
µs
0.6
µs
HIGH
0.6
µs
SU(STA)
HD(DAT)
SU(DAT)
r
0
0.9
µs
Data Set-Up Time
100
20+0.1C
20+0.1C
0.6
ns
Rise Time for Both SDA and SCL Signals
Fall Time for Both SDA and SCL Signals
Set-Up Time for STOP Condition
(Note 14)
(Note 14)
300
300
ns
B
B
ns
f
µs
SU(STO)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: 50Hz mode (internal oscillator) or f
oscillator).
= 256kHz 2% (external
= 307.2kHz 2% (external
EOSC
Note 8: 60Hz mode (internal oscillator) or f
EOSC
oscillator).
Note 2: All voltage values are with respect to GND.
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f
=
EOSC
Note 3: V = 2.7V to 5.5V unless otherwise specified.
280kHz 2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/f pin. The
external oscillator frequency, f
EOSC
CC
+
–
+
–
V
V
= REF – REF , V
= (REF + REF )/2, FS = 0.5V /GAIN;
= (IN + IN )/2.
REF
REFCM
REF
0
+
–
+
–
= IN – IN , V
, is expressed in kHz.
IN
INCM
Note 4: Use internal conversion clock or external conversion clock source
with f = 307.2kHz unless otherwise specified.
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
EOSC
Note 5: Guaranteed by design, not subject to test.
calibration operations.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 13: Guaranteed by design and test correlation.
Note 14: C = capacitance of one bus line in pF.
B
Note 15: All values refer to V
and V
levels.
IH(MIN)
IL(MAX)
2481fd
5
For more information www.linear.com/LTC2481
LTC2481
Typical perForMance characTerisTics
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
(VCC = 2.7V, VREF = 2.5V)
3
2
3
2
3
2
V
V
V
= 5V
= 5V
IN(CM)
V
V
V
= 2.7V
= 2.5V
IN(CM)
V
V
V
= 5V
CC
REF
CC
REF
CC
= 2.5V
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
1
0
–45°C
85°C
1
0
1
0
25°C
–45°C, 25°C, 90°C
–45°C, 25°C, 90°C
–1
–2
–3
–1
–2
–3
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G03
2481 G01
2481 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
12
8
12
8
12
8
V
V
V
= 2.7V
= 2.5V
IN(CM)
V
V
V
= 5V
V
V
V
= 5V
= 5V
IN(CM)
CC
REF
CC
CC
REF
= 2.5V
REF
85°C
= 1.25V
= 1.25V
= 2.5V
IN(CM)
85°C
85°C
25°C
25°C
25°C
4
0
4
0
4
0
–45°C
–45°C
–45°C
–4
–8
–4
–8
–4
–8
–12
–12
–12
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G06
2481 G05
2481 G04
Noise Histogram (6.8sps)
Noise Histogram (7.5sps)
Long-Term ADC Readings
14
12
14
12
5
4
V
= 5V, V
= 5V, V = 0V, V
= 2.5V
10,000 CONSECUTIVE
READINGS
10,000 CONSECUTIVE
READINGS
CC
REF
IN
IN(CM)
GAIN = 256, T = 25°C, RMS NOISE = 0.60µV
A
RMS = 0.59µV
AVERAGE = –0.19µV
RMS = 0.60µV
AVERAGE = –0.69µV
V
V
V
= 5V
V
V
V
= 2.7V
CC
REF
IN
CC
REF
= 0V
IN
3
= 5V
= 2.5V
= 0V
10
8
10
8
2
GAIN = 256
= 25°C
GAIN = 256
T = 25°C
A
1
T
A
0
6
6
–1
–2
–3
–4
–5
4
4
2
2
0
0
–1.8 –1.2 –0.6
0
1.8
–3 –2.4 –1.8 –1.2 –0.6
0
0.6 1.2 1.8
–3 –2.4
0.6 1.2
0
10
30
40
50
60
20
TIME (HOURS)
OUTPUT READING (µV)
OUTPUT READING (µV)
2481 G07
2481 G08
2481 G09
2481fd
6
For more information www.linear.com/LTC2481
LTC2481
Typical perForMance characTerisTics
RMS Noise
vs Input Differential Voltage
RMS Noise vs VIN(CM)
RMS Noise vs Temperature (TA)
1.0
0.9
0.8
0.7
1.0
0.9
0.8
0.7
0.6
0.5
0.4
1.0
0.9
V
V
V
V
= 5V
= 5V
V
V
V
V
= 5V
= 5V
V
V
V
T
= 5V
= 5V
IN(CM)
= 25°C
CC
REF
IN
CC
REF
IN
CC
REF
= 0V
= 0V
= 2.5V
= GND
= GND
IN(CM)
IN(CM)
A
GAIN = 256
GAIN = 256
0.8
0.7
T
A
= 25°C
0.6
0.5
0.4
0.6
0.5
0.4
3
5
6
–1
0
1
2
4
–45
0
30 45 60 75 90
–30 –15
15
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
TEMPERATURE (°C)
V
(V)
INPUT DIFFERENTIAL VOLTAGE (V)
IN(CM)
2481 G11
2481 G12
2481 G10
RMS Noise vs VCC
RMS Noise vs VREF
Offset Error vs VIN(CM)
1.0
0.9
1.0
0.9
0.8
0.7
0.3
0.2
0.1
0
V
V
V
= 5V
= 0V
IN(CM)
V
V
V
= 2.5V
V
V
V
= 5V
= 5V
CC
IN
REF
CC
REF
IN
= 0V
IN
IN(CM)
= GND
= GND
= 0V
GAIN = 256
= 25°C
GAIN = 256
= 25°C
T = 25°C
A
T
A
T
A
0.8
0.7
0.6
0.5
0.4
0.6
0.5
0.4
–0.1
–0.2
–0.3
0
1
2
3
(V)
4
5
4.3
(V)
5.1 5.5
–1
2
3
4
5
6
2.7 3.1 3.5 3.9
V
4.7
0
1
V
V
(V)
REF
CC
IN(CM)
2481 G14
2481 G13
2481 G15
Offset Error vs Temperature
Offset Error vs VCC
Offset Error vs VREF
0.3
0.2
0.1
0
0.3
0.2
0.3
0.2
+
REF = 2.5V
V
= 5V
V
V
V
V
= 5V
REF
CC
CC
–
–
REF = GND
REF = GND
= 5V
V
V
A
= 0V
= GND
= 25°C
V
V
T
= 0V
= GND
= 25°C
= 0V
IN
IN(CM)
IN
IN(CM)
IN
IN(CM)
= GND
T
A
0.1
0.1
0
0
–0.1
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
–0.2
–0.3
4.3
(V)
5.1
5.5
2.7 3.1
3.5 3.9
4.7
0
1
2
3
4
5
–45 –30 –15
0
15 30 45 60 75 90
V
(V)
V
TEMPERATURE (°C)
REF
CC
2481 G17
2481 G18
2481 G16
2481fd
7
For more information www.linear.com/LTC2481
LTC2481
Typical perForMance characTerisTics
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs VCC
PSRR vs Frequency at VCC
310
308
306
304
302
300
310
308
306
304
0
–20
V
V
V
= 2.5V
V
V
= 4.1V DC
= 2.5V
REF
IN
CC
REF
= 0V
+
= GND
IN = GND
IN(CM)
–
IN = GND
–40
T
= 25°C
A
–60
–80
–100
–120
–140
V
V
V
V
= 4.1V
REF
CC
= 2.5V
302
300
= 0V
IN
IN(CM)
= GND
–45 –30 –15
0
15 30 45 60 75 90
2.5
3.5
4.0
(V)
4.5
5.0
5.5
3.0
10k
FREQUENCY AT V (Hz)
1M
1
10
100
1k
100k
TEMPERATURE (°C)
V
CC
CC
2481 G21
2481 G22
2481 G23
Conversion Current
vs Temperature
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
0
–20
–40
200
180
0
V
V
= 4.1V DC 0.7V
= 2.5V
V
V
= 4.1V DC 1.4V
= 2.5V
CC
REF
CC
REF
–20
+
+
IN = GND
IN = GND
–
–
IN = GND
T
IN = GND
T
–40
= 25°C
V
= 5V
CC
= 25°C
A
A
160
–60
–80
–60
–80
V
= 2.7V
CC
140
120
100
–100
–120
–140
–100
–120
–140
30650
30700
30800
30600
30750
0
60
100 120 140 160 180 200 220
–45 –30 –15
0
30
60 75 90
20 40
80
15
45
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
TEMPERATURE (°C)
CC
CC
2481 G25
2481 G24
2481 G26
Sleep Mode Current
vs Temperature
Conversion Current
vs Output Data Rate
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
500
V
= V
CC
REF
+
IN = GND
450
400
350
300
250
200
150
100
–
IN = GND
CA0/f = EXT OSC
0
T
= 25°C
A
V
= 5V
CC
V
= 2.7V
CC
V
= 5V
= 3V
CC
V
CC
–45 –30 –15
0
15 30 45 60 75 90
0
10
20
30
TEMPERATURE (°C)
OUTPUT DATA RATE (READINGS/SEC)
2481 G27
2481 G28
2481fd
8
For more information www.linear.com/LTC2481
LTC2481
Typical perForMance characTerisTics
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
3
2
3
2
3
2
V
V
V
= 2.7V
CC
V
V
V
= 5V
= 5V
IN(CM)
V
V
V
= 5V
CC
REF
CC
= 2.5V
REF
= 2.5V
REF
= 1.25V
IN(CM)
= 2.5V
= 1.25V
IN(CM)
1
0
1
0
1
0
90°C
90°C
25°C, 90°C
–45°C, 25°C
–1
–2
–3
–1
–2
–3
–45°C, 25°C
–1
–2
–3
–45°C
–1.25 –0.75
–0.25
0.25
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G31
2481 G29
2481 G30
Noise Histogram
(2x Speed Mode)
RMS Noise vs VREF
(2x Speed Mode)
Offset Error vs VIN(CM)
(2x Speed Mode)
1.0
0.8
0.6
0.4
0.2
0
200
198
196
194
192
190
188
186
184
182
180
16
14
12
10
8
RMS = 0.86µV
10,000 CONSECUTIVE
READINGS
V
V
V
T
= 5V
CC
AVERAGE = 0.184mV
= 5V
REF
V
V
V
= 5V
= 5V
= 0V
CC
REF
IN
IN
A
= 25°C
= 0V
GAIN = 256
= 25°C
T
A
6
4
V
V
V
= 5V
= 0V
IN(CM)
= 25°C
CC
IN
2
= GND
T
A
0
0
1
2
3
4
5
181.4
183.8
188.6
179
186.2
3
6
–1
1
2
4
5
0
V
(V)
V
(V)
OUTPUT READING (µV)
REF
IN(CM)
2481 G33
2481 G32
2481 G34
Offset Error vs VCC
(2x Speed Mode)
Offset Error vs Temperature
(2x Speed Mode)
250
200
150
100
50
240
230
220
210
200
190
180
170
160
V
V
V
T
= 2.5V
V
V
V
V
= 5V
= 5V
REF
CC
REF
IN
= 0V
IN
IN(CM)
= GND
= 25°C
= 0V
= GND
A
IN(CM)
0
15 30
TEMPERATURE (°C)
2.7
3
3.5
4
4.5
5
5.5
–45 –30 –15
0
45 60 75 90
V
(V)
CC
2481 G36
2481 G35
2481fd
9
For more information www.linear.com/LTC2481
LTC2481
Typical perForMance characTerisTics
Offset Error vs VREF
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
0
–20
240
230
220
210
V
= 4.1V DC
V
V
V
= 5V
= 0V
IN(CM)
= 25°C
CC
CC
IN
+
REF = 2.5V
–
REF = GND
= GND
+
–
IN = GND
T
A
–40
IN = GND
T
= 25°C
A
–60
200
190
–80
–100
–120
–140
180
170
160
10k
FREQUENCY AT V (Hz)
1M
1
10
100
1k
100k
1
2
4
0
5
3
(V)
V
CC
REF
2481 G38
2481 G37
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
0
0
V
= 4.1V DC 0.7V
CC
+
REF = 2.5V
–20
–20
–
REF = GND
+
–
IN = GND
–40
–40 IN = GND
T
= 25°C
A
–60
–80
–60
–80
–100
–120
–100
–120
–140
–140
30650
30700
30800
0
60
100 120 140 160 180 200 220
30600
30750
20 40
80
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
CC
2481 G39
2481 G40
pin FuncTions
+
–
+
–
REF (Pin 1), REF (Pin 3): Differential Reference Input.
IN (Pin 4), IN (Pin 5): Differential Analog Input. The
The voltage on these pins can have any value between
voltage on these pins can have any value between GND
GND and V as long as the reference positive input,
– 0.3V and V + 0.3V. Within these limits the converter
CC
CC
+
–
+
–
REF , is more positive than the reference negative input,
REF , by at least 0.1V.
bipolar input range (V = IN – IN ) extends from –0.5
IN
• V
/GAIN to 0.5 • V /GAIN. Outside this input
REF REF
range the converter produces unique overrange and
underrange output codes.
V
(Pin 2): Positive Supply Voltage. Bypass to GND
CC
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
2481fd
10
For more information www.linear.com/LTC2481
LTC2481
pin FuncTions
2
SCL (Pin 6): Serial Clock Pin of the I C Interface. The
LTC2481 can only act as a slave and the SCL pin only ac-
cepts external serial clock. Data is shifted into the SDA pin
on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating) ad-
2
dress control bit for the device I C address.
2
SDA (Pin 7): Bidirectional Serial Data Line of the I C Inter-
CA0/f (Pin 10): Chip Address Control Pin/External Clock
0
face.Inthetransmittermode(Read),theconversionresult
is output through the SDA pin, while in the receiver mode
(Write), thedeviceconfigurationbitsareinputthroughthe
SDA pin. At data input mode, the pin is high impedance;
while at data output mode, it is an open-drain N-channel
driver and therefore an external pull-up resistor or current
Input Pin. When no transition is detected on the CA0/f
0
pin, it is a two state (HIGH or Floating) address control
2
bit for the device I C address. When the pin is driven by
an external clock signal with a frequency f
of at least
EOSC
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located
source to V is needed.
CC
at a frequency f
/5120 and sets the Chip Address CA0
EOSC
internally to a HIGH.
FuncTional block DiagraM
2
+
REF
V
CC
1
+
IN
SCL
6
+
4
REF
+
–
IN
IN
–
SDA
IN
2
I C
5
7
9
3RD ORDER
∆Σ ADC
SERIAL
INTERFACE
MUX
CA1
CA0/f
0
(1-256)
GAIN
10
–
REF
TEMP
SENSOR
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
–
REF
GND
3
8
2481 FD
2481fd
11
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
CONVERTER OPERATION
Thedevicewillnotacknowledgeanexternalrequestduring
the conversion state. After a conversion is finished, the
device is ready to accept a read/write request. Once the
LTC2481isaddressedforareadoperation,thedevicebegins
outputtingtheconversionresultundercontroloftheserial
clock (SCL). There is no latency in the conversion result.
The data output is 24 bits long and contains a 16-bit plus
signconversionresultplusareadbackoftheconfiguration
bits corresponds to the conversion just performed. This
result is shifted out on the SDA pin under the control of the
SCL. Data is updated on the falling edges of SCL allowing
the user to reliably latch data on the rising edge of SCL.
In write operation, the device accepts one configuration
byte and the data is shifted in on the rising edges of the
SCL. A new conversion is initiated by a STOP condition
following a valid write operation or at the conclusion of a
data read operation (read out all 24 bits).
Converter Operation Cycle
TheLTC2481isalowpower,∆Σ analog-to-digitalconverter
2
with an I C interface. After power on reset, its operation
is made up of three states. The converter operating cycle
beginswiththeconversion,followedbythelowpowersleep
state and ends with the data output/input (see Figure 1).
POWER ON RESET
DEFAULT CONFIGURATION:
EXTERNAL INPUT GAIN = 1
50/60Hz REJECTION
1X SPEED, AUTOCAL
CONVERSION
SLEEP
2
I C INTERFACE
2
TheLTC2481communicatesthroughanI Cinterface.The
2
NO
I C interface is a 2-wire open-drain interface supporting
ACKNOWLEDGE
multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
canneverdrivethebusHIGH. Thebuswiresareexternally
connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both
YES
DATA OUTPUT/INPUT
2
lines are HIGH. Data on the I C-bus can be transferred
at rates of up to 100kbit/s in the Standard-mode and up
STOP
NO
to 400kbit/s in the Fast-mode. The V power should not
OR READ
24-BITS
CC
2
be removed from the device when the I C bus is active to
2
avoid loading the I C bus lines through the internal ESD
YES
2481 F01
protection diodes.
2
Figure 1. LTC2481 State Transition Diagram
Each device on the I C bus is recognized by a unique
address stored in that device and can operate as either
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signalstopermitthattransfer. Atthesametimeanydevice
addressed is considered a slave.
Initially, the LTC2481 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write opera-
tion. The conversion result is held indefinitely in a static
shift register while the converter is in the sleep state.
2481fd
12
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
The LTC2481 can only be addressed as a slave. Once
addressed, itcanreceiveconfigurationbitsortransmitthe
last conversion result. Therefore the serial clock line SCL
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
Acknowledge (ACK) by pulling SDA LOW or leaves SDA
HIGH to indicate a Not Acknowledge (NACK) condition.
Change of data state can only happen while SCL is LOW.
Accessing the Special Features of the LTC2481
The LTC2481 combines a high resolution, low noise ∆Σ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable gain, programmable
digital filterand outputrate control. These specialfeatures
areselectedthroughasingle8-bitserialinputwordduring
the data input/output cycle (see Figure 3).
2
on the I C-bus.
The START and STOP Conditions
A STARTconditionis generatedby transitioningSDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
The LTC2481 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode until a valid write cycle is performed. In this
defaultmode,themeasuredinputisexternal,theGAINis1,
the digital filter simultaneously rejects 50Hz and 60Hz
line frequency noise, and the speed mode is 1x (offset
automatically, continuously calibrated).
The I2C serial interface grants access to any or all special
functionscontainedwithintheLTC2481.Inordertochange
the mode of operation, a valid write address followed by 8
bitsofdataareshiftedintothedevice(seeTable 1).Thefirst
3 bits (GS2, GS1, GS0) control the GAIN of the converter
from 1 to 256. The 4th bit is reserved and should be low.
The 5th bit (IM) is used to select the internal temperature
sensor as the conversion input, while the 6th and 7th bits
(FA,FB)combinetodeterminethelinefrequencyrejection
mode. The 8th bit (SPD) is used to double the output rate
by disabling the offset auto calibration.
When the bus is in use, it stays busy if a repeated START
(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated
START (Sr) conditions are functionally identical to the
START (S).
Data Transferring
2
After the START condition, the I C bus is busy and data
transfer is set between a master and a slave. Data is
2
transferredoverI Cingroupsofninebits(onebyte)followed
by an acknowledge bit, therefore each group takes nine
SCL cycles. The transmitter releases the SDA line during
the acknowledge clock pulse and the receiver issues an
SDA
tSU;DAT
tf
tLOW
tr
tr
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tHIGH
S
Sr
P
S
2481 F02
Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus
2481fd
13
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
1
2
…
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
7-BIT ADDRESS
GS2 GS1 GS0
IM
FA
FB
SPD
W
ACK BY
LTC2481
ACK BY
LTC2481
START BY
MASTER
SLEEP
DATA INPUT
2481 F03
Figure 3. Timing Diagram for Writing to the LTC2481
Table 1. Selecting Special Modes
Rejection
Mode
Gain
GS2 GS1 GS0 IM FA FB SPD Comments
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 256, Autocalibration
External Input, Gain = 1, 2x Speed
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
Any
Rejection
Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Any
Speed
Any Gain
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration
Reserved, Do Not Use
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2481 TBL1
2481fd
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Table 2a. The LTC2481 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
2.5
4
0.625
9.54
65536
5
8
0.312
4.77
65536
5
16
0.156
2.38
65536
5
32
78m
1.19
65536
5
64
39m
0.596
65536
5
128
19.5m
0.298
32768
5
256
UNIT
V
Input Span
LSB
9.76m
0.149
16384
8
38.1
65536
5
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Table 2b. The LTC2481 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
2.5
2
1.25
19.1
65536
5
4
8
16
0.156
2.38
65536
5
32
78m
1.19
65536
5
64
39m
0.596
45875
5
128
19.5m
0.298
22937
5
UNIT
V
Input Span
LSB
0.625
9.54
65536
5
0.312
4.77
65536
5
38.1
65536
5
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
200
200
200
200
200
200
200
200
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
GAIN (GS2, GS1, GS0)
Rejection Mode (FA, FB)
The LTC2481 includes a high accuracy on-chip oscilla
tor with no required external components. Coupled with
a 4th order digital lowpass filter, the LTC2481 rejects
line frequency noise. In the default mode, the LTC2481
simultaneously rejects 50Hz and 60Hz by at least 87dB.
The LTC2481 can also be configured to selectively reject
50Hz or 60Hz to better than 110dB.
The input referred gain of the LTC2481 is adjustable from
1 to 256. With a gain of 1, the differential input range is
-
V
/2 and the common mode input range is rail-to-rail.
REF
As the GAIN is increased, the differential input range is re-
ducedto V /2•GAINbutthecommonmodeinputrange
REF
remains rail-to-rail. As the differential gain is increased,
low level voltages are digitized with greater resolution. At
a gain of 256, the LTC2481 digitizes an input signal range
of 9.76mV with over 16,000 counts.
Speed Mode (SPD)
The LTC2481 continuously performs offset calibrations.
Everyconversioncycle,twoconversionsareautomatically
performed (default) and the results combined. This result
isfreefromoffsetanddrift.Inapplicationswheretheoffset
is not critical, the autocalibration feature can be disabled
with the benefit of twice the output rate.
Temperature Sensor (IM)
The LTC2481 includes an on-chip temperature sensor.
The temperature sensor is selected by setting IM = 1 in
the serial input data stream. Conversions are performed
directly on the temperature sensor by the converter. While
operatinginthismode,thedevicebehavesasatemperature
to bits converter. The digital reading is proportional to
the absolute temperature of the device. This feature
allows the converter to linearize temperature sensors or
continuously remove temperature effects from external
sensors. Several applications leveraging this feature are
presented in more detail in the applications section. While
operating in this mode, the gain is set to 1 and the speed
is set to normal independent of the control bits (GS2,
GS1, GS0 and SPD).
Linearity, full-scale accuracy and full-scale drift are identi-
cal for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conver-
sion cycle easing system overhead and increasing the
effective conversion rate.
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LTC2481 Data Format
LOW if V <0. The second bit is the most significant bit
IN
(MSB) of the result. The first two bits (SIG and MSB) can
be used to indicate over range conditions. If both bits are
HIGH, the differential input voltage is above +FS and the
following 16 bits are set to LOW to indicate an overrange
condition. If both bits are LOW, the input voltage is below
–FS and the following 16 bits are set to HIGH to indicate
an underrange condition. The function of these two bits
is summarized in Table 3. The next 16 bits contain the
conversion results in binary two’s complement format.
The remaining six bits are a readback of the configuration
register.
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2481’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NACK) by leaving
SDA HIGH. If the conversion is complete, it issues an
acknowledge (ACK) by pulling SDA LOW.
TheLTC2481hastworegisters.Theoutputregistercontains
the result of the last conversion and a user programmable
configuration register that sets the converter operation
mode.
Table 3. LTC2481 Status Bits
INPUT RANGE
≥ 0.5 • V
BIT 23 SIG
BIT 22 MSB
Theoutputregistercontainsthelastconversionresult.After
each conversion is completed, the device automatically
enters the sleep state where the supply current is reduced
to 1µA. When the LTC2481 is addressed for a Read
operation, it acknowledges (by pulling SDA LOW) and
acts as a transmitter. The master and receiver can read up
to three bytes from the LTC2481. After a complete Read
operation (3 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same input/output phase will be NACKed. The LTC2481
outputdatastreamis24bitslong, shiftedoutonthefalling
edges of SCL. The first bit is the conversion result sign bit
V
IN
1
1/0
0
1
0
1
0
REF
0V ≤ V < 0.5 • V
IN
REF
–0.5 • V ≤ V < 0V
REF
IN
V
IN
< –0.5 • V
0
REF
+
–
As long as the voltage on the IN and IN pins is main-
tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum
CC
operating range, a conversion result is generated for any
differential input voltage V from –FS = –0.5 • V /GAIN
IN
REF
to +FS = 0.5 • V /GAIN. For differential input voltages
REF
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
inputvoltagesbelow–FS,theconversionresultisclamped
to the value corresponding to –FS – 1LSB.
(SIG), see Tables 3 and 4. This bit is HIGH if V ≥ 0. It is
IN
Table 4. LTC2481 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
*
VIN
BIT 23 SIG
BIT 22 MSB
BIT 21
BIT 20
BIT 19
…
…
…
BIT 6
V * ≥ FS**
IN
1
1
1
0
0
1
0
1
0
1
0
1
FS** – 1LSB
0.5 • FS**
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0.5 • FS** – 1LSB
0
1/0***
0
0
1
0
1
0
1
0
1
…
…
0
1
–1LSB
–0.5 • FS**
0
0
1
1
1
0
0
1
0
1
…
…
0
1
–0.5 • FS** – 1LSB
–FS**
0
1
0
0
1
0
1
0
1
…
…
0
1
V * < –FS**
IN
0
+
–
* The differential input voltage V = IN – IN .
IN
** The full-scale voltage FS = 0.5 • V /GAIN.
REF
*** The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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1
… 7
8
9
1
2 …
9
1
2
3
4
5
6
7
8
9
7-BIT
ADDRESS
R
SGN MSB D15
LSB PG2 PG1 PG0
X
IM
SPD
ACK BY
LTC2481
ACK BY
MASTER
NAK BY
MASTER
START BY
MASTER
SLEEP
DATA OUTPUT
2481 F04
Figure 4. Timing Diagram for Reading from the LTC2481
Initiating a New Conversion
OPERATION SEꢀUENCE
When the LTC2481 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device
is ready for Read/Write operations. After the device ac-
knowledges a Read or Write request, the device exits the
sleepstateandentersthedatainput/outputstate. Thedata
input/outputstateconcludesandtheLTC2481startsanew
conversion once a STOP condition is issued by the master
or all 24 bits of data are read out of the device.
The LTC2481 acts as a transmitter or receiver. The device
may be programmed to perform several functions. These
include measuring an external differential input signal or
anintegratedtemperaturesensor,settingaprogrammable
gain (from 1 to 256), selecting line frequency rejection
(50Hz, 60Hz, or simultaneous 50Hz and 60Hz), and a 2x
speed up mode.
Continuous Read
Duringthedatareadcycle,astopcommandmaybeissued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the 9th clock cycle of a byte read when the
bus is free (the ACK/NACK cycle).
In applications where the configuration does not need to
change for each conversion cycle, the conversion result
can be continuously read. The configuration remains
unchanged from the last value written into the device.
If the device has not been written to since power up, the
configuration is set to the default value (Input External,
GAIN=1, simultaneous 50Hz/60Hz rejection, and 1x
speedmode). TheoperationsequenceisshowninFigure
6. When the conversion is finished, the device may be
addressed for a read operation. At the end of a read
operation, a new conversion begins. At the conclusion
of the conversion cycle, the next result may be read
using the method described above. If the conversion
cycle is not concluded and a valid address selects the
device, the LTC2481 generates a NACK signal indicating
the conversion cycle is in progress.
LTC2481 Address
The LTC2481 has two address pins, enabling one in 6
possible addresses, as shown in Table 5.
Table 5. LTC2481 Address Assignment
CA1
LOW
CA0/f *
Address
001 01 00
001 01 01
001 01 11
010 01 00
010 01 10
010 01 11
0
HIGH
Floating
HIGH
LOW
Floating
Floating
HIGH
Floating
HIGH
HIGH
Floating
* CA0/f is treated as HIGH when driven by a valid external clock.
0
InadditiontotheconfigurableaddresseslistedinTable5,the
LTC2481 also contains a global address (1110111) which
may be used for synchronizing multiple LTC2481s.
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S
R/W
ACK
DATA
Sr
DATA TRANSFERRING
P
7-BIT ADDRESS
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
2481 F05
Figure 5. The LTC2481 Conversion Sequence
S
7-BIT ADDRESS
R
ACK
READ
P
S
7-BIT ADDRESS
R
ACK
READ
P
CONVERSION
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2481 F06
Figure 6. Consecutive Reading at the Same Configuration
S
7-BIT ADDRESS
W ACK
WRITE
Sr
7-BIT ADDRESS
ADDRESS
R
ACK
READ
P
CONVERSION
SLEEP
DATA INPUT
DATA OUTPUT
CONVERSION
2481 F08
Figure 7. Write, Read, Start Conversion
Continuous Read/Write
Synchronizing Multiple LTC2481s with the Global
Address Call
Once the conversion cycle is concluded, the LTC2481 can
be written to then read from, using the repeated Start (Sr)
command.
In applications where several LTC2481s are used on the
2
same I C bus, all LTC2481s can be synchronized with the
global address call. To achieve this, first all the LTC2481s
must have completed the conversion cycle. The master
issues a Start, followed by the LTC2481 global address
1110111andaWriterequest. AllLTC2481swillbeselected
and acknowledge the request. The master then sends
the write byte (Optional) and ends the Write operation
with a STOP. This will update the configuration registers
(if a write byte was sent) and initiate a new conversion
simultaneously on all the LTC2481s, as shown in Figure 9.
In order to synchronize the start of conversion without
affecting the configuration registers, the Write operation
canbeabortedwithaSTOP. Thisinitiatesanewconversion
on all the LTC2481s without changing the configuration
registers.
Figure 7 shows a cycle which begins with a data Write, a
repeated start, followed by a read, and concluded with a
stopcommand.Thefollowingconversionbeginsafterall24
bits are read out of the device or after the STOP command
and uses the newly programmed configuration data.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Configuration Updating
At the conclusion of a conversion cycle, a Write cycle
can be initiated. Once the Write cycle is acknowledged,
a stop (P) command initiates a new conversion. If a new
configuration is required, this data can be written into the
device and a stop command initiates a new conversion,
see Figure 8.
2481fd
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S
7-BIT ADDRESS
W ACK
WRITE (OPTIONAL)
DATA INPUT
P
CONVERSION
SLEEP
CONVERSION
2481 F08
Figure 8. Start a New Conversion without Reading Old Conversion Result
SCL
SDA
LTC2481
LTC2481
…
LTC2481
S
GLOBAL ADDRESS
W ACK WRITE (OPTIONAL)
DATA INPUT
P
ALL LTC2481s IN SLEEP
CONVERSION OF ALL LTC2481s
2481 F09
Figure 9. Synchronize the LTC2481s with the Global Address Call
Easy Drive Input Current Cancellation
directly related to the accuracy of the converter system
clock.TheLTC2481incorporatesahighlyaccurateon-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
The LTC2481 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input
current. This enables external RC networks and high
impedance sensors to directly interface to the LTC2481
without external amplifiers. The remaining common
mode input current is eliminated by either balancing the
differential input impedances or setting the common
mode input equal to the common mode reference (see
AutomaticInputCurrentCancellationsection).Thisunique
architecture does not require on-chip buffers enabling
input signals to swing all the way to ground and up to
Frequency Rejection Selection (CA0/f )
0
TheLTC2481internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz 2% or 60Hz 2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chipconfigurationregister(thedefaultmodeatpower-
up is simultaneous 50Hz/60Hz rejection).
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2481 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
V . Furthermore, the cancellation does not interfere with
CC
the transparent offset and full-scale auto-calibration and
the absolute accuracy (full-scale + offset + linearity) is
maintained even with external RC networks.
signal at the CA0/f pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
0
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For
high resolution, low frequency applications, this filter is
typicallydesignedtorejectlinefrequenciesof50Hzor60Hz
plus their harmonics. The filter rejection performance is
frequency f
of the external signal must be at least
EOSC
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods t
are observed.
and t
HEO
LEO
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While operating with an external conversion clock of a
–80
–85
frequency f
, the LTC2481 provides better than 110dB
EOSC
–90
normal mode rejection in a frequency range of f
/5120
EOSC
–95
4% and its harmonics. The normal mode rejection as a
–100
–105
–110
–115
–120
–125
–130
–135
–140
function of the input frequency deviation from f
is shown in Figure 10.
/5120
EOSC
WheneveranexternalclockisnotpresentattheCA0/f pin,
0
the converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. CA0/f
0
may be tied HIGH or left floating in order to set the chip
address. The LTC2481 operation will not be disturbed if
the change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/5120(%)
2481 F10
EOSC
Figure 10. LTC2481 Normal Mode Rejection When
Using an External Oscillator
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Table 6 summarizes the duration of the conversion state
of each state and the achievable output data rate as a
Power-Up Sequence
function of f
.
EOSC
The LTC2481 automatically enters an internal reset
Ease of Use
state when the power supply voltage V drops below
CC
The LTC2481 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
approximately 2V. This feature guarantees the integrity of
the conversion result.
When the V voltage rises above this critical threshold,
CC
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signalclearsallinternalregisters.FollowingthePORsignal,
the LTC2481 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The first
The LTC2481 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
Table 6. LTC2481 State Duration
STATE
OPERATING MODE
DURATION
CONVERSION
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode 67ms,
Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode 80ms,
Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode 73.6ms,
Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
CA0/f = External Oscillator 41036/f
s, Output Data Rate ≤ f
s, Output Data Rate ≤ f
/41036 Readings/s for 1x Speed Mode
EOSC
/20556 Readings/s for 2x Speed Mode
EOSC
0
EOSC
EOSC
with Frequency f
Hz
20556/f
EOSC
(f
/5120 Rejection)
EOSC
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conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
If the same V
source is used during calibration and
REF
temperature measurement, the actual value of the V
REF
is not needed to measure the temperature as shown in
the calculation below:
RSDA •VREF
On-Chip Temperature Sensor
TC =
–273
SLOPE
The LTC2481 contains an on-chip PTAT (proportional to
absolutetemperature)signalthatcanbeusedasatempera-
ture sensor. The internal PTAT has a typical value of 420mV
at 27°C and is proportional to the absolute temperature
value with a temperature coefficient of 420/(27 + 273) =
1.40mV/°C (SLOPE), as shown in Figure 11. The internal
PTAT signal is used in a single-ended mode referenced to
device ground internally. The GAIN is automatically set to
one (independent of the values of GS0, GS1, GS2) in order
to preserve the PTAT property at the ADC output code
and avoid an out of range error. The 1x speed mode with
automatic offset calibration is automatically selected for
the internal PTAT signal measurement as well.
RSDA
R0SDA
=
• T0+273 –273
( )
600
V
= 5V
CC
IM = 1
SLOPE = 1.40mV/°C
500
400
300
200
When using the internal temperature sensor, if the output
–60
–30
0
30
60
90
120
TEMPERATURE (°C)
code is normalized to R
= V
/V , the temperature
SDA
PTAT REF
2481 F11
is calculated using the following formula:
Figure 11. Internal PTAT Signal vs Temperature
RSDA •VREF
TK =
and
TC =
in Kelvin
Reference Voltage Range
SLOPE
The LTC2481 external reference voltage range is 0.1V
to V . The converter output noise is determined by
CC
RSDA •VREF
–273 in °C
the thermal noise of the front-end circuits, and as such,
SLOPE
its value in nanovolts is nearly constant with reference
where SLOPE is nominally 1.4mV/°C.
voltage. Since the transition noise (600nV) is much less
17
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve absolute
temperature measurements, a one-time calibration is
needed to adjust the SLOPE value. The converter output of
than the quantization noise (V /2 ), a decrease in the
REF
reference voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
thePTATsignal,R0 ,ismeasuredataknowntemperature
SDA
clock (external f signal) at substantially higher output
O
T0 (in °C) and the SLOPE is calculated as:
data rates (see the Output Data Rate section). V must
REF
R0SDA •VREF
be ≥1.1V to use the internal temperature sensor.
SLOPE=
T0+273
Thereferenceinputisdifferential.Thedifferentialreference
+
–
This calibrated SLOPE can be used to calculate the tem-
perature.
input range (V = REF – REF ) is 100mV to V and the
REF
CC
CC
common mode reference input range is 0V to V .
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Input Voltage Range
Driving the Input and Reference
The analog input is truly differential with an absolute/
The input and reference pins of the LTC2481 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 12.
+
–
common mode range for the IN and IN input pins
extending from GND – 0.3V to V + 0.3V. Outside these
CC
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2481 converts the bipolar differential
+
–
inputsignal,V =IN –IN ,from–FSto+FSwhereFS=0.5
IN
• V /GAIN. Beyondthisrange, theconverterindicatesthe
REF
For a simple approximation, the source impedance R
S
overrangeortheunderrangeconditionusingdistinctoutput
codes.Sincethedifferentialinputcurrentcancellationdoes
not rely on an on-chip buffer, current cancellation as well
as DC performance is maintained rail-to-rail.
+
–
+
–
driving an analog input pin (IN , IN , REF or REF ) can be
considered to form, together with R and C (see Fig-
SW
EQ
ure 12), a first order passive network with a time constant
τ = (R + R ) • C . The converter is able to sample the
S
SW
EQ
I
nput signals applied to IN+ and IN– pins may extend by
inputsignalwithbetterthan1ppmaccuracyifthesampling
periodisatleast14timesgreaterthantheinputcircuittime
constant τ. The sampling process on the four input analog
pins is quasi-independent so each time constant should be
considered by itself and, under worst-case circumstances,
the errors may add.
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
withtheIN+andIN–pinswithoutaffectingtheperformance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presentedintheInputCurrent/ReferenceCurrentsections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
Whenusingtheinternaloscillator,theLTC2481’sfront-end
switched-capacitor network is clocked at 123kHz corre-
sponding to an 8.1µs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
shouldbechosensuchthatτ ≤8.1µs/14=580ns.Whenan
externaloscillatoroffrequencyf
isused,thesampling
EOSC
V
CC
+
period is 2.5/f
and, for a settling error of less than
I
EOSC
REF
R
(TYP)
SW
I
LEAK
1ppm, τ ≤ 0.178/f
.
10k
EOSC
+
V
REF
I
LEAK
V
IN(CM) − VREF(CM)
0.5•REQ
I IN+
= I IN–
=
(
)
(
)
V
CC
AVG
AVG
+
I
IN
2
R
(TYP)
10k
2
1.5VREF + VREF(CM) – V
SW
V
(
IN(CM)
)
1.5• VREF − VINCM + VREFCM
0.5•REQ
0.5• VREF • DT
V
IN
I
I
LEAK
LEAK
IN
I REF+
=
−
−
≅
–
(
)
+
AVG
VREF •REQ
REQ
0.5•REQ
VREF •REQ
V
IN
C
EQ
12pF
where:
(TYP)
REF+ + REF–
V
REF+ − REF–
, VREF =
CC
VREFCM
=
–
I
2
IN
R
R
(TYP)
SW
I
I
LEAK
LEAK
10k
V
IN
= IN+ −IN−
–
V
IN
+
IN +IN−
V
INCM
=
2
V
CC
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
REQ = 0.833•1012 / fEOSC EXTERNAL OSCILLATOR
–
–
I
REF
(TYP)
SW
10k
I
I
LEAK
LEAK
2481 F12
(
)
V
REF
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF IS INTERNALLY TIED TO GND
–
SWITCHING FREQUENCY
f
f
= 123kHz INTERNAL OSCILLATOR
SW
SW
= 0.4 • f
EXTERNAL OSCILLATOR
EOSC
Figure 12. LTC2481 Equivalent Analog Input Circuit
2481fd
22
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LTC2481
applicaTions inForMaTion
Automatic Differential Input Current Cancellation
R
R
SOURCE
+
IN
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
C
PAR
V
V
+ 0.5V
– 0.5V
C
C
INCM
INCM
IN
IN
EXT
EXT
≅20pF
LTC2481
SOURCE
–
IN
2481 F13
C
PAR
≅20pF
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required for
1ppmaccuracy.Forexample,a10kΩbridgedrivinga0.1µF
bypass capacitor has a time constant several orders of
magnitudegreaterthantherequiredmaximum.Historically,
settlingissuesweresolvedusingbuffers.Thesebuffersled
toincreasednoise,reducedDCperformance(Offset/Drift),
limited input/output swing (cannot digitize signals near
Figure 13. An RC Network at IN+ and IN–
80
V
V
V
V
T
= 5V
CC
= 5V
REF
60
40
20
+
= 3.75V
= 1.25V
IN
–
IN
= 25°C
A
C
= 0pF
EXT
C
= 100pF
EXT
ground or V ), added system cost and increased power.
0
CC
C
= 1nF, 0.1µF, 1µF
EXT
The LTC2481 uses a proprietary switching algorithm that
forces the average differential input current to zero inde-
pendent of external settling errors. This allows accurate
direct digitization of high impedance sensors without the
need of buffers (see Figures 13 to 15). Additional errors
resulting from mismatched leakage currents must also
be taken into account.
–20
–40
–60
–80
10
100
R
10k
1
100k
1k
(Ω)
SOURCE
2481 F14
Figure 14. +FS Error vs RSOURCE at IN+ and IN–
The switching algorithm forces the average input current
+
on the positive input (I ) to be equal to the average input
IN
–
current on the negative input (I ). Over the complete
80
IN
V
V
V
V
= 5V
CC
conversion cycle, the average differential input current
= 5V
REF
60
40
20
+
= 1.25V
= 3.75V
+
–
IN
–
(I – I ) is zero. While the differential input current
IN
IN
IN
+
–
T
= 25°C
A
is zero, the common mode input current (I + I )/2 is
proportional to the difference between the common mode
input voltage (V
voltage (V
C = 1nF, 0.1µF, 1µF
EXT
IN
IN
0
) and the common mode reference
INCM
).
C
= 100pF
EXT
–20
REFCM
C
= 0pF
EXT
–40
–60
–80
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
10
100
10k
1
100k
1k
(Ω)
R
SOURCE
2481 F15
+
Figure 15. –FS Error vs RSOURCE at IN+ and IN–
errors. Mismatches in source impedances between IN
–
and IN also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
2481fd
23
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LTC2481
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the common mode input current is proportional to the
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
difference between V
and V
. For a reference
INCM
REFCM
+
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74µA(insimultaneous50Hz/60Hzrejectionmode). This
commonmodeinputcurrenthasnoeffectontheaccuracy
used for the external source impedance seen by IN and
–
IN , the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
+
–
if the external source impedances tied to IN and IN are
matched. Mismatches in these source impedances lead
to a fixed offset error but do not affect the linearity or full-
scale reading. A 1% mismatch in 1kΩ source resistances
leads to a 15ppm shift (74µV) in offset voltage.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the com-
mon mode input current varies proportionally with input
voltage. For the case of balanced input impedances, the
common mode input current effects are rejected by the
large CMRR of the LTC2481 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errorsproportionaltothedifferencebetweenthecommon
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 7 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
Reference Current
In a similar fashion, the LTC2481 samples the differential
+
–
reference pins REF and REF transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (C
< 1nF), the voltage on the sampling capacitor
REF
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
will deteriorate the converter offset and
REF
Table 7. Suggested Input Configuration for LTC2481
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
+
+
Larger values of reference capacitors (C > 1nF) may be
Constant
– V
C
> 1nF at Both IN
C
> 1nF at Both IN
REF
EXT
EXT
–
–
V
and IN . Can Take Large and IN . Can Take Large
Source Resistance with Source Resistance.
requiredasreferencefiltersincertainconfigurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
IN(CM)
REF(CM)
REF(CM)
Negligible Error
Unbalanced Resistance
Results in an Offset Which
Can be Calibrated
+
+
Varying
C
> 1nF at Both IN
Minimize IN and
EXT
–
–
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
V
– V
and IN . Can Take Large IN Capacitors and Avoid
Source Resistance with Large Source Impedance
IN(CM)
Negligible Error
(<5k Recommended)
resistanceis1MΩwhichgeneratesafull-scale(V /2)gain
REF
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
errorof0.51ppmforeachohmofsourceresistancedriving
+
–
the REF and REF pins. For 50Hz/60Hz mode, the related
difference resistance is 1.1MΩ and the resulting full-scale
erroris0.46ppm for eachohmofsourceresistancedriving
2481fd
24
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LTC2481
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the REF and REF pins. For 50Hz mode, the related differ-
ence resistance is 1.2MΩ and the resulting full-scale error
is 0.42ppm for each ohm of source resistance driving the
+
–
pin current as expressed in Figure 12. When using internal
oscillatorand60Hzmode,every100Ωofreferencesource
resistance translates into about 0.67ppm additional INL
error.Whenusinginternaloscillatorand50Hz/60Hzmode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillatorand50Hzmode,every100Ωofreferencesource
resistance translates into about 0.56ppm additional INL
+
–
REF and REF pins. When CA0/f is driven by an external
0
oscillatorwithafrequencyf
(externalconversionclock
EOSC
operation), the typical differential reference resistance is
12
0.30 • 10 /f
Ω and each ohm of source resistance
EOSC
+
–
–6
driving the REF or REF pins will result in 1.67 • 10
•
f
ppm gain error. The typical +FS and –FS errors for
is driven by an external oscillator
error. When CA0/f
EOSC
0
various combinations of source resistance seen by the
with a frequency f
, every 100Ω of source resistance
EOSC
+
–
+
–
–6
REF or REF pins and external capacitance connected to
that pin are shown in Figures 16-19.
driving REF or REF translates into about 2.18 • 10
•
f
ppmadditionalINLerror. Figure 20showsthetypical
EOSC
+
INL error due to the source resistance driving the REF
In addition to this gain error, the converter INL per-
formance is degraded by the reference source imped-
–
or REF pins when large C
values are used. The user
REF
is advised to minimize the source impedance driving the
ance. The INL is caused by the input dependent terms
+
–
REF and REF pins.
2
–V /(V • R ) – (0.5 • V • D )/R in the reference
IN
REF
EQ
REF
T
EQ
500
90
V
V
V
V
= 5V
= 5V
= 3.75V
= 1.25V
= 25°C
V
V
V
V
= 5V
CC
CC
C
= 1µF, 10µF
REF
80
70
60
50
40
30
20
10
0
= 5V
REF
REF
+
+
= 3.75V
= 1.25V
IN
–
IN
–
400
300
200
100
0
IN
IN
T
T
= 25°C
A
A
C
= 0.1µF
REF
C
= 0.01µF
REF
C
= 0.001µF
REF
C
= 100pF
REF
C
= 0pF
REF
C
= 0.01µF
REF
–10
0
200
400
R
600
(Ω)
800
1000
0
10
100
R
1k
(Ω)
10k
100k
SOURCE
SOURCE
2481 F18
2481 F16
Figure 16. +FS Error vs RSOURCE at REF+ or REF– (Small CREF
)
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Large CREF
)
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
C
REF
C
= 0.01µF
REF
–100
C
= 0.001µF
C
= 0.01µF
REF
= 100pF
REF
REF
C
= 0pF
–200
–300
–400
–500
C
= 1µF, 10µF
REF
C
= 0.1µF
REF
V
V
V
V
T
= 5V
= 5V
= 1.25V
= 3.75V
= 25°C
V
V
V
V
T
= 5V
CC
CC
= 5V
REF
REF
+
+
= 1.25V
= 3.75V
IN
–
IN
–
IN
A
IN
= 25°C
A
0
10
100
R
1k
10k
100k
0
200
400
R
600
(Ω)
800
1000
(Ω)
SOURCE
SOURCE
2481 F19
2481 F17
Figure 17. –FS Error vs RSOURCE at REF+ or REF– (Small CREF
)
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Large CREF
)
2481fd
25
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In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
+
voltage difference (V
– V
) and a 5V reference,
INCM
used for the external source impedance seen by V
REFCM
REF
–
each Ohm of reference source resistance introduces an
extra (V – V )/(V • R ) full-scale gain error,
and V
, the expected drift of the dynamic current gain
REF
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
REFCM
INCM
REF
EQ
whichis0.074ppmwhenusinginternaloscillatorand60Hz
mode.Whenusinginternaloscillatorand50Hz/60Hzmode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA ( 100nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 5µV
maximum full-scale error.
0.061ppm. If an external clock is used, the corresponding
–6
extra gain error is 0.24 • 10 • f
ppm.
EOSC
The magnitude of the dynamic reference current depends
uponthesizeoftheverystableinternalsamplingcapacitors
andupontheaccuracyoftheconvertersamplingclock.The
accuracy of the internal clock over the entire temperature
10
3500
V
V
= V
REF
V
V
V
= 5V
= 5V
IN(CM)
CC
REF(CM)
= 5V
CC
REF
= V
8
6
3000
2500
R = 1k
CA0/f = EXT CLOCK
= 2.5V
0
IN(CM)
T
= 25°C
A
T
T
= 25°C
= 85°C
A
A
C
= 10µF
REF
4
2
2000
1500
1000
500
R = 500Ω
R = 100Ω
0
–2
–4
–6
–8
–10
0
0
30
–0.5
–0.3
–0.1
/V
0.1
(V)
0.3
0.5
10
20
OUTPUT DATA RATE (READINGS/SEC)
V
IN REF
2481 F20
2481 F22
Figure 22. +FS Error vs Output Data Rate and Temperature
Figure 20. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for CREF > 1µF
50
0
V
V
V
= V
REF
IN(CM)
REF(CM)
= 5V
= V
CC
IN
–500
40
= 0V
CA0/f = EXT CLOCK
0
–1000
T
T
= 25°C
= 85°C
A
A
30
20
–1500
–2000
10
0
T
T
= V
REF
= 25°C
= 85°C
A
A
–2500
–3000
–3500
V
V
IN(CM)
CC
REF(CM)
= 5V
= V
CA0/f = EXT CLOCK
0
–10
0
10
20
30
0
30
10
20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2481 F21
2481 F23
Figure 23. –FS Error vs Output Data Rate and Temperature
Figure 21. Offset Error vs Output Data Rate and Temperature
2481fd
26
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Output Data Rate
Typicalmeasuredperformancecurvesforoutputdatarates
up to 25 readings per second are shown in Figures 21 to
28. Inordertoobtainthehighestpossiblelevelofaccuracy
from this converter at output data rates above 20 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. In certain circumstances, a reduc-
tion of the differential reference voltage may be beneficial.
Whenusingitsinternaloscillator,theLTC2481producesup
to 7.5 samples per second (sps) with a notch frequency of
60Hz,6.25spswithanotchfrequencyof50Hzand6.82sps
with the 50Hz/60Hz rejection mode. The actual output
data rate will depend upon the length of the sleep and
data output phases which are controlled by the user and
which can be made insignificantly short. When operated
with an external conversion clock (CA0/f connected to
0
Input Bandwidth
an external oscillator), the LTC2481 output data rate can
4
The combined effect of the internal SINC digital filter and
be increased as desired. The duration of the conversion
oftheanaloganddigitalautocalibrationcircuitsdetermines
the LTC2481 input bandwidth. When the internal oscillator
isusedwiththenotchsetat60Hz, the3dBinputbandwidth
is 3.63Hz. When the internal oscillator is used with the
notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If
phase is 41036/f . If f
EOSC
= 307.2kHz, the converter
EOSC
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in f
over the nominal 307.2kHz will
EOSC
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by two potential effects, which must
be carefully considered.
an external conversion clock generator of frequency f
EOSC
is connected to the CA0/f pin, the 3dB input bandwidth
0
–6
is 11.8 • 10 • f
.
EOSC
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2481 input bandwidth is shown in
First, a change in f
will result in a proportional change
EOSC
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
quency.Inmanyapplications,thesubsequentperformance
degradation can be substantially reduced by relying upon
theLTC2481’sexceptionalcommonmoderejectionandby
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input filters and should maintain a
very high degree of matching and symmetry in the circuits
Figure 29. When an external oscillator of frequency f
EOSC
is used, the shape of the LTC2481 input bandwidth can
be derived from Figure 29, 60Hz mode curve in which
the horizontal axis is scaled by f
/307200.
EOSC
The conversion noise (600nV
typical for V
= 5V)
RMS
REF
+
–
can be modeled by a white noise source connected to a
noisefreeconverter.Thenoisespectraldensityis47nV√Hz
for an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
driving the IN and IN pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C , C ) are used, the
IN REF
previoussectionprovidesformulaeforevaluatingtheeffect
ofthesourceresistanceupontheconverterperformancefor
any value of f
. If small external input and/or reference
IN REF
EOSC
capacitors (C , C ) are used, the effect of the external
source resistance upon the LTC2481 typical performance
can be inferred from Figures 14, 15, 16 and 17 in which
the horizontal axis is scaled by 307200/f
.
EOSC
2481fd
27
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22
20
18
16
24
20
15
10
5
V
V
= V
REF(CM)
IN(CM)
IN
= 0V
22
CA0/f = EXT CLOCK
= 25°C
0
T
A
20
V
V
= 5V, V
REF
= 2.5V
CC
CC
REF
= V
= 5V
18
16
14
12
T
T
= 25°C
= 85°C
A
A
T
T
= 25°C
= 85°C
A
A
14
12
10
0
–5
V
V
V
= V
REF
= 0V
IN(CM)
CC
IN
REF(CM)
= 5V
V
V
= V
REF
= V
IN(CM)
= V
CC
REF(CM)
= 5V
CA0/f = EXT CLOCK
0
CA0/f = EXT CLOCK
0
RES = LOG 2 (V /NOISE
REF
RES = LOG 2 (V /INL
REF
)
)
MAX
RMS
10
–10
0
30
10
20
0
30
0
30
10
20
10
20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2481 F25
2481 F26
2481 F24
Figure 24. Resolution
(NoiseRMS ≤ 1LSB) vs Output
Data Rate and Temperature
Figure 25. Resolution
(INLMAX ≤ 1LSB) vs Output
Data Rate and Temperature
Figure 26. Offset Error vs Output
Data Rate and Reference Voltage
24
22
22
20
18
16
20
18
V
V
= V
V
V
= V
IN(CM) REF(CM)
IN(CM)
IN
REF(CM)
16
14
12
= 0V
= 0V
IN
14
12
10
CA0/f = EXT CLOCK
= 25°C
CA0/f = EXT CLOCK
0
0
T
T = 25°C
A
RES = LOG 2 (V /INL
A
RES = LOG 2 (V /NOISE
)
)
MAX
REF
RMS
= 2.5V
REF
REF
V
V
= 5V, V
V
V
= 5V, V
REF
= 2.5V
CC
CC
CC
CC
REF
= V
= 5V
= V
= 5V
REF
10
0
30
0
30
10
20
10
20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2481 F27
2481 F28
Figure 27. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 28. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
100
0
–1
50Hz AND
60Hz MODE
–2
60Hz MODE
50Hz MODE
10
1
50Hz MODE
60Hz MODE
–3
–4
–5
–6
0.1
0.1
0
1
2
3
4
5
1
10 100 1k
10k 100k 1M
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
2481 F29
2481 F30
Figure 29. Input Signal Using
the Internal Oscillator
Figure 30. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
2481fd
28
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
When external amplifiers are driving the LTC2481, the
ADC input referred system noise calculation can be
simplified by Figure 30. The noise of an amplifier driving
the LTC2481 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2481 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2481
allows external lowpass filtering without degrading the
DC performance of the device.
corner frequency f . The amplifier noise spectral density
i
is n . From Figure 30, using f as the x-axis selector, we
i
i
canfindonthey-axisthenoiseequivalentbandwidthfreq
i
4
TheSINC digitalfilterprovidesgreaterthan120dBnormal
of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (f ). The
S
LTC2481’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode
signal filtering both in the analog and digital domain.
be calculated as N = n • √freq . The total system noise
i
i
(referred to the LTC2481 input) can now be obtained by
summing as square root of sum of squares the three
ADC input referred noise sources: the LTC2481 internal
Independent of the operating mode, f = 256 • f = 2048
S
N
• f
where f is the notch frequency and f
OUTMAX
N OUTMAX
is the maximum output data rate. In the internal oscilla-
+
noise, the noise of the IN driving amplifier and the noise
tor mode with a 50Hz notch setting, f = 12800Hz, with
–
S
of the IN driving amplifier.
50Hz/60Hz rejection, f = 13960Hz and with a 60Hz notch
S
If the CA0/f pin is driven by an external oscillator of
0
setting f = 15360Hz. In the external oscillator mode, f =
S S
frequency f
, Figure 30 can still be used for noise
EOSC
f
/20. The performance of the normal mode rejection
EOSC
calculation if the x-axis is scaled by f
For large values of the ratio f
/307200.
EOSC
is shown in Figures 31 and 32.
/307200, the Figure 30
EOSC
plot accuracy begins to decrease, but at the same time
the LTC2481 noise floor rises and the noise contribution
of the driving amplifiers lose significance.
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
S S S S S S S S S S S S
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f
S S S S S S S S S S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2481 F32
2481 F31
Figure 31. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 32. Input Normal Mode Rejection at DC
2481fd
29
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
In 1x speed mode, the regions of low rejection occurring
Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2481 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full-scale. In many industrial applications, it is
not uncommon to have to measure microvolt level signals
superimposedonvoltlevelperturbationsandtheLTC2481
is eminently suited for such tasks. When the perturbation
is differential, the specification of interest is the normal
mode rejection for large input signal levels. With a refer-
at integer multiples of f have a very narrow bandwidth.
S
Magnified details of the normal mode rejection curves
are shown in Figure 33 (rejection near DC) and Figure 34
(rejection at f = 256f ) where f represents the notch
S
N
N
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the f value.
N
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 35, 36 and 37. Typical measured values of the
normal mode rejection of the LTC2481 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 35 superimposed over the theoretical calculated
curve. Similarly, the measured normal mode rejection of
the LTC2481 for the 50Hz rejection mode and 50Hz/60Hz
rejection mode are shown in Figures 36 and 37.
ence voltage V = 5V, the LTC2481 has a full-scale dif-
REF
ferential input range of 5V peak-to-peak. Figures 38 and
39 show measurement results for the LTC2481 normal
mode rejection ratio with a 7.5V peak-to-peak (150% of
full scale) input signal superimposed over the more tradi-
tional normal mode rejection ratio results obtained with a
5V peak-to-peak (full-scale) input signal. In Figure 38, the
LTC2481 uses the internal oscillator with the notch set at
60Hz and in Figure 39 it uses the internal oscillator with
the notch set at 50Hz. It is clear that the LTC2481 rejection
performance is maintained with no compromises in this
extreme situation. When operating with large input signal
levels, the user must observe that such signals do not
violate the device absolute maximum ratings.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2481. If passive RC components are placed in
front of the LTC2481, the input dynamic current should
be considered (see Input Current section). In this case,
the differential input current cancellation feature of the
LTC2481 allows external RC networks without significant
degradation in DC performance.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
f
= f
EOSC/5120
N
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–120
0
f
N
2f
N
3f
N
4f
5f
6f
7f
8f
N
250f 252f 254f 256f 258f 260f 262f
N
N
N
N
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT SIGNAL FREQUENCY (Hz)
2481 F33
2481 F34
Figure 33. Input Normal Mode Rejection at DC
Figure 34. Input Normal Mode Rejection at fs = 256fN
2481fd
30
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
0
0
–20
–20
–40
5V
V
5V
V
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2481 F35
2481 F36
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz Notch)
0
0
V
V
V
T
= 5V
= 5V
CC
V
V
= 5V
= 7.5V
IN(P-P)
REF
IN(P-P)
–20
–40
–20
–40
= 2.5V
INCM
(150% OF FULL SCALE)
= 25°C
A
–60
–60
–80
–80
–100
–120
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
220
INPUT FREQUENCY (Hz)
2481 F38
2481 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode)
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (60Hz Notch)
0
–20
V
= 5V
CC
V
= 5V
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2481 F39
Figure 39. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (50Hz Notch)
2481fd
31
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (f )
f
2f
3f
4f 5f
N
6f
7f
8f
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (f )
N
N
2481 F40
2481 F41
Figure 40. Input Normal Mode Rejection 2x Speed Mode
Figure 41. Input Normal Mode Rejection 2x Speed Mode
–70
0
MEASURED DATA
CALCULATED DATA
V
V
V
V
= 5V
CC
= 5V
REF
–80
–20
–40
= 2.5V
INCM
NO AVERAGE
= 5V
IN(P-P)
–90
T
A
= 25°C
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
–140
–60
–80
–100
–120
56
58
60
62
48 50
52
54
0
25 50 75 100 125 150 175 200 225
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
2481 F43
2481 F42
Figure 42. Input Normal Mode Rejection vs Input
Frequency, 2x Speed Mode and 50Hz/60Hz Mode
Figure 43. Input Normal Mode Rejection 2x Speed Mode
5V
C8
1µF
C7
0.1µF
ISOTHERMAL
LT1236
2
6
5
1.7k
1
2
1.7k
IN OUT
TRIM
GND
4
R2
2k
+
6
7
9
10
REF
V
CC
R7
8k
SCL
SDA
CA1
4
5
+
+
–
IN
G1
NC1M4V0
LTC2481
–
R8
1k
CA0/f
0
IN
REF GND
3
8
2481 F44
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
26.3C
Figure 44. Calibration Setup
2481fd
32
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
Using the 2x speed mode of the LTC2481, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
is maintained as shown in Figures 31 and 32. However,
Complete Thermocouple Measurement System with
Cold Junction Compensation
The LTC2481 is ideal for direct digitization of thermo-
couples and other low voltage output sensors. The input
has a typical offset error of 500nV (2.5µV max) offset
the magnified details near DC and f = 256f are different,
S
N
see Figures 40 and 41. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
mode. Typical measured values of the normal mode rejec-
tion of the LTC2481 operating with the internal oscillator
and 2x speed mode is shown in Figure 42.
drift of 10nV/°C and a noise level of 600nV . The input
RMS
span may be optimized for various sensors by setting the
gain of the PGA. Using an external 5V reference with a
PGA gain of 64 gives a 78mV input range—perfect for
thermocouples.
Figure 45 (page 39 of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
meter, the cold junction temperature sensor must be at
the same temperature as the junction between the ther-
mocouple materials and the copper printed circuit board
traces. The tiny LTC2481 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
When the LTC2481 is configured in 2x speed mode, by
1
performing a running average, a SINC notch is combined
4
with the SINC digital filter, yielding the normal mode
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
The LTC2481’s 1.4mV/°C PTAT circuit measures the cold
junction temperature. Once the thermocouple voltage
and cold junction temperature are known, there are
many ways of calculating the thermocouple temperature
including a straight-line approximation, lookup tables or a
polynomial curve fit. Calibration is performed by applying
an accurate 500mV to the ADC input derived from an
LT®1236 reference and measuring the local temperature
with an accurate thermometer as shown in Figure 44. In
calibration mode, the up and down buttons are used to
adjust the local temperature reading until it matches an
accurate thermometer. Both the voltage and temperature
calibration are easily automated.
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effectiveoutputrate,asshowninFigure43.Therawoutput
data provides a better than 70dB rejection over 48Hz to
62.4Hz,whichcoversboth50Hz 2%and60Hz 2%.With
running average on, the rejection is better than 87dB for
both 50Hz 2% and 60Hz 2%.
The complete microcontroller code for this application is
available on the LTC2481 product webpage at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2481()
function controls the operation of the LTC2481 and is
listed below for reference.
2481fd
33
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
/*
LTC248X.h
Processor setup and
Lots of useful defines for configuring the LTC2481 and LTC2485.
*/
#include <16F73.h>
// Device
// 6MHz clock
#use delay(clock=6000000)
//#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT
// Configuration fuses
#rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config.
#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port
#include “PCM73A.h”
#include “lcd.c”
// Various defines
// LCD driver functions
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the
// 8 bit config word.
#define READ
#define WRITE
0x01
0x00
// bitwise OR with address for read or write
#define LTC248XADDR 0b01001000
// The one and only LTC248X in this circuit,
// with both address lines floating.
// Select gain - 1 to 256 (also depends on speed setting)
#define GAIN1 0b00000000
#define GAIN2 0b00100000
#define GAIN3 0b01000000
#define GAIN4 0b01100000
#define GAIN5 0b10000000
#define GAIN6 0b10100000
#define GAIN7 0b11000000
#define GAIN8 0b11100000
// G = 1
// G = 4
// G = 8
(SPD = 0), G = 1
(SPD = 0), G = 2
(SPD = 0), G = 4
(SPD = 1)
(SPD = 1)
(SPD = 1)
(SPD = 1)
// G = 16 (SPD = 0), G = 8
// G = 32 (SPD = 0), G = 16 (SPD = 1)
// G = 64 (SPD = 0), G = 32 (SPD = 1)
// G = 128 (SPD = 0), G = 64 (SPD = 1)
// G = 256 (SPD = 0), G = 128 (SPD = 1)
// Select ADC source - differential input or PTAT circuit
#define VIN
#define PTAT
0b00000000
0b00001000
// Select rejection frequency - 50, 55, or 60Hz
#define R50
#define R55
#define R60
0b00000010
0b00000000
0b00000100
// Speed settings is bit 7 in the 2nd byte
#define SLOW
#define FAST
0b00000000 // slow output rate with autozero
0b00000001 // fast output rate with no autozero
2481fd
34
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
/*
LTC2481.c
Basic voltmeter test program for LTC2481
Reads LTC2481 input at gain = 1, 1X speed mode, converts to volts,
and prints voltage to a 2 line by 16 character LCD display.
Mark Thoren
Linear Technology Corporation
June 23, 2005
Written for CCS PCM compiler, Version 3.182
*/
#include “LTC248X.h”
/*** read_LTC2481() ************************************************************
This is the function that actually does all the work of talking to the LTC2481.
Arguments: addr - device address
config - configuration bits for next conversion
Returns:
zero if conversion is in progress,
32 bit signed integer with lower 8 bits clear, 24 bit LTC2481
output word in the upper 24 bits. Data is left-justified for
compatibility with the 24 bit LTC2485.
the i2c_xxxx() functions do the following:
void i2c_start(void): generate an i2c start or repeat start condition
void i2c_stop(void): generate an i2c stop condition
char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack
boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device
These functions are very compiler specific, and can use either a hardware i2c
port or software emulation of an i2c port. This example uses software emulation.
A good starting point when porting to other processors is to write your own
i2c functions. Note that each processor has its own way of configuring
the i2c port, and different compilers may or may not have built-in functions
for the i2c port.
When in doubt, you can always write a “bit bang” function for troubleshooting purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
Also note that the lower 4 bits are the configuration word from the previous conversion.
2481fd
35
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
*******************************************************************************/
signed int32 read_LTC2481(char addr, char config)
{
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
union
// adc_code.bits32
// adc_code.by.te0
// adc_code.by.te1
// adc_code.by.te2
// adc_code.by.te3
all 32 bits
byte 0
{
signed int32 bits32;
struct fourbytes by;
} adc_code;
byte 1
byte 2
byte 3
// Start communication with LTC2481:
i2c_start();
if(i2c_write(addr | WRITE))// If no acknowledge, return zero
{
i2c_stop();
return 0;
}
i2c_write(config);
i2c_start();
i2c_write(addr | READ);
adc_code.by.te3 = i2c_read();
adc_code.by.te2 = i2c_read();
adc_code.by.te1 = i2c_read();
adc_code.by.te0 = 0;
i2c_stop();
return adc_code.bits32;
} // End of read_LTC2481()
/*** initialize() **************************************************************
Basic hardware initialization of controller and LCD, send Hello message to LCD
*******************************************************************************/
void initialize(void)
{
// General initialization stuff.
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
// This is the important part - configuring the SPI port
setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock
CKP = 0; // Set up clock edges - clock idles low, data changes on
CKE = 1; // falling edges, valid on rising edges.
2481fd
36
For more information www.linear.com/LTC2481
LTC2481
applicaTions inForMaTion
lcd_init();
// Initialize LCD
delay_ms(6);
printf(lcd_putc, “Hello!”);
delay_ms(500);
} // End of initialize()
// Obligatory hello message
// for half a second
*** main() ********************************************************************
Main program initializes microcontroller registers, then reads the LTC2481
repeatedly
*******************************************************************************/
void main()
{
signed int32 x;
float voltage;
int16 timeout;
initialize();
// Integer result from LTC2481
// Variable for floating point math
// Hardware initialization
while(1)
{
delay_ms(1);
// Pace the main loop to something more than 1 ms
// This is a basic error detection scheme. The LTC248X will never take more than
// 163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50Hz, 55Hz, and 60Hz
// rejection modes, respectively.
// If read_LTC248X() does not return non-zero within this time period, something
// is wrong, such as an incorrect i2c address or bus conflict.
if((x = read_LTC2481(LTC248XADDR, GAIN1 | VIN | R55)) != 0)
{
// No timeout, everything is okay
timeout = 0;
// reset timer
x &= 0xFFFFFFC0;
x ^= 0x80000000;
voltage = (float) x;
// clear config bits so they don’t affect math
// Invert MSB, result is 2’s complement
// convert to float
voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31
lcd_putc(‘\f’);
lcd_gotoxy(1,1);
printf(lcd_putc, “V %01.4f”, voltage); // Display voltage
}
// Clear screen
// Goto home position
else
{
++timeout;
}
if(timeout > 200)
{
timeout = 200;
lcd_gotoxy(1,1);
// Prevent rollover
printf(lcd_putc, “ERROR - TIMEOUT”);
delay_ms(500);
}
} // End of main loop
} // End of main()
2481fd
37
For more information www.linear.com/LTC2481
LTC2481
package DescripTion
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN REV B 0309
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2481fd
38
For more information www.linear.com/LTC2481
LTC2481
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/09 Update Tables 3 and 4
16
B
04/10 Added H-grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed),
Converter Characteristics, Power Requirements, Timing Characteristics, and Typical Performance Characteristics
2-10
C
D
06/10 Revised Typical Application drawing
1
2
Added text to I C Interface section
12
09/14 Clarify Temperature Sensor Performance
1, 2
Clarify Performance vs f Frequency, reducing external oscillator max frequency to 1MHz
5, 8, 26, 28
O
2481fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
39
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2481
Typical applicaTion
5V
PIC16F73
RC7
C8
C7
0.1µF
20
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
5V
V
1µF
DD
C6
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
0.1µF
ISOTHERMAL
1.7k
1.7k
Y1
3
2
R2
2k
9
6MHz
6
REF
V
CC
SCL
SDA
OSC1
OSC2
4
5
+
–
IN
7
10
LTC2481
D1
BAT54
R1
10k
IN
10
TYPE K
THERMOCOUPLE
JACK
– CAO/f
O
CA1 GND REF
1
5V
MCLR
9
8
3
(OMEGA MPJ-K-F)
5V
D7
V
CC
D6
D5
D4
EN
RW
RS
2 × 16 CHARACTER
LCD DISPLAY
(OPTREX DMC162488
OR SIMILAR)
6
5
4
3
5V
1
3
R6
5k
9
CONTRAST
V
V
SS
SS
19
GND D0 D1 D2 D3
2
2
5V
2481 F45
R3
R4
R5
CALIBRATE
10k 10k 10k
2
1
DOWN
UP
Figure 45. Complete Type K Thermocouple Meter
relaTeD parTs
PART NUMBER
LT1236A-5
LT1460
DESCRIPTION
COMMENTS
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
24-Bit, No Latency ∆Σ ADC in SO-8
LTC2400
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
0.8µV
Noise, 2ppm INL
24-Bit, No Latency ∆Σ ADC with Differential Inputs
24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP
RMS
LTC2411/LTC2411-1
1.45µV
(LTC2411-1)
Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection
RMS
LTC2413
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
24-Bit, No Latency ∆Σ ADC with Differential Inputs
24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate
8-/16-Channel 24-Bit, No Latency ∆Σ ADCs
High Speed, Low Noise 24-Bit ∆Σ ADC
LTC2415/LTC2415-1
LTC2414/LTC2418
LTC2440
Pin Compatible with the LTC2410
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
Pin Compatible with LTC2482/LTC2484
LTC2480
16-Bit ∆Σ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
LTC2482
LTC2483
LTC2484
LTC2485
Pin Compatible with LTC2480/LTC2484
Pin Compatible with LTC2481/LTC2483
Pin Compatible with LTC2480/LTC2482
Pin Compatible with LTC2481/LTC2483
16-Bit ∆Σ ADC with Easy Drive Inputs
2
16-Bit ∆Σ ADC with Easy Drive Inputs, I C Interface
24-Bit ∆Σ ADC with Easy Drive Inputs
2
24-Bit ∆Σ ADC with Easy Drive Inputs, I C Interface and
Temperature Sensor
2481fd
LT 0914 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
40
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2481
●
●
LINEAR TECHNOLOGY CORPORATION 2005
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