LTC2600CGN [Linear]
Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP; 八通道16位/ 14位/ 12位轨至轨数模转换器采用16引脚SSOP
| 型号： | LTC2600CGN |
| 厂家： | 
Linear |
| 描述： | Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP |
| 文件： | 总16页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2600/LTC2610/LTC2620
Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
U
DESCRIPTIO
FEATURES
The LTC®2600/LTC2610/LTC2620 are octal 16-, 14- and
12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in
16-lead narrow SSOP packages. They have built-in high
performance output buffers and are guaranteed mono-
tonic.
■
Smallest Pin-Compatible Octal DACs:
LTC2600: 16 Bits
LTC2610: 14 Bits
LTC2620: 12 Bits
■
Guaranteed 16-Bit Monotonic Over Temperature
■
Wide 2.5V to 5.5V Supply Range
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive, crosstalk and load regulation in single-
supply, voltage-output multiples.
The parts use a simple SPI/MICROWIRETM compatible
3-wireserialinterfacewhichcanbeoperatedatclockrates
up to 50MHz. Daisy-chain capability and a hardware CLR
function are included.
■
Low Power Operation: 250µA per DAC at 3V
■
Individual Channel Power-Down to 1µA, Max
■
Ultralow Crosstalk between DACs (<10µV)
■
High Rail-to-Rail Output Drive (±15mA, Min)
■
Double-Buffered Digital Inputs
■
Pin-Compatible 10-/8-Bit Versions
(LTC1660/LTC1665)
■
Tiny 16-Lead Narrow SSOP Package
U
The LTC2600/LTC2610/LTC2620 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
lessthan10mVabovezeroscale;andafterpower-up, they
stay at zero scale until a valid write and update take place.
APPLICATIO S
■
Mobile Communications
■
Process Control and Industrial Automation
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Instrumentation
Automatic Test Equipment
■
W
BLOCK DIAGRA
GND
1
16
15
V
V
CC
DAC A
DAC H
V
2
OUT A
OUT H
Differential Nonlinearity (LTC2600)
DAC B
DAC C
DAC G
DAC F
V
V
V
V
3
4
14
13
OUT B
OUT G
OUT F
1.0
V
V
= 5V
REF
CC
0.8
0.6
= 4.096V
0.4
OUT C
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DAC D
DAC E
V
V
5
12
OUT D
REF
OUT E
CLR
SDO
6
7
8
11
10
9
POWER-ON
RESET
0
16384
32768
CODE
49152
65535
CONTROL
LOGIC
DECODE
CS/LD
SCK
2600 G21
32-BIT SHIFT REGISTER
SDI
2600 BD
2600fa
1
LTC2600/LTC2610/LTC2620
W
U
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
(Note 1)
Any Pin to GND........................................... –0.3V to 6V
Any Pin to VCC .............................................–6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC2600C/LTC2610C/LTC2620C .......... 0°C to 70°C
LTC2600I/LTC2610I/LTC2620I.......... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
TOP VIEW
LTC2600CGN
1
2
3
4
5
6
7
8
V
V
V
V
V
16
15
14
13
12
11
10
9
GND
CC
LTC2600IGN
LTC2610CGN
LTC2610IGN
LTC2620CGN
LTC2620IGN
V
V
V
V
OUT H
OUT G
OUT F
OUT E
OUT A
OUT B
OUT C
OUT D
REF
CLR
SDO
SDI
CS/LD
SCK
GN PART MARKING
2600
2600I
2610
2610I
2620
2620I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 150°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620
LTC2610
LTC2600
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
●
●
●
●
12
12
14
14
16
16
Bits
Bits
LSB
LSB
Monotonicity
V
V
V
V
= 5V, V
= 5V, V
= 5V, V
= 4.096V (Note 2)
= 4.096V (Note 2)
= 4.096V (Note 2)
CC
CC
CC
REF
I
I
REF
REF
REF
DNL
INL
Differential Nonlinearity
±0.5
±1
±1
Integral Nonlinearity
Load Regulation
±0.75 ±4
±3 ±16
±12 ±64
= V = 5V, Midscale
CC
= 0mA to 15mA Sourcing
= 0mA to 15mA Sinking
●
●
0.025 0.125
0.025 0.125
0.1
0.1
0.5
0.5
0.3
0.3
2
2
LSB/mA
LSB/mA
OUT
OUT
V
= V = 2.5V, Midscale
CC
OUT
OUT
REF
I
I
= 0mA to 7.5mA Sourcing
= 0mA to 7.5mA Sinking
●
●
0.05 0.25
0.05 0.25
0.2
0.2
1
1
0.8
0.8
4
4
LSB/mA
LSB/mA
ZSE
Zero-Scale Error
Offset Error
V
V
= 5V, V
= 5V, V
= 4.096V Code = 0
= 4.096V (Note 7)
●
●
1
9
1
9
1
9
mV
mV
CC
CC
REF
REF
V
±1
±3
±9
±1
±3
±9
±1
±3
±9
OS
V
Temperature
µV/°C
OS
Coefficient
GE
Gain Error
V
= 5V, V
= 4.096V
●
±0.2 ±0.7
±6.5
±0.2 ±0.7
±6.5
±0.2 ±0.7
±6.5
%FSR
CC
REF
Gain Temperature
Coefficient
ppm/°C
2600fa
2
LTC2600/LTC2610/LTC2620
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER
PSR Power Supply Rejection
CONDITIONS
MIN
TYP
MAX
UNITS
V
= ±10%
–80
dB
CC
R
OUT
DC Output Impedance
V
V
= V = 5V, Midscale; –15mA ≤ I ≤ 15mA
OUT
●
●
0.025
0.030
0.15
0.15
Ω
Ω
REF
REF
CC
= V = 2.5V, Midscale; –7.5mA ≤ I
≤ 7.5mA
CC
OUT
DC Crosstalk (Note 4)
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (per Channel)
±10
±3.5
±7.3
µV
µV/mA
µV
I
Short-Circuit Output Current
V
= 5.5V, V = 5.6V
CC REF
SC
Code: Zero Scale; Forcing Output to V
●
●
15
15
34
34
60
60
mA
mA
CC
Code: Full Scale; Forcing Output to GND
V
= 2.5V, V = 2.6V
CC
REF
Code: Zero Scale; Forcing Output to V
●
●
7.5
7.5
18
24
50
50
mA
mA
CC
Code: Full Scale; Forcing Output to GND
Reference Input
Input Voltage Range
●
●
0
V
V
kΩ
pF
CC
Resistance
Normal Mode
11
16
90
20
Capacitance
I
Reference Current, Power Down Mode All DACs Powered Down
●
0.001
1
µA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
2.5
5.5
V
CC
I
V
V
= 5V (Note 3)
= 3V (Note 3)
●
●
●
●
2.6
2.0
0.35
0.10
4
3.2
1
mA
mA
µA
CC
CC
CC
All DACs Powered Down (Note 3) V = 5V
CC
CC
All DACs Powered Down (Note 3) V = 3V
1
µA
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.5V to 5.5V
= 2.5V to 3.6V
●
●
2.4
2.0
V
V
IH
CC
CC
V
V
V
= 4.5V to 5.5V
= 2.5V to 5.5V
●
●
0.8
0.6
V
V
IL
CC
CC
V
V
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Load Current = –100µA
Load Current = +100µA
●
●
●
●
V
– 0.4
CC
V
V
OH
OL
0.4
±1
8
I
V
= GND to V
CC
µA
pF
LK
IN
C
Digital Input Capacitance
(Note 6)
IN
2600fa
3
LTC2600/LTC2610/LTC2620
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620
LTC2610
LTC2600
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
t
Settling Time (Note 8)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
S
Settling Time for 1LSB Step
(Note 9)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
0.80
1000
12
0.80
1000
12
0.80
1000
12
V/µs
pF
At Midscale Transition
nV • s
kHz
Multiplying Bandwidth
180
180
180
e
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
n
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µV
P-P
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6)
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER
= 2.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
t
t
t
t
t
t
t
t
SDI Valid to SCK Setup
●
●
●
●
●
●
●
4
4
ns
ns
ns
ns
ns
ns
ns
1
SDI Valid to SCK Hold
2
3
4
5
6
7
8
SCK High Time
9
SCK Low Time
9
CS/LD Pulse Width
10
7
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SDO Propagation Delay from SCK Falling Edge
7
C
= 10pF
= 4.5V to 5.5V
= 2.5V to 5.5V
LOAD
V
V
●
●
20
45
ns
ns
CC
CC
t
t
CLR Pulse Width
●
●
●
20
7
ns
ns
9
CS/LD High to SCK Positive Edge
SCK Frequency
10
50% Duty Cycle
50
MHz
Note 5: R = 2kΩ to GND or V
.
CC
Note 1: Absolute maximum ratings are those values beyond which the life
L
of a device may be impaired.
Note 6: Guaranteed by design and not production tested.
Note 2: Linearity and monotonicity are defined from code k to code
L
Note 7: Inferred from measurement at code 256 (LTC2600), code 64
(LTC2610) or code 16 (LTC2620), and at fullscale.
N
N
2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),
L
L
REF
rounded to the nearest whole code. For V = 4.096V and N = 16, k =
REF
L
Note 8: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
CC
REF
256 and linearity is defined from code 256 to code 65,535.
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 3: Digital inputs at 0V or V
.
CC
Note 9: V = 5V, V = 4.096V. DAC is stepped ±1LSB between half
CC
REF
Note 4: DC crosstalk is measured with V = 5V and V = 4.096V, with
CC
REF
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
the measured DAC at midscale, unless otherwise noted.
2600fa
4
LTC2600/LTC2610/LTC2620
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.8
32
24
32
24
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
V
V
= 5V
REF
= 4.096V
= 4.096V
CC
= 4.096V
0.6
16
16
0.4
INL (POS)
INL (NEG)
8
8
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–8
–16
–24
–32
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
2600 G21
2600 G20
2600 G22
DNL vs Temperature
INL vs VREF
DNL vs VREF
1.0
0.8
32
24
1.5
1.0
V
V
= 5V
REF
V
= 5.5V
V
= 5.5V
CC
CC
CC
= 4.096V
0.6
16
0.4
0.5
INL (POS)
INL (NEG)
DNL (POS)
DNL (NEG)
8
DNL (POS)
DNL (NEG)
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–0.5
–1.0
–1.5
–50 –30 –10 10
30
50
70
90
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
V
(V)
REF
REF
2600 G23
2600 G24
2600 G25
Settling to ±1LSB
Settling of Full-Scale Step
V
V
OUT
100µV/DIV
OUT
100µV/DIV
12.3µs
9.7µs
CS/LD
2V/DIV
CS/LD
2V/DIV
2600 G26
2600 G27
2µs/DIV
5µs/DIV
V
= 5V, V
= 4.096V
SETTLING TO ±1LSB
CC
REF
1/4-SCALE TO 3/4-SCALE STEP
= 2k, C = 200pF
V
= 5V, V
= 4.096V
CC
REF
R
CODE 512 TO 65535 STEP
R = 2k, C = 200pF
L
L
L
AVERAGE OF 2048 EVENTS
L
AVERAGE OF 2048 EVENTS
2600fa
5
LTC2600/LTC2610/LTC2620
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2610
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to ±1LSB
8
6
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
4
0.4
V
OUT
2
100µV/DIV
0.2
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
8.9µs
2600 G30
2µs/DIV
V
= 5V, V
= 4.096V
CC
REF
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
L
L
0
4096
8192
12288
16383
0
4096
8192
12288
16383
AVERAGE OF 2048 EVENTS
CODE
CODE
2600 G28
2600 G29
LTC2620
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to ±1LSB
2.0
1.5
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
1.0
6.8µs
0.4
V
OUT
0.5
0.2
1mV/DIV
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
2600 G33
2µs/DIV
V
= 5V, V
= 4.096V
CC
REF
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
0
1024
2048
3072
4095
0
1024
2048
3072
4095
L
L
AVERAGE OF 2048 EVENTS
CODE
CODE
2600 G31
2600 G32
LTC2600/LTC2610/LTC2620
Current Limiting
Load Regulation
Offset Error vs Temperature
0.10
1.0
0.8
3
2
CODE = MIDSCALE
CODE = MIDSCALE
0.08
V
REF
REF
= V = 5V
CC
0.06
0.04
0.6
V
= V = 3V
CC
0.4
1
0.02
0.2
0
0
0
V
REF
= V = 5V
CC
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V = 3V
CC
REF
–1
–2
–3
V
REF
= V = 5V
CC
V
= V = 3V
REF CC
–40 –30 –20 –10
0
10 20 30 40
–35 –25 –15 –5
5
15
25
35
–50 –30 –10 10
30
50
70
90
I
(mA)
I
(mA)
OUT
TEMPERATURE (°C)
OUT
2600 G01
2600 G02
2600 G03
2600fa
6
LTC2600/LTC2610/LTC2620
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Zero-Scale Error vs Temperature
Gain Error vs Temperature
Offset Error vs VCC
3
2.5
2.0
1.5
1.0
0.5
0
0.4
0.3
3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –30 –10 10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
2600 G04
2600 G05
2600 G06
Gain Error vs VCC
ICC Shutdown vs VCC
Large-Signal Response
0.4
0.3
450
400
350
300
250
200
150
100
50
0.2
0.1
V
OUT
0.5V/DIV
0
–0.1
–0.2
–0.3
–0.4
V
= V = 5V
CC
REF
1/4-SCALE TO 3/4-SCALE
2.5µs/DIV
2600 G09
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
CC
(V)
CC
2600 G08
2600 G07
Headroom at Rails
vs Output Current
Power-On Reset Glitch
Midscale Glitch Impulse
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
V
OUT
V
CC
10mV/DIV
3V SOURCING
1V/DIV
12nV-s TYP
4mV PEAK
CS/LD
5V/DIV
V
OUT
10mV/DIV
5V SINKING
2600 G10
2600 G11
250µs/DIV
2.5µs/DIV
3V SINKING
0
1
2
3
4
5
6
7
8
9
10
I
(mA)
OUT
2600 G12
2600fa
7
LTC2600/LTC2610/LTC2620
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Hardware CLR
Supply Current vs Logic Voltage
Exiting Power-Down to Midscale
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
V
= 5V
V
V
= 5V
= 2V
CC
CC
REF
SWEEP SCK, SDI
AND CS/LD
0V TO V
CC
V
OUT
V
OUT
0.5V/DIV
1V/DIV
DACs A TO G IN
POWER-DOWN MODE
CS/LD
5V/DIV
CLR
5V/DIV
2600 G15
2.5µs/DIV
2600 G14
1µs/DIV
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC VOLTAGE (V)
2600 G13
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
V
OUT
10µV/DIV
V
V
V
= 5V
CC
(DC) = 2V
REF
REF
(AC) = 0.2V
P-P
0
1
2
3
4
5
6
7
8
9
10
CODE = FULL SCALE
SECONDS
2600 G17
1k
10k
100k
1M
FREQUENCY (Hz)
2600 G16
Short-Circuit Output Current vs
VOUT (Sourcing)
Short-Circuit Output Current vs
VOUT (Sinking)
0mA
0mA
V
V
= 5.5V
= 5.6V
V
V
= 5.5V
= 5.6V
CC
REF
CC
REF
CODE = 0
SWEPT 0V TO V
CODE = FULL SCALE
V
V
SWEPT V TO 0V
OUT
CC
OUT
CC
1V/DIV
2600 G18
1V/DIV
2600 G19
2600fa
8
LTC2600/LTC2610/LTC2620
U
U
U
PIN FUNCTIONS
LTC2600,LTC2610andLTC2620acceptinputwordlengths
of either 24 or 32 bits.
GND (Pin 1): Analog Ground.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog
Voltage Outputs. The output range is 0 – VREF
.
SDO (Pin 10): Serial Interface Data Output. The serial
outputoftheshiftregisterappearsattheSDOpin.Thedata
transferred to the device via the SDI pin is delayed 32 SCK
rising edges before being output at the next falling edge.
This pin is used for daisy-chain operation.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
WhenCS/LDislow,SCKisenabledforshiftingdataonSDI
into the register. When CS/LD is taken high, SCK is dis-
abled and the specified command (see Table 1) is ex-
ecuted.
CLR (Pin 11): Asynchronous Clear Input. A logic low at
this level-triggered input clears all registers and causes
the DAC voltage outputs to drop to 0V. CMOS and TTL
compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
V
CC (Pin 16): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDIfortransfertothedeviceat therisingedgeofSCK. The
2600fa
9
LTC2600/LTC2610/LTC2620
W
BLOCK DIAGRA
GND
1
16
15
V
V
CC
DAC A
DAC H
V
2
OUT A
OUT H
DAC B
DAC C
DAC G
DAC F
V
V
V
V
3
4
14
13
OUT B
OUT C
OUT G
OUT F
DAC D
DAC E
V
V
5
12
OUT D
REF
OUT E
CLR
SDO
SDI
6
7
8
11
10
9
POWER-ON
RESET
CONTROL
LOGIC
DECODE
CS/LD
SCK
32-BIT SHIFT REGISTER
2600 BD02
W U
W
TI I G DIAGRA
t
1
t
6
t
t
3
t
4
2
SCK
SDI
1
2
3
23
24
t
10
t
t
7
5
CS/LD
SDO
t
8
2600 F01
Figure 1
2600fa
10
LTC2600/LTC2610/LTC2620
U
OPERATIO
Power-On Reset
Serial Interface
TheLTC2600/LTC2610/LTC2620cleartheoutputstozero
scalewhenpowerisfirstapplied,makingsysteminitializa-
tion consistent and repeatable.
TheCS/LDinputisleveltriggered. Whenthisinputistaken
low, it acts as a chip-select signal, powering-on the SDI
andSCKbuffersandenablingtheinputshiftregister. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2600, LTC2610andLTC2620respectively). Datacan
only be transferred to the device when the CS/LD signal is
low.The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2600/
2610/2620containcircuitrytoreducethepower-onglitch:
the analog outputs typically rise less than 10mV above
zero scale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See Power-On Reset Glitch in the Typical Performance
Characteristics section.
Power Supply Sequencing
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DACifithadbeeninpower-downmode. Thedatapathand
registers are shown in the block diagram.
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is
k
2N
VOUT(IDEAL)
=
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device first, fol-
lowed by the 24-bit word as just described. Figure 2b
Table 1.
ADDRESS (n)*
COMMAND*
C3 C2 C1 C0
A3 A2 A1 A0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
*Command and address codes not shown are reserved and should not be used.
2600fa
11
LTC2600/LTC2610/LTC2620
U
OPERATIO
INPUT WORD (LTC2600)
COMMAND
ADDRESS
DATA (16 BITS)
D6
D5 D4 D3 D2 D1
A3 A2
A0
A0
A0
D12
D0
C3
C1
C2
A1
D15 D14 D13
MSB
D11 D10 D9 D8
D7
C0
C0
C0
LSB
2600 TBL01
INPUT WORD (LTC2610)
COMMAND
ADDRESS
DATA (14 BITS + 2 DON’T-CARE BITS)
A3 A2
D12
D6
D5 D4 D3 D2 D1
D0
X
X
C3
C1
A1
D13
D11 D10 D9 D8
D7
C2
MSB
LSB
2600 TBL02
INPUT WORD (LTC2620)
COMMAND
ADDRESS
DATA (12 BITS + 4 DON’T-CARE BITS)
A3 A2
D6
D5 D4 D3 D2 D1
D0
X
X
X
X
C3
C1
A1
D11 D10 D9 D8
MSB
D7
C2
LSB
2600 TBL03
showsthe32-bitsequence.The32-bitwordisrequiredfor
daisy-chain operation, and is also available to accommo-
date microprocessors which have a minimum word width
of 16 bits (2 bytes).
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
Power-Down Mode
Daisy-Chain Operation
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer amplifiers and reference inputs are disabled, and
drawessentiallyzerocurrent.TheDACoutputsareputinto
a high-impedance state, and the output pins are passively
pulled to ground through individual 90k resistors. When
all eight DACs are powered down, the master bias genera-
tion circuit is also disabled. Input- and DAC-register
contents are not disturbed during power-down.
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
TheSDOoutputcanbeusedtofacilitatecontrolofmultiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
inputshiftregisterwhichextendsthroughtheentirechain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the first instruction addresses the last device in the
chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
Any channel or combination of channels can be put into
power-down mode by using command 0100bin combina-
tionwiththeappropriateDACaddress, (n). The16-bitdata
word is ignored. The supply and reference currents are
reduced by approximately 1/8 for each DAC powered
down; the effective resistance at REF (pin 6) rises accord-
ingly, becomingahigh-impedanceinput(typically>1GΩ)
when all eight DACs are powered down.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the first
device as the data input. When the data transfer is com-
plete, CS/LD is taken high, completing the instruction
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
2600fa
12
LTC2600/LTC2610/LTC2620
U
OPERATIO
The selected DAC is powered up as its voltage output is
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.
updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
areinapowered-downstatepriortotheupdatecommand,
the power-up delay is 5µs. If, on the other hand, all eight
DACs are powered down, then the master bias generation
circuit is also disabled and must be restarted. In this case,
the power-up delay is greater: 12µs for VCC = 5V, 30µs for
VCC = 3V.
The PC board should have separate areas for the analog
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
Voltage Outputs
Eachofthe8rail-to-railamplifierscontainedintheseparts
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.025Ω), and will degrade DC crosstalk.
Note that the LTC2600/LTC2610/LTC2620 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25Ω typical channel resistance of the output devices; e.g.,
when sinking 1mA, the minimum output voltage = 25Ω •
1mA = 25mV. See the graph Headroom at Rails vs Output
Current in the Typical Performance Characteristics sec-
tion.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
The amplifiers are stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
“signal” and “power” grounds separated internally and by
reducing shared internal resistance to just 0.005Ω.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
The GND pin functions both as the node to which the
occur.
2600fa
13
LTC2600/LTC2610/LTC2620
U
OPERATIO
2600fa
14
LTC2600/LTC2610/LTC2620
U
OPERATIO
POSITIVE
FSE
V
= V
CC
REF
V
REF
= V
CC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
32, 768
65, 535
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
2600 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2600fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC2600/LTC2610/LTC2620
U
TYPICAL APPLICATIO
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
V
V
V
CC
CC
REF
1
1
TP1
TP2
C1
R1, R3, R4
0.1µF
are 4.99k, 1%
R1
R3
R4
4
5
6
7
R2
7.5k
V
SDA
SS
C2
0.1µF
3
2
6
A2 SCL
11
16
REF
CLR
V
A1 WP
CC
C3
0.1µF
1
8
1
1
1
1
1
1
1
1
1
1
2
TP3
TP14
GND
A0
V
CC
V
V
V
A
B
C
D
E
OUT
OUT
OUT
OUT
DAC A
3
U1
24LC025
4
TP4
DAC B
TP15
GND
SCK
8
7
5
SCK
V
CS
12
13
14
15
TP5
DAC C
LS/LD
V
OUT
14
12
10
8
6
4
13
11
9
7
5
V
F
OUT
+ +
+ +
+ +
+ +
+ +
+ +
+ +
9
TP6
DAC D
SDI
V
OUT
V
OUT
G
H
10
SDO
MOSI
MISO
TP7
DAC E
GND
1
V
REF
V
V
CC
CC
U2
LTC2600CGN
3
1
1
TP8
DAC F
TP16
2
5V
V
IN
C4
C5
0.1µF
J1
TP9
DAC G
0.1µF
HD2X7
R5
7.5k
JP1
TP10
DAC H
R8
22Ω
ON/OFF
3
2
C10
100pF
DISABLE
ADC
7
4
3
2
8
V
IN
1
U4
V
V
MUXOUT ADCIN FS
CC CC
SET
LT1236ACS8-5
2
6
V
REF
V
IN
V
OUT
9
CH0
1
1
5V
TP11
REF
23
R6
7.5k
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
GND
4
CSADC
V
2
3
4.096V
20
25
19
21
24
CS
C7
CSMUX
SCK
C6
0.1µF
JP2
V
4.7µF
6.3V
REF
4-/8-CHANNEL
MUX
20-BIT
ADC
+
SCK
CLK
U5
D
IN
–
LT1461ACS8-4
SD0
2
3
6
V
CC
LTC2424/LTC2428
V
V
OUT
IN
1
26
SHDN
GND
FO
1
1
5V
TP12
CC
REF
5
ZS
SET
GND GND GND GND GND GND GND
16 18 22 27 28
R7
7.5k
V
2
3
C9
0.1µF
C8 REGULATOR
4
1
6
U3
LTC2428CG
1µF
16V
JP3
CC
TP13
GND
V
5V
RELATED PARTS
PART NUMBER
DESCRIPTION
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
COMMENTS
LTC1458: V = 4.5V to 5.5V, V
LTC1458/LTC1458L
= 0V to 4.096V
OUT
OUT
CC
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1654
Dual 14-Bit Rail-to-Rail V
DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
= 5V(3V), Low Power, Deglitched
OUT
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1821
Single 16-Bit V
DAC with Serial Interface in SO-8
V
CC
OUT
Parrallel 5V/3V 16-Bit V
DAC
Low Power, Deglitched, Rail-to-Rail V
OUT
OUT
Octal 10/8-Bit V
DAC in 16-Pin Narrow SSOP
V
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
CC
OUT
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2µs for 10V Step
2600fa
LT/TP 1103 1K REV A • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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