LTC2617CDE#TRPBF_技术文档

LTC2607/LTC2617/LTC2627

16-/14-/12-Bit Dual Rail-to-Rail

2

DACs with I C Interface

Features

Description

The LTC^®2607/LTC2617/LTC2627 are dual 16-, 14- and

12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a

12-leadDFNpackage.Theyhavebuilt-inhighperformance

output buffers and are guaranteed monotonic.

n

Smallest Pin-Compatible Dual DACs:

LTC2607: 16 Bits

LTC2617: 14 Bits

LTC2627: 12 Bits

n

Guaranteed Monotonic Over Temperature

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply,

voltage-output DACs.

n

27 Selectable Addresses

2

n

400kHz I C Interface

n

Wide 2.7V to 5.5V Supply Range

n

Low Power Operation: 260µA per DAC at 3V

2

n

Thepartsusea2-wire, I Ccompatibleserialinterface. The

Power Down to 1µA, Max

n

LTC2607/LTC2617/LTC2627 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). An asynchronous DAC update pin (LDAC) is

also included.

High Rail-to-Rail Output Drive ( 15mA, Min)

n

Ultralow Crosstalk (30µV)

n

Double-Buffered Data Latches

n

Asynchronous DAC Update Pin

n

LTC2607/LTC2617/LTC2627: Power-On Reset to

The LTC2607/LTC2617/LTC2627 incorporate a power-on

resetcircuit.Duringpower-up,thevoltageoutputsriseless

than 10mV above zero scale;and afterpower-up, they stay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2607-1/LTC2617-1/

LTC2627-1 to mid-scale. The voltage outputs stay at mid-

scale until a valid write and update takes place.

Zero Scale

n

LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset

to Mid-Scale

Tiny (3mm × 4mm) 12-Lead DFN Package

n

applications

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5396245 and 6891433. Patent Pending.

n

Mobile Communications

n

Process Control and Industrial Automation

n

Instrumentation

Automatic Test Equipment

n

Block Diagram

9

11

10

8

REFLO

GND

REF

V

CC

Differential Nonlinearity

(LTC2607)

12

V

12-/14-/16-BIT DAC

7

1.0

0.8

V

OUTB

V

= 5V

= 4.096V

CC

OUTA

V

REF

0.6

DAC REGISTER

0.4

0.2

0

INPUT REGISTER

–0.2

–0.4

–0.6

–0.8

–1.0

32-BIT SHIFT REGISTER

0

16384

32768

CODE

49152

65535

2-WIRE INTERFACE

SDA

2607 BD01b

CA0

CA1

LDAC

SCL

CA2

1

2

3

4

5

6

2607 BD01a

26071727fa

ꢀ

LTC2607/LTC2617/LTC2627

aBsolute maximum ratings

pin conFiguration

(Note 1)

TOP VIEW

Any Pin to GND............................................ –0.3V to 6V

Any Pin to V ............................................. –6V to 0.3V

CA0

CA1

1

2

3

4

5

6

12

V

OUTA

CC

11 REFLO

10 GND

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)...................300°C

Operating Temperature Range:

LDAC

SCL

13

9

8

7

REF

SDA

CA2

V

CC

OUTB

LTC2607C/LTC2617C/LTC2627C

DE12 PACKAGE

12-LEAD (4mm s 3mm) PLASTIC DFN

LTC2607C-1/LTC2617C-1/LTC2627C-1 .... 0°C to 70°C

LTC2607I/LTC2617I/LTC2627I

T

= 125°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

LTC2607I-1/LTC2617I-1/LTC2627I-1....–40°C to 85°C

orDer inFormation

LEAD FREE FINISH

LTC2607CDE#PBF

LTC2607IDE#PBF

LTC2607CDE-1#PBF

LTC2607IDE-1#PBF

LTC2617CDE#PBF

LTC2617IDE#PBF

LTC2617CDE-1#PBF

LTC2617IDE-1#PBF

LTC2627CDE#PBF

LTC2627IDE#PBF

LTC2627CDE-1#PBF

LTC2627IDE-1#PBF

TAPE AND REEL

PART MARKING*

2607

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC2607CDE#TRPBF

LTC2607IDE#TRPBF

LTC2607CDE-1#TRPBF

LTC2607IDE-1#TRPBF

LTC2617CDE#TRPBF

LTC2617IDE#TRPBF

LTC2617CDE-1#TRPBF

LTC2617IDE-1#TRPBF

LTC2627CDE#TRPBF

LTC2627IDE#TRPBF

LTC2627CDE-1#TRPBF

LTC2627IDE-1#TRPBF

0°C to 70°C

12-Lead (4mm × 3mm) Plastic DFN

2607

–40°C to 85°C

0°C to 70°C

26071

2617

–40°C to 85°C

0°C to 70°C

2617

–40°C to 85°C

0°C to 70°C

26171

2627

–40°C to 85°C

0°C to 70°C

2627

–40°C to 85°C

0°C to 70°C

26271

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

26071727fa

ꢁ

LTC2607/LTC2617/LTC2627

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), REFLO = 0V,

V_OUTunloaded, unless otherwise noted.

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

l

12

14

16

Bits

LSB

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

0.5

4

1

Integral Nonlinearity

Load Regulation

1.5

5

16

19

64

V

= V = 5V, Mid-Scale

CC

OUT

REF

I

l

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

0.02 0.125

0.03 0.125

0.1

0.5

0.35

0.42

2

LSB/mA

V

= V = 2.7V, Mid-Scale

OUT

REF

I

CC

l

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

0.04 0.25

0.05 0.25

0.2

1

0.7

0.8

4

LSB/mA

l

ZSE

Zero-Scale Error

Offset Error

Code = 0

(Note 6)

1

9

1

7

9

1

7

9

mV

V

OS

1

9

V

OS

Temperature

7

µV/°C

Coefﬁcient

l

GE

Gain Error

0.15

4

0.7

0.15

4

0.7

0.15

4

0.7

%FSR

Gain Temperature

Coefﬁcient

ppm/°C

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C.

REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), REFLO = 0V, V_OUTunloaded, unless otherwise noted.

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

10%

–80

dB

CC

R

DC Output Impedance

V

= V = 5V, Mid-Scale;

REF CC

OUT

l

–15mA ≤ I

≤ 15mA

0.032

0.035

0.15

Ω

OUT

V

= V = 2.7V, Mid-Scale;

CC

REF

–7.5mA ≤ I

≤ 7.5mA

OUT

DC Crosstalk (Note 4)

Due to Full Scale Output Change (Note 5)

Due to Load Current Change

Due to Powering Down (Per Channel)

4

3

30

µV

µV/mA

µV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

SC

CC

REF

l

Code: Zero Scale; Forcing Output to V

15

36

37

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

CC

= 2.7V, V = 2.7V

REF

l

Code: Zero Scale; Forcing Output to V

7.5

22

30

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

l

0

V

kΩ

pF

CC

Resistance

Normal Mode

44

64

30

80

Capacitance

l

I

Reference Current, Power Down Mode

DAC Powered Down

0.001

1

µA

REF

26071727fa

ꢂ

LTC2607/LTC2617/LTC2627

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), REFLO = 0V,

V_OUTunloaded, unless otherwise noted.

SYMBOL PARAMETER

Power Supply

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Positive Supply Voltage

Supply Current

For Speciﬁed Performance

2.7

5.5

V

CC

l

I

V

= 5V (Note 3)

= 3V (Note 3)

0.66

0.52

0.4

1.3

1

mA

µA

CC

DAC Powered Down (Note 3) V = 5V

CC

DAC Powered Down (Note 3) V = 3V

0.10

µA

Digital I/O (Note 11)

l

V

Low Level Input Voltage (SDA and SCL)

High Level Input Voltage (SDA and SCL)

Low Level Input Voltage (LDAC)

0.3V

V

IL

CC

0.7V

IH

CC

l

V

= 4.5V to 5.5V

= 2.7V to 5.5V

0.8

0.6

V

IL(LDAC)

CC

l

V

High Level Input Voltage (LDAC)

V

= 2.7V to 5.5V

= 2.7V to 3.6V

2.4

2.0

V

IH(LDAC)

IL(CAn)

IH(CAn)

CC

l

Low Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1

0.15V

V

CC

l

High Level Input Voltage on CAn (n = 0, 1, 2)

Resistance from CAn (n = 0, 1, 2)

See Test Circuit 1

See Test Circuit 2

0.85V

V

CC

R

10

kΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

l

Resistance from CAn (n = 0, 1, 2)

to GND to Set CAn = GND

See Test Circuit 2

Sink Current = 3mA

kΩ

Resistance from CAn (n = 0, 1, 2)

2

0

MΩ

to V or GND to Set CAn = Float

CC

l

V

Low Level Output Voltage

Output Fall Time

0.4

V

t

V = V

to V = V

,

20 + 0.1C

250

ns

OF

O

B

IH(MIN)

O

IL(MAX)

B

C = 10pF to 400pF (Note 9)

l

t

I

Pulse Width of Spikes Suppressed by Input Filter

Input Leakage

0

50

1

ns

µA

pF

SP

IN

0.1V ≤ V ≤ 0.9V

CC

IN

CC

C

I/O Pin Capacitance

Note 12

10

400

10

IN

Capacitive Load for Each Bus Line

B

External Capacitive Load on Address

Pins CAn (n = 0, 1, 2)

CAX

26071727fa

ꢃ

LTC2607/LTC2617/LTC2627

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), REFLO = 0V,

V_OUTunloaded, unless otherwise noted.

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

t

Settling Time (Note 7)

0.024% ( 1LSB at 12 Bits)

0.006% ( 1LSB at 14 Bits)

0.0015% ( 1LSB at 16 Bits)

7

9

7

9

10

µs

S

Settling Time for 1LSB Step

(Note 8)

0.024% ( 1LSB at 12 Bits)

0.006% ( 1LSB at 14 Bits)

0.0015% ( 1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.8

1000

12

0.8

1000

12

0.8

1000

12

V/µs

pF

At Mid-Scale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise Density At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

µV

P-P

timing characteristics ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (See Figure 1) (Notes 10, 11)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

= 2.7V to 5.5V

l

f

t

SCL Clock Frequency

0

0.6

400

kHz

µs

ns

µs

ns

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

HD(STA)

LOW

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

1.3

0.6

0

0.9

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-Up Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

(Note 9)

20 + 0.1C

0.6

300

B

f

B

SU(STO)

BUF

1.3

Falling Edge of 9th Clock of the 3rd Input Byte to

LDAC High or Low Transition

400

1

l

t

LDAC Low Pulse Width

20

ns

2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: R = 2kΩ to GND or V .

L CC

Note 6: Inferred from measurement at code k (Note 2) and at full scale.

L

Note 7: V = 5V, V

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

CC

REF

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 2: Linearity and monotonicity are deﬁned from code k to code

L

Note 8: V = 5V, V = 4.096V. DAC is stepped 1LSB between half

CC

REF

N

2N – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

L

REF

scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

rounded to the nearest whole code. For V

= 4.096V and N = 16, k =

REF

L

Note 9: C = capacitance of one bus line in pF.

B

256 and linearity is deﬁned from code 256 to code 65,535.

Note 10: All values refer to V

and V

levels.

IL(MAX)

IH(MIN)

Note 3: SDA, SCL and LDAC at 0V or V , CA0, CA1 and CA2 Floating.

CC

Note 11: These speciﬁcations apply to LTC2607/LTC2607-1,

LTC2617/LTC2617-1, LTC2627/LTC2627-1.

Note 12: Guaranteed by design and not production tested.

Note 4: DC crosstalk is measured with V = 5V and V

= 4.096V, with

REF

CC

the measured DAC at mid-scale, unless otherwise noted.

26071727fa

ꢄ

LTC2607/LTC2617/LTC2627

typical perFormance characteristics

LTC2607

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

32

24

1.0

0.8

32

24

V

= 5V

REF

V

= 5V

REF

V

= 5V

CC

= 4.096V

REF

CC

= 4.096V

V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–16

–24

–32

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

2607 G01

2607 G02

2607 G03

DNL vs Temperature

INL vs V_REF

DNL vs V_REF

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

= 5.5V

V

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

DNL (POS)

DNL (NEG)

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–0.5

–1.0

–1.5

–16

–24

–32

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

REF

(V)

V

(V)

REF

2607 G04

2607 G05

2607 G06

Settling to 1LSB

Settling of Full-Scale Step

V

OUT

V

OUT

100µV/DIV

±00µV/DIV

±2.3µs

9.7µs

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

SCL

2V/DIV

9TH CLOCK OF

3RD DATA ꢀYTE

2607 G07

2607 G08

2µs/DIV

5µs/DIV

V

= 5V, V

= 4.096V

REF

CC

SETTLING TO ±±LSꢀ

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

V

= 5V, V

= 4.096V

CC

REF

R

L

CODE 5±2 TO 65535 STEP

AVERAGE OF 2048 EVENTS

26071727fa

ꢅ

LTC2607/LTC2617/LTC2627

typical perFormance characteristics

LTC2617

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

0.2

100µV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9µs

2607 G11

2µs/DIV

V

= 5V, V

= 4.096V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

L

0

4096

8192

CODE

12288

16383

0

4096

8192

CODE

12288

16383

AVERAGE OF 2048 EVENTS

2607 G09

2607 G10

LTC2627

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

2.0

1.5

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

1.0

6.8µs

0.4

V

OUT

0.5

0.2

1mV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2607 G14

2µs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

R

0

1024

2048

CODE

3072

4095

0

1024

2048

CODE

3072

4095

L

AVERAGE OF 2048 EVENTS

2607 G12

2607 G13

26071727fa

ꢆ

LTC2607/LTC2617/LTC2627

typical perFormance characteristics

LTC2607/LTC2617/LTC2627

Current Limiting

Load Regulation

Offset Error vs Temperature

0.10

0.08

0.06

0.04

0.02

0

1.0

0.8

3

2

CODE = MID-SCALE

V

= V = 5V

CC

REF

0.6

= V = 3V

CC

0.4

1

0.2

0

V

= V = 5V

CC

REF

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 3V

CC

REF

–1

–2

–3

V

= V = 5V

CC

V

= V = 3V

REF CC

–40 –30 –20 –10

0

10 20 30 40

–35 –25 –15 –5

5

15

25

35

–50 –30 –10 10

30

50

70

90

I

(mA)

I

(mA)

TEMPERATURE (°C)

OUT

2607 G15

2607 G16

2607 G17

Zero-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs V_CC

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

(V)

CC

2607 G18

2607 G19

2607 G20

Gain Error vs V_CC

I_CCShutdown vs V_CC

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2607 G21

2607 G22

26071727fa

ꢇ

LTC2607/LTC2617/LTC2627

typical perFormance characteristics

LTC2607/LTC2617/LTC2627

Large-Signal Response

Mid-Scale Glitch Impulse

Power-On Reset to Zeroscale

TRANSITION FROM

MS-1 TO MS

V

OUT

V

CC

10mV/DIV

1V/DIV

V

OUT

0.5V/DIV

TRANSITION FROM

MS TO MS-1

9TH CLOCK

OF 3RD DATA

BYTE

4mV PEAK

SCL

2V/DIV

V

= V = 5V

CC

REF

V

OUT

1/4-SCALE TO 3/4-SCALE

10mV/DIV

2607 G24

2607 G25

2.5µs/DIV

2607 G23

250µs/DIV

Headroom at Rails

vs Output Current

Power-On Reset to Midscale

Supply Current vs Logic Voltage

950

900

850

800

750

700

650

600

550

500

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= V

CC

REF

5V SOURCING

V

CC

= 5V

SWEEP LDAC

OV TO V

CC

3V SOURCING

1V/DIV

5V SINKING

V

CC

3V SINKING

V

OUT

2607 G27

500µs/DIV

0

1

2

3

4

I

5

(mA)

6

7

8

9

10

0

0.5

1

1.5

2

2.5

5

3

3.5

4

4.5

LOGIC VOLTAGE (V)

OUT

2607 G26

2607 G28

Output Voltage Noise,

0.1Hz to 10Hz

Multiplying Bandwidth

Supply Current vs Logic Voltage

0

–3

1300

1200

1100

1000

V

= 5V

CC

SWEEP SCL AND

SDA OV TO V

AND V TO OV

CC

–6

CC

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

V

OUT

HYSTERSIS

370mV

10µV/DIV

900

800

700

600

500

V

= 5V

CC

(DC) = 2V

REF

0

1

2

3

4

5

6

7

8

9

10

(AC) = 0.2V

P-P

CODE = FULL SCALE

SECONDS

2607 G31

1k

10k

100k

1M

1

2

4

0

5

3

FREQUENCY (Hz)

LOGIC VOLTAGE (V)

2607 G30

2607 G029

26071727fa

ꢈ

LTC2607/LTC2617/LTC2627

typical perFormance characteristics

LTC2607/LTC2617/LTC2627

Short-Circuit Output Current vs

V_OUT(Sinking)

Short-Circuit Output Current vs

V_OUT(Sourcing)

50

0

–10

–20

–30

V

= 5.5V

REF

CODE = 0

V

= 5.5V

REF

CC

= 5.6V

CODE = FULL SCALE

40

30

20

V

SWEPT 0V TO V

V

SWEPT V TO 0V

OUT

CC

OUT CC

10

0

–40

–50

0

2

3

4

5

6

0

2

3

4

5

6

1

1V/DIV

2607 G32

2607 G33

pin Functions

CA0 (Pin 1): Chip Address Bit 0. Tie this pin to V , GND

CA2 (Pin 6): Chip Address Bit 2. Tie this pin to V , GND

CC

2

or leave it ﬂoating to select an I C slave address for the

part (Table 1).

CA1 (Pin 2): Chip Address Bit 1. Tie this pin to V , GND

V

(Pin 7): DAC Analog Voltage Output. The output

OUTB

CC

2

or leave it ﬂoating to select an I C slave address for the

range is V

to V

.

REFLO

REF

part (Table 1).

V

(Pin 8): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V.

CC

LDAC (Pin 3): Asynchronous DAC Update. A falling edge

of this input after four bytes have been written into the part

immediately updates the DAC register with the contents of

the input register. A low on this input without a complete

32-bit (four bytes including the slave address) data write

transfer to the part wakes up sleeping DACs without up-

dating the DAC output. Software power-down is disabled

when LDAC is low. LDAC is disabled when tied high.

REF (Pin 9): Reference Voltage Input. The input range

is V ≤ V ≤ V .

REFLO

REF

CC

GND (Pin 10): Analog Ground.

REFLO (Pin 11): Reference Low. The voltage at this pin

sets the zero scale (ZS)voltage ofallDACs. The V

REFLO

can be used at voltages up to 1V for V = 5V, or 100mV

CC

for V = 3V.

CC

SCL (Pin 4): Serial Clock Input Pin. Data is shifted into

the SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current

V

(Pin 12): DAC Analog Voltage Output. The output

OUTA

range is V

to V

.

REFLO

REF

Exposed Pad (Pin 13): Ground. Must be soldered to

PCB ground.

source to V .

CC

SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance while data is shifted in and an open-

drainN-channeloutputduringacknowledgment.Requires

a pull-up resistor or current source to V

CC.

26071727fa

ꢀ0

LTC2607/LTC2617/LTC2627

Block Diagram

9

11

10

8

REFLO

GND

REF

V

CC

12-/14-/16-BIT DAC

12

V

7

V

OUTB

OUTA

DAC REGISTER

INPUT REGISTER

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

SDA

CA0

CA1

LDAC

SCL

CA2

5

6

1

2

3

4

2607 BD

test circuits

Test Circuit 1

Test Circuit 2

V

DD

R

/R /R

INH INL INF

100Ω

/V

CAn

V

IH(CAn) IL(CAn)

GND

2607 TC

26071727fa

ꢀꢀ

LTC2607/LTC2617/LTC2627

timing Diagrams

26071727fa

ꢀꢁ

LTC2607/LTC2617/LTC2627

operation

Power-On Reset

2

speciﬁcations. For an I C bus operating in the fast mode,

anactivepull-upwillbenecessaryifthebuscapacitanceis

The LTC2607/LTC2617/LTC2627 clear the outputs to

zero scale when power is ﬁrst applied, making system

initialization consistent and repeatable. The LTC2607-1/

LTC2617-1/LTC2627-1setthevoltageoutputstomidscale

when power is ﬁrst applied.

greaterthan200pF. TheV powershouldnotberemoved

CC

2

from the LTC2607/LTC2617/LTC2627 when the I C bus

2

is active to avoid loading the I C bus lines through the

internal ESD protection diodes.

The LTC2607/LTC2617/LTC2627 are receive-only (slave)

devices. The master can write to the LTC2607/LTC2617/

LTC2627.TheLTC2607/LTC2617/LTC2627donotrespond

to a read from the master.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2607/

LTC2617/LTC2627 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground (typ) during power-on. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

high to low while SCL is high.

Power Supply Sequencing

When the master has ﬁnished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

The voltage at REF (Pin 9) should be kept within the range

–0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-

REF

CC

ings). Particular care should be taken to observe these

2

limitsduringpowersupplyturn-onandturn-offsequences,

another I C device.

when the voltage at V (Pin 8) is in transition.

CC

Acknowledge

Transfer Function

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releasestheSDAline(HIGH)duringtheAcknowledgeclock

pulse. The slave-receiver must pull down the SDA bus line

during the Acknowledge clock pulse so that it remains a

stable LOW during the HIGH period of this clock pulse.

The LTC2607/LTC2617/LTC2627 respond to a write by a

master in this manner. The LTC2607/LTC2617/LTC2627

do not acknowledge a read (retains SDA HIGH during the

period of the Acknowledge clock pulse).

The digital-to-analog transfer function is:

k







V_OUT(IDEAL)

=

V_REF− V_REFLO+ V

REFLO

(

)





^N

2

where k is the decimal equivalent of the binary DAC

input code, N is the resolution and V

REF (Pin 6).

is the voltage at

REF

Serial Digital Interface

The LTC2607/LTC2617/LTC2627 communicate with a

2

host using the standard 2-wire I C interface. The Timing

Diagrams (Figures 1 and 2) show the timing relationship

of the signals on the bus. The two bus lines, SDA and

SCL, must be high when the bus is not in use. External

pull-up resistors or current sources are required on these

lines. The value of these pull-up resistors is dependent

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set

to any one of three states: V , GND or ﬂoat. This results

CC

2

on the power supply and can be obtained from the I C

26071727fa

ꢀꢂ

LTC2607/LTC2617/LTC2627

operation

in 27 selectable addresses for the part. The slave address

assignments are shown in Table 1.

The addresses corresponding to the states of CA0, CA1

and CA2 and the global address are shown in Table 1. The

maximum capacitive load allowed on the address pins

(CA0,CA1andCA2)is10pF,asthesepinsaredrivenduring

address detection to determine if they are ﬂoating.

Table 1. Slave Address Map

CA2

GND

CA1

GND

CA0

GND

SA6 SA5 SA4 SA3 SA2 SA1 SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

FLOAT

Write Word Protocol

GND

V

CC

The master initiates communication with the LTC2607/

LTC2617/LTC2627withaSTARTconditionanda7-bitslave

address followed by the Write bit (W) = 0. The LTC2607/

LTC2617/LTC2627 acknowledges by pulling the SDA pin

low at the 9th clock if the 7-bit slave address matches the

address of the parts (set by CA0, CA1 and CA2) or the

global address. The master then transmits three bytes of

data.TheLTC2607/LTC2617/LTC2627acknowledgeseach

byte of data by pulling the SDA line low at the 9th clock of

eachdatabytetransmission.Afterreceivingthreecomplete

bytesofdata,theLTC2607/LTC2617/LTC2627executesthe

command speciﬁed in the 24-bit input word.

GND

FLOAT

GND

FLOAT FLOAT

FLOAT

GND

V

CC

GND

V

CC

V

CC

V

CC

GND

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

V

CC

FLOAT FLOAT

FLOAT FLOAT FLOAT

FLOAT FLOAT

GND

V

CC

If more than three data bytes are transmitted after a valid

7-bitslaveaddress,theLTC2607/LTC2617/LTC2627donot

acknowledge the extra bytes of data (SDA is high during

the 9th clock).

FLOAT

V

GND

CC

FLOAT

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND

The format of the three data bytes is shown in Figure 3.

The ﬁrst byte of the input word consists of the 4-bit com-

mandwordC3-C0, and4-bitDACaddressA3-A0. Thenext

two bytes consist of the 16-bit data word. The 16-bit data

word consists of the 16-, 14- or 12-bit input code, MSB

to LSB, followed by 0, 2 or 4 don’t care bits (LTC2607,

LTC2617 and LTC2627 respectively). A typical LTC2607

write transaction is shown in Figure 4.

FLOAT

GND

V

CC

FLOAT

GND

FLOAT FLOAT

FLOAT

V

CC

V

GND

CC

FLOAT

V

CC

GLOBAL ADDRESS

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 2. The ﬁrst four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

In addition to the address selected by the address pins,

the parts also respond to a global address. This address

allows a common write to all LTC2607, LTC2617 and

LTC2627 parts to be accomplished with one 3-byte write

transaction on the I C bus. The global address is a 7-bit

on-chip hardwired address and is not selectable by CA0,

CA1 and CA2.

2

26071727fa

ꢀꢃ

LTC2607/LTC2617/LTC2627

operation

Write Word Protocol for LTC2607/LTC2617/LTC1627

W

A

1STDATABYTE

A

2NDDATABYTE

A

3RDDATABYTE

A

P

S

SLAVEADDRESS

INPUT WORD

Input Word (LTC2607)

C3

C1

A3 A2 A1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

C2

C0

A0

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2617)

C3

C1

A3 A2 A1

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

2ND DATA BYTE 3RD DATA BYTE

X

C2

C0

1ST DATA BYTE

Input Word (LTC2627)

C3

C1

A3 A2 A1

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

C2

C0

2607 F03

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Figure 3

appropriateDACaddress. The16-bitdatawordisignored.

Thesupplyandreferencecurrentsarereducedbyapproxi-

mately 50% for each DAC powered down; the effective

resistance at REF (Pin 9) rises accordingly, becoming a

high-impedance input (typically > 1GΩ) when both DACs

are powered down.

Table 2

COMMAND*

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register

Update (Power Up) DAC Register

Write to and Update (Power Up)

Power Down

Normal operation can be resumed by executing any

command which includes a DAC update, as shown in

Table 2 or performing an asychronous update (LDAC) as

describedinthenextsection.TheselectedDACispowered

upasitsvoltageoutputisupdated.WhenaDACinpowered-

down state is powered up and updated, normal settling

is delayed. If one of the two DACs is in a powered- down

state prior to the update command, the power up delay is

5µs. If on the other hand, both DACs are powered down,

the main bias generation circuit has been automatically

shut down in addition to the DAC ampliﬁers and reference

input and so the power up delay time is

No Operation

ADDRESS*

A3 A2 A1 A0

0

1

0

1

0

1

0

1

DAC A

DAC B

All DACs

*Command and address codes not shown are reserved and should not be used.

Power-Down Mode

Forpower-constrainedapplications,thepower-downmode

can be used to reduce the supply current whenever one or

both of the DAC outputs are not needed. When in power-

down,thebufferampliﬁers,biascircuitsandreferenceinput

are disabled and draw essentially zero current. The DAC

outputsareputintoahighimpedancestate,andtheoutput

12µs (for V = 5V) or 30µs (for V = 3V)

CC

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the

LDAC pin asynchronously updates the DAC registers with

the contents of the input registers. Asynchronous update

is disabled when the input word is being clocked into

the part.

pins are passively pulled to V

through 90k resistors.

REFLO

Input-registerandDAC-registercontentsarenotdisturbed

during power-down.

Either or both DAC channels can be put into power-down

mode by using command 0100b in combination with the

26071727fa

ꢀꢄ

LTC2607/LTC2617/LTC2627

operation

If a complete input word has been written to the part, a low

on the LDAC pin causes the DAC registers to be updated

with the contents of the input registers.

Board Layout

The excellent load regulation performance is achieved in

partbyseparatingthesignalandpowergroundsasREFLO

and GND pins, respectively.

If the input word is being written to the part, a low going

pulseontheLDACpinbeforethecompletionofthreebytes

ofdatapowersuptheDACsbutdoesnotcausetheoutputs

to be updated. If LDAC remains low after a complete input

wordhasbeenwrittentothepart,thenLDACisrecognized,

the command speciﬁed in the 24-bit word just transferred

is executed and the DAC outputs updated.

The PC Board should have separate areas for the analog

and digital sections of the circuit. This keeps the digital

signals away from the sensitive analog signals and facili-

tates the use of separate digital and analog ground planes

that have minimal interaction with each other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground. Ideally, the

analog ground plane should be located on the component

side of the board, and should be allowed to run under the

part to shield it from noise. Analog ground should be a

continuous and uninterrupted plane, except for necessary

lead pads and vias, with signal traces on another layer.

The DACs are powered up when LDAC is taken low, inde-

2

pendent of any activity on the I C bus.

If LDAC is low at the falling edge of the 9th clock of the

3rd byte of data, it inhibits any software power-down

command that was speciﬁed in the input word. LDAC is

disabled when tied high.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. Resistance from the GND pin to the analog power

supply return should be as low as possible. Resistance

herewilladddirectlytothechannelresistanceoftheoutput

device when sinking load current. When a zero scale DAC

output voltage of zero is required, the REFLO pin should

be connected to system star ground. Any shared trace

resistance between REFLO and GND pins is undesirable

since it adds to the effective DC output impedance (typi-

Voltage Output

Both of the two rail-to-rail ampliﬁers have guaranteed

load regulation when sourcing or sinking up to 15mA at

5V (7.5mA at 3V).

Load regulation is a measure of the ampliﬁers’ ability to

maintain the rated voltage accuracy over a wide range

of load conditions. The measured change in output volt-

age per milliampere of forced load current change is

expressed in LSB/mA.

Ω) of the part.

cally 0.035

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The ampliﬁers’ DC output

impedance is 0.035Ω when driving a load well away from

the rails.

Rail-to-Rail Output Considerations

Inanyrail-to-railvoltageoutputdevice,theoutputislimited

to voltages within the supply range.

Since the analog output of the device cannot go below

ground,itmaylimitforthelowestcodesasshowninFigure

5b. Similarly, limiting can occur near full scale when the

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited

by the 30Ω typical channel resistance of the output

devices; e.g., when sinking 1mA, the minimum output

voltage = 30Ω • 1mA = 30mV. See the graph Headroom

at Rails vs Output Current in the Typical Performance

Characteristics section.

REF pin is tied to V . If V = V and the DAC full-scale

CC

REF

CC

error (FSE) is positive, the output for the highest codes

limits at V as shown in Figure 5c. No full-scale limiting

CC

will occur if V is less than V – FSE.

REF

CC

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting

can occur.

The ampliﬁers are stable driving capacitive loads of up

to 1000pF.

26071727fa

ꢀꢅ

LTC2607/LTC2617/LTC2627

operation

26071727fa

ꢀꢆ

LTC2607/LTC2617/LTC2627

package Description

DE/UE Package

12-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1695 Rev D)

0.70 p0.05

3.30 p0.05

1.70 p 0.05

3.60 p0.05

2.20 p0.05

PACKAGE OUTLINE

0.25 p 0.05

2.50 REF

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.40 p 0.10

4.00 p0.10

(2 SIDES)

R = 0.115

TYP

7

12

R = 0.05

TYP

3.30 p0.10

3.00 p0.10

(2 SIDES)

1.70 p 0.10

PIN 1

TOP MARK

(NOTE 6)

PIN 1 NOTCH

R = 0.20 OR

0.35 s 45o

CHAMFER

(UE12/DE12) DFN 0806 REV D

6

1

0.25 p 0.05

0.75 p0.05

0.200 REF

0.50 BSC

2.50 REF

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

26071727fa

ꢀꢇ

LTC2607/LTC2617/LTC2627

revision history

REV

DATE

DESCRIPTION

PAGE NUMBER

A

1/10

Revised Features

1

2

Added Pin Conﬁguration and Updated Order Information

Added Text to Serial Digital Interface Section

13

26071727fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ꢀꢈ

LTC2607/LTC2617/LTC2627

typical application

Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

5V

V

REF

1V TO 5V

0.1µF

8

6

REF

2

1

V

CC

3

1

2

6

V

FS

CC

LDAC

CA0

CA1

CA2

SET

100Ω

7.5k

7

3

4

V

CH 1

CH 0

OUTB

9

8

7

SCK

SDO

CS

DAC

OUTPUT B

LTC2607

SPI BUS

LTC2422

4

5

100Ω

7.5k

12

2

SCL

SDA

V

I C BUS

OUTA

10

F

O

ZS

GND

6

DAC

OUTPUT A

SET

5

GND

10, 13

REFLO

2607 TA01

relateD parts

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458: V = 4.5V to 5.5V, V

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

= 0V to 4.096V

OUT

CC

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1664

Single 16-Bit V

DACs with Serial Interface in SO-8

V

CC

OUT

Parallel 5V/3V 16-Bit V

DACs

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 10/8-Bit V

DACs in 16-Pin Narrow SSOP

V

CC

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Quad 10-Bit V

DAC in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

LTC1821

Parallel 16-Bit Voltage Output DAC

Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP

Precision 16-Bit Settling in 2µs for 10V Step

LTC2600/LTC2610/

LTC2620

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2601/LTC2611/

LTC2621

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

DACs in 16-Lead SSOP

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2604/LTC2614/

LTC2624

Quad 16-/14-/12-Bit V

Octal 16-/14-/12-Bit V

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

2

LTC2605/LTC2615/

LTC2625

DACs with I C Interface

250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

2

Output, I C Interface

2

LTC2606/LTC2616/

LTC2626

16-/14-/12-Bit V

DACs with I C Interface

270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

2

Output, I C Interface

2

LTC2609/LTC2619/

LTC2629

Quad 16-/14-/12-Bit V

DACs with I C Interface

250µA Range per DAC, 2.7V to 5.5V Supply Range,

OUT

Rail-to-Rail Output with Separate V Pins for Each DAC

REF

26071727fa

LT 0110 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢁ0

●

 LINEAR TECHNOLOGY CORPORATION 2005

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2617CDE#TRPBF
厂家：	Linear
描述：	LTC2617 - 14-Bit Dual Rail-to-Rail DAC with I<sup>2</sup>C Interface; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总20页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2617CDE#TRPBF [Linear]

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