LTC2617IDE#PBF [Linear]
LTC2617 - 14-Bit Dual Rail-to-Rail DAC with I<sup>2</sup>C Interface; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C;
| 型号： | LTC2617IDE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2617 - 14-Bit Dual Rail-to-Rail DAC with I<sup>2</sup>C Interface; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C |
| 文件： | 总24页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2633
2
Dual 12-/10-/8-Bit I C
V DACs with
OUT
10ppm/°C Reference
Description
Features
n
Integrated Precision Reference
The LTC®2633 is a family of dual 12-, 10-, and 8-bit
voltage-output DACs with an integrated, high accuracy,
low drift reference in an 8-lead TSOT-23 package. It has
rail-to-rail output buffers and is guaranteed monotonic.
TheLTC2633-Lhasafull-scaleoutputof2.5V,andoperates
from a single 2.7V to 5.5V supply. The LTC2633-H has a
full-scale output of 4.096V, and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to the external
reference voltage.
2.5V Full-Scale 10ppm/°C (LTC2633-L)
4.096V Full-Scale 10ppm/°C (LTC2633-H)
n
Maximum INL Error: 1LSꢀ (LTC2633A-12)
n
Low Noise: 0.75mV 0.1Hz to 200kHz
P-P
n
Guaranteed Monotonic Over –40°C to 125°C
Temperature Range
n
n
n
n
n
n
Selectable Internal or External Reference
2.7V to 5.5V Supply Range (LTC2633-L)
Low Power: 0.4mA at 3V
Power-on-Reset to Zero-Scale/Mid-Scale/Hi-Z
Double-Buffered Data Latches
8-Lead ThinSOT™ Package
2
These DACs communicate via a 2-wire I C-compatible
serialinterface.TheLTC2633operatesinboththestandard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). The LTC2633 incorporates a power-on reset
circuit. Options are available for reset to zero-scale, reset
tomid-scaleininternalreferencemode, resettomid-scale
in external reference mode, or reset with all DAC outputs
in a high impedance state after power-up.
applications
n
Mobile Communications
n
Process Control and Industrial Automation
n
Power Supply Margining
Portable Equipment
Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,
6937178, 7414561.
n
n
Block Diagram
REF
INTERNAL
REFERENCE
Integral Nonlinearity (LTC2633A-LZ12)
SWITCH
INL Curve
GND
V
REF
2
V
= 3V
CC
INTERNAL REF.
V
V
CC
1
0
V
OUTA
OUTB
DAC A
DAC B
CONTROL
POWER-ON
–1
–2
DECODE LOGIC
RESET
SCL
SDA
0
1024
2048
CODE
3072
4095
2
I C
CA0
2
ADDRESS
DECODE
I C INTERFACE
2633 TA01
2633 BD
2633fb
1
LTC2633
aBsolute maximum ratings
pin conFiguration
(Notes 1, 2)
Supply Voltage (V ) ................................... –0.3V to 6V
CC
SCL, SDA ..................................................... –0.3V to 6V
OUTA OUTB CC
TOP VIEW
V
, V
....................–0.3V to Min(V + 0.3V, 6V)
SCL 1
CA0 2
REF 3
GND 4
8 SDA
CA0...................................–0.3V to Min(V + 0.3V, 6V)
CC
7 V
6 V
5 V
CC
REF ...................................–0.3V to Min(V + 0.3V, 6V)
CC
OUTB
OUTA
Operating Temperature Range
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
LTC2633C ................................................ 0°C to 70°C
LTC2633H (Note 3) ............................ –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
T
= 150°C (NOTE 6), θ = 195°C/W
JA
JMAX
orDer inFormation
A
C
LTC2633
TS8 –L
Z
12
#TRM PꢀF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
I = Reset to Mid-Scale in Internal Reference Mode
X = Reset to Mid-Scale in External Reference Mode (2.5V Full-Scale
Voltage, Internal Reference Mode Option Only)
O = Reset to Mid-Scale in Internal Reference Mode, DACs High Z
(2.5V Full-Scale Voltage, Internal Reference Mode Option Only)
Z = Reset to Zero-Scale in Internal Reference Mode
FULL-SCALE VOLTAGE INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = 1LSB Maximum INL (12-Bit)
PRODUCT PART NUMꢀER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2633fb
2
LTC2633
proDuct selection guiDe
POWER-ON
REFERENCE
MODE
PART
MARKING**
VFS WITH INTERNAL
REFERENCE
POWER-ON RESET
TO CODE
MAXIMUM
INL
PART NUMꢀER
RESOLUTION
V
CC
LTFTC
LTFTB
LTFSZ
LTFTV
LTFTF
LTFTD
2.5V • (4095/4096)
2.5V • (4095/4096)
2.5V • (4095/4096)
2.5V • (4095/4096)
4.096V • (4095/4096)
4.096V • (4095/4096)
Mid-Scale
Mid-Scale
Internal
External
Internal
Internal
Internal
Internal
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
1LSB
1LSB
1LSB
1LSB
1LSB
1LSB
LTC2633A-LI12
LTC2633A-LX12
LTC2633A-LZ12
LTC2633A-LO12*
LTC2633A-HI12
LTC2633A-HZ12
Zero-Scale
High Impedance
Mid-Scale
Zero-Scale
LTFTC
LTFTJ
LTFTQ
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-LI12
LTC2633-LI10
LTC2633-LI8
LTFTB
LTFTH
LTFTP
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
External
External
External
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-LX12
LTC2633-LX10
LTC2633-LX8
LTFSZ
LTFTG
LTFTN
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Zero-Scale
Zero-Scale
Zero-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-LZ12
LTC2633-LZ10
LTC2633-LZ8
LTFTV
LTFTW
LTFTX
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
High Impedance
High Impedance
High Impedance
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-LO12*
LTC2633-LO10*
LTC2633-LO8*
LTFTF
LTFTM
LTFTS
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-HI12
LTC2633-HI10
LTC2633-HI8
LTFTD
LTFTK
LTFTR
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Zero-Scale
Zero-Scale
Zero-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
2.5LSB
1LSB
0.5LSB
LTC2633-HZ12
LTC2633-HZ10
LTC2633-HZ8
* Contact Linear Technology for other Hi-Z options.
**The temperature grade is identified by a label on the shipping container.
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)
LTC2633-8
LTC2633-10
LTC2633-12
LTC2633A-12
SYMꢀOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
LSB
Monotonicity
V
V
= 3V, Internal Ref. (Note 4)
= 3V, Internal Ref. (Note 4)
CC
DNL
Differential
Nonlinearity
0.5
0.5
1
1
1
CC
l
l
l
INL
Integral Nonlinearity
Zero Scale Error
Offset Error
V
CC
V
CC
V
CC
V
CC
= 3V, Internal Ref. (Note 4)
= 3V, Internal Ref., Code = 0
= 3V, Internal Ref. (Note 5)
= 3V, Internal Ref.
0.05 0.5
0.2
0.5
0.5
10
1
5
1
0.5
0.5
10
2.5
5
0.5
0.5
0.5
10
LSB
mV
ZSE
0.5
0.5
10
5
5
V
V
5
5
5
5
mV
OS
V
Temperature
OS
µV/°C
OSTC
Coefficient
l
GE
Gain Error
V
CC
= 3V, Internal Ref.
0.2 0.8
0.2 0.8
0.2 0.8
0.2 0.8 %FSR
2633fb
3
LTC2633
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)
LTC2633-8
LTC2633-10
LTC2633-12
LTC2633A-12
SYMꢀOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
GE
Gain Temperature
Coefficient
V
CC
= 3V, Internal Ref. (Note 10)
C-Grade
H-Grade
TC
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
Load Regulation
Internal Ref., Mid-Scale,
= 3V 10%,
l
l
V
0.009 0.016
0.009 0.016
0.035 0.064
0.035 0.064
0.14 0.256
0.14 0.256
0.14 0.256 LSB/mA
0.14 0.256 LSB/mA
CC
–5mA ≤ I
≤ 5mA
OUT
V
= 5V 10%,
CC
–10mA ≤ I
≤ 10mA
OUT
R
DC Output
Impedance
Internal Ref., Mid-Scale,
= 3V 10%,
OUT
l
l
V
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
Ω
CC
–5mA ≤ I
≤ 5mA
OUT
V
= 5V 10%,
CC
–10mA ≤ I
≤ 10mA
OUT
SYMꢀOL PARAMETER
CONDITIONS
MIN
TYP
0 to V
MAX
UNITS
V
DAC Output Span
External Reference
Internal Reference
V
V
OUT
REF
0 to 2.5
PSR
Power Supply Rejection
V
CC
= 3V 10% or 5V 10%
–80
dB
I
SC
Short Circuit Output Current (Note 6)
V
FS
= V = 5.5V
CC
l
l
Sinking
Zero Scale; V
shorted to V
27
–28
48
–48
mA
mA
OUT
CC
Sourcing
Full Scale; V
shorted to GND
OUT
l
DAC I
DAC Output Current in High Impedance LO Options Only
Mode
0.01
0.5
µA
SD
Power Supply
l
V
Positive Supply Voltage
Supply Current (Note 7)
For Specified Performance
2.7
5.5
V
CC
l
l
l
l
I
CC
V
CC
V
CC
V
CC
V
CC
= 3V, V = 2.5V, External Reference
0.3
0.4
0.3
0.4
0.5
0.6
0.5
0.6
mA
mA
mA
mA
REF
= 3V, Internal Reference
= 5V V = 2.5V, External Reference
REF
= 5V, Internal Reference
l
I
SD
Supply Current in Power-Down Mode
(Note 7)
V
CC
= 5V
0.5
2
µA
Reference Input
Input Voltage Range
l
l
1
V
V
kΩ
pF
CC
Resistance
120
160
12
200
Capacitance
l
l
I
Reference Current, Power Down Mode
DAC Powered Down
0.005
5
µA
REF
Reference Output
Output Voltage
1.24
1.25
10
1.26
V
ppm/°C
kΩ
Reference Temperature Coefficient
Output Impedance
0.5
10
Capacitive Load Driving
Short Circuit Current
µF
V
CC
= 5.5V, REF Shorted to GND
2.5
mA
2633fb
4
LTC2633
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)
SYMꢀOL PARAMETER
Digital I/O
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Low Level Input Voltage
(SDA and SCL)
(Note 14)
(Note 11)
–0.5
0.3V
V
V
IL
CC
V
High Level Input Voltage
(SDA and SCL)
0.7V
CC
IH
l
l
l
V
V
Low Level Input Voltage on CA0
High Level Input Voltage on CA0
Resistance from CA0
See Test Circuit 1
See Test Circuit 1
See Test Circuit 2
0.15V
V
V
IL(CA0)
IH(CA0)
CC
0.85V
CC
R
R
R
10
10
kΩ
INH
INL
INF
OL
to V to Set CA0 = V
CC
CC
l
l
Resistance from CA0
to GND to Set CA0 = GND
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
kΩ
Resistance from CA0 to V or GND to
2
0
MΩ
CC
Set CA0 = Float
l
l
V
Low Level Output Voltage
Output Fall Time
0.4
V
t
t
I
V = V
B
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 12)
l
Pulse Width of Spikes Suppressed by
Input Filter
0
50
ns
SP
IN
l
l
l
l
Input Leakage
0.1V ≤ V ≤ 0.9V
1
8
µA
pF
pF
pF
CC
IN
CC
C
C
C
I/O Pin Capacitance
(Note 8)
IN
Capacitive Load for Each Bus Line
400
10
B
External Capacitive Load on Address Pin
CA0
CA0
AC Performance
t
s
Settling Time
V
= 3V (Note 9)
CC
0.39% ( 1LSB at 8 Bits)
0.098% ( 1LSB at 10 Bits)
0.024% ( 1LSB at 12 Bits)
3.4
4.0
4.5
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
1.0
500
2.8
V/µs
pF
At Mid-Scale Transition
nV•s
nV•s
kHz
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Output Voltage Noise Density
1 DAC Held at FS, 1 DAC Switch 0-FS
External Reference
5.2
320
e
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
180
160
200
180
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
n
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference
30
35
680
730
µV
µV
µV
µV
P-P
P-P
P-P
P-P
C
= 0.1µF
REF
2633fb
5
LTC2633
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13)
LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)
SYMꢀOL PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
0.6
HD(STA)
LOW
1.3
µs
0.6
µs
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
0.6
µs
0
0.9
µs
Data Set-Up Time
100
ns
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
(Note 12)
(Note 12)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
B
B
ns
f
µs
SU(STO)
BUF
Bus Free Time Between a Stop and Start
Condition
1.3
µs
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)
LTC2633-8
LTC2633-10
LTC2633-12
LTC2633A-12
SYMꢀOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
LSB
Monotonicity
V
V
= 5V, Internal Ref. (Note 4)
= 5V, Internal Ref. (Note 4)
CC
DNL
Differential
Nonlinearity
0.5
0.5
1
1
1
CC
l
l
l
INL
Integral Nonlinearity
Zero Scale Error
Offset Error
V
CC
V
CC
V
CC
V
CC
= 5V, Internal Ref. (Note 4)
= 5V, Internal Ref., Code = 0
= 5V, Internal Ref. (Note 5)
= 5V, Internal Ref.
0.05 0.5
0.2
0.5
0.5
10
1
5
1
0.5
0.5
10
2.5
5
0.5
0.5
0.5
10
LSB
mV
ZSE
0.5
0.5
10
5
5
V
OS
5
5
5
5
mV
V
OSTC
V
Temperature
OS
µV/°C
Coefficient
l
GE
GE
Gain Error
V
= 5V, Internal Ref.
0.2
0.8
0.2 0.8
0.2 0.8
0.2 0.8
%FSR
CC
Gain Temperature
Coefficient
V
= 5V, Internal Ref. (Note 10)
C-Grade
H-Grade
TC
CC
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
l
l
Load Regulation
V
= 5V 10%, Internal Ref.
0.006 0.01
0.022 0.04
0.09 0.16
0.09 0.16 LSB/mA
CC
CC
Mid-Scale, –10mA ≤ I
≤ 10mA
OUT
R
OUT
DC Output
Impedance
V
= 5V 10%, Internal Ref.
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
Mid-Scale, –10mA ≤ I
≤ 10mA
OUT
2633fb
6
LTC2633
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)
SYMꢀOL PARAMETER
CONDITIONS
MIN
TYP
0 to V
MAX
UNITS
V
DAC Output Span
External Reference
Internal Reference
V
V
OUT
REF
0 to 4.096
PSR
Power Supply Rejection
V
= 5V 10%
–80
dB
CC
FS
I
SC
Short Circuit Output Current (Note 6)
V
= V = 5.5V
CC
l
l
Sinking
Sourcing
Zero Scale; V
shorted to V
27
–28
48
–48
mA
mA
OUT
CC
Full Scale; V
shorted to GND
OUT
Power Supply
l
V
Positive Supply Voltage
Supply Current (Note 7)
For Specified Performance
4.5
5.5
V
CC
l
l
I
CC
V
CC
V
CC
= 5V, V =4.096V, External Reference
0.4
0.5
0.6
0.7
mA
mA
REF
= 5V, Internal Reference
l
I
SD
Supply Current in Power-Down Mode
(Note 7)
V
CC
= 5V
0.5
2
µA
Reference Input
Input Voltage Range
l
l
1
V
V
kΩ
pF
CC
Resistance
120
160
12
200
Capacitance
l
l
I
Reference Current, Power Down Mode
DAC Powered Down
0.005
5
µA
REF
Reference Output
Output Voltage
2.032
2.048
10
2.064
V
ppm/°C
kΩ
Reference Temperature Coefficient
Output Impedance
0.5
10
Capacitive Load Driving
Short Circuit Current
µF
V
CC
= 5.5V, REF Shorted to GND
4
mA
Digital I/O
l
l
V
Low Level Input Voltage
(SDA and SCL)
(Note 14)
(Note 11)
–0.5
0.7V
0.3V
V
V
IL
CC
V
IH
High Level Input Voltage
(SDA and SCL)
CC
l
l
l
V
V
Low Level Input Voltage on CA0
High Level Input Voltage on CA0
Resistance from CA0
See Test Circuit 1
See Test Circuit 1
See Test Circuit 2
0.15V
V
V
IL(CA0)
CC
0.85V
IH(CA0)
CC
R
R
R
10
10
kΩ
INH
INL
INF
OL
to V to Set CA0 = V
CC
CC
l
l
Resistance from CA0
to GND to Set CA0 = GND
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
kΩ
Resistance from CA0 to V or GND to
2
0
MΩ
CC
Set CA0 = Float
l
l
V
Low Level Output Voltage
Output Fall Time
0.4
V
t
t
I
V = V
B
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 12)
l
l
Pulse Width of Spikes Suppressed by
Input Filter
0
50
1
ns
SP
IN
Input Leakage
0.1V ≤ V ≤ 0.9V
CC
µA
CC
IN
2633fb
7
LTC2633
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)
SYMꢀOL PARAMETER
CONDITIONS
MIN
TYP
MAX
8
UNITS
pF
l
l
l
C
C
C
I/O Pin Capacitance
(Note 8)
IN
Capacitive Load for Each Bus Line
400
10
pF
B
External Capacitive Load on Address Pin
CA0
pF
CA0
AC Performance
t
s
Settling Time
V
= 5V (Note 9)
CC
0.39% ( 1LSB at 8 Bits)
0.098% ( 1LSB at 10 Bits)
0.024% ( 1LSB at 12 Bits)
3.7
4.0
4.7
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
1.0
500
3.0
V/µs
pF
At Mid-Scale Transition
nV•s
nV•s
kHz
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Output Voltage Noise Density
1 DAC Held at FS, 1 DAC Switch 0-FS
External Reference
6.7
320
e
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
180
160
250
230
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
n
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference
30
40
680
750
µV
µV
µV
µV
P-P
P-P
P-P
P-P
C
= 0.1µF
REF
2633fb
8
LTC2633
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13)
LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)
SYMꢀOL PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
0.6
HD(STA)
LOW
1.3
µs
0.6
µs
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
0.6
µs
0
0.9
µs
Data Set-Up Time
100
ns
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
(Note 12)
(Note 12)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
B
B
ns
f
µs
SU(STO)
BUF
Bus Free Time Between a Stop and Start
Condition
1.3
µs
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7. Digital inputs at 0V or V
.
CC
Note 2. All voltages are with respect to GND
Note 8. Guaranteed by design and not production tested.
Note 3. High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
Note 9. Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 4. Linearity and monotonicity are defined from code k to code
L
Note 10. Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
N
N
2 –1, where N is the resolution and k is given by k = 0.016 • (2 / V ),
L
L
FS
rounded to the nearest whole code. For V = 2.5V and N = 12, k = 26 and
FS
L
Note 11. Maximum V = V
+ 0.5V
CC(MAX)
IH
linearity is defined from code 26 to code 4,095. For V = 4.096V and
FS
Note 12. C = capacitance of one bus line in pF
B
N = 12, k = 16 and linearity is defined from code 16 to code 4,095.
L
Note 13. All values refer to V = V
and V = V
levels.
IH
IH(MIN)
IL
IL(MAX)
Note 5. Inferred from measurement at code 16 (LTC2633-12), code 4
(LTC2633-10) or code 1 (LTC2633-8), and at full scale.
Note 6. This IC includes current limiting that is intended to protect the
Note 14. Minimum V exceeds the absolute maximum rating. This
IL
condition won’t damage the IC, but could degrade performance.
device during momentary overload conditions. Junction temperature can
2633fb
9
LTC2633
typical perFormance characteristics
TA = 25°C unless otherwise noted.
LTC2633-L12 (Internal Reference, VFS = 2.5V)
INL vs Temperature
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
0.5
1.0
0.5
V
= 3V
V
= 3V
V
= 3V
CC
CC
CC
0.5
0
INL (POS)
0
0
–0.5
INL (NEG)
–0.5
–1.0
–0.5
–1.0
–1.0
–50 –25
0
25 50 75 100 125 150
0
1024
2048
3072
4095
0
1024
2048
3072
4095
TEMPERATURE (°C)
CODE
CODE
2633 G03
2633 G01
2633 G02
Reference Output Voltage vs
Temperature
DNL vs Temperature
1.0
1.260
1.255
1.250
1.245
1.240
V
= 3V
V
= 3V
CC
CC
0.5
0
DNL (POS)
DNL (NEG)
–0.5
–1.0
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
2633 G04
2633 G05
Settling to 1LSꢀ Rising
Settling to 1LSꢀ Falling
9TH CLOCK OF
3RD DATA BYTE
3/4 SCALE TO 1/4 SCALE STEP
V
= 3V, V = 2.5V
CC
FS
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
SCL
5V/DIV
V
OUT
1LSB/DIV
3.6µs
4.5µs
V
9TH CLOCK OF
3RD DATA BYTE
OUT
1/4 SCALE TO 3/4 SCALE STEP
SCL
5V/DIV
1LSB/DIV
V
= 3V, V = 2.5V
CC
FS
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
2µs/DIV
2633 G06
2633 G07
2633fb
10
LTC2633
typical perFormance characteristics
TA = 25°C unless otherwise noted.
LTC2633-H12 (Internal Reference, VFS = 4.096V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.5
1.0
0.5
1.0
0.5
V
= 5V
V
= 5V
V
= 5V
CC
CC
CC
INL (POS)
INL (NEG)
0
0
0
–0.5
–1.0
–0.5
–1.0
–0.5
–1.0
0
1024
2048
3072
4095
0
1024
2048
3072
4095
–50 –25
0
25 50 75 100 125 150
CODE
CODE
TEMPERATURE (°C)
2633 G08
2633 G09
2633 G10
Reference Output Voltage vs
Temperature
DNL vs Temperature
1.0
2.068
2.058
2.048
2.038
2.028
V
= 5V
V
= 5V
CC
CC
0.5
0
DNL (POS)
DNL (NEG)
–0.5
–1.0
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
2633 G11
2633 G12
Settling to 1LSꢀ Rising
Settling to 1LSꢀ Falling
3/4 SCALE TO 1/4 SCALE
STEP
9TH CLOCK OF
3RD DATA BYTE
SCL
5V/DIV
V
= 5V, V = 4.095V
CC
FS
RL = 2k, CL = 100pF
V
OUT
AVERAGE OF 256 EVENTS
1LSB/DIV
4.7µs
3.8µs
9TH CLOCK OF
3RD DATA BYTE
V
SCL
5V/DIV
OUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
V
= 5V, V = 4.095V
CC
FS
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
2µs/DIV
2633 G13
2633 G14
2633fb
11
LTC2633
typical perFormance characteristics
TA = 25°C unless otherwise noted.
Differential Nonlinearity (DNL)
LTC2633-10
Integral Nonlinearity (INL)
1.0
0.5
1.0
0.5
V
CC
V
FS
= 3V
= 2.5V
V
CC
V
FS
= 3V
= 2.5V
INTERNAL REF
INTERNAL REF
0
0
–0.5
–1.0
–0.5
–1.0
0
256
512
768
1023
0
256
512
768
1023
CODE
CODE
2633 G15
2633 G16
LTC2633-8
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
0.50
0.25
0
0.50
0.25
0
V
CC
V
FS
= 3V
= 2.5V
V
CC
V
FS
= 3V
= 2.5V
INTERNAL REF
INTERNAL REF
–0.25
–0.50
–0.25
–0.50
0
64
128
192
255
0
64
128
192
255
CODE
CODE
2633 G18
2633 G17
LTC2633
Load Regulation
Current Limiting
Offset Error vs Temperature
10
8
3
2
0.20
0.15
0.10
0.05
0
V
CC
V
CC
V
CC
= 5V (LTC2633-H)
= 5V (LTC2633-L)
= 3V (LTC2633-L)
V
CC
V
CC
V
CC
= 5V (LTC2633-H)
= 5V (LTC2633-L)
= 3V (LTC2633-L)
6
4
1
2
0
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
–1
–2
–3
INTERNAL REFERENCE
CODE = MID-SCALE
INTERNAL REFERENCE
CODE = MID-SCALE
–30
–20
–10
0
10
20
30
–50 –25
0
25 50 75 100 125 150
–30
–20
–10
0
10
20
30
I
(mA)
TEMPERATURE (°C)
OUT
I
(mA)
2633 G19
OUT
2633 G21
2633 G20
2633fb
12
LTC2633
typical perFormance characteristics
TA = 25°C unless otherwise noted.
LTC2633
Large-Signal Response
Mid-Scale-Glitch Impulse
Power-On Reset Glitch
LTC2633-L
9TH CLOCK OF
3RD DATA BYTE
SCL
5V/DIV
LTC2633-H12, V = 5V
CC
3nV•s TYPICAL
V
CC
2V/DIV
V
OUT
0.5V/DIV
V
OUT
ZERO-SCALE
V
OUT
2mV/DIV
10mV/DIV
LTC2633-L12, V = 3V
CC
2.8nV•s TYPICAL
V
= V = 5V
CC
FS
1/4 SCALE to 3/4 SCALE
2633 G24
2µs/DIV
2µs/DIV
200µs/DIV
2633 G22
2633 G23
Headroom at Rails vs Output
Current
Exiting Power-Down to Mid-Scale
Power-On Reset to Mid-Scale
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
9TH CLOCK OF
3RD DATA BYTE
V
CC
2V/DIV
SCL
5V/DIV
LTC2633-H
3V (LTC2633-L) SOURCING
DAC B IN
POWER-DOWN
MODE
V
OUTA
0.5V/DIV
LTC2633-L
5V SINKING
V
OUT
0.5V/DIV
LTC2633-H
V
= 5V
CC
3V (LTC2633-L) SINKING
INTERNAL REF.
200µs/DIV
5µs/DIV
0
1
2
3
4
I
5
6
7
8
9
10
2633 G27
(mA)
2633 G26
OUT
2633 G25
Exiting Power-Down for Hi-Z
Option
Supply Current vs Logic Voltage
1.2
1.0
0.8
0.6
0.4
0.2
SWEEP SDA, SCL
BETWEEN
9TH CLOCK OF
3RD DATA BYTE
ON AND V
CC
SCL
V
= 5V
CC
5V/DIV
LTC2633-LO, V = 3V
CC
DAC OUTPUT SET
TO MID-SCALE
DAC OUTPUT DRIVEN
BY 1V SOURCE
THROUGH 15k
RESISTOR
V
OUT
500mV/DIV
V
= 3V
HIGH-IMPEDANCE
(POWER-DOWN) MODE
CC
(LTC2633-L)
0
1
2
3
4
5
5µs/DIV
LOGIC VOLTAGE (V)
2633 G28
2633 G29
2633fb
13
LTC2633
typical perFormance characteristics
LTC2633
TA = 25°C unless otherwise noted.
Multiplying ꢀandwidth
Noise Voltage vs Frequency
Gain Error vs Reference Input
500
400
300
200
100
0
2
0
0.8
0.6
V
= 5V
V
= 5.5V
CC
CC
CODE = MID-SCALE
GAIN ERROR OF 2 CHANNELS
INTERNAL REFERENCE
–2
0.4
–4
0.2
–6
LTC2633-H
LTC2633-L
0
–8
–10
–12
–14
–16
–18
–0.2
–0.4
–0.6
–0.8
V
V
V
= 5V
REF(DC)
REF(AC)
CC
= 2V
= 0.2V
P-P
CODE = FULL-SCALE
100
1k
10k
100k
1M
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1k
10k
100k
1M
FREQUENCY (Hz)
REFERENCE VOLTAGE (V)
FREQUENCY (Hz)
2633 G32
2633 G33
2633 G31
0.1Hz to 10Hz Voltage Noise
Gain Error vs Temperature
DAC to DAC Crosstalk (Dynamic)
1.0
0.5
V
= 5V, V = 2.5V
FS
CC
9TH CLOCK OF
3RD DATA BYTE
CODE = MID-SCALE
SCL
5V/DIV
INTERNAL REFERENCE
1 DAC
SWITCH 0-FS
2V/DIV
10µV/DIV
0
LTC2633-H12, V = 5V
CC
6.7nV•s TYP
V
OUT
–0.5
2mV/DIV
–1.0
2632 G34
2µs/DIV
–50 –25
0
25 50 75 100 125 150
1s/DIV
TEMPERATURE (°C)
2633 G35
2633 G36
pin Functions
SCL (Pin 1): Serial Clock Input Pin. Data is shifted into the
(0.1µF is recommended) and must be buffered when
driving external DC load current.
SDApinattherisingedgesoftheclock.Thishighimpedance
pin requires a pull-up resistor or current source to V .
CC
GND (Pin 4): Ground.
CA0 (Pin 2): Chip Address Bit 0. Tie this pin to V , GND
CC
V
, V
(Pins 5,6): DAC Analog Voltage Output.
OUTA OUTꢀ
2
or leave it floating to select an I C slave address for the
V
(Pin 7): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V
part (see Table 1).
CC
CC
(LTC2633-L) or 4.5V ≤ V ≤ 5.5V (LTC2633-H). Bypass
CC
REF (Pin 3): Reference Voltage Input or Output. When
external reference mode is selected, REF is an input (1V ≤
to GND with a 0.1µF capacitor.
SDA (Pin 8): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open drain
N-channeloutputduringacknowledgement. SDArequires
V
≤ V ) where the voltage supplied sets the full-scale
REF
CC
DAC output voltage. When internal reference is selected,
the 10ppm/°C 1.25V (LTC2633-L) or 2.048V (LTC2633-H)
internal reference (half full-scale) is available at the pin.
This output may be bypassed to GND with up to 10µF
a pull-up resistor or current source to V .
CC
2633fb
14
LTC2633
Block Diagram
REF
INTERNAL
REFERENCE
SWITCH
GND
V
REF
V
V
CC
V
OUTA
OUTB
DAC A
DAC B
CONTROL
DECODE LOGIC
POWER-ON
RESET
SCL
SDA
2
I C
CA0
2
ADDRESS
DECODE
I C INTERFACE
2633 BD
test circuit Test circuits for I2C digital I/O (see Electrical Characteristics)
Test Circuit 1
Test Circuit 2
V
DD
100Ω
CA0
R
/R
R
INH INL/ INF
V
/V
IH(CA0) IL(CA0)
CA0
2633 TC01
2633 TC02
GND
timing Diagram
SDA
t
f
t
BUF
t
r
t
t
t
LOW
SU(DAT)
HD(STA)
t
f
t
r
t
SP
SCL
t
HD(STA)
t
t
t
t
HD(DAT)
HIGH
SU(STA)
S
SU(STO)
P
S
S
2633 F01
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V LEVELS
IL(MAX)
Figure 1. I2C Timing
SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
1ST DATA BYTE
ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK
2ND DATA BYTE
3RD DATA BYTE
START
SDA
SCL
W
ACK
9
X
5
X
6
X
7
X
8
ACK
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
1
2
3
4
2633 F02
Figure 2. Typical LTC2633 Write Transaction
2633fb
15
LTC2633
operation
The LTC2633 is a family of dual voltage output DACs in an
8-lead TSOT package. Each DAC can operate rail-to-rail
using an external reference, or with its full-scale voltage
set by an integrated reference. Eighteen combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero-
scale, mid-scale in internal reference mode, or mid-scale
inexternalreferencemode), DACpower-downoutputload
(high impedance or 200kΩ), and full-scale voltage (2.5V
or 4.096V) are available. The LTC2633 is controlled using
Power Supply Sequencing
The voltage at REF (Pin 3) must be kept within the range
–0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-
REF
CC
ings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at V is in transition.
CC
Transfer Function
2
The digital-to-analog transfer function is:
a 2-wire I C interface.
k
Power-On Reset
VOUT(IDEAL)
=
VREF
2N
TheLTC2633-HZ/LTC2633-LZcleartheoutputtozero-scale
when power is first applied, making system initialization
consistent and repeatable.
where k is the decimal equivalent of the binary DAC input
code,Nistheresolution,andV iseither2.5V(LTC2633-LI/
REF
Forsomeapplications,downstreamcircuitsareactivedur-
ingDACpower-up,andmaybesensitivetononzerooutputs
from the DAC during this time. The LTC2633 contains
circuitry to reduce the power-on glitch: the analog output
typically rises less than 10mV above zero scale during
power-on.Ingeneral,theglitchamplitudedecreasesasthe
power supply ramp time is increased. See power-on reset
glitch in the Typical Performance Characteristics section.
LTC2633-LX/LTC2633-LO/LTC2633-LZ) or 4.096V
(LTC2633-HI/LTC2633-HZ) when in internal reference
mode, and the voltage at REF when in external reference
mode.
2
I C Serial Interface
The LTC2633 communicates with a host using the stan-
2
dard 2-wire I C interface. The Timing Diagram (Figures
1 and 2) show the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply
The LTC2633-HI/LTC2633-LI/LTC2633-LX provide an
alternative reset, setting the output to mid-scale when
power is first applied. The LTC2633-LI/ and LTC2633-HI
power up in internal reference mode, with the output set
to a mid-scale voltage of 1.25V and 2.048V respectively.
TheLTC2633-LXpower-upinexternalreferencemode,with
the output set to mid-scale of the external reference. The
LTC2633-LO powers up in internal reference mode with
all the DAC channels placed in the high impedance state
(powered down). Input and DAC registers are set to the
mid-scalecode, andonlytheinternalreferenceispowered
up, causing supply current to be typically 180µA upon
power up. Default reference mode selection is described
in the Reference Modes section.
2
and can be obtained from the I C specifications. For an
2
I C bus operating in the fast mode, an active pull-up will
be necessary if the bus capacitance is greater than 200pF.
The LTC2633 is a receive-only (slave) device. The master
can write to the LTC2633. The LTC2633 will not acknowl-
edge (NAK) a read request from the master.
2633fb
16
LTC2633
operation
START (S) and STOP (P) Conditions
In addition to the address selected by the address pin,
the part also responds to a global address. This address
allows a common write to all LTC2633 parts to be ac-
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
2
complished using one 3-byte write transaction on the I C
bus. The global address, listed at the end of Tables 1, is a
7-bit hardwired address not selectable by CA0. If another
address is required, please consult the factory.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
The maximum capacitive load allowed on the address pin
(CA0) is 10pF, as these pins are driven during address
detection to determine if they are floating.
2
another I C device.
Write Word Protocol
Acknowledge
The master initiates communication with the LTC2633
with a START condition and a 7-bit slave address followed
by the write bit (W) = 0. The LTC2633 acknowledges by
pulling the SDA pin low at the 9th clock if the 7-bit slave
address matches the address of the part (set by CA0) or
the global address. The master then transmits three bytes
of data. The LTC2633 acknowledges each byte of data
by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2633 executes the command specified in
the 24-bit input word.
The acknowledge (ACK) signal is used for handshaking
betweenthemasterandtheslave.AnACKgeneratedbythe
slave lets the master know that the latest byte of informa-
tion was properly received. The ACK related clock pulse is
generated by the master. The master releases the SDA line
(HIGH)duringtheACKclockpulse.Theslave-receivermust
pull down the SDA bus line during the ACK clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse. The LTC2633 responds to a write by a
master in this manner but does not acknowledge a read
operation; in that case, SDA is retained HIGH during the
period of the ACK clock pulse.
If more than three data bytes are transmitted after a valid
7-bitslaveaddress,theLTC2633doesnotacknowledgethe
extra bytes of data (SDA is high during the 9th clock).
Chip Address
The state of pin CA0 determines the slave address of the
part.Thispincanbesettoanyoneofthreestates:V ,GND
CC
or float. This results in 3 selectable addresses for the part.
The slave address assignments is shown in Table 1.
Table 1. Slave Address Map
CA0
A6
0
A5
0
A4
1
A3
0
A2
0
A1
0
A0
0
GND
FLOAT
0
0
1
0
0
0
1
V
0
0
1
0
0
1
0
CC
GLOBAL ADDR
1
1
1
0
0
1
1
2633fb
17
LTC2633
operation
Table 3. Command Codes
COMMAND*
The format of the three data bytes is shown in Figure
3. The first byte of the input word consists of the 4-bit
command, followed by the 4-bit DAC address. The next
two bytes contain the 16-bit data word, which consists
of the 12-, 10- or 8-bit input code, MSB to LSB, followed
by 4, 6 or 8 don’t-care bits (LTC2633-12, LTC2633-10
and LTC2633-8 respectively). A typical LTC2633 write
transaction is shown in Figure 4.
C3 C2 C1 C0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power-Up) DAC Register n
Write to Input Register n, Update (Power-Up) All
Write to and Update (Power-Up) DAC Register n
Power-Down n
Power-Down Chip (All DAC’s and Reference)
Select Internal Reference (Power-Up Reference)
The command bit assignments (C3-C0) and address (A3-
A0) assignments are shown in Tables 3 and 4. The first
four commands in the table consist of write and update
operations. A write operation loads a 16-bit data word
from the 32-bit shift register into the input register. In an
update operation, the data word is copied from the input
register to the DAC register. Once copied into the DAC
register, the data word becomes the active 12-, 10-, or
8-bit input code, and is converted to an analog voltage at
the DAC output. Write to and update combines the first
two commands. The update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
Select External Reference (Power-Down Internal
Reference)
1
1
1
1
No Operation
*Command codes not shown are reserved and should not be used.
Table 4. Address Codes
ADDRESS (n)*
A3 A2 A1 A0
0
0
1
0
0
1
0
0
1
0
1
1
DAC A
DAC B
All DACs
* Address codes not shown are reserved and should not be used.
WRITE WORD PROTOCOL LTC2633
S
W
A2
A2
A2
A
A
A
A
D1
X
P
SLAVE ADDRESS
1ST DATA BYTE
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
INPUT WORD (LTC2633-12)
C3 C2 C1 C0
A3
A1
A1
A1
A0
D11 D10
D9
D7
D5
D8
D7
D6
D4
D2
D5
D3
D1
D4
D2
D0
D3
D1
X
D2
D0
X
D0
X
X
X
X
X
X
X
X
X
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
INPUT WORD (LTC2633-10)
C3 C2 C1 C0
A3
A0
A0
D9
D7
D8
D6
D6
D5
X
X
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
INPUT WORD (LTC2633-8)
C3
C2
C1
C0
A3
D4
D3
X
X
X
X
2633 F03
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
Figure 3. Command and Data Input Format
2633fb
18
LTC2633
operation
2633fb
19
LTC2633
operation
Reference Modes
the output pins are passively pulled to ground through
individual 200kΩ resistors (LTC2633-LI/LTC2633-LX/
LTC2633-LO/LTC2633-LZ/LTC2633-HI/LTC2633-HZ). For
the LTC2633-LO options, the output pins are not passively
pulled to ground, but are also placed in a high impedance
state (open-circuited state) during power-down, typically
drawing less than 0.1µA. The LTC2633-LO options power-
up with all DAC outputs in this high impedance state. They
remain that way until given a software update command.
ForallLTC2633options, Input-andDAC-registercontents
are not disturbed during power-down.
For applications where an accurate external reference is
either not available, or not desirable due to limited space,
the LTC2633 has a user-selectable, integrated reference.
The integrated reference voltage is internally amplified
by 2x to provide the full-scale DAC output voltage range.
The LTC2633-LI/LTC2633-LX/LTC2633-LO/LTC2633-LZ
provides a full-scale output of 2.5V. The LTC2633-HI/
LTC2633-HZ provides a full-scale output of 4.096V. The
internal reference can be useful in applications where
the supply voltage is poorly regulated. Internal reference
mode can be selected by using command 0110b, and is
thepower-ondefaultforLTC2633-HZ/LTC2633-LZ,aswell
as for LTC2633-HI/LTC2633-LI/LTC2633-LO.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combi-
nation with the appropriate DAC address, (n). The supply
current is reduced approximately 30% for each DAC
powered down. The integrated reference is automatically
powered down when external reference is selected using
command0111b.Inaddition,alltheDACchannelsandthe
integrated reference together can be put into power-down
mode using Power Down Chip command 0101b. When
the integrated reference is in power-down mode, the REF
pin becomes high impedance (typically > 1GΩ). For all
power-down commands the 16-bit data word is ignored.
The10ppm/°C,1.25V(LTC2633-LI/LTC2633-LX/LTC2633-
LO/LTC2633-LZ) or 2.048V (LTC2633-HI/LTC2633-HZ)
internal reference is available at the REF pin. Adding
bypass capacitance to the REF pin will improve noise
performance; 0.1µF is recommended and up to 10µF can
bedrivenwithoutoscillation.Thisoutputmustbebuffered
when driving an external DC load current.
Alternatively, the DAC can operate in external reference
modeusingcommand0111b.Inthismode,aninputvoltage
supplied externally to the REF pin provides the reference
Normal operation resumes after executing any command
that includes a DAC update, (as shown in Table 1). The
selected DAC is powered up as its voltage output is up-
dated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If
less than two DACs are in a powered-down state prior to
the update command, the power-up delay time is 10µs.
However, if both DACs and the integrated reference are
powereddown, thenthemainbiasgenerationcircuitblock
has been automatically shut down in addition to the DAC
amplifiersandreferencebuffers.Inthiscase,thepowerup
delay time is 12µs. The power-up of the integrated refer-
ence depends on the command that powered it down. If
the reference is powered down using the select external
reference command (0111b), then it can only be powered
backupusingselectinternalreferencecommand(0110b).
However, if the reference was powered down using power
down chip command (0101b), then in addition to select
(1V ≤ V ≤ V ) and the supply current is reduced. The
REF
CC
external reference voltage supplied sets the full-scale DAC
output voltage. External reference mode is the power-on
default for LTC2633-LX.
The reference mode of LTC2633-HZ/LTC2633-LZ/
LTC2633-HI/LTC2633-LI/LTC2633-LO (internal reference
power-on default), can be changed by software command
after power up. The same is true for LTC2633-LX (external
reference power-on default).
Power-Down Mode
Forpower-constrainedapplications,power-downmodecan
be used to reduce the supply current whenever less than
two DAC outputs are needed. When in power-down, the
buffer amplifiers, bias circuits, and integrated reference
circuits are disabled, and draw essentially zero current.
The DAC outputs are put into a high impedance state, and
2633fb
20
LTC2633
operation
internal reference command (0110b), any command in
software that powers up the DACs will also power up the
integrated reference.
50Ω • 1mA, or 50mV). See the graph Headroom at Rails
vs Output Current in the Typical Performance Character-
istics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Voltage Output
The LTC2633’s integrated rail-to-rail amplifier has guaran-
teed load regulation when sourcing or sinking up to 10mA
at 5V, and 5mA at 3V.
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
SincetheanalogoutputoftheDACcannotgobelowground,
it may limit for the lowest codes as shown in Figure 5b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V . If V = V and the DAC full-scale error
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change
in units from LSB/mA to Ω. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
CC
REF
CC
(FSE) is positive, the output for the highest codes limits
at V , as shown in Figure 5c. No full-scale limiting can
CC
occur if V is less than V –FSE.
REF
CC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
POSITIVE
FSE
V
= V
CC
REF
V
REF
= V
CC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
2633 F05
(c)
OUTPUT
VOLTAGE
0V
0
2,048
4,095
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 ꢀits).
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2633fb
21
LTC2633
operation
ꢀoard Layout
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2633 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2633 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2633 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
package Description
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
2.90 BSC
(NOTE 4)
0.40
MAX
0.65
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
TS8 TSOT-23 0710 REV A
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2633fb
22
LTC2633
revision history
REV
DATE
DESCRIPTION
PAGE NUMꢀER
A
3/11
Revised part numbering.
2 to 9, 13, 16,
20, 26
B
3/11
Revised title of Typical Application.
24
2633fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2633
typical application
Voltage Margining Application with LTC3850 (1.2V 5ꢁ) LTC2633-LO Option Only
V
IN
6.5V
TO 14V
0.1µF
4.7µF
5V
CMDSH-3
2.2k
100k
3
7
6
REF
V
CC
0.1µF
V
PGOOD INTV
LTC3850EUF
0.1µF
IN
CC
LTC2633CTS8-L012
RJK0305DPB
10k
15k
I
TG1
LM
5
DAC A
DAC B
10k
BOOST1
SW1
0.1µF
2.2µH
0.008k
0.22µF
2
1
8
V
OUT
1.2V 5ꢀ
FREQ
CA0
SCL
SDA
4
RJK0301DPB
BG1
GND
2
TO I C
1nF
3.32k
BUS
PGND
10k
10k
+
I
SENSE1
TH1
1nF
500kHz
100pF
MODE/PLLIN
TKSS1
RUN1
–
1nF
10k
SENSE1
10nF
V
FB1
SGND
63.4k
15pF
2633 TA02
20k
relateD parts
PART NUMꢀER
DESCRIPTION
COMMENTS
LTC2632
Dual 12-/10-/8-Bit, SPI V
Internal Reference
DACs with
2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail
Output, 8-Pin ThinSOT™ Package
OUT
2
LTC2607/LTC2617/ Dual 16-/14-/12-Bit, I C V
DACs with
DACs with
260μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead SSOP Package
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package
1.5μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package
OUT
OUT
LTC2627
External Reference
LTC2602/LTC2612/ Dual 16-/14-/12-Bit SPI V
LTC2622
LTC1662
External Reference
Dual 10-Bit, SPI V
Reference
DAC with External
OUT
2
LTC2630/LTC2631 Single 12-/10-/8-Bit, SPI/ I C V
with 10ppm/°C Reference
DACs
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output,
in SC70 (LTC2630)/ ThinSOT (LTC2631)
OUT
LTC2640
Single 12-/10-/8-Bit, SPI V
10ppm/°C Reference
DACs with
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, in ThinSOT
OUT
2
LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I C V
10ppm/°C Reference
DACs with 2.5LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages
OUT
2
LTC2636/LTC2637 Octal 12-/10-/8-Bit, SPI/I C V
DACs with 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages
OUT
10ppm/°C Reference
2
LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I C V
10ppm/°C Max Reference
DACs with
4LSB INL Max at 16-Bits and 2mV Offset Error, Rail-to-Rail Output,
20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages
OUT
2
LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I C V
DACs with
4LSB INL Max at 16-Bits and 2mV Offset Error, Rail-to-Rail Output,
20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages
OUT
10ppm/°C Max Reference
2633fb
LT 0311 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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