LTC2619CGN-1_技术文档

LTC2609/LTC2619/LTC2629

Quad 16-/14-/12-Bit

Rail-to-Rail DACs with

I²C Interface

U

DESCRIPTIO

FEATURES

The LTC^®2609/LTC2619/LTC2629 are quad 16-, 14- and

12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a

16-lead SSOP package. They have built-in high perfor-

mance output buffers and are guaranteed monotonic.

■

Smallest Pin-Compatible Quad DACs:

LTC2609: 16 Bits

LTC2619: 14 Bits

LTC2629: 12 Bits

■

Guaranteed Monotonic Over Temperature

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply,

voltage-output DACs.

Thepartsusea2-wire, I²Ccompatibleserialinterface. The

LTC2609/LTC2619/LTC2629 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz).

■

Separate Reference Inputs

■

27 Selectable Addresses

400kHz I²C^™Interface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 250µA per DAC at 3V

■

Individual Channel Power Down to 1µA (Max)

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Ultralow Crosstalk Between DACs (5µV)

■

LTC2609/LTC2619/LTC2629: Power-On Reset to

The LTC2609/LTC2619/LTC2629 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise

lessthan10mVabovezeroscale;afterpower-up,theystay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2609-1/LTC2619-1/

LTC2629-1 to midscale. The voltage outputs stay at

midscale until a valid write and update take place.

Zero Scale

■

LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset

to Midscale

Tiny 16-Lead Narrow SSOP Package

■

U

APPLICATIO S

■

Mobile Communications

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5396245. Patent pending.

■

Process Control and Industrial Automation

■

Automatic Test Equipment and Instrumentation

W

BLOCK DIAGRA

V

REFLO

2

GND

1

CC

16

REFA

3

4

15 REFD

Differential Nonlinearity

DAC A

DAC B

DAC D

DAC C

V

OUTA

14

V

OUTD

(LTC2609)

1.0

0.8

V

= 5V

REF

CC

= 4.096V

V

OUTB

5

6

13

V

OUTC

0.6

0.4

REFB

12 REFC

0.2

CONTROL

LOGIC

0

–0.2

–0.4

–0.6

–0.8

–1.0

32-BIT SHIFT REGISTER

11 CA0

10 CA1

8

9

SCL

SDA

ADDRESS

DECODE

LOGIC

2

I C

0

16384

32768

CODE

49152

65535

INTERFACE

7

CA2

2609 G02

2609 BD

26091929f

1

LTC2609/LTC2619/LTC2629

W W W

U

(Note 1)

ABSOLUTE AXI U RATI GS

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V_CC.............................................–6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ –65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

Operating Temperature Range:

LTC2609C/LTC2619C/LTC2629C

LTC2609C-1/LTC2619C-1/LTC2629C-1 ... 0°C to 70°C

LTC2609I/LTC2619I/LTC2629I

LTC2609I-1/LTC2619I-1/LTC2629I-1.. –40°C to 85°C

W U

/O

PACKAGE RDER I FOR ATIO

GN PART MARKING

ORDER PART NUMBER

TOP VIEW

2609

LTC2609CGN

LTC2609CGN-1

LTC2609IGN

LTC2609IGN-1

LTC2619CGN

LTC2619CGN-1

LTC2619IGN

GND

REFLO

REFA

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

26091

2609I

2609I1

2619

REFD

V

OUTD

V

OUTA

OUTC

V

REFC

CA0

CA1

SDA

OUTB

26191

2619I

2619I1

2629

26291

2629I

2629I1

REFB

CA2

LTC2619IGN-1

LTC2629CGN

LTC2629CGN-1

LTC2629IGN

SCL

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 135°C, θ_JA= 150°C

LTC2629IGN-1

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. REFA = REFB = REFC = REFD = 4.096V (V_CC= 5V), REFA = REFB =

REFC = REFD = 2.048V (V_CC= 2.7V), REFLO = 0V, V_OUTunloaded, unless otherwise noted.

LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

●

12

14

16

Bits

LSB

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

±0.5

±4

±1

±4 ±16

±1

Integral Nonlinearity

Load Regulation

±1

±16 ±64

V

= V = 5V, Midscale

CC

OUT

REF

I

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

●

0.02 0.125

0.1

0.5

0.3

0.4

2

LSB/mA

V

= V = 2.7V, Midscale

OUT

REF

I

CC

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

●

0.04 0.25

0.05 0.25

0.2

1

0.7

0.8

4

LSB/mA

ZSE

Zero-Scale Error

Offset Error

Code = 0

(Note 4)

●

1.5

±1

±6

9

1.5

±1

±6

9

1.5

±1

±6

9

mV

V

OS

±9

V

OS

Temperature

µV/°C

Coefficient

GE

Gain Error

●

±0.1 ±0.7

±3

±0.1 ±0.7

±3

±0.1 ±0.7

±3

%FSR

Gain Temperature

Coefficient

ppm/°C

26091929f

2

LTC2609/LTC2619/LTC2629

The ● denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. REFA = REFB = REFC = REFD = 4.096V (V_CC= 5V), REFA = REFB =

REFC = REFD = 2.048V (V_CC= 2.7V), REFLO = 0V, V_OUTunloaded, unless otherwise noted. (Note 9)

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

±10%

–80

dB

R

DC Output Impedance

V

REF

V

REF

= V = 5V, Midscale; –15mA ≤ I ≤ 15mA

OUT

●

0.030

0.035

0.15

Ω

OUT

CC

= V = 2.7V, Midscale; –7.5mA ≤ I

≤ 7.5mA

CC

OUT

DC Crosstalk (Note 10)

Due to Full-Scale Output Change (Note 11)

Due to Load Current Change

Due to Powering Down (Per Channel)

±5

±4

µV

µV/mA

µV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

CC REF

SC

Code: Zero Scale; Forcing Output to V

●

15

36

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

CC

= 2.7V, V = 2.7V

REF

Code: Zero Scale; Forcing Output to V

●

7.5

22

30

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

●

0

V

kΩ

pF

CC

Resistance

Normal Mode

88

125

14

160

Capacitance

I

Reference Current, Power Down Mode DAC Powered Down

●

0.001

1

µA

REF

Power Supply

V

Positive Supply Voltage

Supply Current

For Specified Performance

●

2.7

5.5

V

CC

I

V

CC

V

CC

= 5V (Note 3)

= 3V (Note 3)

●

1.25

1

0.35

0.15

2

1.6

1

mA

µA

CC

DAC Powered Down (Note 3) V = 5V

CC

DAC Powered Down (Note 3) V = 3V

1

µA

Digital I/O (Note 9)

V

Low Level Input Voltage

(SDA and SCL)

●

0.3V

V

IL

CC

High Level Input Voltage

(SDA and SCL)

0.7V

CC

IH

Low Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1

See Test Circuit 2

Sink Current = 3mA

0.15V

V

IL(CAn)

IH(CAn)

CC

High Level Input Voltage on CAn

(n = 0, 1, 2)

0.85V

V

CC

R

Resistance from CAn (n = 0, 1, 2)

10

kΩ

MΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1, 2)

to GND to Set CAn = GND

Resistance from CAn (n = 0, 1, 2)

2

0

to V or GND to Set CAn = Float

CC

V

Low Level Output Voltage

Output Fall Time

●

0.4

V

t

I

V = V

B

to V = V

,

20 + 0.1C

250

ns

OF

O

IH(MIN)

O

IL(MAX)

B

C = 10pF to 400pF (Note 7)

Pulse Width of Spikes Suppressed

by Input Filter

●

0

50

ns

SP

Input Leakage

0.1V ≤ V ≤ 0.9V

●

1

µA

pF

IN

CC

IN

CC

C

I/O Pin Capacitance

(Note 12)

10

IN

Capacitive Load for Each Bus Line

400

10

B

External Capacitive Load on Address

Pins CAn (n = 0, 1, 2)

CAX

26091929f

3

LTC2609/LTC2619/LTC2629

The ● denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. REFA = REFB = REFC = REFD = 4.096V (V_CC= 5V), REFA = REFB =

REFC = REFD = 2.048V (V_CC= 2.7V), REFLO = 0V, V_OUTunloaded, unless otherwise noted.

LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

SYMBOL PARAMETER

AC Performance

CONDITIONS

UNITS

t

Settling Time (Note 5)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

7

9

7

9

10

µs

S

Settling Time for 1LSB Step

(Note 6)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.7

1000

12

0.7

1000

12

0.7

1000

12

V/µs

pF

At Midscale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise Density At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

µV

P-P

W U

TI I G CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (See Figure 1) (Notes 8, 9)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

= 2.7V to 5.5V

f

t

SCL Clock Frequency

●

0

0.6

400

kHz

µs

ns

µs

ns

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

HD(STA)

LOW

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

1.3

0.6

0

0.9

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-Up Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

(Note 7)

20 + 0.1C

0.6

300

B

f

B

SU(STO)

BUF

1.3

Falling Edge of 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition

400

1

t

LDAC Low Pulse Width

●

20

ns

2

Note 1: Absolute maximum ratings are those values beyond which the life

of a device may be impaired.

Note 6: V = 5V, V = 4.096V. DAC is stepped ±1LSB between half

CC REF

scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

Note 7: C = capacitance of one bus line in pF.

Note 2: Linearity and monotonicity are defined from code k to code

L

B

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

Note 8: All values refer to V

and V

levels.

L

REF

IH(MIN)

IL(MAX)

rounded to the nearest whole code. For V = 4.096V and N = 16, k =

REF

L

Note 9: These specifications apply to LTC2609/LTC2609-1,

LTC2619/LTC2619-1, LTC2629/LTC2629-1.

256 and linearity is defined from code 256 to code 65,535.

Note 3: SDA, SCL at 0V or V , CA0, CA1 and CA2 floating.

CC

Note 10: DC crosstalk is measured with V = 5V, REFA = REFB = REFC =

CC

Note 4: Inferred from measurement at code k (see Note 2) and at full

REFD = 4.096V, with the measured DAC at midscale, unless otherwise

noted.

L

scale.

Note 5: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 11: R = 2kΩ to GND or V

Note 12: Guaranteed by design and not production tested.

.

CC

REF

L

CC

26091929f

4

LTC2609/LTC2619/LTC2629

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2609

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

1.0

0.8

32

24

32

24

V

= 5V

REF

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–8

–16

–24

–32

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

2609 G02

2609 G01

2609 G03

DNL vs Temperature

INL vs V_REF

DNL vs V_REF

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

CC

= 5.5V

V

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

DNL (POS)

DNL (NEG)

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–0.5

–1.0

–1.5

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

REF

(V)

V

(V)

REF

2609 G04

2609 G05

2609 G06

Settling to ±1LSB

Settling of Full-Scale Step

V

OUT

100µV/DIV

OUT

100µV/DIV

12.3µs

9.7µs

9TH CLOCK

OF 3RD DATA

BYTE

9TH CLOCK OF

3RD DATA BYTE

SCL

2V/DIV

SCR

2V/DIV

2609 G07

2609 G08

2µs/DIV

5µs/DIV

V

= 5V, V

= 4.096V

REF

SETTLING TO ±1LSB

CC

CODE 512 TO 65535 STEP

AVERAGE OF 2048 EVENTS

CC

1/4 SCALE TO 3/4 SCALE STEP

= 2k, C = 200pF

V

= 5V, V

= 4.096V

REF

R

L

AVERAGE OF 2048 EVENTS

26091929f

5

LTC2609/LTC2619/LTC2629

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2619

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to ±1LSB

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

100µV/DIV

0.2

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9µs

2609 G11

2µs/DIV

V

= 5V, V

= 4.096V

REF

CC

1/4 SCALE TO 3/4 SCALE STEP

R

= 2k, C = 200pF

L

0

4096

8192

CODE

12288

16383

0

4096

8192

CODE

12288

16383

AVERAGE OF 2048 EVENTS

2609 G09

2609 G10

LTC2629

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to ±1LSB

2.0

1.5

1.0

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.8

0.6

= 4.096V

1.0

6.8µs

0.4

V

OUT

0.5

1mV/DIV

0.2

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2609 G14

2µs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4 SCALE TO 3/4 SCALE STEP

= 2k, C = 200pF

R

L

0

1024

2048

CODE

3072

4095

0

1024

2048

CODE

3072

4095

AVERAGE OF 2048 EVENTS

2609 G12

2609 G13

26091929f

6

LTC2609/LTC2619/LTC2629

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2609/LTC2619/LTC2629

Current Limiting

Load Regulation

Offset Error vs Temperature

1.0

0.8

3

2

0.10

0.08

CODE = MIDSCALE

V

= V = 5V

CC

REF

0.6

0.06

V

REF

= V = 3V

CC

0.4

0.04

1

0.2

0.02

0

V

REF

= V = 5V

CC

–0.2

–0.4

–0.6

–0.8

–1.0

–0.02

–0.04

–0.06

–0.08

–0.10

V

= V = 3V

CC

REF

–1

–2

–3

V

REF

= V = 3V

CC

V

= V = 5V

CC

REF

–35 –25 –15 –5

I

5

15

25

35

–50 –30 –10 10

30

50

70

90

–40 –30 –20 –10

I

0

10 20 30 40

(mA)

TEMPERATURE (°C)

(mA)

OUT

2609 G16

2609 G17

2609 G15

Gain Error vs Temperature

Offset Error vs V_CC

Zero-Scale Error vs Temperature

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

(V)

CC

2609 G18

2609 G19

2609 G20

Gain Error vs V_CC

I_CCShutdown vs V_CC

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2609 G22

2609 G21

26091929f

7

LTC2609/LTC2619/LTC2629

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2609/LTC2619/LTC2629

Large-Signal Response

Midscale Glitch Impulse

Power-On Reset Glitch

TRANSITION FROM

MS-1 TO MS

V

OUT

V

CC

10mV/DIV

1V/DIV

V

OUT

TRANSITION FROM

MS TO MS-1

0.5V/DIV

9TH CLOCK

OF 3RD DATA

BYTE

4mV PEAK

SCL

2V/DIV

V

= V = 5V

CC

V

REF

OUT

1/4 SCALE TO 3/4 SCALE

10mV/DIV

2609 G24

2609 G25

2.5µs/DIV

250µs/DIV

2.5µs/DIV

2609 G23

Headroom at Rails

vs Output Current

Supply Current vs Logic Voltage

Power-On Reset to Midscale

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V

= 5V

V

= V

CC

REF

5V SOURCING

SWEEP SCL

AND SDA

0V TO V

CC

AND V TO 0V

CC

3V SOURCING

1V/DIV

V

CC

5V SINKING

V

OUT

3V SINKING

0

2606 G27

500µs/DIV

0

0.5

1

1.5

2

2.5

5

1

2

3

4

5

6

7

8

9

10

3 3.5 4 4.5

LOGIC VOLTAGE (V)

I

(mA)

OUT

2609 G28

2609 G26

26091929f

8

LTC2609/LTC2619/LTC2629

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2609/LTC2619/LTC2629

Output Voltage Noise,

0.1Hz to 10Hz

Multiplying Bandwidth

0

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

V

OUT

10µV/DIV

V

= 5V

CC

(DC) = 2V

REF

0

1

2

3

4

5

6

7

8

9

10

(AC) = 0.2V

P-P

SECONDS

CODE = FULL SCALE

2609 G30

1k

10k

100k

1M

FREQUENCY (Hz)

2609 G29

Short-Circuit Output Current vs

V_OUT(Sourcing)

Short-Circuit Output Current vs

V_OUT(Sinking)

50

40

30

20

0

–10

–20

–30

V = 5.5V

CC

V = 5.6V

REF

V = 5.5V

CC

V = 5.6V

REF

CODE = 0

SWEPT 0V TO V

CODE = FULL SCALE

SWEPT V TO 0V

V

OUT

CC

10

0

–40

–50

0

2

3

4

5

6

1

0

2

3

4

5

6

1

1V/DIV

2609 G31

2609 G32

26091929f

9

LTC2609/LTC2619/LTC2629

U

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance pin while data is shifted in and is an

open-drain N-channel output during acknowledgment.

SDA requires a pull-up resistor or current source to V_CC.

REFLO(Pin2): ReferenceLow. Thevoltageatthispinsets

the zero scale (ZS) voltage of all DACs. This pin can be

raised up to 1V above ground at V_CC= 5V or 100mV above

ground at V_CC= 3V.

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 1).

REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage

InputsforeachDAC. REFxsetsthefull-scalevoltageofthe

DACs. REFLO ≤ REFx ≤ V_CC.

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 1).

V

_OUTAto V_OUTD(Pins 4, 5, 13, 14): DAC Analog Voltage

Outputs. The output range is from REFLO to REFx.

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 1).

V

_CC(Pin 16): Supply Voltage Input. 2.7V ≤ V_CC≤ 5.5V.

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the

SDA pin at the rising edges of the clock. This high

impedancepinrequiresapull-upresistororcurrentsource

to V_CC.

26091929f

10

LTC2609/LTC2619/LTC2629

W

BLOCK DIAGRA

V

CC

REFLO

2

GND

1

16

REFA

3

4

15 REFD

DAC A

DAC B

DAC D

DAC C

V

14

V

OUTA

OUTD

V

OUTB

5

6

13

V

OUTC

REFB

12 REFC

CONTROL

LOGIC

32-BIT SHIFT REGISTER

11 CA0

10 CA1

8

9

SCL

SDA

ADDRESS

DECODE

LOGIC

2

I C

INTERFACE

7

CA2

2609 BD

26091929f

11

LTC2609/LTC2619/LTC2629

TEST CIRCUITS

Test Circuit 1

Test Circuit 2

V

DD

R /R /R

INH INL INF

100Ω

CAn

V

/V

IH(CAn) IL(CAn)

GND

2609 TC

W U

W

TI I G DIAGRA S

SDA

t

f

t

SU(DAT)

t

SP

t

r

t

BUF

f

LOW

r

HD(STA)

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

HIGH

S

P

S

HD(DAT)

2609 F01

ALL VOLTAGE LEVELS REFER TO V

AND V

LEVELS

IH(MIN)

IL(MAX)

Figure 1

26091929f

12

LTC2609/LTC2619/LTC2629

U

OPERATIO

Power-On Reset

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and REFx is the voltage at REFA,

REFB, REFC and REFD (Pins 3, 6, 12 and 15).

The LTC2609/LTC2619/LTC2629 clear the outputs to

zero scale when power is first applied, making system

initialization consistent and repeatable. The LTC2609-1/

LTC2619-1/LTC2629-1setthevoltageoutputstomidscale

when power is first applied.

Serial Digital Interface

TheLTC2609/LTC2619/LTC2629communicatewithahost

using the standard 2-wire I²C interface. The Timing Dia-

gram (Figure 1) shows the timing relationship of the sig-

nals on the bus. The two bus lines, SDA and SCL, must be

high when the bus is not in use. External pull-up resistors

or current sources are required on these lines. The value

of these pull-up resistors is dependent on the power sup-

plyandcanbeobtainedfromtheI²Cspecifications.Foran

I²C bus operating in the fast mode, an active pull-up will

be necessary if the bus capacitance is greater than 200pF.

For some applications, downstream circuits are active

during DAC power-up and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2609/

LTC2619/LTC2629 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground(typ)duringpower-on.SeePower-OnResetGlitch

in the Typical Performance Characteristics section.

TheLTC2609/LTC2619/LTC2629arereceive-only(slave)

devices. The master can write to the LTC2609/LTC2619/

LTC2629. The LTC2609/LTC2619/LTC2629 do not re-

spond to a read from the master.

Power Supply Sequencing

The voltage at REFx (Pins 3, 6, 12 and 15) should be kept

within the range –0.3V ≤ REFx ≤ V_CC+ 0.3V (see Absolute

Maximum Ratings). Particular care should be taken to

observe these limits during power supply turn-on and

turn-off sequences, when the voltage at V_CC(Pin 16) is in

transition. TheREFxpinscanbeclampedtostaybelowthe

maximum voltage by using Schottky diodes as shown in

Figure 2, thereby easing sequencing constraints.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

ASTARTconditionisgeneratedbytransitioningSDAfrom

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generatedbytransitioningSDAfromlowtohighwhileSCL

is high. The bus is then free for communication with

another I²C device.

V

CC

16

V

CC

LTC2609/

LTC2619/

LTC2629

3

REFA

REFB

REFC

REFD

REFA

REFB

REFC

REFD

6

12

15

Acknowledge

2609 F02

TheAcknowledgesignalisusedforhandshakingbetween

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge re-

lated clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

bus line during the Acknowledge clock pulse so that it

Figure 2. Use of Schottky Diodes for Power Supply Sequencing

Transfer Function

The digital-to-analog transfer function is:

⎛

⎞

k

V_OUT(IDEAL)

=

[REFx – REFLO] + REFLO

⎜

⎝

⎟

⎠

N

2

26091929f

13

LTC2609/LTC2619/LTC2629

U

OPERATIO

remainsastableLOWduringtheHIGHperiodofthisclock

pulse. The LTC2609/LTC2619/LTC2629 respond to a

write by a master in this manner. The LTC2609/LTC2619/

LTC2629 do not acknowledge a read (retains SDA HIGH

during the period of the Acknowledge clock pulse).

Inadditiontotheaddressselectedbytheaddresspins, the

parts also respond to a global address. This address

allows a common write to all LTC2609, LTC2619 and

LTC2629 parts to be accomplished with one 3-byte write

transaction on the I²C bus. The global address is a 7-bit

on-chip hardwired address and is not selectable by CA0,

CA1 and CA2.

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set to

any one of three states: V_CC, GND or float. This results in

27 selectable addresses for the part. The slave address

assignments are shown in Table 1.

The addresses corresponding to the states of CA0, CA1

and CA2 and the global address are shown in Table 1. The

maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF, as these pins are driven

during address detection to determine if they are floating.

Table 1. Slave Address Map

Write Word Protocol

CA2

GND

CA1

GND

CA0

GND

SA6 SA5 SA4 SA3 SA2 SA1 SA0

The master initiates communication with the LTC2609/

LTC2619/LTC2629withaSTARTconditionanda7-bitslave

address followed by the Write bit (W) = 0. The LTC2609/

LTC2619/LTC2629 acknowledges by pulling the SDA pin

low at the 9th clock if the 7-bit slave address matches the

addressoftheparts(setbyCA0,CA1andCA2)ortheglobal

address.Themasterthentransmitsthreebytesofdata.The

LTC2609/LTC2619/LTC2629 acknowledges each byte of

databypullingtheSDAlinelowatthe9thclockofeachdata

byte transmission. After receiving three complete bytes of

data, the LTC2609/LTC2619/LTC2629 executes the com-

mand specified in the 24-bit input word.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

FLOAT

GND

V

CC

GND

FLOAT

GND

FLOAT

GND

V

CC

GND

V

GND

CC

GND

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

GND

V

CC

FLOAT

GND

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2609/LTC2619/LTC2629 do

not acknowledge the extra bytes of data (SDA is high

during the 9th clock).

FLOAT

V

CC

V

GND

CC

FLOAT

TheformatofthethreedatabytesisshowninFigure3.The

first byte of the input word consists of the 4-bit command

and 4-bit DAC address. The next two bytes consist of the

16-bit data word. The 16-bit data word consists of the

16-, 14- or 12-bit input code, MSB to LSB, followed by 0,

2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629

respectively). AtypicalLTC2609writetransactionisshown

in Figure 4.

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

V

CC

V

GND

CC

FLOAT

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 2. The first four commands in the table

consist of write and update operations. A write operation

V

CC

GLOBAL ADDRESS

26091929f

14

LTC2609/LTC2619/LTC2629

U

OPERATIO

Write Word Protocol for LTC2609/LTC2619/LTC1629

W

A

1ST DATA BYTE

A

2ND DATA BYTE

A

3RD DATA BYTE

A

P

S

SLAVE ADDRESS

INPUT WORD

Input Word (LTC2609)

C3

C1

A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

C2

C0

1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE

Input Word (LTC2619)

C3

C1

A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

C2

C0

1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE

Input Word (LTC2629)

C3

C1

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

C2

C0 A3 A2 A1 A0

2609 F03

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Figure 3

Table 2

COMMAND*

C3 C2 C1 C0

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer amplifiers, bias circuits and reference inputs are

disabled, and draw essentially zero current. The DAC

outputs are put into a high impedance state, and the

output pins are passively pulled to REFLO through

individual 90k resistors. Input- and DAC-register contents

are not disturbed during power down.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

No Operation

ADDRESS (n)*

A3 A2 A1 A0

Any channel or combination of channels can be put into

power-down mode by using command 0100b in

combination with the appropriate DAC address, (n). The

16-bit data word is ignored. The supply current is reduced

by approximately 1/4 for each DAC powered down.

The effective resistance at REFx (Pins 3, 6, 12 and 15)

are at high impedance (typically > 1GΩ) when the corre-

sponding DACs are powered down. Normal operation can

be resumed by executing any command which includes a

DAC update, as shown in Table 2.

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

All DACs

*Command and address codes not shown are reserved and should not be used.

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DACifithadbeeninpower-downmode. Thedatapathand

registers are shown in the Block Diagram.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state

is powered up and updated, normal settling is delayed. If

less than four DACs are in a powered-down state prior to

the update command, the power-up delay time is 5µs.

If on the other hand, all four DACs are powered down,

26091929f

15

LTC2609/LTC2619/LTC2629

U

OPERATIO

then the main bias generation circuit block has been

automatically shut down in addition to the individual DAC

amplifiersandreferenceinputs. Inthiscase, thepower-up

delay time is 12µs (for V_CC= 5V) or 30µs (for V_CC= 3V).

The PC board should have separate areas for the analog

anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Voltage Output

The rail-to-rail amplifier has guaranteed load regulation

when sourcing or sinking up to 15mA at 5V (7.5mA at

2.7V).

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a

continuous and uninterrupted plane, except for necessary

lead pads and vias, with signal traces on another layer.

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is

expressed in LSB/mA.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. When a zero scale

DAC output voltage of zero is desired, REFLO (Pin 2)

should be connected to system star ground.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The amplifier’s DC output

impedance is 0.035Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30Ω typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30Ω • 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteris-

tics section.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

Since the analog output of the device cannot go below

ground, it may limit for the lowest codes as shown in

Figure 4b. Similarly, limiting can occur near full scale

when the REF pins are tied to V_CC. If REFx = V_CCand the

DAC full-scale error (FSE) is positive, the output for the

highest codes limits at V_CCas shown in Figure 4c. No full-

scale limiting can occur if REFx is less than V_CC– FSE.

The amplifier is stable driving capacitive loads of up to

1000pF.

Board Layout

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by keeping

“signal” and “power” grounds separate.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting

can occur.

26091929f

16

LTC2609/LTC2619/LTC2629

U

OPERATIO

26091929f

17

LTC2609/LTC2619/LTC2629

U

OPERATIO

26091929f

18

LTC2609/LTC2619/LTC2629

U

TYPICAL APPLICATIO

Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters

V

REF

REFA

JP3

REFB

JP4

REFC

JP5

REFD

JP6

ADC REF

JP7

1

3

5

A

B

2

4

6

1

3

5

A

B

2

4

6

1

3

5

A

B

2

4

6

1

3

5

A

B

2

4

6

1

3

5

A

B

2

4

6

C1

0.1µF

V

CC

C

V

CC

5V

REF

16

4.096V

2.048V

REF

V

CC

LTC2609CGN

11

10

7

4

E2

E3

E4

E5

E6

E7

E8

E9

CA0

CA1

CA2

V

OUTA

3

REFA

5

V

OUTB

V

OUTB

6

REFB

13

12

14

15

V

OUTC

REFC

9

8

SDA

SCL

V

OUTD

2

I C

REFD

E10

E11

REFLO GND

V

GND

REF

CC

2

1

C4

C5

0.1µF

JP1 REFLO

C3

100pF

R5

7.5k

EXT

EXT REFLO

REFLO

R8

22Ω

3

JP2

ON/OFF

GND

V

CC

7

4

2

8

DISABLE

ADC

MUXOUT ADCIN FSSET

V

LTC2428CG

CH0

CC CC

V

5V

REF

IN

9

LT1790ACS6-5

6

5

10 CH1

11 CH2

12 CH3

13 CH4

14 CH5

15 CH6

17 CH7

4

3

R6

23

V

OUT

IN

C7

C6

CSADC

7.5k

20

25

19

21

24

CS

1µF

0.1µF

NC

CSMUX

SCK

CLK

DIN

SD0

F0

6.3V

8-CHANNEL

MUX

20-BIT

ADC

+

GND GND

SCK

MOSI

MISO

SPI

BUS

–

1

2

26

4.096V

5

ZSSET

REF

LT1790ACS6-4.096

R7

7.5k

6

4

GND GND GND GND GND GND GND

16 18 22 27 28

V

OUT

IN

C9

1µF

6.3V

C8

0.1µF

1

6

3

5

2609 TA02

NC

GND GND

1

2

2.048V

REF

LT1790ACS6-2.048

6

4

V

OUT

IN

C11

1µF

6.3V

C10

0.1µF

3

5

NC

GND GND

1

2

26091929f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC2609/LTC2619/LTC2629

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ± .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V = 4.5V to 5.5V, V

= 0V to 4.096V

CC

OUT

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

OUT

LTC1654

Dual 14-Bit Rail-to-Rail V

DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1821

Single 16-Bit V

DACs with Serial Interface in SO-8

V

CC

OUT

Parallel 5V/3V 16-Bit V

DACs

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 10/8-Bit V

DACs in 16-Pin Narrow SSOP

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Parallel 16-Bit Voltage Output DAC

Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP

Precision 16-Bit Settling in 2µs for 10V Step

LTC2600/LTC2610

LTC2620

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2601/LTC2611

LTC2621

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2602/LTC2612

LTC2622

Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2604/LTC2614

LTC2624

Quad 16-/14-/12-Bit V

DACs in 16-Lead SSOP

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

Output, SPI Serial Interface

2

LTC2605/LTC2615

LTC2625

Octal 16-/14-/12-Bit V

DACs with I C Interface in 16-Lead SSOP 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

Output

2

LTC2606/LTC2616

LTC2626

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN with I C Interface 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

Output

26091929f

LT/LW/TP 0505 500 • PRINTED IN THE USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2619CGN-1
厂家：	Linear
描述：	Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface 四通道16位/ 14位/ 12位轨至轨DAC，带有I2C接口
文件：	总20页 (文件大小：319K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2619CGN-1 [Linear]

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LTC2619CGN-1#PBF

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