LTC2622IMS8#TRPBF [Linear]
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| 型号： | LTC2622IMS8#TRPBF |
| 厂家： | 
Linear |
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LTC2602/LTC2612/LTC2622
Dual 16-/14-/12-Bit
Rail-to-Rail DACs in 8-Lead MSOP
U
DESCRIPTIO
FEATURES
The LTC®2602/LTC2612/LTC2622 are dual 16-,14- and
12-bit, 2.5V-to-5.5Vrail-to-railvoltage-outputDACs, ina
tiny 8-lead MSOP package. They have built-in high per-
formance output buffers and are guaranteed monotonic.
■
Smallest Pin-Compatible Dual DACs:
LTC2602: 16-Bits
LTC2612: 14-Bits
LTC2622: 12-Bits
■
Guaranteed 16-Bit Monotonic Over Temperature
These parts establish advanced performance standards
for output drive, crosstalk and load regulation in single-
supply, voltage output multiples.
■
Wide 2.5V to 5.5V Supply Range
■
Low Power Operation: 300µA per DAC at 3V
■
Individual Channel Power-Down to 1µA, Max
■
The parts use a simple SPI/MICROWIRE™ compatible
3-wire serial interface which can be operated at clock
rates up to 50MHz.
Ultralow Crosstalk between DACs (30µV)
■
High Rail-to-Rail Output Drive (±15mA)
■
Double-Buffered Data Latches
■
Pin-Compatible 10-Bit Version (LTC1661)
The LTC2602/LTC2612/LTC2622 incorporate a power-
on reset circuit. During power-up, the voltage outputs
rise less than 10mV above zero scale, and after power-
up, they stay at zero scale until a valid write and update
take place.
■
Tiny 8-Lead MSOP Package
U
APPLICATIO S
■
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
■
■
■
W
BLOCK DIAGRA
LTC2602
Differential Nonlinearity (DNL)(LTC2602)
1.0
V
V
= 5V
REF
CC
16-BIT
DAC A
16-BIT
DAC B
0.8
0.6
= 4.096V
V
V
V
8
7
5
6
OUT A
OUT B
0.4
0.2
GND
CC
0
–0.2
–0.4
–0.6
–0.8
–1.0
CONTROL
LOGIC
DECODE
1
2
4
3
REF
SDI
CS/LD
SCK
24-BIT SHIFT REGISTER
0
16384
32768
CODE
49152
65535
2602 TA01
2602 BD01
2602f
1
LTC2602/LTC2612/LTC2622
W
U
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
(Note 1)
Any Pin to GND........................................... –0.3V to 6V
Any Pin to VCC ........................................................ –6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC2602C/LTC2612C/LTC2622C .......... 0°C to 70°C
LTC2602I/LTC2612I/LTC2622I.......... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
LTC2602CMS8
LTC2602IMS8
LTC2612CMS8
LTC2612IMS8
LTC2622CMS8
LTC2622IMS8
TOP VIEW
CS/LD
SCK
SDI
1
2
3
4
8 V
OUT A
7 GND
6 V
5 V
CC
REF
OUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
TJMAX = 125°C, θJA = 300°C/W
LTACX
LTACY
LTACZ
LTADA
LTADB
LTADC
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2622
LTC2612
LTC2602
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
●
●
●
●
12
12
14
14
16
16
Bits
Bits
LSB
LSB
Monotonicity
V
V
V
V
= 5V, V
= 5V, V
= 5V, V
= 4.096V (Note 2)
= 4.096V (Note 2)
= 4.096V (Note 2)
CC
CC
CC
REF
I
I
REF
REF
REF
DNL
INL
Differential Nonlinearity
±0.5
±1
±1
Integral Nonlinearity
Load Regulation
±0.75 ±4
±3 ±16
±12 ±64
= V = 5V, Midscale
CC
= 0mA to 15mA Sourcing
= 0mA to 15mA Sinking
●
●
0.025 0.125
0.05 0.125
0.1
0.2
0.5
0.5
0.4
0.65
2
2
LSB/mA
LSB/mA
OUT
OUT
V
= V = 2.5V, Midscale
CC
OUT
OUT
REF
I
I
= 0mA to 7.5mA Sourcing
= 0mA to 7.5mA Sinking
●
●
0.05 0.25
0.1 0.25
0.2
0.4
1
1
0.9
1.3
4
4
LSB/mA
LSB/mA
ZSE
Zero-Scale Error
Offset Error
V
V
= 5V, V
= 5V, V
= 4.096V Code = 0
= 4.096V, (Note 7)
●
●
1
9
1
9
1
9
mV
mV
CC
CC
REF
REF
V
OS
±1
±5
±9
±1
±5
±9
±1
±5
±9
V
OS
Temperature
µV/°C
Coefficient
GE
Gain Error
V
= 5V, V
= 4.096V
●
±0.1 ±0.7
±3
±0.1 ±0.7
±3
±0.1 ±0.7
±3
%FSR
CC
REF
Gain Temperature
Coefficient
ppm/°C
2602f
2
LTC2602/LTC2612/LTC2622
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2602/LTC2612/LTC2622
SYMBOL PARAMETER
PSRR Power Supply Rejection Ratio
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 5V ±10%
–80
dB
CC
R
OUT
DC Output Impedance
V
V
= V = 5V, Midscale; –15mA ≤ I ≤ 15mA
OUT
●
●
0.05
0.05
0.15
0.15
Ω
Ω
REF
REF
CC
= V = 2.5V, Midscale; –7.5mA ≤ I
≤ 7.5mA
CC
OUT
DC Crosstalk (Note 4)
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (per Channel)
±30
±16
±4
µV
µV/mA
µV
I
Short-Circuit Output Current
V
= 5.5V, V = 5.5V
CC REF
SC
Code: Zero Scale; Forcing Output to V
●
●
15
15
34
38
60
60
mA
mA
CC
Code: Full Scale; Forcing Output to GND
V
= 2.5V, V = 2.5V
CC
REF
Code: Zero Scale; Forcing Output to V
●
●
7.5
7.5
20
28
50
50
mA
mA
CC
Code: Full Scale; Forcing Output to GND
Reference Input
Input Voltage Range
●
●
0
V
V
kΩ
pF
CC
Resistance
Normal Mode
44
64
23
80
Capacitance
I
Reference Current, Power Down Mode All DACs Powered Down
●
0.001
1
µA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
2.5
5.5
V
CC
I
V
V
= 5V (Note 3)
= 3V (Note 3)
●
●
●
●
0.7
0.6
0.35
0.10
1.3
1
1
1
mA
mA
µA
CC
CC
CC
All DACs Powered Down (Note 3) V = 5V
CC
CC
All DACs Powered Down (Note 3) V = 3V
µA
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.5V to 5.5V
= 2.5V to 3.6V
●
●
2.4
2.0
V
V
IH
CC
CC
V
V
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
= 2.5V to 5.5V
●
●
●
0.8
0.6
0.5
V
V
V
IL
CC
CC
CC
I
Digital Input Leakage
V
= GND to V
CC
●
●
±1
µA
LK
IN
C
Digital Input Capacitance
(Note 6)
8
pF
IN
LTC2622
LTC2612
LTC2602
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
t
Settling Time (Note 8)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
s
Settling Time for
1LSB Step (Note 9)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
0.80
1000
12
0.80
1000
12
0.80
1000
12
V/µs
pF
At Midscale Transition
nV • s
kHz
Multiplying Bandwidth
180
180
180
e
n
Output Voltage Noise
Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µV
P-P
2602f
3
LTC2602/LTC2612/LTC2622
W U
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6)
LTC2602/LTC2612/LTC2622
SYMBOL PARAMETER
= 2.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
t
t
t
t
t
t
t
t
SDI Valid to SCK Setup
●
●
●
●
●
●
●
●
●
4
4
ns
ns
1
SDI Valid to SCK Hold
SCK High Time
2
9
ns
3
SCK Low Time
9
ns
4
CS/LD Pulse Width
10
7
ns
5
LSB SCK High to CS/LD High
CS/LD Low to SCK High
CS/LD High to SCK Positive Edge
SCK Frequency
ns
6
7
ns
7
7
ns
10
50% Duty Cycle
50
MHz
Note 5: R = 2kΩ to GND or V at the output of the DAC not being tested.
Note 1: Absolute maximum ratings are those values beyond which the life
L
CC
of a device may be impaired.
Note 6: Guaranteed by design and not production tested.
Note 2: Linearity and monotonicity are defined from code k to code
L
Note 7: Inferred from measurement at code 256 (LTC2602), code 64
(LTC2612) or code 16 (LTC2622), and at fullscale.
N
N
2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),
L
L
REF
rounded to the nearest whole code. For V = 4.096V and N = 16, k =
REF
L
Note 8: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
CC
REF
256 and linearity is defined from code 256 to code 65,535.
and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 3: Digital inputs at 0V or V
.
CC
Note 9: V = 5V, V = 4.096V. DAC is stepped ±LBS between half scale
CC
REF
Note 4: DC crosstalk is measured with V = 5V and V
= 4.096V, with
CC
REF
and half scale –1. Load is 2k in parallel with 200pF to GND.
the measured DAC at midscale, unless otherwise noted.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.8
32
24
32
24
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
V
V
= 5V
REF
= 4.096V
CC
= 4.096V
0.6
16
16
0.4
INL (POS)
INL (NEG)
8
8
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–8
–16
–24
–32
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
2602 G21
2602 G20
2602 G22
2602f
4
LTC2602/LTC2612/LTC2622
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602)
DNL vs Temperature
INL vs VREF
DNL vs VREF
1.0
0.8
32
24
1.5
1.0
V
V
= 5V
REF
V
= 5.5V
V
= 5.5V
CC
CC
CC
= 4.096V
0.6
16
0.4
0.5
INL (POS)
INL (NEG)
DNL (POS)
DNL (NEG)
8
DNL (POS)
DNL (NEG)
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–0.5
–1.0
–1.5
–50 –30 –10 10
30
50
70
90
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
V
(V)
REF
REF
2602 G23
2602 G24
2602 G25
Settling to ±1LSB
Settling of Full-Scale Step
V
V
OUT
100µV/DIV
OUT
100µV/DIV
12.3µs
9.7µs
CS/LD
2V/DIV
CS/LD
2V/DIV
2602 G26
2602 G27
2µs/DIV
= 4.096V
5µs/DIV
V
= 5V, V
V
CC
= 5V, V
= 4.096V
CC
1/4-SCALE TO 3/4-SCALE STEP
= 2k, C = 200pF
REF
REF
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
SETTLING TO ±1LSB
R
L
L
AVERAGE OF 2048 EVENTS
(LTC2612)
Integral Nonlinearity (INL)
Settling to ±1LSB
Differential Nonlinearity (DNL)
8
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
6
0.6
4
0.4
V
OUT
2
100µV/DIV
0.2
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
8.9µs
2602 G30
2µs/DIV
V
= 5V, V
= 4.096V
CC
REF
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
L
L
0
4096
8192
12288
16383
0
4096
8192
12288
16383
AVERAGE OF 2048 EVENTS
CODE
CODE
2602 G28
2602 G29
2602f
5
LTC2602/LTC2612/LTC2622
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2622)
Settling to ±1LSB
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
1.0
0.8
2.0
1.5
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
1.0
6.8µs
0.4
V
OUT
0.5
1mV/DIV
0.2
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
2602 G33
2µs/DIV
V
= 5V, V
= 4.096V
CC
REF
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
L
L
0
1024
2048
3072
4095
0
1024
2048
3072
4095
AVERAGE OF 2048 EVENTS
CODE
CODE
2602 G32
2602 G31
(LTC2602/LTC2612/LTC2622)
Current Limiting
Offset Error vs Temperature
Load Regulation
0.10
1.0
0.8
3
2
CODE = MIDSCALE
CODE = MIDSCALE
0.08
V
REF
REF
= V = 5V
CC
0.06
0.04
0.6
V
= V = 3V
CC
0.4
1
0.02
0.2
0
0
0
V
REF
= V = 5V
CC
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V = 3V
CC
REF
–1
–2
–3
V
REF
= V = 5V
CC
V
= V = 3V
REF CC
–40 –30 –20 –10
0
10 20 30 40
–35 –25 –15 –5
5
15
25
35
–50 –30 –10 10
30
50
70
90
I
(mA)
I
(mA)
OUT
TEMPERATURE (°C)
OUT
2602 G01
2602 G02
2602 G03
Zero-Scale Error vs Temperature
Gain Error vs Temperature
Offset Error vs VCC
3
2.5
2.0
1.5
1.0
0.5
0
0.4
0.3
3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –30 –10 10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
2602 G04
2602 G05
2602 G06
2602f
6
LTC2602/LTC2612/LTC2622
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602/LTC2612/LTC2622)
Gain Error vs VCC
ICC Shutdown vs VCC
Large-Signal Settling
0.4
0.3
450
400
350
300
250
200
150
100
50
0.2
0.1
V
OUT
0.5V/DIV
0
–0.1
–0.2
–0.3
–0.4
V
= V = 5V
CC
REF
1/4-SCALE TO 3/4-SCALE
2.5µs/DIV
2602 G09
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
(V)
CC
CC
2602 G08
2602 G07
Headroom at Rails vs Output
Current
Midscale Glitch Impulse
Power-On Reset Glitch
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
V
OUT
V
CC
1V/DIV
10mV/DIV
3V SOURCING
12nV-s TYP
4mV PEAK
CS/LD
5V/DIV
V
OUT
10mV/DIV
5V SINKING
2602 G10
2602 G11
3V SINKING
2.5µs/DIV
250µs/DIV
0
1
2
3
4
5
6
7
8
9
10
I
(mA)
OUT
2602 G12
Supply Current vs Logic Voltage
Exiting Power-Down to Midscale
Multiplying Frequency Response
0
–3
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
V
= 5V
V
V
= 5V
= 2V
CC
CC
REF
SWEEP SCK, SDI
AND CS/LD
–6
0V TO V
CC
–9
V
OUT
0.5V/DIV
–12
–15
–18
–21
–24
–27
–30
–33
–36
ONE DAC IN
POWER DOWN MODE
CS/LD
5V/DIV
V
V
V
= 5V
CC
(DC) = 2V
REF
REF
(AC) = 0.2V
P-P
2.5µs/DIV
2602 G14
CODE = FULL SCALE
1k
10k
100k
1M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
FREQUENCY (Hz)
LOGIC VOLTAGE (V)
2602 G16
2602 G13
2602f
7
LTC2602/LTC2612/LTC2622
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2602/LTC2612/LTC2622)
Short-Circuit Output Current vs
OUT (Sourcing)
Output Voltage Noise,
0.1Hz to 10Hz
Short-Circuit Output Current vs
VOUT (Sinking)
V
0mA
V
OUT
10µV/DIV
0mA
V
V
= 5.5V
= 5.6V
V
V
= 5.5V
= 5.6V
CC
REF
CC
REF
CODE = 0
SWEPT 0V TO V
CODE = FULL SCALE
0
1
2
3
4
5
6
7
8
9
10
V
V
OUT
SWEPT V TO 0V
OUT
CC
CC
SECONDS
2602 G17
1V/DIV
2602 G18
1V/DIV
2602 G19
2602f
8
LTC2602/LTC2612/LTC2622
U
U
U
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
WhenCS/LDislow,SCKisenabledforshiftingdataonSDI
into the register. When CS/LD is taken high, SCK is dis-
abled and the specified command (see Table 1) is ex-
ecuted.
LTC2602/LTC2612/LTC2622 accept input word lengths
of either 24 or 32 bits.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT B and VOUT A (Pins 5 and 8): DAC Analog Voltage
Outputs. The output range is 0 – VREF
.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
VCC (Pin 6): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
GND (Pin 7): Analog Ground.
SDI (Pin 3): Serial Interface Data Input. Data is applied to
SDIfortransfertothedeviceat therisingedgeofSCK. The
W
BLOCK DIAGRA
V
V
V
8
DAC A
DAC B
5
6
OUT A
OUT B
GND
7
CC
CONTROL
LOGIC
DECODE
1
2
4
3
REF
SDI
CS/LD
SCK
24-BIT SHIFT REGISTER
2602 BD
W U
W
TI I G DIAGRA
t
1
t
t
t
3
t
4
6
2
SCK
SDI
1
2
3
23
24
t
10
C3
C2
C1
D1
D0
t
t
7
5
CS/LD
2602 F01
Figure 1
2602f
9
LTC2602/LTC2612/LTC2622
U
OPERATIO
Power-On Reset
TheLTC2602/LTC2612/LTC2622cleartheoutputstozero
scalewhenpowerisfirstapplied,makingsysteminitializa-
tion consistent and repeatable.
Serial Interface
TheCS/LDinputisleveltriggered. Whenthisinputistaken
low, it acts as a chip-select signal, activating the SDI and
SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2602, LTC2612andLTC2622respectively). Datacan
only be transferred to the device when the CS/LD signal is
low.The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2602/
LTC2612/LTC2622 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
smallerbyreducingtheramprateofthepowersupply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
during power-on. See Power-On Reset Glitch in the Typi-
cal Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 6) is in transition.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DACifithadbeeninpower-downmode. Thedatapathand
registers are shown in the block diagram.
Transfer Function
The digital-to-analog transfer function is
k
2N
VOUT(IDEAL)
=
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 4).
Table 1.
COMMAND*
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits to accommodate microprocessors
which have a minimum word width of 16 bits (2 bytes). To
usethe32-bitwordwidth, 8don’t-carebitsaretransferred
to the device first, followed by the 24-bit word as just
described. Figure 2b shows the 32-bit sequence.
C3 C2 C1 C0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
Power-Down Mode
No Operation
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than two outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high-impedance state, and the
ADDRESS (n)*
A3 A2 A1 A0
0
0
1
0
0
1
0
0
1
0
1
1
DAC A
DAC B
All DACs
*Command and address codes not shown are reserved and should not be used.
2602f
10
LTC2602/LTC2612/LTC2622
U
OPERATIO
INPUT WORD (LTC2602)
COMMAND
ADDRESS
DATA (16 BITS)
A3 A2
A0
D12
D6
D5 D4 D3 D2 D1
D0
C3
C1
A1
D15 D14 D13
MSB
D11 D10 D9 D8
D7
C2
C0
LSB
2602 TBL01
INPUT WORD (LTC2612)
COMMAND
ADDRESS
DATA (14 BITS + 2 DON’T-CARE BITS)
A3 A2
A0
A0
D12
D6
D5 D4 D3 D2 D1
D0
X
X
X
C3
C1
A1
D13
D11 D10 D9 D8
D7
C2
C0
MSB
LSB
2602 TBL02
INPUT WORD (LTC2622)
COMMAND
ADDRESS
DATA (12 BITS + 4 DON’T-CARE BITS)
A3 A2
D6
D5 D4 D3 D2 D1
D0
X
X
X
C3
C1
A1
D11 D10 D9 D8
MSB
D7
C2
C0
LSB
2602 TBL03
output pins are passively pulled to ground through indi-
vidual 90kΩ resistors. Input- and DAC-register contents
are not disturbed during power-down.
Voltage Outputs
Each of the two rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Either channel or both channels can be put into power-
downmodebyusingcommand0100bincombinationwith
the appropriate DAC address, (n). The 16-bit data word is
ignored.Thesupplyandreferencecurrentsarereducedby
approximately 50% for each DAC powered down; the
effective resistance at REF (pin 4) rises accordingly,
becoming a high-impedance input (typically > 1GΩ) when
both DACs are powered down.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.050Ω when driving a load well away from
the rails.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
poweredupandupdated, normalsettlingisdelayed. Ifone
of the two DACs is in a powered-down state prior to the
update command, the power-up delay is 5µs. If, on the
other hand, both DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power up delay time is
12µs (for VCC = 5V) or 30µs (for VCC = 3V).
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25Ω typical channel resistance of the output devices; e.g.,
when sinking 1mA, the minimum output voltage = 25Ω •
1mA = 25mV. See the graph Headroom at Rails vs Output
Current in the Typical Performance Characteristics sec-
tion.
The amplifiers are stable driving capacitive loads of up to
1000pF.
2602f
11
LTC2602/LTC2612/LTC2622
U
OPERATIO
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.050Ω), and will degrade DC crosstalk.
Note that the LTC2602/LTC2612/LTC2622 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Board Layout
The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
“signal” and “power” grounds separated internally and by
reducing shared internal resistance.
The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.
Rail-to-Rail Output Considerations
The PC board should have separate areas for the analog
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
2602f
12
LTC2602/LTC2612/LTC2622
U
OPERATIO
2602f
13
LTC2602/LTC2612/LTC2622
U
OPERATIO
POSITIVE
FSE
V
= V
CC
REF
V
REF
= V
CC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
32, 768
65, 535
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
2600 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2602f
14
LTC2602/LTC2612/LTC2622
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0603
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
2602f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC2602/LTC2612/LTC2622
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458: V = 4.5V to 5.5V, V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
= 0V to 4.096V
OUT
OUT
CC
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1654
Dual 14-Bit Rail-to-Rail V
DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
= 5V(3V), Low Power, Deglitched
OUT
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1661
Single 16-Bit V
DAC with Serial Interface in SO-8
V
CC
OUT
Parrallel 5V/3V 16-Bit V
DAC
Low Power, Deglitched, Rail-to-Rail V
OUT
OUT
Octal 10/8-Bit V
DAC in 16-Pin Narrow SSOP
V
V
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
CC
CC
Dual 10-Bit V
DAC in 8-Lead MSOP Package
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610/
LTC2620
Octal 16/14/12-Bit Rail-to-Rail DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range
Rail-to-Rail Output
2602f
LT/TP 1003 1K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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