LTC2624CGN-1#TRPBF_技术文档

LTC2604/LTC2614/LTC2624

Quad 16-Bit Rail-to-Rail DACs

in 16-Lead SSOP

FEATURES

DESCRIPTION

The LTC^®2604/LTC2614/LTC2624 are quad 16-,14- and

12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in

16-leadnarrowSSOPpackages.Thesepartshaveseparate

referenceinputsforeachDAC. Theyhavebuilt-inhighper-

formance output buffers and are guaranteed monotonic.

n

Smallest Pin Compatible Quad 16-Bit DAC:

LTC2604: 16-Bits

LTC2614: 14-Bits

LTC2624: 12-Bits

n

Guaranteed 16-Bit Monotonic Over Temperature

n

Separate Reference Inputs for each DAC

These parts establish advanced performance standards

for output drive, crosstalk and load regulation in single-

supply, voltage output multiples.

n

Wide 2.5V to 5.5V Supply Range

n

Low Power Operation: 250μA per DAC at 3V

n

Individual DAC Power-Down to 1μA, Max

n

The parts use a simple SPI/MICROWIRE compatible

3-wireserialinterfacewhichcanbeoperatedatclockrates

up to 50MHz. Daisy-chain capability and a hardware CLR

function are included.

Ultralow Crosstalk Between DACs (<5μV)

High Rail-to-Rail Output Drive ( 15mA)

Double Buffered Digital Inputs

LTC2604-1/LTC2614-1/LTC2624-1: Power-On Reset

to Midscale

16-Lead Narrow SSOP Package

The LTC2604/LTC2614/LTC2624 incorporate a power-on

resetcircuit.Duringpower-up,thevoltageoutputsriseless

than 10mV above zero scale; and after power-up, they stay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2604-1/LTC2614-1

/LTC2624-1 to midscale. The voltage outputs stay at mid-

scale until a valid write and update take place.

n

APPLICATIONS

n

Mobile Communications

n

Process Control and Industrial Automation

n

Instrumentation

Automatic Test Equipment

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

n

BLOCK DIAGRAM

V

CC

GND

1

REF LO

2

16

REF D

15

Differential Nonlinearity (LTC2604)

REF A

3

1.0

V

OUT D

14

V

= 5V

REF

CC

DAC D

DAC C

0.8

0.6

= 4.096V

V

OUTA

4

DAC A

DAC B

0.4

V

OUT C

13

0.2

0

V

OUTB

5

REF C

12

–0.2

–0.4

–0.6

–0.8

–1.0

REF B

6

CLR

11

CONTROL

LOGIC

SDO

10

CS/LD

7

DECODE

0

16384

32768

CODE

49152

65535

SCK

8

SDI

9

2604 TA01

32-BIT SHIFT REGISTER

2604 BD

2604fd

1

LTC2604/LTC2614/LTC2624

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Any Pin to GND............................................ –0.3V to 6V

1

2

3

4

5

6

7

8

V

CC

16

15

14

13

12

11

10

9

GND

REF LO

REF A

Any Pin to V ............................................. –6V to 0.3V

CC

REF D

Maximum Junction Temperature .......................... 125°C

V

OUT D

Operating Temperature Range

V

OUT A

OUT C

LTC2604C/LTC2614C/LTC2624C ............. 0°C to 70°C

LTC2604C-1/LTC2614C-1/

REF C

CLR

SDO

SDI

V

OUT B

REF B

CS/LD

SCK

LTC2624C-1............................................. 0°C to 70°C

LTC2604I/LTC2614I/LTC2624I.............–40°C to 85°C

LTC2604I-1/LTC2614I-1/

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θ = 150°C/W

LTC2624I-1 ..........................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC2604CGN#PBF

LTC2604CGN-1#PBF

LTC2604IGN#PBF

LTC2604IGN-1#PBF

LTC2614CGN#PBF

LTC2614CGN-1#PBF

LTC2614IGN#PBF

LTC2614IGN-1#PBF

LTC2624CGN#PBF

LTC2624CGN-1#PBF

LTC2624IGN#PBF

LTC2624IGN-1#PBF

TAPE AND REEL

PART MARKING

2604

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC2604CGN#TRPBF

LTC2604CGN-1#TRPBF

LTC2604IGN#TRPBF

LTC2604IGN-1#TRPBF

LTC2614CGN#TRPBF

LTC2614CGN-1#TRPBF

LTC2614IGN#TRPBF

LTC2614IGN-1#TRPBF

LTC2624CGN#TRPBF

LTC2624CGN-1#TRPBF

LTC2624IGN#TRPBF

LTC2624IGN-1#TRPBF

0°C to 70°C

16-Lead Narrow SSOP Package

26041

2604I

0°C to 70°C

–40°C to 85°C

0°C to 70°C

2604I1

2614

26141

2614I

0°C to 70°C

–40°C to 85°C

0°C to 70°C

2614I1

2624

26241

2624I

0°C to 70°C

–40°C to 85°C

2624I1

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The ● denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B =

REF C = REF D = 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded, unless otherwise noted. (Note 10)

LTC2624/LTC2624-1 LTC2614/LTC2614-1 LTC2604/LTC2604-1

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN

TYP

MAX MIN TYP MAX MIN

TYP MAX UNITS

l

12

14

16

Bits

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

0.5

4

1

LSB

Integral Nonlinearity

0.9

4

16

14

64

LSB

2604fd

2

LTC2604/LTC2614/LTC2624

ELECTRICAL CHARACTERISTICS ^The● denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B =

REF C = REF D = 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded, unless otherwise noted. (Note 10)

LTC2624/LTC2624-1 LTC2614/LTC2614-1 LTC2604/LTC2604-1

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX MIN TYP MAX MIN

TYP MAX UNITS

Load Regulation

V

= V = 5V, Midscale

REF CC

l

I

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

0.025 0.125

0.1

0.5

0.3

2

LSB/mA

OUT

I

OUT

V

= V = 2.5V, Midscale

OUT

REF

CC

l

I

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

0.05 0.25

0.2

1

0.7

4

LSB/mA

I

l

ZSE

Zero-Scale Error

Offset Error

1.5

5

9

1.5

5

9

1.5

5

9

mV

V

(Note 7)

9

OS

V

Temperature

μV/°C

OS

Coefﬁcient

l

GE

Gain Error

0.1

5

0.7

0.1

5

0.7

0.1

5

0.7

ꢀFSR

Gain Temperature

Coefﬁcient

ppm/°C

The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. REF

A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D = 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded,

unless otherwise noted. (Note 10)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PSR

Power Supply Rejection

V

CC

V

CC

= 5V 10ꢀ

= 3V 10ꢀ

–80

dB

l

R

OUT

DC Output Impedance

DC Crosstalk (Note 4)

V

= V = 5V, Midscale; –15mA ≤ I ≤ 15mA

OUT

0.025

0.030

0.15

Ω

REF

CC

= V = 2.5V, Midscale; –7.5mA ≤ I

≤ 7.5mA

CC

OUT

Due to Full Scale Output Change (Note 5)

Due to Load Current Change

Due to Powering Down (per Channel)

5

1

3.5

μV

μV/mA

μV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

SC

CC REF

l

Code: Zero Scale; Forcing Output to V

15

34

36

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

= 2.5V, V = 2.5V

CC

REF

l

Code: Zero Scale; Forcing Output to V

7.5

18

24

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

l

0

V

μA

kΩ

pF

CC

Resistance

Normal Mode

88

128

14

160

Capacitance

l

I

Reference Current, Power Down Mode All DACs Powered Down

0.001

1

μA

REF

Power Supply

V

Positive Supply Voltage

Supply Current

For Speciﬁed Performance

2.5

5.5

V

CC

l

I

CC

V

= 5V (Note 3)

= 3V (Note 3)

1.3

1

0.35

0.10

2

1.6

1

mA

μA

CC

All DACs Powered Down (Note 3) V = 5V

CC

All DACs Powered Down (Note 3) V = 3V

1

μA

Digital I/O

l

V

IH

Digital Input High Voltage

V

CC

V

CC

= 2.5V to 5.5V

= 2.5V to 3.6V

2.4

2.0

V

2604fd

3

LTC2604/LTC2614/LTC2624

ELECTRICAL CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B =

REF C = REF D = 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded, unless otherwise noted. (Note 10)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Digital Input Low Voltage

V

CC

V

CC

= 4.5V to 5.5V

= 2.5V to 5.5V

0.8

0.6

V

IL

l

V

Digital Output High Voltage

Digital Output Low Voltage

Digital Input Leakage

Load Current = –100μA

Load Current = +100μA

V

CC

– 0.4

V

OH

0.4

1

OL

I

LK

V

= GND to V

CC

μA

pF

IN

C

Digital Input Capacitance

(Note 6)

8

IN

The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. REF

A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D = 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded,

unless otherwise noted. (Note 10)

LTC2624/LTC2624-1 LTC2614/LTC2614-1 LTC2604/LTC2604-1

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN

TYP

MAX MIN TYP MAX MIN

TYP MAX UNITS

t

Settling Time (Note 8)

0.024ꢀ ( 1LSB at 12 Bits)

0.006ꢀ ( 1LSB at 14 Bits)

0.0015ꢀ ( 1LSB at 16 Bits)

7

9

7

9

10

μs

s

Settling Time for

1LSB Step (Note 9)

0.024ꢀ ( 1LSB at 12 Bits)

0.006ꢀ ( 1LSB at 14 Bits)

0.0015ꢀ ( 1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

μs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.80

1000

12

0.80

1000

12

0.80

1000

12

V/μs

pF

At Midscale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

n

Output Voltage Noise

Density

At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV√Hz

Output Voltage Noise

0.1Hz to 10Hz

15

μV

P–P

TIMING CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D

= 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded, unless otherwise noted. (Note 10)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

= 2.5V to 5.5V

CC

l

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

4

ns

1

2

3

4

5

6

7

8

9

SCK Low Time

9

CS/LD Pulse Width

10

7

LSB SCK High to CS/LD High

CS/LD Low to SCK High

7

SDO Propagation Delay from SCK Falling Edge C_LOAD= 10pF

l

V

_CC= 4.5V to 5.5V

_CC= 2.5V to 5.5V

20

45

ns

V

l

t

9

CLR Pulse Width

20

ns

2604fd

4

LTC2604/LTC2614/LTC2624

TIMING CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D

= 2.048V (V_CC= 2.5V), REF LO = 0V, V_OUTunloaded, unless otherwise noted. (Note 10)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ns

l

t

CS/LD High to SCK Positive Edge

SCK Frequency

7

10

50ꢀ Duty Cycle

50

MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: R = 2kΩ to GND or V .

L CC

Note 6: Guaranteed by design and not production tested.

Note 7: Inferred from measurement at code 256 (LTC2604), code 64

(LTC2614) or code 16 (LTC2624), and at full scale.

Note 2: Linearity and monotonicity are deﬁned from code k to code

L

Note 8: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and

CC

REF

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

L

REF

3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

rounded to the nearest whole code. For V = 4.096V and N = 16,

REF

Note 9: V = 5V, V = 4.096V. DAC is stepped 1LSB between half scale

CC

REF

k = 256, linearity is deﬁned from code 256 to code 65,535.

L

and half scale –1. Load is 2k in parallel with 200pF to GND.

Note 3: Digital inputs at 0V or V

.

CC

Note 10: These speciﬁcations apply to LTC2604/LTC2604-1, LTC2614/

LTC2614-1, LTC2624/LTC2624-1.

Note 4: DC crosstalk is measured with V = 5V and V = 4.096V, with

CC

REF

the measured DAC at midscale, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)

Current Limiting

Load Regulation

Offset Error vs Temperature

0.10

0.08

0.06

0.04

0.02

0

1.0

0.8

3

2

CODE = MIDSCALE

V

= V = 5V

CC

REF

0.6

= V = 3V

CC

0.4

1

0.2

0

V

= V = 5V

CC

REF

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 3V

CC

REF

–1

–2

–3

V

= V = 5V

CC

V

= V = 3V

REF CC

–40 –30 –20 –10

0

10 20 30 40

–35 –25 –15 –5

5

15

25

35

–50 –30 –10 10

30

50

70

90

I

(mA)

I

(mA)

OUT

TEMPERATURE (°C)

OUT

2604 G01

2604 G02

2604 G03

Zero-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs V_CC

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

2

1

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

(V)

CC

2604 G04

2604 G05

2604 G06

2604fd

5

LTC2604/LTC2614/LTC2624

TYPICAL PERFORMANCE CHARATERISTICS

(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)

Gain Error vs V_CC

I_CCShutdown vs V_CC

Large-Signal Settling

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

V

OUT

0.5V/DIV

0

–0.1

–0.2

–0.3

–0.4

V

= V = 5V

CC

REF

1/4-SCALE TO 3/4-SCALE

2.5μs/DIV

2604 G09

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2604 G07

2604 G08

Midscale Glitch Impulse

Power-On Reset Glitch

Power-On Reset to Midscale

V

= V

CC

REF

V

OUT

V

CC

10mV/DIV

1V/DIV

12nV-s TYP

2.5μs/DIV

V

CC

4mV PEAK

1V/DIV

CS/LD

5V/DIV

V

OUT

1V/DIV

10mV/DIV

2604 G10

2604 G34

2604 G11

500μs/DIV

250μs/DIV

Headroom at Rails

vs Output Current

Supply Current vs Logic Voltage

Exiting Power-Down to Midscale

2.0

1.8

1.6

1.4

1.2

1.0

0.8

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 5V

CC

V

= 5V

REF

CC

5V SOURCING

SWEEP SCK, SDI

= 2V

AND CS/LD

0V TO V

CC

V

OUT

0.5V/DIV

3V SOURCING

DACs A-C IN

POWER-DOWN MODE

CS/LD

5V/DIV

5V SINKING

3V SINKING

2.5μs/DIV

2604 G14

0

1

2

3

4

I

5

(mA)

6

7

8

9

10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

LOGIC VOLTAGE (V)

OUT

2604 G12

2604 G13

2604fd

6

LTC2604/LTC2614/LTC2624

TYPICAL PERFORMANCE CHARATERISTICS

(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)

Hardware CLR Hardware CLR to Midscale

Multiplying Frequency Response

0

–3

V

= 5V

REF

CODE = FULL SCALE

CC

= 4.096V

–6

V

OUT

1V/DIV

–9

V

OUT

–12

–15

–18

–21

–24

–27

–30

–33

–36

1V/DIV

CLR

5V/DIV

CLR

5V/DIV

V

= 5V

CC

(DC) = 2V

REF

2604 G15

(AC) = 0.2V

2604 G35

P-P

1μs/DIV

CODE = FULL SCALE

1k

10k

100k

1M

FREQUENCY (Hz)

2604 G16

Output Voltage Noise,

0.1Hz to 10Hz

Short-Circuit Output Current vs

_OUT(Sinking)

Short-Circuit Output Current vs

V_OUT(Sourcing)

V

0

–10

–20

–30

50

40

30

20

V

= 5.5V

= 5.6V

V

= 5.5V

= 5.6V

CC

REF

CC

REF

V

CODE = FULL SCALE

CODE =

V

0

V

SWEPT V TO 0V

SWEPT 0V TO V

OUT

CC

OUT

CC

V

OUT

10μV/DIV

–40

–50

10

0

1

2

3

4

5

6

7

8

9

10

SECONDS

2604 G17

0

2

3

4

5

6

0

2

3

4

5

6

1

1V/DIV

2604 G19

2604 G18

(LTC2604/LTC2604-1)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

1.0

0.8

32

24

32

V

= 5V

REF

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

24

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–16

–24

–32

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

0

16384

32768

CODE

49152

65535

TEMPERATURE (°C)

2604 G21

2604 G22

2604 G20

2604fd

7

LTC2604/LTC2614/LTC2624

TYPICAL PERFORMANCE CHARATERISTICS

(LTC2604/LTC2604-1)

DNL vs Temperature

INL vs V_REF

DNL vs V_REF

1.5

1.0

0.8

32

24

V

= 5V

REF

V

= 5.5V

V

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

0.2

DNL (POS)

DNL (NEG)

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–0.5

–1.0

–1.5

–16

–24

–32

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

(V)

V

(V)

REF

2604 G23

2604 G24

2604 G25

Settling to 1LSB

Settling of Full-Scale Step

V

OUT

100μV/DIV

12.3μs

9.7μs

CS/LD

2V/DIV

CS/LD

2V/DIV

2604 G26

2604 G27

2μs/DIV

5μs/DIV

V

= 5V, V

= 4.096V

V

= 5V, V

= 4.096V

REF

CC

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

CODE 512 TO 65535 STEP

AVERAGE OF 2048 EVENTS

SETTLING TO 1LSB

R

L

AVERAGE OF 2048 EVENTS

(LTC2614/LTC2614-1)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

1.0

0.8

8

6

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

0.2

100μV/DIV

0

CS/LD

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9μs

2604 G30

2μs/DIV

V

= 5V, V

= 4.096V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

0

4096

8192

12288

16383

0

4096

8192

12288

16383

L

AVERAGE OF 2048 EVENTS

CODE

2604 G28

2604 G29

2604fd

8

LTC2604/LTC2614/LTC2624

TYPICAL PERFORMANCE CHARATERISTICS

(LTC2624/LTC2624-1)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

2.0

1.5

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

1.0

6.8μs

0.4

V

OUT

0.5

0.2

1mV/DIV

0

CS/LD

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2604 G33

2μs/DIV

V

CC

= 5V, V

= 4.096V

REF

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

R

L

0

1024

2048

3072

4095

0

1024

2048

3072

4095

L

AVERAGE OF 2048 EVENTS

CODE

2604 G31

2604 G32

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

The LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/

LTC2624-1 accept input word lengths of either 24 or

32 bits.

REF LO (Pin 2): Reference Low. The voltage at this pin

sets the zero scale (ZS) voltage of all DACs. This pin can

be raised up to 1V above ground at V = 5V or 100mV

SDO (Pin 10): Serial Interface Data Output. This pin is

used for daisy-chain operation. The serial output of the

shift register appears at the SDO pin. The data transferred

to the device via the SDI pin is delayed 32 SCK rising

edges before being output at the next falling edge. SDO

is an active output and does not go high impedance, even

when CS/LD is taken to a logic high level.

CC

above ground at V = 3V.

CC

REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Refer-

ence Voltage Inputs for each DAC. REF x sets the full scale

voltage of the DACs. 0V ≤ REF x ≤ V .

CC

V

to V

(Pins 4, 5, 13, 14): DAC Analog Voltage

OUT A

OUT D

Outputs. The output range is from REF LO to REF x.

CLR (Pin 11): Asynchronous Clear Input. A logic low at

this level-triggered input clears all registers and causes

the DAC voltage outputs to drop to 0V for the LTC2604/

LTC2614/LTC2624.Alogiclowatthisinputsetsallregisters

to midscale code and causes the DAC voltage outputs to

go to midscale for the LTC2604-1/LTC2614-1/LTC2624-1.

CMOS and TTL compatible.

CS/LD(Pin7):SerialInterfaceChipSelect/LoadInput.When

CS/LD is low, SCK is enabled for shifting data on SDI into

the register. When CS/LD is taken high, SCK is disabled

and the speciﬁed command (see Table 1) is executed.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL

compatible.

V

CC

(Pin 16): Supply Voltage Input. 2.5V ≤ V ≤ 5.5V.

CC

SDI (Pin 9): Serial Interface Data Input. Data is applied to

SDI for transfer to the device at the rising edge of SCK.

2604fd

9

LTC2604/LTC2614/LTC2624

BLOCK DIAGRAM

V

CC

GND

1

REF LO

2

16

REF D

15

REF A

3

V

OUT D

14

DAC D

DAC C

V

OUTA

4

DAC A

DAC B

V

OUT C

13

V

OUTB

5

REF C

12

REF B

6

CLR

11

CONTROL

LOGIC

SDO

10

CS/LD

7

DECODE

SCK

8

SDI

9

32-BIT SHIFT REGISTER

2604 BD

TIMING DIAGRAM

t

1

t

4

6

2

3

SCK

SDI

1

2

3

23

24

t

10

t

7

5

CS/LD

t

8

SDO

2604 F01

Figure 1

OPERATION

Power-On Reset

outputs from the DAC during this time. The LTC2604/

LTC2614/LTC2624 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground (typ) during power-on. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

The LTC2604/LTC2614/LTC2624 clear the outputs to

zero scale when power is ﬁrst applied, making system

initialization consistent and repeatable. The LTC2604-1/

LTC2614-1/LTC2624-1setthevoltageoutputstomidscale

when power is ﬁrst applied.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

2604fd

10

LTC2604/LTC2614/LTC2624

OPERATION

Power Supply Sequencing

Table 1.

COMMAND*

The voltage at REF (Pins 3, 6, 12 and 15) should be kept

within the range –0.3V ≤ REF x ≤ V + 0.3V (see Abso-

lute Maximum Ratings). Particular care should be taken

to observe these limits during power supply turn-on and

turn-off sequences, when the voltage at V (Pin 16) is

in transition.

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

CC

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

CC

No Operation

ADDRESS (n)*

A3 A2 A1 A0

Transfer Function

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

All DACs

The digital-to-analog transfer function is

ꢀ

ꢃ

^Nꢄ

k

V_OUT(IDEAL)

=

[REF x – REFLO]+REFLO

ꢅ

ꢂ

ꢁ

2

*Command and address codes not shown are reserved and should not

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and REF x is the voltage at REF

A, REF B, REF C and REF D (Pins 3, 6, 12 and 15).

be used.

(LTC2604, LTC2614 and LTC2624 respectively). Data can

only be transferred to the device when the CS/LD signal

is low. The rising edge of CS/LD ends the data transfer

and causes the device to carry out the action speciﬁed in

the 24-bit input word. The complete sequence is shown

in Figure 2a.

Serial Interface

TheCS/LDinputisleveltriggered. Whenthisinputistaken

low, it acts as a chip-select signal, powering-on the SDI

and SCK buffers and enabling the input shift register. Data

(SDI input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded ﬁrst; then the 4-bit

DAC address, A3-A0; and ﬁnally the 16-bit data word. The

data word comprises the 16-, 14- or 12-bit input code,

ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁrst four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

INPUT WORD (LTC2604)

COMMAND

ADDRESS

DATA (16 BITS)

A3 A2

A0

D12

D6

D5 D4 D3 D2 D1

D0

C3

C1

C2

A1

D15 D14 D13

MSB

D11 D10 D9 D8

D7

C0

LSB

2604 TBL01

INPUT WORD (LTC2614)

COMMAND

ADDRESS

DATA (14 BITS + 2 DON’T-CARE BITS)

A3 A2

A0

D12

D6

D5 D4 D3 D2 D1

D0

X

C3

C1

A1

D13

D11 D10 D9 D8

D7

C2

C0

MSB

LSB

2604 TBL02

INPUT WORD (LTC2624)

COMMAND

ADDRESS

DATA (12 BITS + 4 DON’T-CARE BITS)

A3 A2

D6

D5 D4 D3 D2 D1

D0

X

C3

C1

A1

D11 D10 D9 D8

MSB

D7

C2

C0

LSB

2604 TBL03

2604fd

11

LTC2604/LTC2614/LTC2624

OPERATION

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path

and registers are shown in the block diagram.

Power-Down Mode

Forpower-constrainedapplications,power-downmodecan

be used to reduce the supply current whenever less than

four outputs are needed. When in power-down, the buffer

ampliﬁers, bias circuits and reference inputs are disabled,

and draw essentially zero current. The DAC outputs are

put into a high-impedance state, and the output pins are

passively pulled to ground through individual 90k resis-

tors. Input- and DAC-register contents are not disturbed

during power-down.

While the minimum input word is 24 bits, it may optionally

be extended to 32 bits. To use the 32-bit word width, 8

don’t-care bits are transferred to the device ﬁrst, followed

by the 24-bit word as just described. Figure 2b shows the

32-bit sequence. The 32-bit word is required for daisy-

chain operation, and is also available to accommodate

microprocessors which have a minimum word width of

16 bits (2 bytes).

Any channel or combination of channels can be put into

power-down mode by using command 0100 in combi-

b

nation with the appropriate DAC address, (n). The 16-bit

data word is ignored. The supply current is reduced by

approximately 1/4 for each DAC powered down. The ef-

fective resistance at REF x (pins 3, 6, 12 and 15) are at

high-impedance input (typically > 1GΩ) when the cor-

responding DACs are powered down.

Daisy-Chain Operation

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state

is powered up and updated, normal settling is delayed. If

less than four DACs are in a powered-down state prior to

theupdatecommand, thepower-updelaytimeis5μs. Ifon

the other hand, all four DACs are powered down, then the

main bias generation circuit block has been automatically

shut down in addition to the individual DAC ampliﬁers and

reference inputs. In this case, the power up delay time is

TheSDOoutputcanbeusedtofacilitatecontrolofmultiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDIandCS/LD). Sucha“daisy-chain”seriesisconﬁgured

by connecting SDO of each upstream device to SDI of the

next device in the chain. The shift registers of the devices

are thus connected in series, effectively forming a single

input shift register which extends through the entire

chain. Because of this, the devices can be addressed and

controlledindividuallybysimplyconcatenatingtheirinput

words; the ﬁrst instruction addresses the last device in

the chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

12μs (for V = 5V) or 30μs (for V = 3V).

CC

Voltage Outputs

Each of the four rail-to-rail ampliﬁers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

In use, CS/LD is ﬁrst taken low. Then the concatenated

input data is transferred to the chain, using SDI of the

ﬁrst device as the data input. When the data transfer is

complete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the no-operation command

(1111) for the other devices in the chain.

Load regulation is a measure of the ampliﬁer’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

permilliampereofforcedloadcurrentchangeisexpressed

in LSB/mA.

2604fd

12

LTC2604/LTC2614/LTC2624

OPERATION

2604fd

13

LTC2604/LTC2614/LTC2624

OPERATION

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The ampliﬁers’ DC output

impedance is 0.025Ω when driving a load well away from

the rails.

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shielditfromnoise.Analoggroundshouldbeacontinuous

and uninterrupted plane, except for necessary lead pads

and vias, with signal traces on another layer.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30Ω typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30Ω • 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteristics

section.

The GND pin functions as a return path for power sup-

ply currents in the device and should be connected to

analog ground. Resistance from the GND pin to system

star ground should be as low as possible. When a zero

scale DAC output voltage of zero is desired, the REFLO pin

(pin 2) should be connected to system star ground.

The ampliﬁers are stable driving capacitive loads of up

to 1000pF.

Rail-to-Rail Output Considerations

Inanyrail-to-railvoltageoutputdevice,theoutputislimited

to voltages within the supply range.

Board Layout

TheexcellentloadregulationandDCcrosstalkperformance

of these devices is achieved in part by keeping “signal”

and “power” grounds separate.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure3b.Similarly,limitingcanoccurnearfullscalewhen

the REF pins are tied to V . If REF x = V and the DAC

CC

The PC board should have separate areas for the analog

anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

full-scale error (FSE) is positive, the output for the highest

codes limits at V as shown in Figure 3c. No full-scale

CC

limiting can occur if REF x is less than V – FSE.

CC

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting

can occur.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

POSITIVE

FSE

V

= V

CC

REF

V

= V

CC

REF

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

OUTPUT

VOLTAGE

(c)

0

32,768

INPUT CODE

65,535

0V

NEGATIVE

OFFSET

(a)

INPUT CODE

2600 F03

(b)

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect

of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

2604fd

14

LTC2604/LTC2614/LTC2624

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 .005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 .004

(0.38 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2604fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC2604/LTC2614/LTC2624

TYPICAL APPLICATION

5V

1k

10k

0.1μF

10pF

10k

49.9Ω

0.01μF

20Ω

70MHz IN

OUT

47pF

ZC830

49.9Ω

20pF

ZC830

DAC A

DAC B

DAC D

OPTIONAL

20k

DAC C

20k

0.1μF

CS/LD

SCK

0.1μF

SDI

LTC2604

5V

LO

2.74k

1ꢀ

2.74k

1ꢀ

100k

2.74k

1ꢀ

2.74k

1ꢀ

90°

I + Q

MODULATOR

Q INPUT

I INPUT

5V

2.74k

1ꢀ

2.74k

1ꢀ

0°

2.74k

1ꢀ

2.74k

1ꢀ

RF

2604 F04

*ZETEX

(516) 543-7100

Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and

DAC D to Trim for Minimum LO Feedthrough in a Mixer

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V = 4.5V to 5.5V, V

= 0V to 4.096V

OUT

CC

OUT

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V

DAC

Programmable Speed/Power

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1821

Single 16-Bit V

DAC with Serial Interface in SO-8

V

= 5V(3V), Low Power, Deglitched

OUT

CC

Parallel 5V/3V 16-Bit V

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 8-Bit/10-Bit V

DAC in 16-Pin Narrow SSOP

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2μs for 10V Step

250μA per DAC, 2.5V to 5.5V Supply Range

300μA per DAC, 2.5V to 5.5V Supply Range

LTC2600/LTC2610/LTC2620 Octal 16-Bit/14-Bit/12-Bit Rail-to-Rail DACs in 16-Lead SSOP

LTC2602/LTC2612/LTC2622 Dual 16-Bit/14-Bit/12-Bit Rail-to-Rail DACs in 8-Lead MSOP

2604fd

LT 0309 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2624CGN-1#TRPBF
厂家：	Linear
描述：	LTC2624 - Quad 12-Bit Rail-to-Rail DACs in 16-Lead SSOP; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总16页 (文件大小：302K)
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LTC2624CGN-1#TRPBF [Linear]

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