LTC2625CGN-1#TR_技术文档

LTC2605/LTC2615/LTC2625

Octal 16-/14-/12-Bit

Rail-to-Rail DACs in 16-Lead SSOP

U

DESCRIPTIO

FEATURES

The LTC^®2605/LTC2615/LTC2625 are octal 16-, 14-

and 12-bit,2.7Vto5.5Vrail-to-railvoltage-outputDACsin

16-lead narrow SSOP packages. They have built-in

high performance output buffers and are guaranteed

monotonic.

■

Smallest Pin-Compatible Octal DACs:

LTC2605: 16 Bits

LTC2615: 14 Bits

LTC2625: 12 Bits

■

Guaranteed Monotonic Over Temperature

400kHz I²C Interface

Wide 2.7V to 5.5V Supply Range

■

These parts establish new board-density benchmarks

for 16- and 14-bit DACs and advance performance

standards for output drive, crosstalk and load regulation

in single-supply, voltage-output multiples.

The parts use the 2-wire I²C compatible serial interface.

The LTC2605/LTC2615/LTC2625 operate in both the

standard mode (maximum clock rate of 100kHz) and the

fast mode (maximum clock rate of 400kHz).

■

Low Power Operation: 250µA per DAC at 3V

■

Individual Channel Power-Down to 1µA, Max

■

Ultralow Crosstalk Between DACs (<10µV)

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Digital Inputs

27 Selectable Addresses

LTC2605/LTC2615/LTC2625: Power-On Reset to

Zero Scale

The LTC2605/LTC2615/LTC2625 incorporate a power-on

■

LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset

reset circuit. During power-up, the voltage outputs rise

lessthan10mVabovezeroscale;andafterpower-up, they

stay at zero scale until a valid write and update take place.

The power-on reset circuit resets the LTC2605-1/

LTC2615-1/LTC2625-1 to midscale. The voltage output

stays at midscale until a valid write and update

takes place.

to Midscale

Tiny 16-Lead Narrow SSOP Package

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APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

Instrumentation

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Automatic Test Equipment

W

BLOCK DIAGRA

GND

1

16

15

V

CC

DAC A

DAC H

V

2

OUT A

OUT H

Differential Nonlinearity (LTC2605)

1.0

V

= 5V

REF

CC

DAC B

DAC C

DAC G

DAC F

V

OUT G

V

OUT F

3

4

14

13

OUT B

OUT C

0.8

0.6

= 4.096V

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

DAC D

DAC E

V

5

12

OUT D

OUT E

REF

CA0

CA1

6

7

11

10

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

0

16384

32768

CODE

49152

65535

CA2

2605 G02

9

SDA

SCL

8

2605/15/25 BD

2605f

1

LTC2605/LTC2615/LTC2625

W W W

U

(Note 1)

ABSOLUTE AXI U RATI GS

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V_CC.............................................–6V to 0.3V

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

Operating Temperature Range

LTC2605C/LTC2615C/LTC2625C ............. 0°C to 70°C

LTC2605C-1/LTC2615C-1/LTC2625C-1 ... 0°C to 70°C

LTC2605I/LTC2615I/LTC2625I ............ –40°C to 85°C

LTC2605I-1/LTC2615I-1/LTC2625I-1 .. –40°C to 85°C

W U

/O

PACKAGE RDER I FOR ATIO

ORDER PART NUMBER

GN PART MARKING

TOP VIEW

LTC2605CGN

LTC2605CGN-1

LTC2605IGN

LTC2605IGN-1

LTC2615CGN

LTC2615CGN-1

LTC2615IGN

2605

1

2

3

4

5

6

7

8

V

16

15

14

13

12

11

10

9

GND

CC

26051

2605I

26O5I1

2615

V

OUT H

OUT G

OUT F

OUT E

OUT A

OUT B

OUT C

OUT D

REF

26151

2615I

2615I1

2625

26251

2625I

2625I1

CA0

CA1

SDA

CA2

SCL

LTC2615IGN-1

LTC2625CGN

LTC2625CGN-1

LTC2625IGN

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θ = 150°C/W

T

JMAX

JA

LTC2625IGN-1

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded,

unless otherwise noted.

LTC2625/-1

LTC2615/-1

LTC2605/-1

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

●

12

14

16

Bits

LSB

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

±0.5

±4

±1

Integral Nonlinearity

Load Regulation

±1

±4 ±16

±18 ±64

V

= V = 5V, Midscale

CC

OUT

REF

I

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

●

0.02 0.125

0.03 0.125

0.07 0.5

0.10 0.5

0.3

0.4

2

LSB/mA

V

= V = 2.7V, Midscale

OUT

REF

I

CC

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

●

0.04 0.25

0.07 0.25

0.15

0.20

1

0.6

0.8

4

LSB/mA

ZSE

Zero-Scale Error

Offset Error

Code = 0

(Note 4)

●

1.7

±1

±5

9

1.7

±1

±5

9

1.7

±1

±5

9

mV

V

OS

±9

V

OS

Temperature

µV/°C

Coefficient

GE

Gain Error

●

±0.1 ±0.7

±8

±0.1 ±0.7

±8

±0.1 ±0.7

±8

%FSR

Gain Temperature

Coefficient

ppm/°C

2605f

2

LTC2605/LTC2615/LTC2625

E

LECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

unless otherwise noted. (Note 9)

temperature range, otherwise specifications are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded,

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

±10%

–80

dB

CC

R

OUT

DC Output Impedance

V

= V = 5V, Midscale; –15mA ≤ I ≤ 15mA

OUT

●

0.02

0.03

0.15

Ω

REF

CC

= V = 2.7V, Midscale; –7.5mA ≤ I

≤ 7.5mA

CC

OUT

DC Crosstalk (Note 10)

Due to Full Scale Output Change (Note 11)

Due to Load Current Change

Due to Powering Down (per Channel)

±10

±3.5

±7

µV

µV/mA

µV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

CC REF

SC

Code: Zero Scale; Forcing Output to V

●

15

34

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

= 2.7V, V = 2.7V

CC

REF

Code: Zero Scale; Forcing Output to V

●

7.5

20

27

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

●

0

V

kΩ

pF

CC

Resistance

Normal Mode

11

16

90

20

Capacitance

I

Reference Current, Power Down Mode DAC Powered Down

●

0.001

1

µA

REF

Power Supply

V

Positive Supply Voltage

Supply Current

For Specified Performance

●

2.7

5.5

V

CC

I

V

= 5V (Note 3)

= 3V (Note 3)

●

2.50

2.00

0.38

0.16

4.0

3.2

1.0

mA

µA

CC

DAC Powered Down (Note 3) V = 5V

CC

DAC Powered Down (Note 3) V = 3V

µA

Digital I/O (Note 9)

V

Low Level Input Voltage

(SDA and SCL)

●

0.3V

V

IL

CC

V

High Level Input Voltage

(SDA and SCL)

0.7V

CC

IH

V

Low Level Input Voltage (CA0 to CA2) See Test Circuit 1

High Level Input Voltage (CA0 to CA2) See Test Circuit 1

●

0.15V

V

IL(CA)

IH(CA)

CC

0.85V

CC

R

Resistance from CA (n = 0,1,2)

See Test Circuit 2

Sink Current = 3mA

10

kΩ

INH

INL

INF

OL

n

to V to Set CA = V

CC

n

Resistance from CA (n = 0,1,2)

●

kΩ

n

to GND to Set CA = GND

n

Resistance from CA (n = 0,1,2)

2

0

MΩ

n

to V or GND to Set CA = FLOAT

CC

n

V

Low Level Output Voltage

Output Fall Time

●

0.4

V

t

I

V = V

to V = V

,

20 + 0.1C

250

ns

OF

O

IH(MIN)

O

IL(MAX)

B

C = 10pF to 400pF (Note 7)

B

Pulse Width of Spikes Surpassed

by Input Filter

●

0

50

ns

SP

Input Leakage

0.1V ≤ V ≤ 0.9V

●

1

µA

pF

IN

CC

IN

CC

C

I/O Pin Capacitance

(Note 12)

10

IN

Capacitance Load for Each Bus Line

400

10

B

External Capacitive Load on

Address Pins CA0, CA1 and CA2

CAn

2605f

3

LTC2605/LTC2615/LTC2625

The ● denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

unless otherwise noted.

temperature range, otherwise specifications are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded,

LTC2625/-1

LTC2615/-1

LTC2605/-1

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

t

Settling Time (Note 5)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

7

9

7

9

10

µs

S

Settling Time for 1LSB Step

(Note 6)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.80

1000

12

0.80

1000

12

0.80

1000

12

V/µs

pF

At Midscale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise Density At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

µV

P-P

W U

TI I G CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (See Figure 1) (Notes 8, 9)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

= 2.7V to 5.5V

CC

f

t

SCL Clock Frequency

●

0

0.6

400

kHz

µs

ns

µs

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Program

Data Hold Time

HD(STA)

LOW

1.3

0.6

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

0

0.9

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-Up Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

(Note 7)

20 + 0.1C

0.6

300

B

f

B

SU(STO)

BUF

1.3

Note 1: Absolute maximum ratings are those values beyond which the life

of a device may be impaired.

Note 6: V = 5V, V = 4.096V. DAC is stepped ±1LSB between half

CC REF

scale and half scale – 1. Load is 2kΩ in parallel with 200pF to GND.

Note 7: C = capacitance of one bus line in pF.

Note 2: Linearity and monotonicity are defined from code k to code

L

B

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

L

REF

Note 8: All values refer to V

and V

levels.

IH(MIN)

IL(MAX)

rounded to the nearest whole code. For V = 4.096V and N = 16,

REF

Note 9: These specifications apply to LTC2605/LTC2605-1, LTC2615/

LTC2615-1 and LTC2625/LTC2625-1.

k = 256 and linearity is defined from code 256 to code 65,535.

L

Note 3: SDA, SCL at 0V or V , CA0, CA1 and CA2 floating.

CC

Note 10: DC Crosstalk is measured with V = 5V and V = 4096V, with

CC

REF

Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),

code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and

at full scale.

the measured DAC at midscale, unless otherwise noted.

Note 11: R = 2kΩ to GND or V

.

CC

L

Note 12: Guaranteed by design and not production tested.

Note 5: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale

CC

REF

and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND.

2605f

4

LTC2605/LTC2615/LTC2625

ELECTRICAL CHARACTERISTICS

Test Circuit 1

Test Circuit 2

V

DD

100Ω

CA

n

R

/R /R

INH INL INF

V

/V

IH(CA ) IL(CA )

n

2605/15/25 EC01

2605/15/25 EC02

GND

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605

Differential Nonlinearity (DNL)

INL vs Temperature

Integal Nonlinearity (INL)

1.0

0.8

32

24

32

24

V

= 5V

REF

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–8

–16

–24

–32

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

2605 G02

2605 G01

2605 G03

INL vs V_REF

DNL vs V_REF

DNL vs Temperature

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

= 5.5V

CC

V

= 5.5V

CC

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

0.5

DNL (POS)

DNL (NEG)

8

0.2

DNL (POS)

DNL (NEG)

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–0.5

–1.0

–1.5

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

V

3

4

5

TEMPERATURE (°C)

V

(V)

REF

(V)

REF

2605 G04

2605 G05

2605 G06

2605f

5

LTC2605/LTC2615/LTC2625

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605

Settling to ±1LSB

Settling of Full-Scale Step

V

OUT

100µV/DIV

12.3µs

9.7µs

9TH CLOCK

OF 3RD DATA

BYTE

9TH CLOCK OF

3RD DATA BYTE

SCL

2V/DIV

SCR

2V/DIV

2605 G07

2605 G08

2µs/DIV

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

AVERAGE OF 2048 EVENTS

5µs/DIV

V

= 5V, V

REF

SETTLING TO ±1LSB

V = 5V, V = 4.096V

CC

CODE 512 TO 65535 STEP

AVERAGE OF 2048 EVENTS

CC

REF

R

L

LTC2615

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to ±1LSB

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

0.2

100µV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9µs

2605 G11

2µs/DIV

V

= 5V, V

= 4.096V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

0

4096

8192

CODE

12288

16383

L

0

4096

8192

CODE

12288

16383

AVERAGE OF 2048 EVENTS

2605 G09

2605 G10

LTC2625

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to ±1LSB

2.0

1.5

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

1.0

6.8µs

0.4

V

OUT

0.5

0.2

1mV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2605 G14

2µs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

R

0

1024

2048

CODE

3072

4095

0

1024

2048

CODE

3072

4095

L

AVERAGE OF 2048 EVENTS

2605 G12

2605 G13

2605f

6

LTC2605/LTC2615/LTC2625

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Current Limiting

Load Regulation

Offset Error vs Temperature

1.0

0.8

0.10

0.08

3

2

CODE = MIDSCALE

V

= V = 5V

CC

REF

0.6

0.06

= V = 3V

CC

0.4

0.04

1

0.2

0.02

0

V

= V = 5V

CC

REF

–0.2

–0.4

–0.6

–0.8

–1.0

–0.02

–0.04

–0.06

–0.08

–0.10

V

= V = 3V

CC

REF

–1

–2

–3

V

= V = 3V

CC

V

= V = 5V

CC

REF

–35 –25 –15 –5

I

5

15

25

35

–40 –30 –20 –10

I

0

10 20 30 40

–50 –30 –10 10

30

50

70

90

(mA)

TEMPERATURE (°C)

OUT

2606 G16

2605 G15

2605 G17

Zero-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs V_CC

0.4

0.3

3

2

3

2.5

2.0

1.5

1.0

0.5

0

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

V

(V)

TEMPERATURE (°C)

CC

2605 G19

2605 G20

2605 G18

Large-Signal Response

Gain Error vs V_CC

I_CCShutdown vs V_CC

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

V

OUT

0.5V/DIV

0

–0.1

–0.2

–0.3

–0.4

V

= V = 5V

CC

REF

1/4-SCALE TO 3/4-SCALE

2.5µs/DIV

2605 G23

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2605 G22

2605 G21

2605f

7

LTC2605/LTC2615/LTC2625

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Headroom at Rails

vs Output Current

Midscale Glitch Impulse

Power-On Reset Glitch

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5V SOURCING

TRANSITION FROM

MS-1 TO MS

V

OUT

V

CC

1V/DIV

10mV/DIV

3V SOURCING

TRANSITION FROM

MS TO MS-1

9TH CLOCK

OF 3RD DATA

BYTE

4mV PEAK

SCL

2V/DIV

V

OUT

10mV/DIV

5V SINKING

2605 G24

2605 G25

3V SINKING

2.5µs/DIV

250µs/DIV

0

1

2

3

4

5

6

7

8

9

10

I

(mA)

OUT

2605 G26

Multiplying Bandwidth

Supply Current vs Logic Voltage

Power-On Reset to Midscale

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

0

V

= V

CC

REF

V

= 5V

CC

–3

–6

SWEEP SCL

AND SDA 0V

TO V AND

CC

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

V

TO 0V

CC

1V/DIV

V

CC

V

= 5V

CC

(DC) = 2V

REF

0

1

2

3

4

5

V

OUT

(AC) = 0.2V

P-P

2605 G28

CODE = FULL SCALE

LOGIC VOLTAGE (V)

2605 G27

500µs/DIV

1k

10k

100k

1M

FREQUENCY (Hz)

2605 G29

Output Voltage Noise,

0.1Hz to 10Hz

Short-Circuit Output Current vs

V_OUT(Sinking)

Short-Circuit Output Current vs

V_OUT(Sourcing)

0mA

–10mA

–20mA

–30mA

–40mA

–50mA

40mA

30mA

20mA

10mA

0mA

V

OUT

10µV/DIV

V

= 5.5V

REF

CODE = 0

V

= 5.5V

REF

CC

= 5.6V

CODE = FULL SCALE

0

1

2

3

4

5

6

7

8

9

10

V

OUT

SWEPT 0V TO V

V

SWEPT V TO 0V

CC

OUT CC

SECONDS

2605 G30

0

1

2

3

4

5

0

1

2

3

4

5

1V/DIV

2605 G32

1V/DIV

2605 G31

2605f

8

LTC2605/LTC2615/LTC2625

U

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This is

a high impedance pin while data is shifted in. It is an open-

drain N-channel output during acknowledgment. This pin

requires a pull-up resistor or current source to V_CC.

V_{OUT A}to V_{OUT H}(Pins 2-5 and 12-15): DAC Analog

Voltage Output. The output range is 0V to V_REF

.

REF (Pin 6): Reference Voltage Input. 0V ≤ V_REF≤ V_CC.

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 2).

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 2).

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the

SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current

source to V_CC.

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V_CC, GND

orleaveitfloatingtoselectanI²Cslaveaddressforthepart

(Table 2).

V

_CC(Pin 16): Supply Voltage Input. 2.7V ≤ V_CC≤ 5.5V.

W

BLOCK DIAGRA

GND

1

16

15

V

CC

DAC A

DAC H

V

2

OUT A

OUT H

DAC B

DAC C

DAC G

DAC F

V

OUT G

V

OUT F

3

4

14

13

OUT B

OUT C

DAC D

DAC E

V

OUT D

V

OUT E

5

12

REF

CA0

CA1

6

7

11

10

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

CA2

9

SDA

SCL

8

2605/15/25 BD01

W U

W

TI I G DIAGRA

SDA

t

f

SU(DAT)

t

BUF

f

LOW

r

HD(STA)

SP

r

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

S

P

S

HD(DAT)

HIGH

2605/15/25 TD01

ALL VOLTAGE LEVELS REFER TO V

AND V LEVELS

IL(MAX)

IH(MIN)

Figure 1

2605f

9

LTC2605/LTC2615/LTC2625

U

OPERATIO

Power-On Reset

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and V_REFis the voltage at REF

(Pin 6).

The LTC2605/LTC2615/LTC2625 clear the outputs to

zero scale when power is first applied, making system

initialization consistent and repeatable. The LTC2605-1/

LTC2615-1/LTC2625-1setthevoltageoutputstomidscale

when power is first applied.

Serial Digital Interface

The LTC2605/LTC2615/LTC2625 communicate with a

host using the standard 2-wire digital interface. The

Timing Diagram (Figure 1) shows the timing relationship

of the signals on the bus. The two bus lines, SDA and SCL,

must be high when the bus is not in use. External pull-up

resistors or current sources are required on these lines.

The value of these pull-up resistors is dependent on the

power supply and can be obtained from the I²C specifica-

tions. For an I²C bus operating in the fast mode, an active

pull-up will be necessary if the bus capacitance is greater

than 200pF.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2605/

LTC2615/LTC2625 contain circuitry to reduce the

power-on glitch: the analog outputs typically rise less

than 10mV above zero scale during power on if the

power supply is ramped to 5V in 1ms or more. In general,

the glitch amplitude decreases as the power supply ramp

time is increased. See Power-On Reset Glitch in the

Typical Performance Characteristics section.

The LTC2605/LTC2615/LTC2625 are receive-only (slave)

devices. The master can write to the LTC2605/LTC2615/

LTC2625. The LTC2605/LTC2615/LTC2625 do not

respond to a read from the master.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

–0.3V ≤ V_REF≤ V_CC+ 0.3V (see Absolute Maximum

Ratings). Particular care should be taken to observe these

limitsduringpowersupplyturn-onandturn-offsequences,

when the voltage at V_CC(Pin 16) is in transition.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

ASTARTconditionisgeneratedbytransitioningSDAfrom

high to low while SCL is high.

Transfer Function

The digital-to-analog transfer function is

k

2

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT(IDEAL)

=

V

REF

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generatedbytransitioningSDAfromlowtohighwhileSCL

is high. The bus is then free for communication with

another I²C device.

N

Table 1.

ADDRESS (n)*

COMMAND*

A3 A2 A1 A0

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

All DACs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

No Operation

*Address and command codes not shown are reserved and should not be used.

2605f

10

LTC2605/LTC2615/LTC2625

U

OPERATIO

WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625

S

W

A

1ST DATA BYTE

A

2ND DATA BYTE

INPUT WORD

A

P

SLAVE ADDRESS

3RD DATA BYTE

INPUT WORD (LTC2605)

A3 A2

1ST DATA BYTE

INPUT WORD (LTC2615)

A3 A2

1ST DATA BYTE

INPUT WORD (LTC2625)

A3 A2

1ST DATA BYTE

A0

D12

D6

D4

D2

D0

X

C3

C1

A1

D15 D14 D13

D11 D10 D9 D8

D5 D4 D3 D2 D1

3RD DATA BYTE

C2

C0

D7

D5

D3

2ND DATA BYTE

C3

C1

D13 D12 D11

D10

D9 D8 D7 D6

D3 D2 D1 D0

3RD DATA BYTE

X

C2

C0

2ND DATA BYTE

C3

C1

D11 D10 D9

D8

D7 D6 D5 D4

D1 D0

X

C2

C0

2605/2615/2625 O01

2ND DATA BYTE

3RD DATA BYTE

Figure 2

maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

during the Acknowledge clock pulse so that it remains a

stableLOWduringtheHIGHperiodofthisclockpulse.The

LTC2605/LTC2615/LTC2625 respond to a write by a mas-

ter in this manner. The LTC2605/LTC2615/LTC2625 do

not acknowledge a read (it retains SDA HIGH during the

period of the Acknowledge clock pulse).

Write Word Protocol

The master initiates communication with the LTC2605/

LTC2615/LTC2625 with a START condition and a 7-bit

slave address followed by the Write bit (W) = 0. The

LTC2605/LTC2615/LTC2625acknowledgesbypullingthe

SDA pin low at the 9th clock if the 7-bit slave address

matches the address of the parts (set by CA0, CA1 and

CA2) or the global address. The master then transmits

three bytes of data. The LTC2605/LTC2615/LTC2625

acknowledgeseachbyteofdatabypullingtheSDAlinelow

at the 9th clock of each data byte transmission. After

receiving three complete bytes of data, the LTC2605/

LTC2615/LTC2625 executes the command specified in

the 24-bit input word.

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set to

any one of three states: V_CC, GND or FLOAT. This results

in 27 selectable addresses for the part. The addresses

corresponding to the states of CA0, CA1 and CA2 and the

global address are shown in Table 2.

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2605/LTC2615/LTC2625 do

not acknowledge the extra bytes of data (SDA is high

during the 9th clock).

TheformatofthethreedatabytesisshowninFigure2.Thefirst

byte of the input word consists of the 4-bit command and 4-

bit DAC address. The next two bytes consist of the 16-bit data

word. The 16-bit data word consists of the 16-, 14- or 12-bit

input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits

In addition to the address selected by the address pins, the

partsalsorespondtoaglobaladdress. Thisaddressallows

a common write to all LTC2605, LTC2615 and LTC2625

parts to be accomplished with one 3-byte write transaction

on the I²C bus. The global address is a 7-bit hardwired

address and is not selectable by CA0, CA1 and CA2. The

2

(LTC2605, LTC2615 and LTC2625 respectively). A typical I C

write transaction is shown in Figure 3.

2605f

11

LTC2605/LTC2615/LTC2625

U

OPERATIO

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads the 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DACifithadbeeninpower-downmode. Thedatapathand

registers are shown in the block diagram.

Power Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than eight outputs are needed. When in power-down, the

buffer amplifiers and reference inputs are disabled and

drawessentiallyzerocurrent.TheDACoutputsareputinto

a high-impedance state, and the output pins are passively

pulled to ground through individual 90k resistors. When

all eight DACs are powered down, the bias generation

circuit is also disabled. Input- and DAC- registers are not

disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100_bin

combination with the appropriate DAC address, (n). The

16-bit data word is ignored. The supply and reference

currents are reduced by approximately 1/8 for each DAC

powereddown;theeffectiveresistanceatREF(Pin6)rises

accordingly, becoming a high-impedance input (typically

>1GΩ) when all eight DACs are powered down.

Table 2. Slave Address Map

CA2

GND GND

GND GND FLOAT

GND GND

CA1

CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0

GND

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V

CC

GND FLOAT GND

GND FLOAT FLOAT

GND FLOAT

V

CC

GND

V

CC

V

CC

V

CC

GND

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output

is updated.

FLOAT

V

CC

FLOAT GND

FLOAT GND FLOAT

FLOAT GND

GND

V

There is an initial delay as the DAC powers up before it

begins its usual settling behavior. If less than eight DACs

are in a powered-down state prior to the updated

command, the power-up delay is 5µs. If, on the other

hand, all eight DACs are powered down, then the bias

generation circuit is also disabled and must be restarted.

In this case, the power-up delay is greater: 12µs for

V_CC= 5V, 30µs for V_CC= 3V.

CC

FLOAT FLOAT GND

FLOAT FLOAT FLOAT

FLOAT FLOAT

V

CC

FLOAT

V

CC

V

CC

V

CC

GND

FLOAT

V

CC

V

GND

GND FLOAT

GND

CC

V

CC

Voltage Outputs

FLOAT GND

FLOAT FLOAT

Each of the eight rail-to-rail amplifiers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

FLOAT

V

CC

V

CC

V

CC

V

CC

GND

FLOAT

Load regulation is a measure of the amplifier’s ability

to maintain the rated voltage accuracy over a wide range

ofloadconditions.Themeasuredchangeinoutputvoltage

per milliampere of forced load current change is

expressed in LSB/mA.

V

CC

GLOBAL ADDRESS

2605f

12

LTC2605/LTC2615/LTC2625

U

OPERATIO

DC output impedance is equivalent to load regulation and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The amplifier’s DC output

impedance is 0.020Ω when driving a load well away from

the rails.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continu-

ous and uninterrupted plane, except for necessary lead

pads and vias, with signal traces on another layer.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

30Ω typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30Ω • 1mA = 30mV. See the graph Headroom at Rails vs

OutputCurrentintheTypicalPerformanceCharacteristics

section.

The GND pin of the part should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. Resistance here will

add directly to the effective DC output impedance of the

device (typically 0.020Ω), and will degrade DC crosstalk.

Note that the LTC2605/LTC2615/LTC2625 are no more

susceptible to these effects than other parts of their type;

on the contrary, they allow layout-based performance

improvements to shine rather than limiting attainable

performance with excessive internal resistance.

The amplifiers are stable driving capacitive loads of up

to 1000pF.

Board Layout

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by keeping

“signal” and “power” grounds separated internally and by

reducing shared internal resistance to just 0.005Ω.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

The GND pin functions both as the node to which the

reference and output voltages are referred and as a return

path for power currents in the device. Because of this,

careful thought should be given to the grounding scheme

and board layout in order to ensure rated performance.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 4b. Similarly, limiting can occur near full scale

when the REF pin is tied to V_CC. If V_REF= V_CCand the DAC

full-scale error (FSE) is positive, the output for the highest

codes limits at V_CCas shown in Figure 4c. No full-scale

limiting can occur if V_REFis less than V_CC– FSE.

The PC board should have separate areas for the analog

anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimalcapacitiveandresistiveinteractionwitheach other.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting

can occur.

2605f

13

LTC2605/LTC2615/LTC2625

U

OPERATIO

2605f

14

LTC2605/LTC2615/LTC2625

U

OPERATIO

POSITIVE

FSE

V

REF

= V

CC

V

= V

CC

REF

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

(c)

OUTPUT

VOLTAGE

0

32, 768

65, 535

INPUT CODE

(a)

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

2605/15/25 O05

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect

of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 .005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 .004

(0.38 0.10)

× 45°

.053 – .068

(1.351 – 1.727)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0 – 8 TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

GN16 (SSOP) 0502

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2605f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC2605/LTC2615/LTC2625

U

TYPICAL APPLICATIO

Demonstration Circuit—LTC2428 20-Bit ADC Measures Key Performance Parameters

ADDRESS SELECTION

V

CC

REF

C1

0.1µF

C2

0.1µF

6

16

REF

V

CC

11

10

7

2

TP3

CA0

CA1

CA2

V

A

B

C

D

E

OUT

DAC A

3

4

TP4

DAC B

5

V

CC

12

13

14

15

TP5

DAC C

V

OUT

10k

V

F

OUT

9

8

TP6

DAC D

SDA

SCL

V

G

H

2

OUT

I C

BUS

DAC OUTPUTS

TP7

DAC E

V

REF

V

CC

GND

1

U2

LTC2605CGN

TP8

DAC F

C4

0.1µF

C5

0.1µF

TP9

DAC G

R5

7.5k

JP1

R8

22

ON/OFF

3

TP10

DAC H

C10

100pF

2

DISABLE

ADC

V

IN

7

4

3

2

8

U4

1

LT1236ACS8-5

V

MUXOUT ADCIN FS

CC CC

SET

2

6

V

REF

V

IN

V

OUT

1

9

CH0

5V

TP11

REF

23

R6

7.5k

10 CH1

11 CH2

12 CH3

13 CH4

14 CH5

15 CH6

17 CH7

GND

4

CSADC

V

2

3

4.096V

20

25

19

21

24

CS

C7

4.7µF

6.3V

C6

0.1µF

CSMUX

SCK

JP2

REF

V

4-/8-CHANNEL

MUX

20-BIT

+

SCK

SPI

BUS

ADC

CLK

U5

D

IN

LT1461ACS8-4

–

2

3

6

SD0

V

CC

V

OUT

IN

1

26

SHDN

GND

5V

TP12

FO

REF

5

ZS

SET

V

CC

2

3

GND GND GND GND GND GND GND

16 18 22 27 28

R7

7.5k

C9

0.1µF

C8 REGULATOR

4

1µF

16V

JP3

1

6

U3

LTC2428CG

TP13

GND

V

CC

2605 TA01

5V

RELATED PARTS

PART NUMBER

DESCRIPTION

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

COMMENTS

LTC1458: V = 4.5V to 5.5V, V

LTC1458/LTC1458L

= 0V to 4.096V

OUT

CC

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V

DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1821

Single 16-Bit V

DAC with Serial Interface in SO-8

V

CC

OUT

Parrallel 5V/3V 16-Bit V

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 10-/8-Bit V

DAC in 16-Pin Narrow SSOP

V

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

CC

OUT

Parallel 16-Bit Voltage Output DAC

Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP

Precision 16-Bit Settling in 2µs for 10V Step

250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail

Output, SPI Interface

LTC2600/LTC2610/

LTC2620

OUT

LTC2601/LTC2611/

LTC2621

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail

Output, SPI Interface

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail

Output, SPI Interface

OUT

LTC2604/LTC2614/

LTC2624

Quad 16-/14-/12-Bit V

DACs in 16-Lead SSOP

250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail

OUT

Output, SPI Interface

2

LTC2606/LTC2616/

LTC2626

Single 16-/14-/12-Bit V

DACs with I C Interface in 10-Lead DFN 270µA per DAC, 2.7V–5.5V Supply Range, Rail-to-Rail

OUT

2

Output, I C Interface

2605f

LT/LWI/TP 0405 500 • PRINTED IN THE USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

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型号：	LTC2625CGN-1#TR
厂家：	Linear
描述：	LTC2625 - Octal 12-Bit Rail-to-Rail DACs in 16-Lead SSOP; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 转换器数模转换器光电二极管
文件：	总16页 (文件大小：317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2625CGN-1#TR [Linear]

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