LTC2624CGN_技术文档

LTC2604/LTC2614/LTC2624

Quad 16-Bit Rail-to-Rail DACs

in 16-Lead SSOP

U

FEATURES

DESCRIPTIO

The LTC^®2604/LTC2614/LTC2624 are quad 16-,14- and

12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in

16-lead narrow SSOP packages. These parts have sepa-

rate reference inputs for each DAC. They have built-in

high performance output buffers and are guaranteed

monotonic.

■

Smallest Pin Compatible Quad 16-Bit DAC:

LTC2604: 16-Bits

LTC2614: 14-Bits

LTC2624: 12-Bits

■

Guaranteed 16-Bit Monotonic Over Temperature

■

Separate Reference Inputs for each DAC

■

Wide 2.5V to 5.5V Supply Range

These parts establish advanced performance standards

for output drive, crosstalk and load regulation in single-

supply, voltage output multiples.

The parts use a simple SPI/MICROWIRE^TMcompatible

3-wire serial interface which can be operated at clock

ratesupto50MHz.Daisy-chaincapabilityandahardware

CLR function are included.

■

Low Power Operation: 250µA per DAC at 3V

■

Individual DAC Power-Down to 1µA, Max

■

Ultralow Crosstalk Between DACs (<5µV)

■

High Rail-to-Rail Output Drive (±15mA)

■

Double Buffered Digital Inputs

■

16-Lead Narrow SSOP Package

U

APPLICATIO S

The LTC2604/LTC2614/LTC2624 incorporate a power-

on reset circuit. During power-up, the voltage outputs

rise less than 10mV above zero scale; and after power-

up, they stay at zero scale until a valid write and update

take place.

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

Automatic Test Equipment

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corp.

W

BLOCK DIAGRA

V

CC

GND

1

REF LO

2

REF A

3

16

REF D

15

Differential Nonlinearity (LTC2604)

V

OUT D

14

1.0

DAC D

DAC C

V

= 5V

REF

CC

0.8

0.6

= 4.096V

V

OUTA

DAC A

DAC B

4

V

OUT C

13

0.4

0.2

V

OUTB

5

REF C

12

0

–0.2

–0.4

–0.6

–0.8

–1.0

REF B

6

CLR

11

CONTROL

LOGIC

SDO

10

CS/LD

7

DECODE

0

16384

32768

CODE

49152

65535

SCK

8

SDI

9

32-BIT SHIFT REGISTER

2604 TA01

2604 BD

2604f

1

LTC2604/LTC2614/LTC2624

W

U

W W W

U

/O

ABSOLUTE AXI U RATI GS

PACKAGE RDER I FOR ATIO

(Note 1)

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V_CC............................................ –6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LTC2604/LTC2614/LTC2624C ............... 0°C to 70°C

LTC2604/LTC2614/LTC2624I ............ –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

ORDER PART

TOP VIEW

NUMBER

1

2

3

4

5

6

7

8

V

CC

16

15

14

13

12

11

10

9

GND

REF LO

REF A

LTC2604CGN

LTC2604IGN

LTC2614CGN

LTC2614IGN

LTC2624CGN

LTC2624IGN

REF D

V

OUT D

V

OUT C

V

OUT A

REF C

CLR

SDO

SDI

V

OUT B

REF B

CS/LD

SCK

GN PART MARKING

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 150°C/W

2604

2604I

2614

2614I

2624

2624I

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D = 2.048V (V_CC= 2.5V),

REF LO = 0V, V_OUTunloaded, unless otherwise noted.

LTC2624

LTC2614

LTC2604

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

●

12

14

16

Bits

LSB

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity

±0.5

±1

Integral Nonlinearity

Load Regulation

±0.9 ±4

±4 ±16

±14 ±64

V

= V = 5V, Midscale

CC

OUT

REF

I

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

●

0.025 0.125

0.1

0.5

0.3

2

LSB/mA

V

= V = 2.5V, Midscale

OUT

REF

I

CC

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

●

0.05 0.25

0.2

1

0.7

4

LSB/mA

ZSE

Zero-Scale Error

Offset Error

●

1.5

9

1.5

9

1.5

9

mV

V

(Note 7)

±1.5 ±9

±5

±1.5 ±9

±5

±1.5 ±9

±5

OS

V

Temperature

µV/°C

OS

Coefficient

GE

Gain Error

●

±0.1 ±0.7

±5

±0.1 ±0.7

±5

±0.1 ±0.7

±5

%FSR

Gain Temperature

Coefficient

ppm/°C

LTC2604/LTC2614/LTC2624

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

= 5V ±10%

= 3V ±10%

–80

dB

CC

R

OUT

DC Output Impedance

V

= V = 5V, Midscale; –15mA ≤ I ≤ 15mA

OUT

●

0.025

0.030

0.15

Ω

REF

CC

= V = 2.5V, Midscale; –7.5mA ≤ I

≤ 7.5mA

CC

OUT

2604f

2

LTC2604/LTC2614/LTC2624

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D = 2.048V (V_CC= 2.5V),

REF LO = 0V, V_OUTunloaded, unless otherwise noted.

LTC2604/LTC2614/LTC2624

SYMBOL PARAMETER

DC Crosstalk (Note 4)

CONDITIONS

MIN

TYP

MAX

UNITS

Due to Full Scale Output Change (Note 5)

Due to Load Current Change

Due to Powering Down (per Channel)

±5

±1

±3.5

µV

µV/mA

µV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

CC REF

SC

Code: Zero Scale; Forcing Output to V

●

15

34

36

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

= 2.5V, V = 2.5V

CC

REF

Code: Zero Scale; Forcing Output to V

●

7.5

18

24

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

●

0

V

kΩ

pF

CC

Resistance

Normal Mode

88

128

14

160

Capacitance

I

Reference Current, Power Down Mode All DACs Powered Down

●

0.001

1

µA

REF

Power Supply

V

Positive Supply Voltage

Supply Current

For Specified Performance

●

2.5

5.5

V

CC

I

V

= 5V (Note 3)

= 3V (Note 3)

●

1.3

1

0.35

0.10

2

1.6

1

mA

µA

CC

All DACs Powered Down (Note 3) V = 5V

CC

All DACs Powered Down (Note 3) V = 3V

1

µA

Digital I/O

V

Digital Input High Voltage

Digital Input Low Voltage

V

= 2.5V to 5.5V

= 2.5V to 3.6V

●

2.4

2.0

V

IH

CC

V

= 4.5V to 5.5V

= 2.5V to 5.5V

●

0.8

0.6

V

IL

CC

V

Digital Output High Voltage

Digital Output Low Voltage

Digital Input Leakage

Load Current = –100µA

Load Current = +100µA

●

V

– 0.4

CC

V

OH

OL

0.4

±1

8

I

V

= GND to V

CC

µA

pF

LK

IN

C

Digital Input Capacitance

(Note 6)

IN

LTC2624

LTC2614

LTC2604

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

t

Settling Time (Note 8)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

7

9

7

9

10

µs

s

Settling Time for

1LSB Step (Note 9)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.80

1000

12

0.80

1000

12

0.80

1000

12

V/µs

pF

At Midscale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise

Density

At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

µV

P-P

2604f

3

LTC2604/LTC2614/LTC2624

W U

TI I G CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T_A= 25°C. REF A = REF B = REF C = REF D = 4.096V (V_CC= 5V), REF A = REF B = REF C = REF D = 2.048V (V_CC= 2.5V),

REF LO = 0V, V_OUTunloaded, unless otherwise noted.

LTC2604/LTC2614/LTC2624

SYMBOL PARAMETER

= 2.5V to 5.5V

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

t

SDI Valid to SCK Setup

●

4

ns

1

SDI Valid to SCK Hold

2

3

4

5

6

7

SCK High Time

9

SCK Low Time

9

CS/LD Pulse Width

10

7

LSB SCK High to CS/LD High

CS/LD Low to SCK High

SDO Propagation Delay from SCK Falling Edge

7

t₈

C_LOAD= 10pF

V

_CC= 4.5V to 5.5V

●

20

45

ns

V_CC= 2.5V to 5.5V

t₉

CLR Pulse Width

●

20

7

ns

t

CS/LD High to SCK Positive Edge

SCK Frequency

10

50% Duty Cycle

50

MHz

Note 5: R = 2kΩ to GND or V

.

Note 1: Absolute maximum ratings are those values beyond which the life

L

CC

of a device may be impaired.

Note 6: Guaranteed by design and not production tested.

Note 2: Linearity and monotonicity are defined from code k to code

L

Note 7: Inferred from measurement at code 256 (LTC2604), code 64

(LTC2614) or code 16 (LTC2624), and at full scale.

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

L

REF

rounded to the nearest whole code. For V

= 4.096V and N = 16,

REF

Note 8: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale

CC

REF

k = 256, linearity is defined from code 256 to code 65,535.

L

and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 3: Digital inputs at 0V or V

.

CC

Note 9: V = 5V, V = 4.096V. DAC is stepped 1LSB between half scale

CC

REF

Note 4: DC crosstalk is measured with V = 5V and V

= 4.096V, with

CC

REF

and half scale –1. Load is 2k in parallel with 200pF to GND.

the measured DAC at midscale, unless otherwise noted.

U W

(LTC2604/LTC2614/LTC2624)

TYPICAL PERFOR A CE CHARACTERISTICS

Offset Error vs Temperature

Current Limiting

Load Regulation

0.10

0.08

1.0

0.8

3

2

CODE = MIDSCALE

V

REF

= V = 5V

CC

0.06

0.6

V

= V = 3V

CC

0.04

0.4

1

0.02

0.2

0

V

REF

= V = 5V

CC

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 3V

CC

REF

–1

–2

–3

V

REF

= V = 5V

CC

V

= V = 3V

REF CC

–40 –30 –20 –10

0

10 20 30 40

–35 –25 –15 –5

5

15

25

35

–50 –30 –10 10

30

50

70

90

I

(mA)

I

(mA)

TEMPERATURE (°C)

OUT

2604 G01

2604 G02

2604 G03

2604f

4

LTC2604/LTC2614/LTC2624

TYPICAL PERFOR A CE CHARACTERISTICS ^{(LTC2604/LTC2614/LTC2624)}

U W

Zero-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs V_CC

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

(V)

CC

2604 G04

2604 G05

2604 G06

Gain Error vs V_CC

I_CCShutdown vs V_CC

Large-Signal Settling

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

V

OUT

0.5V/DIV

0

–0.1

–0.2

–0.3

–0.4

V

= V = 5V

CC

REF

1/4-SCALE TO 3/4-SCALE

2.5µs/DIV

2604 G09

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2604 G07

2604 G08

Headroom at Rails vs Output

Current

Midscale Glitch Impulse

Power-On Reset Glitch

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5V SOURCING

V

OUT

V

CC

10mV/DIV

3V SOURCING

1V/DIV

12nV-s TYP

4mV PEAK

CS/LD

5V/DIV

V

OUT

10mV/DIV

5V SINKING

2604 G11

2604 G10

3V SINKING

250µs/DIV

2.5µs/DIV

0

1

2

3

4

5

6

7

8

9

10

I

(mA)

OUT

2604 G12

2604f

5

LTC2604/LTC2614/LTC2624

U W

(LTC2604/LTC2614/LTC2624)

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Logic Voltage

Exiting Power-Down to Midscale

Hardware CLR

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

V

= 5V

= 2V

V

= 5V

CC

REF

CC

SWEEP SCK, SDI

AND CS/LD

0V TO V

CC

V

OUT

V

OUT

0.5V/DIV

1V/DIV

DACs A-C IN

POWER-DOWN MODE

CS/LD

5V/DIV

CLR

5V/DIV

2604 G15

2.5µs/DIV

2604 G14

1µs/DIV

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

LOGIC VOLTAGE (V)

2604 G13

Output Voltage Noise,

0.1Hz to 10Hz

Short-Circuit Output Current vs

V_OUT(Sinking)

Multiplying Frequency Response

0

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

V

OUT

10µV/DIV

0mA

V

= 5.5V

REF

CODE = 0

CC

V

= 5V

CC

= 5.6V

(DC) = 2V

REF

(AC) = 0.2V

P-P

0

1

2

3

4

5

6

7

8

9

10

V

SWEPT 0V TO V

OUT

CC

CODE = FULL SCALE

SECONDS

2604 G17

1k

10k

100k

1M

1V/DIV

2604 G18

FREQUENCY (Hz)

2604 G16

Short-Circuit Output Current vs

_OUT(Sourcing)

V

0mA

V

= 5.5V

REF

CC

= 5.6V

CODE = FULL SCALE

V

OUT

SWEPT V TO 0V

CC

1V/DIV

2604 G19

2604f

6

LTC2604/LTC2614/LTC2624

U W

(LTC2604)

TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

32

24

1.0

0.8

32

24

V

= 5V

REF

V

= 5V

REF

CC

V

= 5V

REF

= 4.096V

CC

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–8

–16

–24

–32

–50 –30 –10 10

30

50

70

90

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

TEMPERATURE (°C)

2604 G22

2604 G21

2604 G20

DNL vs Temperature

INL vs V_REF

DNL vs V_REF

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

= 5.5V

V

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

DNL (POS)

DNL (NEG)

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–0.5

–1.0

–1.5

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

(V)

V

(V)

REF

2604 G23

2604 G24

2604 G25

Settling to ±1LSB

Settling of Full-Scale Step

V

OUT

100µV/DIV

12.3µs

9.7µs

CS/LD

2V/DIV

CS/LD

2V/DIV

2604 G27

2604 G26

5µs/DIV

2µs/DIV

V

= 5V, V

= 4.096V

V

= 5V, V

= 4.096V

CC

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

REF

CODE 512 TO 65535 STEP

AVERAGE OF 2048 EVENTS

SETTLING TO ±1LSB

R

L

AVERAGE OF 2048 EVENTS

2604f

7

LTC2604/LTC2614/LTC2624

U W

TYPICAL PERFOR A CE CHARACTERISTICS

(LTC2614)

Settling to ±1LSB

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

100µV/DIV

0.2

0

CS/LD

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9µs

2604 G30

2µs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

L

0

4096

8192

12288

16383

0

4096

8192

12288

16383

AVERAGE OF 2048 EVENTS

CODE

2604 G28

2604 G29

(LTC2624)

Settling to ±1LSB

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

2.0

1.5

1.0

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.8

0.6

= 4.096V

1.0

6.8µs

0.4

V

OUT

0.5

1mV/DIV

0.2

0

CS/LD

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2604 G33

2µs/DIV

V

= 5V, V

= 4.096V

CC

REF

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

L

0

1024

2048

3072

4095

0

1024

2048

3072

4095

AVERAGE OF 2048 EVENTS

CODE

2604 G31

2604 G32

U

PIN FUNCTIONS

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.

WhenCS/LDislow,SCKisenabledforshiftingdataonSDI

into the register. When CS/LD is taken high, SCK is

disabled and the specified command (see Table 1) is

executed.

GND (Pin 1): Analog Ground.

REFLO(Pin2):ReferenceLow.Thevoltageatthispinsets

the zero scale (ZS) voltage of all DACs. The voltage range

is 0 ≤ REF LO ≤ V_CC– 2.5V.

REFA,REFB,REFC,REFD(Pins3,6,12,15):Reference

Voltage Inputs for each DAC. REF x sets the full scale

voltage of the DACs. 0V ≤ REF x ≤ V_CC.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL

compatible.

SDI (Pin 9): Serial Interface Data Input. Data is applied to

SDIfortransfertothedeviceat therisingedgeofSCK. The

LTC2604/LTC2614/LTC2624 accepts input word lengths

V_{OUT A}to V_{OUT D}(Pins 4, 5, 13, 14): DAC Analog Voltage

Outputs. The output range is from REF LO to REF x.

of either 24 or 32 bits.

2604f

8

LTC2604/LTC2614/LTC2624

U

PIN FUNCTIONS

SDO (Pin 10): Serial Interface Data Output. The serial

outputoftheshiftregisterappearsattheSDOpin.Thedata

transferred to the device via the SDI pin is delayed 32 SCK

rising edges before being output at the next falling edge.

This pin is used for daisy-chain operation.

CLR(Pin11):AsynchronousClearInput.Alogiclowatthis

level-triggered input clears all registers and causes the

DAC voltage outputs to drop to 0V. CMOS and TTL-

compatible.

V_CC(Pin 16): Supply Voltage Input. 2.5V ≤ V_CC≤ 5.5V.

W

BLOCK DIAGRA

V

CC

GND

1

REF LO

2

16

REF D

15

REF A

3

V

OUT D

14

DAC D

DAC C

V

OUTA

4

DAC A

DAC B

V

OUT C

13

V

OUTB

5

REF C

12

REF B

6

CLR

11

CONTROL

LOGIC

SDO

10

CS/LD

7

DECODE

SCK

8

SDI

9

32-BIT SHIFT REGISTER

2604 BD

W U

W

TI I G DIAGRA

t

1

t

6

t

4

2

3

SCK

SDI

1

2

3

23

24

t

10

t

7

5

CS/LD

SDO

t

8

2604 F01

Figure 1

2604f

9

LTC2604/LTC2614/LTC2624

U

OPERATIO

Table 1.

COMMAND*

Power-On Reset

TheLTC2604/LTC2614/LTC2624cleartheoutputstozero

scalewhenpowerisfirstapplied,makingsysteminitializa-

tion consistent and repeatable.

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2604/

LTC2614/LTC2624 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground(typ)duringpower-on.SeePower-OnResetGlitch

in the Typical Performance Characteristics section.

No Operation

ADDRESS (n)*

A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

All DACs

*Command and address codes not shown are reserved and should not be used.

Power Supply Sequencing

only be transferred to the device when the CS/LD signal is

low.The rising edge of CS/LD ends the data transfer and

causes the device to carry out the action specified in the

24-bit input word. The complete sequence is shown in

Figure 2a.

The voltage at REF (Pins 3, 6, 12 and 15) should be kept

within the range –0.3V ≤ REF x≤ V_CC+ 0.3V (see Absolute

Maximum Ratings). Particular care should be taken to

observe these limits during power supply turn-on and

turn-off sequences, when the voltage at V_CC(Pin 16) is in

transition.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DACifithadbeeninpower-downmode. Thedatapathand

registers are shown in the block diagram.

Transfer Function

The digital-to-analog transfer function is

k

2^N

V_OUT(IDEAL)

=

[REFx –REFLO]+REFLO

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and REF x is the voltage at REF A,

REF B, REF C and REF D (Pins 3, 6, 12 and 15).

Serial Interface

TheCS/LDinputisleveltriggered. Whenthisinputistaken

low, it acts as a chip-select signal, powering-on the SDI

andSCKbuffersandenablingtheinputshiftregister. Data

(SDI input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded first; then the 4-bit

DAC address, A3-A0; and finally the 16-bit data word. The

data word comprises the 16-, 14- or 12-bit input code,

ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits

(LTC2604, LTC2614andLTC2624respectively). Datacan

While the minimum input word is 24 bits, it may optionally

be extended to 32 bits. To use the 32-bit word width, 8

don’t-care bits are transferred to the device first, followed

by the 24-bit word as just described. Figure 2b shows the

32-bit sequence. The 32-bit word is required for daisy-

chain operation, and is also available to accommodate

microprocessorswhichhaveaminimumwordwidthof16

bits (2 bytes).

2604f

10

LTC2604/LTC2614/LTC2624

U

OPERATIO

INPUT WORD (LTC2604)

COMMAND

ADDRESS

DATA (16 BITS)

A3 A2

A0

D12

D6

D5 D4 D3 D2 D1

D0

C3

C1

A1

D15 D14 D13

MSB

D11 D10 D9 D8

D7

C2

C0

LSB

2604 TBL01

INPUT WORD (LTC2614)

COMMAND

ADDRESS

DATA (14 BITS + 2 DON’T-CARE BITS)

A3 A2

A0

D12

D6

D5 D4 D3 D2 D1

D0

X

C3

C1

A1

D13

D11 D10 D9 D8

D7

C2

C0

MSB

LSB

2604 TBL02

INPUT WORD (LTC2624)

COMMAND

ADDRESS

DATA (12 BITS + 4 DON’T-CARE BITS)

A3 A2

D6

D5 D4 D3 D2 D1

D0

X

C3

C1

A1

D11 D10 D9 D8

MSB

D7

C2

C0

LSB

2604 TBL03

Daisy-Chain Operation

Power-Down Mode

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge.

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer amplifiers, bias circuits and reference inputs are

disabled, and draw essentially zero current. The DAC

outputs are put into a high-impedance state, and the

output pins are passively pulled to ground through indi-

vidual 90k resistors. Input- and DAC-register contents are

not disturbed during power-down.

TheSDOoutputcanbeusedtofacilitatecontrolofmultiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDI and CS/LD). Such a “daisy chain” series is configured

by connecting SDO of each upstream device to SDI of the

next device in the chain. The shift registers of the devices

are thus connected in series, effectively forming a single

inputshiftregisterwhichextendsthroughtheentirechain.

Because of this, the devices can be addressed and con-

trolled individually by simply concatenating their input

words; the first instruction addresses the last device in the

chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

Any channel or combination of channels can be put into

power-down mode by using command 0100_bin combina-

tionwiththeappropriateDACaddress, (n). The16-bitdata

wordisignored. Thesupplycurrentisreducedbyapproxi-

mately 1/4 for each DAC powered down. The effective

resistance at REF x (pins 3, 6, 12 and 15) are at high-

impedance input (typically > 1GΩ) when the correspond-

ing DACs are powered down.

In use, CS/LD is first taken low. Then the concatenated

input data is transferred to the chain, using SDI of the first

device as the data input. When the data transfer is com-

plete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the no-operation command

(1111) for the other devices in the chain.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state is

poweredupandupdated,normalsettlingisdelayed.Ifless

than four DACs are in a powered-down state prior to the

updatecommand,thepower-updelaytimeis5µs.Ifonthe

2604f

11

LTC2604/LTC2614/LTC2624

U

OPERATIO

otherhand,allfourDACsarepowereddown,thenthemain

bias generation circuit block has been automatically shut

down in addition to the individual DAC amplifiers and

reference inputs. In this case, the power up delay time is

12µs (for V_CC= 5V) or 30µs (for V_CC= 3V).

The PC board should have separate areas for the analog

anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Voltage Outputs

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continu-

ous and uninterrupted plane, except for necessary lead

pads and vias, with signal traces on another layer.

Each of the four rail-to-rail amplifiers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is ex-

pressed in LSB/mA.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. When a zero scale

DAC output voltage of zero is desired, the REFLO pin

(pin 2) should be connected to system star ground.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The amplifiers’ DC output

impedance is 0.025Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

30Ω typical channel resistance of the output devices; e.g.,

when sinking 1mA, the minimum output voltage = 30Ω •

1mA = 25mV. See the graph Headroom at Rails vs Output

Current in the Typical Performance Characteristics

section.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur near full scale

when the REF pins are tied to V_CC. If REF x = V_CCand the

DAC full-scale error (FSE) is positive, the output for the

highest codes limits at V_CCas shown in Figure 3c. No full-

scale limiting can occur if REF x is less than V_CC– FSE.

The amplifiers are stable driving capacitive loads of up to

1000pF.

Board Layout

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by keeping

“signal” and “power” grounds separate.

2604f

12

LTC2604/LTC2614/LTC2624

U

OPERATIO

2604f

13

LTC2604/LTC2614/LTC2624

U

OPERATIO

POSITIVE

FSE

V

= V

CC

REF

V

REF

= V

CC

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

(c)

OUTPUT

VOLTAGE

0

32, 768

65, 535

INPUT CODE

(a)

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

2604 F03

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect

of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

2604f

14

LTC2604/LTC2614/LTC2624

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2604f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC2604/LTC2614/LTC2624

U

TYPICAL APPLICATIO

5V

1k

10k

0.1µF

10k

20Ω

10k

49.9Ω

0.01µF

70MHz IN

OUT

10pF

20pF

47pF

ZC830

49.9Ω

ZC830

DAC A

DAC C

DAC B

DAC D

OPTIONAL

20k

CS/LD

SCK

SDI

0.1µF

LTC2604

5V

LO

2.74k

1%

2.74k

1%

100k

2.74k

1%

2.74k

1%

90°

I + Q

MODULATOR

Q INPUT

I INPUT

5V

2.74k

1%

2.74k

1%

0°

2.74k

1%

2.74k

1%

RF

2604 F04

*ZETEX

(516) 543-7100

Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and

DAC D to Trim for Minimum LO Feedthrough in a Mixer.

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458: V = 4.5V to 5.5V, V

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

= 0V to 4.096V

OUT

CC

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V

DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1821

Single 16-Bit V

DAC with Serial Interface in SO-8

V

CC

OUT

Parrallel 5V/3V 16-Bit V

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 8/10-Bit V

DAC in 16-Pin Narrow SSOP

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2µs for 10V Step

250µA per DAC, 2.5V to 5.5V Supply Range

300µA per DAC, 2.5V to 5.5V Supply Range

LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP

LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP

2604f

LT/TP 0304 1K • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

LINEAR TECHNOLOGY CORPORATION 2004

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2624CGN
厂家：	Linear
描述：	Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP 四通道16位轨至轨数模转换器采用16引脚SSOP 转换器数模转换器光电二极管
文件：	总16页 (文件大小：389K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2624CGN [Linear]

相关型号：

LTC2624CGN#PBF

LTC2624CGN#TR

LTC2624CGN-1#PBF

LTC2624CGN-1#TRPBF

LTC2624IGN

LTC2624IGN-1#PBF

LTC2624IGN-1#TRPBF

LTC2624_15

LTC2625

LTC2625CGN

LTC2625CGN#PBF

LTC2625CGN#TR