LTC2626CDD-1#TR [Linear]
暂无描述;LTC2606/LTC2616/LTC2626
16-/14-/12-Bit Rail-to-Rail DACs
with I2C Interface
U
DESCRIPTIO
FEATURES
The LTC®2606/LTC2616/LTC2626 are single 16-, 14-
and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs
in a 10-lead DFN package. They have built-in high perfor-
mance output buffers and are guaranteed monotonic.
■
Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits
■
Guaranteed 16-Bit Monotonic Over Temperature
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
Thepartsusea2-wire, I2Ccompatibleserialinterface. The
LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
■
27 Selectable Addresses
400kHz I2CTM Interface
■
■
Wide 2.7V to 5.5V Supply Range
■
Low Power Operation: 270µA at 3V
■
Power Down to 1µA, Max
■
High Rail-to-Rail Output Drive (±15mA, Min)
■
Double-Buffered Data Latches
Asynchronous DAC Update Pin
■
■
LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale
The LTC2606/LTC2616/LTC2626 incorporate a power-on
resetcircuit.Duringpower-up,thevoltageoutputsriseless
than10mVabovezeroscale;andafterpower-up, theystay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.
■
LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset
to Midscale
■
Tiny (3mm × 3mUm) 10-Lead DFN Package
APPLICATIO S
■
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
■
■
W
BLOCK DIAGRA
9
6
Differential Nonlinearity
(LTC2606)
V
REF
CC
SCL
1.0
V
V
V
= 5V
REF
3
2
OUT
CC
INPUT
REGISTER
DAC
REGISTER
16-BIT DAC
7
0.8
0.6
= 4.096V
2
I C
INTERFACE
0.4
SDA
0.2
CONTROL
LOGIC
0
–0.2
–0.4
–0.6
–0.8
–1.0
CA0
CA1
CA2
4
5
1
2
I C
ADDRESS
DECODE
0
16384
32768
CODE
49152
65535
LDAC
10
GND
8
2606 G02
2606 BD
26061626f
1
LTC2606/LTC2616/LTC2626
W W W
U
(Note 1)
ABSOLUTE AXI U RATI GS
Any Pin to GND........................................... –0.3V to 6V
Any Pin to VCC .............................................–6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ –65°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C
Operating Temperature Range:
LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I.. –40°C to 85°C
W U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
CA2
SDA
SCL
CA0
CA1
1
2
3
4
5
10 LDAC
LTC2616CDD
LTC2616IDD
LTC2606CDD
LTC2606IDD
LTC2626CDD
LTC2626IDD
9
8
7
6
V
CC
11
GND
V
OUT
LTC2606CDD-1
LTC2606IDD-1
LTC2616CDD-1
LTC2616IDD-1
LTC2626CDD-1
LTC2626IDD-1
REF
DD PACKAGE
DD PART MARKING
LAJX
DD PART MARKING
LBPQ
DD PART MARKING
LBPS
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
LAJW
LBPR
LBPT
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
●
●
●
●
12
12
14
14
16
16
Bits
Bits
LSB
LSB
Monotonicity
(Note 2)
(Note 2)
DNL
INL
Differential Nonlinearity (Note 2)
±0.5
±4
±1
±1
Integral Nonlinearity
Load Regulation
±1
±4 ±16
±14 ±64
V
= V = 5V, Midscale
CC
OUT
OUT
REF
I
I
= 0mA to 15mA Sourcing
= 0mA to 15mA Sinking
●
●
0.025 0.125
0.05 0.125
0.1
0.2
0.5
0.5
0.5
0.7
2
2
LSB/mA
LSB/mA
V
= V = 2.7V, Midscale
OUT
OUT
REF
I
I
CC
= 0mA to 7.5mA Sourcing
= 0mA to 7.5mA Sinking
●
●
0.05 0.25
0.1 0.25
0.2
0.4
1
1
0.9
1.5
4
4
LSB/mA
LSB/mA
ZSE
Zero-Scale Error
Offset Error
Code = 0
(Note 5)
●
●
1
9
1
9
1
9
mV
mV
V
±1
±5
±9
±1
±5
±9
±1
±5
±9
OS
V
Temperature
µV/°C
OS
Coefficient
GE
Gain Error
●
±0.1 ±0.7
±8.5
±0.1 ±0.7
±8.5
±0.1 ±0.7
±8.5
%FSR
Gain Temperature
Coefficient
ppm/°C
26061626f
2
LTC2606/LTC2616/LTC2626
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
unless otherwise noted. (Note 11)
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
SYMBOL PARAMETER
PSR Power Supply Rejection
CONDITIONS
MIN
TYP
MAX
UNITS
V
= ±10%
–81
dB
CC
R
OUT
DC Output Impedance
V
V
= V = 5V, Midscale; –15mA ≤ I ≤ 15mA
OUT
●
●
0.05
0.06
0.15
0.15
Ω
Ω
REF
REF
CC
= V = 2.7V, Midscale; –7.5mA ≤ I
≤ 7.5mA
CC
OUT
I
Short-Circuit Output Current
V
= 5.5V, V = 5.5V
CC REF
SC
Code: Zero Scale; Forcing Output to V
●
●
15
15
34
36
60
60
mA
mA
CC
Code: Full Scale; Forcing Output to GND
V
= 2.7V, V = 2.7V
CC
REF
Code: Zero Scale; Forcing Output to V
●
●
7.5
7.5
22
29
50
50
mA
mA
CC
Code: Full Scale; Forcing Output to GND
Reference Input
Input Voltage Range
●
●
0
V
V
kΩ
pF
CC
Resistance
Normal Mode
88
124
15
160
Capacitance
I
Reference Current, Power Down Mode DAC Powered Down
●
0.001
1
µA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
2.7
5.5
V
CC
I
V
V
= 5V (Note 3)
= 3V (Note 3)
●
●
●
●
0.340
0.27
0.35
0.10
0.5
0.4
1
mA
mA
µA
CC
CC
CC
DAC Powered Down (Note 3) V = 5V
CC
CC
DAC Powered Down (Note 3) V = 3V
1
µA
Digital I/O (Note 11)
V
V
V
V
V
V
Low Level Input Voltage
(SDA and SCL)
●
●
–0.5
0.3V
V
V
IL
CC
High Level Input Voltage
(SDA and SCL)
(Note 8)
0.7V
CC
IH
Low Level Input Voltage (LDAC)
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
●
●
0.8
0.6
V
V
IL(LDAC)
IH(LDAC)
IL(CAn)
IH(CAn)
CC
CC
High Level Input Voltage (LDAC)
V
V
= 2.7V to 5.5V
= 2.7V to 3.6V
●
●
2.4
2.0
V
V
CC
CC
Low Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
See Test Circuit 1
See Test Circuit 2
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
●
●
●
●
●
0.15V
V
CC
High Level Input Voltage on CAn
(n = 0, 1, 2)
0.85V
V
CC
R
R
R
Resistance from CAn (n = 0, 1, 2)
10
10
kΩ
kΩ
MΩ
INH
INL
INF
OL
to V to Set CAn = V
CC
CC
Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
Resistance from CAn (n = 0, 1, 2)
2
0
to V or GND to Set CAn = Float
CC
V
Low Level Output Voltage
Output Fall Time
●
●
0.4
V
t
t
I
V = V
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 9)
B
Pulse Width of Spikes Suppressed
by Input Filter
●
0
50
ns
SP
Input Leakage
0.1V ≤ V ≤ 0.9V
CC
●
●
●
●
1
µA
pF
pF
pF
IN
CC
IN
C
C
C
I/O Pin Capacitance
10
IN
Capacitive Load for Each Bus Line
400
10
B
External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
CAX
26061626f
3
LTC2606/LTC2616/LTC2626
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX
SYMBOL PARAMETER
AC Performance
CONDITIONS
UNITS
t
Settling Time (Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
S
Settling Time for 1LSB Step
(Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
0.75
1000
12
0.75
1000
12
0.75
1000
12
V/µs
pF
At Midscale Transition
nV • s
kHz
Multiplying Bandwidth
180
180
180
e
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
n
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µV
P-P
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
= 2.7V to 5.5V
f
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
●
●
●
●
●
●
●
●
●
●
●
●
0
0.6
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
HD(STA)
LOW
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
1.3
0.6
0.6
0
0.9
Data Set-Up Time
100
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
(Note 9)
(Note 9)
20 + 0.1C
20 + 0.1C
0.6
300
300
B
B
f
SU(STO)
BUF
1.3
Falling Edge of 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
400
1
t
LDAC Low Pulse Width
●
20
ns
2
Note 6: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
Note 1: Absolute maximum ratings are those values beyond which the life
CC
REF
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
of a device may be impaired.
Note 7: V = 5V, V = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 2: Linearity and monotonicity are defined from code k to code
CC
REF
L
N
N
2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),
L
L
REF
rounded to the nearest whole code. For V = 4.096V and N = 16, k =
256 and linearity is defined from code 256 to code 65,535.
REF
L
Note 8: Maximum V = V + 0.5V
IH
CC(MAX)
Note 9: C = capacitance of one bus line in pF.
B
Note 3: Digital inputs at 0V or V
.
CC
Note 10: All values refer to V
and V
levels.
IH(MIN)
IL(MAX)
Note 4: Guaranteed by design and not production tested.
Note 11: These specifications apply to LTC2606/LTC2606-1,
LTC2616/LTC2616-1, LTC2626/LTC2626-1.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full scale.
26061626f
4
LTC2606/LTC2616/LTC2626
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2606
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.8
32
24
32
24
V
V
= 5V
REF
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
CC
= 4.096V
= 4.096V
= 4.096V
0.6
16
16
0.4
INL (POS)
INL (NEG)
8
8
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–8
–16
–24
–32
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
2606 G02
2606 G01
2606 G03
DNL vs Temperature
INL vs VREF
DNL vs VREF
1.0
0.8
32
24
1.5
1.0
V
V
= 5V
REF
V
CC
= 5.5V
V
= 5.5V
CC
CC
= 4.096V
0.6
16
0.4
0.5
INL (POS)
INL (NEG)
DNL (POS)
DNL (NEG)
8
DNL (POS)
DNL (NEG)
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–16
–24
–32
–0.5
–1.0
–1.5
–50 –30 –10 10
30
50
70
90
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
V
REF
(V)
V
(V)
REF
2606 G04
2606 G05
2606 G06
Settling to ±1LSB
Settling of Full-Scale Step
V
V
OUT
100µV/DIV
OUT
100µV/DIV
12.3µs
9.7µs
9TH CLOCK
OF 3RD DATA
BYTE
9TH CLOCK OF
3RD DATA BYTE
SCL
2V/DIV
SCR
2V/DIV
2606 G07
2606 G08
2µs/DIV
5µs/DIV
V
= 5V, V
= 4.096V
REF
SETTLING TO ±1LSB
CC
1/4-SCALE TO 3/4-SCALE STEP
= 2k, C = 200pF
V
= 5V, V
= 4.096V
CC
REF
R
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
L
L
AVERAGE OF 2048 EVENTS
26061626f
5
LTC2606/LTC2616/LTC2626
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2616
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to ±1LSB
8
6
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
4
0.4
V
OUT
2
100µV/DIV
0.2
0
0
9TH CLOCK
OF 3RD DATA
BYTE
SCL
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
8.9µs
2606 G11
2µs/DIV
V
= 5V, V
= 4.096V
REF
CC
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
L
L
0
4096
8192
CODE
12288
16383
0
4096
8192
CODE
12288
16383
AVERAGE OF 2048 EVENTS
2606 G09
2606 G10
LTC2626
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to ±1LSB
2.0
1.5
1.0
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
0.8
0.6
= 4.096V
1.0
6.8µs
0.4
V
OUT
0.5
1mV/DIV
0.2
0
0
9TH CLOCK
OF 3RD DATA
BYTE
SCL
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
2606 G14
2µs/DIV
= 4.096V
V
= 5V, V
REF
CC
1/4-SCALE TO 3/4-SCALE STEP
= 2k, C = 200pF
R
L
L
0
1024
2048
CODE
3072
4095
0
1024
2048
CODE
3072
4095
AVERAGE OF 2048 EVENTS
2606 G12
2606 G13
26061626f
6
LTC2606/LTC2616/LTC2626
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Current Limiting
Load Regulation
Offset Error vs Temperature
1.0
0.8
0.10
0.08
3
2
CODE = MIDSCALE
CODE = MIDSCALE
V
V
= V = 5V
CC
REF
REF
0.6
0.06
= V = 3V
CC
0.4
0.04
1
0.2
0.02
0
0
0
V
REF
= V = 5V
CC
–0.2
–0.4
–0.6
–0.8
–1.0
–0.02
–0.04
–0.06
–0.08
–0.10
V
= V = 3V
CC
REF
REF
–1
–2
–3
V = V = 3V
REF CC
V
= V = 5V
CC
–35 –25 –15 –5
5
15
25
35
–40 –30 –20 –10
0
10 20 30 40
–50 –30 –10 10
30
50
70
90
I
(mA)
I
(mA)
OUT
TEMPERATURE (°C)
OUT
2606 G18
2606 G17
2606 G19
Zero-Scale Error vs Temperature
Gain Error vs Temperature
Offset Error vs VCC
0.4
0.3
3
2
3
2.5
2.0
1.5
1.0
0.5
0
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –30 –10 10
30
50
70
90
2.5
3
3.5
4
4.5
5
5.5
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
CC
2606 G21
2606 G22
2606 G20
Gain Error vs VCC
ICC Shutdown vs VCC
0.4
0.3
450
400
350
300
250
200
150
100
50
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
(V)
CC
CC
2606 G23
2606 G24
26061626f
7
LTC2606/LTC2616/LTC2626
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Large-Signal Response
Midscale Glitch Impulse
Power-On Reset Glitch
V
OUT
V
CC
1V/DIV
10mV/DIV
V
OUT
0.5V/DIV
9TH CLOCK
OF 3RD DATA
BYTE
4mV PEAK
SCL
2V/DIV
V
= V = 5V
CC
REF
V
OUT
10mV/DIV
1/4-SCALE TO 3/4-SCALE
2606 G26
2606 G27
2.5µs/DIV
2606 G25
2.5µs/DIV
250µs/DIV
Headroom at Rails
vs Output Current
Power-On Reset to Midscale
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
CC
REF
5V SOURCING
3V SOURCING
1V/DIV
V
CC
5V SINKING
3V SINKING
V
OUT
2606 G29
500µs/DIV
0
1
2
3
4
5
6
7
8
9
10
I
(mA)
OUT
2606 G28
Supply Current vs Logic Voltage
Supply Current vs Logic Voltage
650
600
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
= 5V
V
= 5V
CC
CC
SWEEP LDAC
SWEEP SCL AND
SDA 0V TO V
0V TO V
CC
CC
AND V TO 0V
CC
550
HYSTERESIS
370mV
500
450
400
350
300
– 250
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC VOLTAGE (V)
LOGIC VOLTAGE (V)
2606 G30
2606 G31
26061626f
8
LTC2606/LTC2616/LTC2626
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
V
OUT
10µV/DIV
V
V
V
= 5V
CC
(DC) = 2V
REF
REF
0
1
2
3
4
5
6
7
8
9
10
(AC) = 0.2V
P-P
SECONDS
CODE = FULL SCALE
2606 G33
1k
10k
100k
1M
FREQUENCY (Hz)
2606 G32
Short-Circuit Output Current vs
VOUT (Sourcing)
Short-Circuit Output Current vs
VOUT (Sinking)
0mA
0mA
V
V
= 5.5V
= 5.6V
V
V
= 5.5V
= 5.6V
CC
REF
CC
REF
CODE = 0
SWEPT 0V TO V
CODE = FULL SCALE
V
V
OUT
SWEPT V TO 0V
OUT
CC
CC
1V/DIV
2606 G18
1V/DIV
2606 G19
26061626f
9
LTC2606/LTC2616/LTC2626
U
U
U
PIN FUNCTIONS
CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND
orleaveitfloatingtoselectanI2Cslaveaddressforthepart
(Table 1).
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT (Pin 7): DAC Analog Voltage Output. The output
range is 0V to VREF
.
SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to VCC.
GND (Pin 8): Analog Ground.
VCC (Pin 9): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
LDAC (Pin 10): Asynchronous DAC Update. A falling edge
onthisinputafterfourbyteshavebeenwrittenintothepart
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part does not update the DAC output.
Software power-down is disabled when LDAC is low.
SCL (Pin 3): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedancepinrequiresapull-upresistororcurrentsource
to VCC.
CA0 (Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND
orleaveitfloatingtoselectanI2Cslaveaddressforthepart
(Table 1).
Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.
CA1 (Pin 5): Chip Address Bit 1. Tie this pin to VCC, GND
orleaveitfloatingtoselectanI2Cslaveaddressforthepart
(Table 1).
26061626f
10
LTC2606/LTC2616/LTC2626
W
BLOCK DIAGRA
9
6
V
CC
REF
SCL
3
V
OUT
INPUT
REGISTER
DAC
REGISTER
16-BIT DAC
7
2
I C
INTERFACE
SDA
2
CONTROL
LOGIC
CA0
4
2
I C
CA1
5
ADDRESS
DECODE
CA2
1
LDAC
10
GND
8
2606 BD
TEST CIRCUITS
Test Circuit 1
Test Circuit 2
V
DD
R /R /R
INH INL INF
100Ω
CAn
CAn
V
/V
IH(CAn) IL(CAn)
GND
2606 TC
26061626f
11
LTC2606/LTC2616/LTC2626
W U
W
TI I G DIAGRA S
26061626f
12
LTC2606/LTC2616/LTC2626
U
OPERATIO
Power-On Reset
power supply and can be obtained from the I2C specifica-
tions. For an I2C bus operating in the fast mode, an active
pull-up will be necessary if the bus capacitance is greater
than 200pF.
The LTC2606/LTC2616/LTC2626 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2606-1/
LTC2616-1/LTC2626-1setthevoltageoutputstomidscale
when power is first applied.
The LTC2606/LTC2616/LTC2626 are receive-only (slave)
devices. The master can write to the LTC2606/LTC2616/
LTC2626. The LTC2606/LTC2616/LTC2626 do not re-
spond to a read from the master.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2606/
LTC2616/LTC2626 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground(typ)duringpower-on.SeePower-OnResetGlitch
in the Typical Performance Characteristics section.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
ASTARTconditionisgeneratedbytransitioningSDAfrom
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generatedbytransitioningSDAfromlowtohighwhileSCL
is high. The bus is then free for communication with
another I2C device.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 9) is in transition.
Acknowledge
TheAcknowledgesignalisusedforhandshakingbetween
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remainsastableLOWduringtheHIGHperiodofthisclock
pulse. The LTC2606/LTC2616/LTC2626 respond to a
write by a master in this manner. The LTC2606/LTC2616/
LTC2626 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).
Transfer Function
The digital-to-analog transfer function is:
k
2
⎛
⎜
⎝
⎞
⎟
⎠
VOUT(IDEAL)
=
V
REF
N
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Digital Interface
TheLTC2606/LTC2616/LTC2626communicatewithahost
using the standard 2-wire I2C interface. The Timing Dia-
grams (Figures 1 and 2) show the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or float. This results in
27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
26061626f
13
LTC2606/LTC2616/LTC2626
U
OPERATIO
Table 1. Slave Address Map
Write Word Protocol
CA2
GND
CA1
GND
CA0
GND
A6 A5 A4 A3 A2 A1 A0
The master initiates communication with the LTC2606/
LTC2616/LTC2626withaSTARTconditionanda7-bitslave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
addressoftheparts(setbyCA0,CA1andCA2)ortheglobal
address.Themasterthentransmitsthreebytesofdata.The
LTC2606/LTC2616/LTC2626 acknowledges each byte of
databypullingtheSDAlinelowatthe9thclockofeachdata
byte transmission. After receiving three complete bytes of
data, the LTC2606/LTC2616/LTC2626 executes the com-
mand specified in the 24-bit input word.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
GND
FLOAT
GND
GND
V
CC
GND
FLOAT
FLOAT
FLOAT
GND
GND
FLOAT
GND
V
CC
GND
V
V
V
GND
CC
CC
CC
GND
FLOAT
GND
V
CC
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
FLOAT
GND
V
CC
FLOAT
FLOAT
FLOAT
GND
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
FLOAT
V
CC
V
GND
CC
V
V
FLOAT
CC
CC
TheformatofthethreedatabytesisshowninFigure3.The
first byte of the input word consists of the 4-bit command
and four don’t care bits. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626
respectively). AtypicalLTC2606writetransactionisshown
in Figure 4.
V
CC
V
V
V
V
V
V
V
V
V
GND
GND
GND
CC
CC
CC
CC
CC
CC
CC
CC
CC
FLOAT
GND
V
CC
FLOAT
FLOAT
FLOAT
GND
FLOAT
V
CC
V
V
V
GND
CC
CC
CC
Thecommandassignments(C3-C0)areshowninTable2.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an ana-
log voltage at the DAC output. The update operation also
powersuptheDACifithadbeeninpower-downmode.The
data path and registers are shown in the Block Diagram.
FLOAT
V
CC
GLOBAL ADDRESS
Inadditiontotheaddressselectedbytheaddresspins, the
parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
Power-Down Mode
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.
For power-constrained applications, power-down mode
canbeusedtoreducethesupplycurrentwhenevertheDAC
output is not needed. When in power-down, the buffer
amplifier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into
26061626f
14
LTC2606/LTC2616/LTC2626
U
OPERATIO
Write Word Protocol for LTC2606/LTC2616/LTC1626
W
A
1ST DATA BYTE
A
2ND DATA BYTE
A
3RD DATA BYTE
A
P
S
SLAVE ADDRESS
INPUT WORD
Input Word (LTC2606)
C3
C1
X
X
X
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2ND DATA BYTE 3RD DATA BYTE
C2
C0
X
X
X
1ST DATA BYTE
Input Word (LTC2616)
C3
C1
X
X
X
X
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2ND DATA BYTE 3RD DATA BYTE
X
X
X
C2
C0
1ST DATA BYTE
Input Word (LTC2626)
C3
C1
X
X
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
C2
C0
2606 F03
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
Figure 3
Table 2
COMMAND*
C3 C2 C1 C0
automatically shut down in addition to the DAC amplifier
and reference input and so the power up delay time is
12µs (for VCC = 5V) or 30µs (for VCC = 3V)
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
Write to Input Register
Update (Power Up) DAC Register
Write to and Update (Power Up)
Power Down
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC register with
the contents of the input register. Asynchronous update is
disabledwhentheinputwordisbeingclockedintothepart.
No Operation
*Command codes not shown are reserved and should not be used.
a high impedance state, and the output pin is passively
pulled to ground through 90k resistors. Input- and DAC-
register contents are not disturbed during power-down.
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.
The DAC channel can be put into power-down mode by
using command 0100b. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective
resistance at REF becomes a high impedance input
(typically > 1GΩ).
If the input word is being written to the part, a low going
pulseontheLDACpinbeforethecompletionofthreebytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog-
nized, the command specified in the 24-bit word just
transferred is executed and the DAC output is updated.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as de-
scribed in the next section. The DAC is powered up as its
voltage output is updated. When the DAC in powered-
down state is powered up and updated, normal settling is
delayed. The main bias generation circuit block has been
The DAC is powered up when LDAC is taken low, indepen-
dent of any activity on the I2C bus.
If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down com-
mand that was specified in the input word.
26061626f
15
LTC2606/LTC2616/LTC2626
U
OPERATIO
Voltage Output
from sensitive analog signals and facilitates the use of
separate digital and analog ground planes which have
minimalcapacitiveandresistiveinteractionwitheachother.
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at 3V).
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.050Ω when driving a load well away from
the rails.
The GND pin of the part should be connected to analog
ground.ResistancefromtheGNDpintosystemstarground
should be as low as possible. Resistance here will add
directly to the effective DC output impedance of the device
(typically 0.050Ω). Note that the LTC2606/LTC2616/
LTC2626arenomoresusceptibletotheseeffectsthanother
partsoftheirtype;onthecontrary,theyallowlayout-based
performance improvements to shine rather than limiting
attainableperformancewithexcessiveinternalresistance.
When drawing a load current from either rail, the output
voltageheadroomwithrespecttothatrailislimitedbythe
25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteris-
tics section.
Rail-to-Rail Output Considerations
The amplifier is stable driving capacitive loads of up to
1000pF.
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Board Layout
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 5c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
The excellent load regulation performance is achieved in
part by keeping “signal” and “power” grounds separated
internally and by reducing shared internal resistance.
The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
ThePCboardshouldhaveseparateareasfortheanalogand
digitalsectionsofthecircuit.Thiskeepsdigitalsignalsaway
26061626f
16
LTC2606/LTC2616/LTC2626
U
OPERATIO
26061626f
17
LTC2606/LTC2616/LTC2626
U
OPERATIO
26061626f
18
LTC2606/LTC2616/LTC2626
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 5)
(DD10) DFN 0403
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
26061626f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC2606/LTC2616/LTC2626
U
TYPICAL APPLICATIO
Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters
5V
5V
V
REF
1V TO 5V
0.1µF
0.1µF
9
6
2
1
V
CC
10
4
2
3
5
LDAC
CA0
SDA
SCL
CA1
CA2
V
V
FS
CC
REF
SET
9
8
7
10
CA0
I C BUS
CA1
SCK
SDO
CS
100Ω
7.5k
100pF
7
3
SPI BUS
2
LTC2606
V
IN
LTC2421
V
OUT
F
O
1
ZS
GND
6
GND
8
CA2
SET
DAC
OUTPUT
5
2606 TA01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458: V = 4.5V to 5.5V, V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
= 0V to 4.096V
OUT
OUT
CC
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1654
Dual 14-Bit Rail-to-Rail V DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
= 5V(3V), Low Power, Deglitched
OUT
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1821
Single 16-Bit V
DACs with Serial Interface in SO-8
V
CC
OUT
Parallel 5V/3V 16-Bit V
DACs
Low Power, Deglitched, Rail-to-Rail V
OUT
OUT
Octal 10/8-Bit V
DACs in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
Parallel 16-Bit Voltage Output DAC
Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610
LTC2620
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
LTC2601/LTC2611
LTC2621
Single 16-/14-/12-Bit V
DACs in 10-Lead DFN
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
LTC2602/LTC2612
LTC2622
Dual 16-/14-/12-Bit V
DACs in 8-Lead MSOP
DACs in 16-Lead SSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
OUT
Output, SPI Serial Interface
LTC2604/LTC2614
LTC2624
Quad 16-/14-/12-Bit V
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
26061626f
LT/TP 1204 1K • PRINTED IN THE USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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©LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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