LTC2627IDE_技术文档

LTC2607/LTC2617/LTC2627

16-/14-/12-Bit Dual Rail-to-Rail

DACs with I²C Interface

U

FEATURES

DESCRIPTIO

The LTC^®2607/LTC2617/LTC2627 are dual 16-, 14- and

12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a

12-lead DFN package. They have built-in high perfor-

mance output buffers and are guaranteed monotonic.

■

Smallest Pin-Compatible Dual DACs:

LTC2607: 16 Bits

LTC2617: 14 Bits

LTC2627: 12 Bits

■

Guaranteed Monotonic Over Temperature

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply,

voltage-output DACs.

Thepartsusea2-wire, I²Ccompatibleserialinterface. The

LTC2607/LTC2617/LTC2627 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). An asynchronous DAC update pin (LDAC) is

also included.

■

27 Selectable Addresses

400kHz I²C^TMInterface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 260µA per DAC at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Ultralow Crosstalk (30µV)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2607/LTC2617/LTC2627: Power-On Reset to

The LTC2607/LTC2617/LTC2627 incorporate a power-on

resetcircuit.Duringpower-up,thevoltageoutputsriseless

than10mVabovezeroscale;andafterpower-up, theystay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2607-1/LTC2617-1/

LTC2627-1 to midscale. The voltage outputs stay at

midscale until a valid write and update takes place.

Zero Scale

■

LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset

to Midscale

■

^{Tiny (3mm × 4m}U^{m) 12-Lead DFN Package}

APPLICATIO S

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5396245 and 6891433. Patent Pending

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

■

W

BLOCK DIAGRA

REFLO

11

GND

10

REF

9

V

CC

8

Differential Nonlinearity

(LTC2607)

1.0

0.8

V

OUTA

V

OUTB

12

12-/14-/16-BIT DAC

7

V

= 5V

CC

= 4.096V

REF

0.6

0.4

DAC REGISTER

0.2

0

INPUT REGISTER

–0.2

–0.4

–0.6

–0.8

–1.0

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

0

16384

32768

CODE

49152

65535

2607 G02

1

2

3

4

5

6

LDAC

CA0

CA1

SCL

SDA

CA2

2607 BD

26071727f

1

LTC2607/LTC2617/LTC2627

W W W

U

(Note 1)

ABSOLUTE AXI U RATI GS

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V_CC........................................................ –6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ –65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

Operating Temperature Range:

LTC2607C/LTC2617C/LTC2627C

LTC2607C-1/LTC2617C-1/LTC2627C-1 ... 0°C to 70°C

LTC2607I/LTC2617I/LTC2627I

LTC2607I-1/LTC2617I-1/LTC2627I-1.. –40°C to 85°C

W U

/O

PACKAGE RDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

LTC2607CDE

LTC2607IDE

LTC2607CDE-1

LTC2607IDE-1

ORDER PART

NUMBER

ORDER PART

NUMBER

CA0

CA1

1

2

3

4

5

6

12

V

OUTA

11 REFLO

10 GND

LTC2617CDE

LTC2617IDE

LTC2627CDE

LTC2627IDE

13

LDAC

SCL

9

8

7

REF

LTC2617CDE-1

LTC2617IDE-1

LTC2627CDE-1

LTC2627IDE-1

SDA

CA2

V

CC

OUTB

DE12 PART MARKING*

DE12 PACKAGE

12-LEAD (4mm × 3mm) PLASTIC DFN

2607

26071

2617

26171

2626

26271

T

= 125°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 13) IS GND

MUST BE SOLDERED TO PCB

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

*The temperature grade is identified by a label on the shipping container.

ELECTRICAL CHARACTERISTICS ^The

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. REF = 4.096V (V = 5V), REF = 2.048V (V = 2.7V), REFLO = 0V,

A

CC

V

OUT

unloaded, unless otherwise noted.

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

UNITS

●

12

14

16

Bits

LSB

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

±0.5

±1

Integral Nonlinearity

Load Regulation

± 1.5 ±4

±5 ± 16

± 19 ± 64

V

= V = 5V, Midscale

CC

OUT

REF

I

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

●

0.02 0.125

0.03 0.125

0.1

0.5

0.35

0.42

2

LSB/mA

V

= V = 2.7V, Midscale

OUT

REF

I

CC

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

●

0.04 0.25

0.05 0.25

0.2

1

0.7

0.8

4

LSB/mA

ZSE

Zero-Scale Error

Offset Error

Code = 0

(Note 6)

●

1

9

1

9

1

9

mV

V

±1

±7

±9

±1

±7

±9

±1

±7

±9

OS

V

Temperature

µV/°C

OS

Coefficient

GE

Gain Error

●

±0.15 ±0.7

±4

±0.15 ±0.7

±4

±0.15 ±0.7

±4

%FSR

Gain Temperature

Coefficient

ppm/°C

26071727f

2

LTC2607/LTC2617/LTC2627

The

●

denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T = 25°C. REF = 4.096V (V = 5V), REF = 2.048V (V = 2.7V), REFLO = 0V,

A

CC

V

unloaded, unless otherwise noted.

OUT

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

±10%

–80

dB

CC

R

OUT

DC Output Impedance

= V = 5V, Midscale;

REF CC

–15mA ≤ I

≤ 15mA

●

0.032

0.035

0.15

Ω

OUT

V

= V = 2.7V, Midscale;

CC

REF

–7.5mA ≤ I

≤ 7.5mA

OUT

DC Crosstalk (Note 4)

Due to Full Scale Output Change (Note 5)

Due to Load Current Change

Due to Powering Down (per channel)

±4

±3

±30

µV

µV/mA

µV

I

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

CC REF

SC

Code: Zero Scale; Forcing Output to V

●

15

36

37

60

mA

CC

Code: Full Scale; Forcing Output to GND

V

= 2.7V, V = 2.7V

CC

REF

Code: Zero Scale; Forcing Output to V

●

7.5

22

30

50

mA

CC

Code: Full Scale; Forcing Output to GND

Reference Input

Input Voltage Range

●

0

44

V

80

V

kΩ

pF

CC

Resistance

Capacitance

Normal Mode

64

30

I

Reference Current, Power Down Mode

DAC Powered Down

For Specified Performance

●

0.001

1

µA

REF

Power Supply

V

I

Positive Supply Voltage

Supply Current

2.7

5.5

V

CC

V

= 5V (Note 3)

= 3V (Note 3)

●

0.66

0.52

0.4

1.3

1

mA

µA

CC

DAC Powered Down (Note 3) V = 5V

CC

DAC Powered Down (Note 3) V = 3V

0.10

µA

Digital I/O (Note 11)

V

Low Level Input Voltage (SDA and SCL)

High Level Input Voltage (SDA and SCL)

Low Level Input Voltage (LDAC)

●

0.3V

V

IL

CC

0.7V

IH

CC

V

= 4.5V to 5.5V

= 2.7V to 5.5V

●

0.8

0.6

IL(LDAC)

CC

V

R

High Level Input Voltage (LDAC)

V

= 2.7V to 5.5V

= 2.7V to 3.6V

●

2.4

2.0

V

IH(LDAC)

IL(CAn)

IH(CAn)

CC

Low Level Input Voltage on CAn

(n = 0, 1, 2)

High Level Input Voltage on CAn (n = 0, 1, 2)

See Test Circuit 1

●

0.15V

CC

See Test Circuit 1

See Test Circuit 2

●

0.85V

V

kΩ

CC

Resistance from CAn (n = 0, 1, 2)

10

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1, 2)

to GND to Set CAn = GND

See Test Circuit 2

Sink Current = 3mA

●

kΩ

Resistance from CAn (n = 0, 1, 2)

2

0

MΩ

to V or GND to Set CAn = Float

CC

V

Low Level Output Voltage

Output Fall Time

●

0.4

250

V

ns

t

V = V

to V = V

,

20 + 0.1C

OF

O

B

IH(MIN)

O

IL(MAX)

B

C = 10pF to 400pF (Note 9)

t

I

C

Pulse Width of Spikes Suppressed by Input Filter

Input Leakage

I/O Pin Capacitance

Capacitive Load for Each Bus Line

External Capacitive Load on Address

Pins CAn (n = 0, 1, 2)

●

0

50

1

10

400

10

ns

µA

pF

SP

IN

0.1V ≤ V ≤ 0.9V

Note 12

CC

IN

CC

IN

B

CAX

26071727f

3

LTC2607/LTC2617/LTC2627

The

●

denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T = 25°C. REF = 4.096V (V = 5V), REF = 2.048V (V = 2.7V), REFLO = 0V,

A

CC

V

OUT

unloaded, unless otherwise noted.

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

SYMBOL PARAMETER

AC Performance

CONDITIONS

UNITS

t

Settling Time (Note 7)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

7

9

7

9

10

µs

S

Settling Time for 1LSB Step

(Note 8)

±0.024% (±1LSB at 12 Bits)

±0.006% (±1LSB at 14 Bits)

±0.0015% (±1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

0.8

1000

12

0.8

1000

12

0.8

1000

12

V/µs

pF

At Midscale Transition

nV • s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise Density At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

µV

P-P

W U

TI I G CHARACTERISTICS

The

●

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (See Figure 1) (Notes 10, 11)

A

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

= 2.7V to 5.5V

f

t

SCL Clock Frequency

●

0

0.6

400

kHz

µs

ns

µs

ns

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

HD(STA)

LOW

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

1.3

0.6

0

0.9

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-Up Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

(Note 9)

20 + 0.1C

0.6

300

B

f

B

SU(STO)

BUF

1.3

Falling Edge of 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition

400

1

t

LDAC Low Pulse Width

●

20

ns

2

Note 1: Absolute maximum ratings are those values beyond which the life of

Note 6: Inferred from measurement at code k (Note 2) and at full scale.

L

a device may be impaired.

Note 7: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and

CC

REF

Note 2: Linearity and monotonicity are defined from code k to code

3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

L

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

rounded to the nearest whole code. For V = 4.096V and N = 16, k = 256

L

REF

L

Note 8: V = 5V, V = 4.096V. DAC is stepped ±1LSB between half scale

CC

REF

and half scale – 1. Load is 2k in parallel with 200pF to GND.

and linearity is defined from code 256 to code 65,535.

Note 9: C = capacitance of one bus line in pF.

B

Note 3: SDA, SCL and LDAC at 0V or V , CA0, CA1 and CA2 Floating.

CC

Note 10: All values refer to V

and V

levels.

IH(MIN)

IL(MAX)

Note 4: DC crosstalk is measured with V = 5V and V = 4.096V, with the

CC

REF

Note 11: These specifications apply to LTC2607/LTC2607-1,

LTC2617/LTC2617-1, LTC2627/LTC2627-1.

Note 12: Guaranteed by design and not production tested.

measured DAC at midscale, unless otherwise noted.

Note 5: R = 2kΩ to GND or V

.

CC

L

26071727f

4

LTC2607/LTC2617/LTC2627

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

1.0

0.8

32

24

32

24

V

= 5V

REF

V

= 5V

CC

= 4.096V

REF

V

= 5V

REF

CC

= 4.096V

V

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–8

–16

–24

–32

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

2607 G02

2607 G01

2607 G03

DNL vs Temperature

INL vs V

DNL vs V

REF

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

= 5.5V

V

CC

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

DNL (POS)

DNL (NEG)

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–0.5

–1.0

–1.5

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

(V)

V

(V)

REF

2607 G04

2607 G05

2607 G06

Settling to ±1LSB

Settling of Full-Scale Step

V

OUT

100µV/DIV

12.3µs

9.7µs

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

9TH CLOCK OF

3RD DATA BYTE

SCL

2V/DIV

2607 G08

5µs/DIV

2607 G07

2µs/DIV

V

= 5V, V

= 4.096V

REF

SETTLING TO ±1LSB

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

V

= 5V, V

= 4.096V

CC

REF

CODE 512 TO 65535 STEP

R

L

AVERAGE OF 2048 EVENTS

26071727f

5

LTC2607/LTC2617/LTC2627

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2617

Settling to ±1LSB

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

0.2

100µV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

8.9µs

2607 G11

2µs/DIV

V

= 5V, V

= 4.096V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

0

4096

8192

CODE

12288

16383

0

4096

8192

CODE

12288

16383

L

AVERAGE OF 2048 EVENTS

2607 G09

2607 G10

LTC2627

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

Settling to ±1LSB

2.0

1.5

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

1.0

6.8µs

0.4

V

OUT

0.5

0.2

1mV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

SCL

2V/DIV

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

2607 G14

2µs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

R

0

1024

2048

CODE

3072

4095

0

1024

2048

CODE

3072

4095

L

AVERAGE OF 2048 EVENTS

2607 G12

2607 G13

26071727f

6

LTC2607/LTC2617/LTC2627

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Current Limiting

Load Regulation

Offset Error vs Temperature

0.10

0.08

1.0

0.8

3

2

CODE = MIDSCALE

V

REF

= V = 5V

CC

0.06

0.6

V

= V = 3V

CC

0.04

0.4

1

0.02

0.2

0

V

REF

= V = 5V

CC

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 3V

CC

REF

–1

–2

–3

V

= V = 5V

CC

V

= V = 3V

CC

REF

–40 –30 –20 –10

0

10 20 30 40

–35 –25 –15 –5

5

15

25

35

–50 –30 –10 10

30

50

70

90

I

(mA)

I

(mA)

OUT

TEMPERATURE (°C)

OUT

2607 G15

2607 G16

2607 G17

Gain Error vs Temperature

Zero-Scale Error vs Temperature

Offset Error vs V

CC

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

(V)

CC

2607 G18

2607 G19

2607 G20

Gain Error vs V

I

Shutdown vs V

CC

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V

(V)

CC

2607 G22

2607 G21

26071727f

7

LTC2607/LTC2617/LTC2627

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Large-Signal Response

Midscale Glitch Impulse

Power-On Reset to Zeroscale

TRANSITION FROM

MS-1 TO MS

V

OUT

V

CC

10mV/DIV

V

1V/DIV

OUT

TRANSITION FROM

MS TO MS-1

0.5V/DIV

9TH CLOCK

OF 3RD DATA

BYTE

4mV PEAK

SCL

2V/DIV

V

= V = 5V

CC

REF

V

OUT

1/4-SCALE TO 3/4-SCALE

10mV/DIV

2606 G26

2607 G25

2.5µs/DIV

2607 G23

250µs/DIV

Headroom at Rails

vs Output Current

Power-On Reset to Midscale

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= V

CC

REF

5V SOURCING

3V SOURCING

1V/DIV

5V SINKING

V

CC

3V SINKING

V

OUT

2607 G27

500µs/DIV

0

1

2

3

4

5

6

7

8

9

10

I

(mA)

OUT

2607 G26

Supply Current vs Logic Voltage

1300

1200

1100

1000

950

900

850

800

750

700

650

600

550

500

V

= 5V

CC

SWEEP SCL AND

V

= 5V

CC

SDA OV TO V

AND V TO OV

CC

SWEEP LDAC

CC

OV TO V

CC

HYSTERSIS

370mV

900

800

700

600

500

1

2

4

0

5

3

0

0.5

1

1.5

2

2.5

5

3

3.5 4 4.5

LOGIC VOLTAGE (V)

2607 G029

2607 G28

26071727f

8

LTC2607/LTC2617/LTC2627

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Output Voltage Noise,

0.1Hz to 10Hz

Multiplying Bandwidth

0

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

V

OUT

10µV/DIV

V

= 5V

CC

(DC) = 2V

REF

0

1

2

3

4

5

6

7

8

9

10

(AC) = 0.2V

P-P

SECONDS

CODE = FULL SCALE

2607 G31

1k

10k

100k

1M

FREQUENCY (Hz)

2607 G30

Short-Circuit Output Current vs

(Sourcing)

Short-Circuit Output Current vs

OUT

V

OUT

V

(Sinking)

50

40

30

20

0

–10

–20

–30

V

= 5.5V

= 5.6V

V

REF

= 5.5V

= 5.6V

CC

REF

CC

V

CODE = 0

V

CODE = FULL SCALE

SWEPT V TO 0V

SWEPT 0V TO V

V

OUT

CC

10

0

–40

–50

0

2

3

4

5

6

1

0

2

3

4

5

6

1

1V/DIV

2607 G32

2607 G33

26071727f

9

LTC2607/LTC2617/LTC2627

U

PIN FUNCTIONS

CA0 (Pin 1): Chip Address Bit 0. Tie this pin to V_CC, GND

or leave it floating to select an I²C slave address for the

part (Table 1).

SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance while data is shifted in and an open-

drainN-channeloutputduringacknowledgment.Requires

a pull-up resistor or current source to V_CC.

CA1 (Pin 2): Chip Address Bit 1. Tie this pin to V_CC, GND

or leave it floating to select an I²C slave address for the

part (Table 1).

CA2 (Pin 6): Chip Address Bit 2. Tie this pin to V_CC, GND

or leave it floating to select an I²C slave address for the

part (Table 1).

LDAC (Pin 3): Asynchronous DAC Update. A falling edge

of this input after four bytes have been written into the part

immediately updates the DAC register with the contents of

the input register. A low on this input without a complete

32-bit (four bytes including the slave address) data write

transfer to the part wakes up sleeping DACs without

updating the DAC output. Software power-down is dis-

abled when LDAC is low. LDAC is disabled when tied high.

V_OUTB(Pin 7): DAC Analog Voltage Output. The output

range is V_REFLOto V_REF

.

V

_CC(Pin 8): Supply Voltage Input. 2.7V ≤ V_CC≤ 5.5V.

REF (Pin 9): Reference Voltage Input. The input range

is V_REFLO≤ V_REF≤ V_CC.

GND (Pin 10): Analog Ground.

SCL (Pin 4): Serial Clock Input Pin. Data is shifted into the

SDA pin at the rising edges of the clock. This high

impedancepinrequiresapull-upresistororcurrentsource

to V_CC.

REFLO (Pin 11): Reference Low. The voltage at this pin

sets the zero scale (ZS) voltage of all DACs. The V_REFLOpin

can be used at voltages up to 1V for V_CC= 5V, or 100mV

for V_CC= 3V.

V_OUTA(Pin 12): DAC Analog Voltage Output. The output

range is V_REFLOto V_REF

.

Exposed Pad (Pin 13): Ground. Must be soldered to

PCB ground.

26071727f

10

LTC2607/LTC2617/LTC2627

W

BLOCK DIAGRA

REFLO

GND

10

REF

9

V

CC

11

8

V

OUTB

12-/14-/16-BIT DAC

12

OUTA

7

DAC REGISTER

INPUT REGISTER

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

5

6

1

2

3

4

LDAC

SDA

CA2

CA0

CA1

SCL

2607 BD

TEST CIRCUITS

Test Circuit 1

Test Circuit 2

V

DD

R /R /R

INH INL INF

100Ω

CAn

V

/V

IH(CAn) IL(CAn)

GND

2607 TC

26071727f

11

LTC2607/LTC2617/LTC2627

W U

W

TI I G DIAGRA S

26071727f

12

LTC2607/LTC2617/LTC2627

U

OPERATIO

Power-On Reset

The value of these pull-up resistors is dependent on the

power supply and can be obtained from the I²C specifica-

tions. For an I²C bus operating in the fast mode, an active

pull-up will be necessary if the bus capacitance is greater

than 200pF.

The LTC2607/LTC2617/LTC2627 clear the outputs to

zero scale when power is first applied, making system

initialization consistent and repeatable. The LTC2607-1/

LTC2617-1/LTC2627-1setthevoltageoutputstomidscale

when power is first applied.

The LTC2607/LTC2617/LTC2627 are receive-only (slave)

devices. The master can write to the LTC2607/LTC2617/

LTC2627. The LTC2607/LTC2617/LTC2627 do not re-

spond to a read from the master.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2607/

LTC2617/LTC2627 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground(typ)duringpower-on.SeePower-OnResetGlitch

in the Typical Performance Characteristics section.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

ASTARTconditionisgeneratedbytransitioningSDAfrom

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generatedbytransitioningSDAfromlowtohighwhileSCL

is high. The bus is then free for communication with

another I²C device.

Power Supply Sequencing

The voltage at REF (Pin 9) should be kept within the range

–0.3V ≤ V_REF≤ V_CC+ 0.3V (see Absolute Maximum

Ratings). Particular care should be taken to observe these

limitsduringpowersupplyturn-onandturn-offsequences,

when the voltage at V_CC(Pin 8) is in transition.

Acknowledge

TheAcknowledgesignalisusedforhandshakingbetween

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge re-

lated clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

bus line during the Acknowledge clock pulse so that it

remainsastableLOWduringtheHIGHperiodofthisclock

pulse. The LTC2607/LTC2617/LTC2627 respond to a

write by a master in this manner. The LTC2607/LTC2617/

LTC2627 do not acknowledge a read (retains SDA HIGH

during the period of the Acknowledge clock pulse).

Transfer Function

The digital-to-analog transfer function is:

k

⎛

⎞

V_OUT(IDEAL)

=

V_REF− V_REFLO+ V

REFLO

(

)

⎜

⎝

⎟

⎠

N

2

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and V_REFis the voltage at

REF (Pin 6).

Serial Digital Interface

TheLTC2607/LTC2617/LTC2627communicatewithahost

using the standard 2-wire I²C interface. The Timing Dia-

grams (Figures 1 and 2) show the timing relationship of

the signals on the bus. The two bus lines, SDA and SCL,

must be high when the bus is not in use. External pull-up

resistors or current sources are required on these lines.

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set to

any one of three states: V_CC, GND or float. This results in

26071727f

13

LTC2607/LTC2617/LTC2627

U

OPERATIO

Table 1. Slave Address Map

The addresses corresponding to the states of CA0, CA1

and CA2 and the global address are shown in Table 1. The

maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF, as these pins are driven

during address detection to determine if they are floating.

CA2

GND

CA1

GND

CA0

GND

SA6 SA5 SA4 SA3 SA2 SA1 SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

FLOAT

GND

V

CC

GND

FLOAT

GND

FLOAT

Write Word Protocol

GND

V

CC

The master initiates communication with the LTC2607/

LTC2617/LTC2627withaSTARTconditionanda7-bitslave

address followed by the Write bit (W) = 0. The LTC2607/

LTC2617/LTC2627 acknowledges by pulling the SDA pin

low at the 9th clock if the 7-bit slave address matches the

addressoftheparts(setbyCA0,CA1andCA2)ortheglobal

address.Themasterthentransmitsthreebytesofdata.The

LTC2607/LTC2617/LTC2627 acknowledges each byte of

databypullingtheSDAlinelowatthe9thclockofeachdata

byte transmission. After receiving three complete bytes of

data, the LTC2607/LTC2617/LTC2627 executes the com-

mand specified in the 24-bit input word.

GND

V

GND

CC

GND

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

V

CC

V

GND

CC

FLOAT

V

CC

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2607/LTC2617/LTC2627 do

not acknowledge the extra bytes of data (SDA is high

during the 9th clock).

V

GND

CC

FLOAT

GND

V

CC

FLOAT

GND

FLOAT

TheformatofthethreedatabytesisshowninFigure3.The

first byte of the input word consists of the 4-bit command

word C3-C0, and 4-bit DAC address A3-A0. The next two

bytesconsistofthe16-bitdataword. The16-bitdataword

consists of the 16-, 14- or 12-bit input code, MSB to LSB,

followed by 0, 2 or 4 don’t care bits (LTC2607, LTC2617

andLTC2627respectively).AtypicalLTC2607writetrans-

action is shown in Figure 4.

V

CC

V

GND

CC

FLOAT

V

CC

GLOBAL ADDRESS

27 selectable addresses for the part. The slave address

assignments are shown in Table 1.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 2. The first four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DACifithadbeeninpower-downmode. Thedatapathand

registers are shown in the Block Diagram.

Inadditiontotheaddressselectedbytheaddresspins, the

parts also respond to a global address. This address

allows a common write to all LTC2607, LTC2617 and

LTC2627 parts to be accomplished with one 3-byte write

transaction on the I²C bus. The global address is a 7-bit

on-chip hardwired address and is not selectable by CA0,

CA1 and CA2.

26071727f

14

LTC2607/LTC2617/LTC2627

U

OPERATIO

Write Word Protocol for LTC2607/LTC2617/LTC1627

W

A

1ST DATA BYTE

A

2ND DATA BYTE

A

3RD DATA BYTE

A

P

S

SLAVE ADDRESS

INPUT WORD

Input Word (LTC2607)

C3

C1

A3 A2 A1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

C2

C0

A0

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2617)

C3

C1

A3 A2 A1

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

2ND DATA BYTE 3RD DATA BYTE

X

C2

C0

1ST DATA BYTE

Input Word (LTC2627)

C3

C1

A3 A2 A1

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

C2

C0

2607 F03

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Figure 3

Table 2

COMMAND*

C3 C2 C1 C0

ignored. The supply and reference currents are reduced

by approximately 50% for each DAC powered down; the

effective resistance at REF (Pin 9) rises accordingly,

becoming a high-impedance input (typically > 1GΩ)

when both DACs are powered down.

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register

Update (Power Up) DAC Register

Write to and Update (Power Up)

Power Down

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 2

or performing an asychronous update (LDAC) as

describedinthenextsection.TheselectedDACispowered

up as its voltage output is updated. When a DAC in

powered-down state is powered up and updated, normal

settling is delayed. If one of the two DACs is in a powered-

down state prior to the update command, the power up

delay is 5µs. If on the other hand, both DACs are powered

down, the main bias generation circuit has been automati-

cally shut down in addition to the DAC amplifiers and

reference input and so the power up delay time is

No Operation

ADDRESS*

A3 A2 A1 A0

0

1

0

1

0

1

0

1

DAC A

DAC B

All DACs

*Command and address codes not shown are reserved and should not be used.

Power-Down Mode

Forpower-constrainedapplications,thepower-downmode

can be used to reduce the supply current whenever one or

both of the DAC outputs are not needed. When in power-

down,thebufferamplifiers,biascircuitsandreferenceinput

aredisabledanddrawessentiallyzerocurrent.TheDACout-

putsareputintoahighimpedancestate,andtheoutputpins

are passively pulled to V_REFLOthrough 90k resistors.

Input-registerandDAC-registercontentsarenotdisturbed

during power-down.

12µs (for V_CC= 5V) or 30µs (for V_CC= 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the

LDAC pin asynchronously updates the DAC registers with

the contents of the input registers. Asynchronous update

is disabled when the input word is being clocked into

the part.

Either or both DAC channels can be put into power-down

mode by using command 0100_bin combination with the

appropriate DAC address. The 16-bit data word is

26071727f

15

LTC2607/LTC2617/LTC2627

U

OPERATIO

If a complete input word has been written to the part, a low

on the LDAC pin causes the DAC registers to be updated

with the contents of the input registers.

Board Layout

The excellent load regulation performance is achieved in

partbyseparatingthesignalandpowergroundsasREFLO

and GND pins, respectively.

If the input word is being written to the part, a low going

pulseontheLDACpinbeforethecompletionofthreebytes

ofdatapowersuptheDACsbutdoesnotcausetheoutputs

to be updated. If LDAC remains low after a complete input

word has been written to the part, then LDAC is recog-

nized, the command specified in the 24-bit word just

transferred is executed and the DAC outputs updated.

The PC Board should have separate areas for the analog

and digital sections of the circuit. This keeps the digital

signals away from the sensitive analog signals and facili-

tates the use of separate digital and analog ground planes

that have minimal interaction with each other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground. Ideally, the

analog ground plane should be located on the component

side of the board, and should be allowed to run under the

part to shield it from noise. Analog ground should be a

continuous and uninterrupted plane, except for necessary

lead pads and vias, with signal traces on another layer.

The DACs are powered up when LDAC is taken low,

independent of any activity on the I²C bus.

If LDAC is low at the falling edge of the 9th clock of the 3rd

byte of data, it inhibits any software power-down

command that was specified in the input word. LDAC is

disabled when tied high.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. Resistance from the GND pin to the analog power

supply return should be as low as possible. Resistance

here will add directly to the channel resistance of the

output device when sinking load current. When a zero

scaleDACoutputvoltageofzeroisrequired,theREFLOpin

should be connected to system star ground. Any shared

trace resistance between REFLO and GND pins is undesir-

able since it adds to the effective DC output impedance

Voltage Output

Bothofthetworail-to-railamplifiershaveguaranteedload

regulation when sourcing or sinking up to 15mA at 5V

(7.5mA at 3V).

Load regulation is a measure of the amplifiers’ ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is

expressed in LSB/mA.

(typically 0.035Ω) of the part.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The amplifiers’ DC output

impedance is 0.035Ω when driving a load well away from

the rails.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

Since the analog output of the device cannot go below

ground, it may limit for the lowest codes as shown in

Figure 5b. Similarly, limiting can occur near full scale

when the REF pin is tied to V_CC. If V_REF= V_CCand the DAC

full-scale error (FSE) is positive, the output for the highest

codes limits at V_CCas shown in Figure 5c. No full-scale

limiting will occur if V_REFis less than V_CC– FSE.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30Ω typical channel resistance of the output

devices; e.g., when sinking 1mA, the minimum output

voltage = 30Ω • 1mA = 30mV. See the graph Headroom

at Rails vs Output Current in the Typical Performance

Characteristics section.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting

can occur.

The amplifiers are stable driving capacitive loads of up to

1000pF.

26071727f

16

LTC2607/LTC2617/LTC2627

U

OPERATIO

26071727f

17

LTC2607/LTC2617/LTC2627

U

OPERATIO

26071727f

18

LTC2607/LTC2617/LTC2627

U

PACKAGE DESCRIPTIO

DE/UE Package

12-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1695)

0.65 ±0.05

3.50 ±0.05

2.20 ±0.05 (2 SIDES)

1.70 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50

BSC

3.30 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.38 ± 0.10

4.00 ±0.10

(2 SIDES)

R = 0.115

TYP

7

12

R = 0.20

TYP

1.70 ± 0.10

(2 SIDES)

3.00 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PIN 1

NOTCH

(UE12) DFN 0603

6

0.25 ± 0.05

1

0.75 ±0.05

0.200 REF

0.50

BSC

3.30 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

26071727f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC2607/LTC2617/LTC2627

U

TYPICAL APPLICATIO

Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

5V

V

REF

1V TO 5V

0.1µF

8

6

REF

2

1

V

CC

3

1

2

6

V

FS

CC

LDAC

CA0

CA1

CA2

SET

100Ω

7.5k

7

3

4

V

CH 1

CH 0

OUTB

OUTA

9

8

7

SCK

SDO

CS

DAC

OUTPUT B

LTC2607

SPI BUS

LTC2422

4

5

100Ω

7.5k

12

2

SCL

SDA

I C BUS

10

F

O

ZS

GND

6

DAC

OUTPUT A

SET

5

GND

10, 13

REFLO

2607 TA01

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458: V = 4.5V to 5.5V, V

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

= 0V to 4.096V

OUT

CC

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L

LTC1657/LTC1657L

LTC1660/LTC1665

LTC1664

Single 16-Bit V

DACs with Serial Interface in SO-8

V

CC

OUT

Parallel 5V/3V 16-Bit V

DACs

Low Power, Deglitched, Rail-to-Rail V

OUT

Octal 10/8-Bit V

DACs in 16-Pin Narrow SSOP

V

CC

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Quad 10-Bit V

DAC in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

LTC1821

Parallel 16-Bit Voltage Output DAC

Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP

Precision 16-Bit Settling in 2µs for 10V Step

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

LTC2600/LTC2610/

LTC2620

OUT

LTC2601/LTC2611/

LTC2621

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

Output, SPI Serial Interface

OUT

LTC2604/LTC2614/

LTC2624

Quad 16-/14-/12-Bit V

Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

Output, SPI Serial Interface

2

LTC2605/LTC2615/

LTC2625

DACs with I C Interface

250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

2

Output, I C Interface

2

LTC2606/LTC2616/

LTC2626

16-/14-/12-Bit V

DACs with I C Interface

270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

2

Output, I C Interface

2

LTC2609/LTC2619/

LTC2629

Quad 16-/14-/12-Bit V

DACs with I C Interface

250µA Range per DAC, 2.7V to 5.5V Supply Range,

OUT

Rail-to-Rail Output with Separate V Pins for Each DAC

REF

26071727f

LT/LWI/TP 0705 500 • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

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型号：	LTC2627IDE
厂家：	Linear
描述：	16-/14-/12-Bit Dual Rail-to-Rail DACs with I2C Interface 16位/ 14位/ 12位双通道轨至轨DAC，带有I2C接口
文件：	总20页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2627IDE [Linear]

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