LTC2630ACSC6-HM12#TR

LTC2630

Single 12-/10-/8-Bit Rail-to-

Rail DACs with Integrated

Reference in SC70

FEATURES

DESCRIPTION

The LTC^®2630 is a family of 12-, 10-, and 8-bit voltage-

output DACs with an integrated, high-accuracy, low-drift

reference in a 6-lead SC70 package. It has a rail-to-rail

output buffer and is guaranteed monotonic.

■

Integrated Precision Reference

2.5V Full Scale 10ppm/°C (LTC2630-L)

4.096V Full Scale 10ppm/°C (LTC2630-H)

■

Maximum INL Error: 1 LSB (LTC2630A-12)

■

Low Noise: 0.7mV , 0.1Hz to 200kHz

P-P

The LTC2630-L has a full-scale output of 2.5V, and

operates from a single 2.7V to 5.5V supply. The

LTC2630-Hhasafull-scaleoutputof4.096V, andoperates

from a 4.5V to 5.5V supply. Each DAC can also operate in

supplyasreferencemode, whichsetsthefull-scaleoutput

to the supply voltage.

■

Guaranteed Monotonic over Temperature

Selectable Internal Reference or Supply as Reference

2.7V to 5.5V Supply Range (LTC2630-L)

Low Power Operation: 180µA at 3V

Power Down to 1.5µA Maximum (C and I Grades)

Power-on Reset to Zero or Midscale Options

SPI Serial Interface

The parts use a simple SPI/MICROWIRE™ compatible

3-wire serial interface which operates at clock rates up

to 50MHz.

Double-Buffered Data Latches

Tiny 6-Lead SC70 Package

The LTC2630 incorporates a power-on reset circuit. Op-

tions are available for reset to zero or reset to midscale

after power-up.

APPLICATIONS

■

Mobile Communications

■

Process Control and Industrial Automation

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5396245, 5859606, 6891433 and 6937178.

■

Automatic Test Equipment

Portable Equipment

■

Automotive

TYPICAL APPLICATION

V

Integral Nonlinearity (LTC2630A-LZ12)

CC

INTERNAL

REFERENCE

1.0

V

CC

V

FS

= 3V

= 2.5V

SDI

0.5

0

CONTROL

DECODE LOGIC

RESISTOR

DIVIDER

24-BIT

SCK

SHIFT

REGISTER

DACREF

DAC

–0.5

–1.0

CS/LD

V

OUT

INPUT

REGISTER

DAC

REGISTER

2048

3072

0

4095

1024

CODE

GND

2630 TA03

2630 BD

2630f

1

LTC2630

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Supply Voltage (V ) ................................... –0.3V to 6V

CC

CS/LD 1

SCK 2

SDI 3

6 V

OUT

CS/LD, SCK, SDI.......................................... –0.3V to 6V

5 GND

V

.................................. –0.3V to min(V + 0.3V, 6V)

OUT

CC

4 V

CC

Operating Temperature Range

LTC2630C ................................................ 0°C to 70°C

LTC2630I ............................................. –40°C to 85°C

LTC2630H.......................................... –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

SC6 PACKAGE

6-LEAD PLASTIC SC70

= 150°C (Note 4), θ = 300°C/W

T

JMAX

JA

ORDER INFORMATION

LTC2630

A

C

SC6 –L

M

12

#TRM PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = Tape and Reel

TRM = 500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

M = Reset to Mid-Scale

Z = Reset to Zero-Scale

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

SC6 = 6-Lead SC70

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

ELECTRICAL GRADE (OPTIONAL)

A = 1 LSB Maximum INL (12-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2630f

2

LTC2630

PRODUCT SELECTION GUIDE

PART NUMBER

LTC2630A-LM12

LTC2630A-LZ12

LTC2630A-HM12

LTC2630A-HZ12

LTC2630-LM12

LTC2630-LM10

LTC2630-LM8

V

FS

WITH INTERNAL REFERENCE

2.5V • (4095/4096)

4.096V • (4095/4096)

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

POWER-ON RESET TO CODE

RESOLUTION

12-Bit

V

MAXIMUM INL

CC

Mid-Scale

Zero

2.7V–5.5V

4.5V–5.5V

2.7V–5.5V

1LSB

12-Bit

Mid-Scale

Zero

12-Bit

1LSB

12-Bit

1LSB

Mid-Scale

12-Bit

2LSB

10-Bit

1LSB

8-Bit

0.5LSB

LTC2630-LZ12

LTC2630-LZ10

LTC2630-LZ8

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero

12-Bit

10-Bit

8-Bit

2.7V–5.5V

2LSB

1LSB

0.5LSB

LTC2630-HM12

LTC2630-HM10

LTC2630-HM8

LTC2630-HZ12

LTC2630-HZ10

LTC2630-HZ8

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Zero

12-Bit

10-Bit

8-Bit

4.5V–5.5V

2LSB

1LSB

0.5LSB

2LSB

12-Bit

10-Bit

8-Bit

Zero

1LSB

Zero

0.5LSB

2630f

3

LTC2630

ELECTRICAL CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating

unloaded unless otherwise speciﬁed.

temperature range, otherwise speciﬁcations are at T = 25°C. V = 2.7V to 5.5V, V

OUT

A

CC

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (V = 2.5V)

FS

LTC2630-8

LTC2630-10

LTC2630-12

LTC2630A-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

●

8

10

12

Bits

Monotonicity

V

CC

= 3V, Internal Ref. (Note 2)

DNL

INL

Differential Nonlinearity V = 3V, Internal Ref. (Note 2)

0.5

1

2

1

LSB

mV

CC

Integral Nonlinearity

Zero Scale Error

Offset Error

V

CC

V

CC

V

CC

V

CC

= 3V, Internal Ref. (Note 2)

= 3V, Internal Ref., Code = 0

= 3V, Internal Ref. (Note 3)

0.05 0.5

0.2

0.5

10

1

0.5

10

0.5

10

ZSE

0.5

10

5

V

5

mV

OS

V

Temperature

μV/°C

OSTC

OS

Coefﬁcient

●

FSE

Full Scale Error

V

= 3V, Internal Ref.

0.2 0.8

0.2

0.8

%FSR

CC

V

Full Scale Voltage

Temperature

Coefﬁcient

= 3V, Internal Ref. (Note 8)

FSTC

C-Grade

I-Grade

H-Grade

10

ppm/°C

●

Load Regulation

V

= 3V 10% or 5V 10%,

0.008 0.016

0.03 0.064

0.13 0.256

LSB/

mA

CC

Internal Ref., Midscale,

–5mA ≤ I

≤ 5mA

OUT

R

OUT

DC Output Impedance

V

= 3V 10% or 5V 10%,

CC

0.08 0.156

Ω

Internal Ref., Midscale,

–5mA ≤ I ≤ 5mA

OUT

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DAC Output Span

Supply as Reference

Internal Reference

0V to V

V

OUT

CC

0V to 2.5

PSR

Power Supply Rejection

V

CC

= 3V 10% or 5V 10%

–80

dB

I

SC

Short Circuit Output Current (Note 4)

V

FS

= V = 5.5V

CC

●

Sinking

Zero Scale; V

Shorted to V

27

–28

50

–50

mA

OUT

CC

Sourcing

Full Scale; V

Shorted to GND

OUT

Power Supply

●

V

Power Supply Voltage

Supply Current (Note 5)

For Speciﬁed Performance

Midscale

2.7

5.5

V

CC

I

CC

●

μA

V

CC

V

CC

V

CC

V

CC

= 3V, Supply as Reference

= 3V, Internal Reference

= 5V, Supply as Reference

= 5V, Internal Reference

160

180

190

220

240

250

260

●

I

Supply Current in Shutdown Mode (Note 5) V = 5V, C-Grade, I-Grade

0.36

1.5

3

μA

SD

CC

V

= 5V, H-Grade

CC

Digital I/O

●

V

Digital Input High Voltage

V

= 3.6V to 5.5V

= 2.7V to 3.6V

2.4

2.0

V

IH

CC

●

V

Digital Input Low Voltage

V

= 4.5V to 5.5V

= 2.7V to 4.5V

0.8

0.6

V

IL

CC

●

I

Digital Input Leakage

V

= GND to V

CC

1

μA

LK

IN

C

Digital Input Capacitance

(Note 6)

2.5

pF

IN

2630f

4

LTC2630

ELECTRICAL CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise speciﬁed.

A

CC

OUT

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (V = 2.5V)

FS

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN

TYP

MAX

UNITS

t

Settling Time

V

= 3V (Note 7)

CC

S

μs

0.39% ( 1LSB at 8 Bits)

0.098% ( 1LSB at 10 Bits)

0.024% ( 1LSB at 12 Bits)

3.2

3.9

4.4

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1.0

500

2

V/μs

pF

At Midscale Transition

nV•s

e

Output Voltage Noise Density

At f = 1kHz, Supply as Reference

At f = 10kHz, Supply as Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

160

150

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz, Supply as Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, Supply as Reference

0.1Hz to 200kHz, Internal Reference

20

650

700

μV

P-P

μV

P-P

μV

P-P

μV

P-P

TIMING CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T = 25°C. V = 2.7V to 5.5V. (See Figure 1) (Note 6).

A

CC

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (V = 2.5V)

FS

SYMBOL PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

●

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

1

4

ns

2

9

ns

3

SCK Low Time

9

ns

4

CS/LD Pulse width

10

7

ns

5

SCK High to CS/LD High

CS/LD Low to SCK High

CS/LD High to SCK Positive Edge

SCK Frequency

ns

6

7

ns

7

ns

10

50% Duty Cycle

50

MHz

2630f

5

LTC2630

ELECTRICAL CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating

unloaded unless otherwise speciﬁed.

temperature range, otherwise speciﬁcations are at T = 25°C. V = 4.5V to 5.5V, V

OUT

A

CC

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (V = 4.096V)

FS

LTC2630-8

LTC2630-10

LTC2630-12

LTC2630A-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

●

8

10

12

Bits

Monotonicity

V

CC

= 5V, Internal Ref. (Note 2)

DNL

INL

Differential Nonlinearity V = 5V, Internal Ref. (Note 2)

0.5

1

2

1

LSB

mV

CC

Integral Nonlinearity

Zero Scale Error

Offset Error

V

CC

V

CC

V

CC

V

CC

= 5V, Internal Ref. (Note 2)

= 5V, Internal Ref., Code = 0

= 5V, Internal Ref. (Note 3)

0.05 0.5

0.2

0.5

10

1

0.5

10

0.5

10

ZSE

0.5

10

5

V

OS

5

mV

V

Temperature

μV/°C

OSTC

OS

Coefﬁcient

●

FSE

Full Scale Error

V

= 5V, Internal Ref.

0.2 0.8

0.2

0.8 %FSR

CC

V

Full Scale Voltage

Temperature

Coefﬁcient

= 5V, Internal Ref. (Note 8)

FSTC

C-Grade

I-Grade

H-Grade

10

ppm/°C

●

Load Regulation

V

= 5V 10%, Internal Ref.,

0.006 0.01

0.025 0.04

0.10 0.16

LSB/

mA

CC

Midscale, –10mA ≤ I

≤ 10mA

OUT

R

DC Output Impedance

V

= 5V 10%, Internal Ref.,

0.1 0.156

Ω

OUT

CC

Midscale, –10mA ≤ I

≤ 10mA

OUT

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DAC Output Span

Supply as Reference

Internal Reference

0V to V

V

OUT

CC

0V to 4.096

PSR

Power Supply Rejection

V

CC

= 5V 10%

–80

dB

I

SC

Short Circuit Output Current (Note 4)

V

FS

= V = 5.5V

CC

●

Sinking

Zero Scale; V

Shorted to V

27

–28

50

–50

mA

OUT

CC

Sourcing

Full Scale; V

Shorted to GND

OUT

Power Supply

●

V

Power Supply Voltage

Supply Current (Note 5)

For Speciﬁed Performance

Midscale

CC

4.5

2.4

5.5

V

CC

I

CC

●

V

= 5V, Supply as Reference

= 5V, Internal Reference

180

200

260

280

μA

●

I

SD

Supply Current in Shutdown Mode (Note 5) V = 5V, C-Grade, I-Grade

0.36

1.5

3

μA

CC

V

= 5V, H-Grade

Digital I/O

●

V

IH

V

IL

Digital Input High Voltage

Digital Input Low Voltage

Digital Input Leakage

V

0.8

1

I

LK

V

= GND to V

μA

pF

IN

CC

C

IN

Digital Input Capacitance

(Note 6)

2.5

2630f

6

LTC2630

ELECTRICAL CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise speciﬁed.

A

CC

OUT

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (V = 4.096V)

FS

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN

TYP

MAX

UNITS

t

S

Settling Time

V

= 5V (Note 7)

CC

μs

0.39% ( 1LSB at 8 Bits)

0.098% ( 1LSB at 10 Bits)

0.024% ( 1LSB at 12 Bits)

3.7

4.4

4.8

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1.0

500

2.4

V/μs

pF

At Midscale Transition

nV•s

e

Output Voltage Noise Density

At f = 1kHz, Supply as Reference

At f = 10kHz, Supply as Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

210

200

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz, Supply as Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, Supply as Reference

0.1Hz to 200kHz, Internal Reference

20

650

750

μV

P-P

μV

P-P

μV

P-P

μV

P-P

TIMING CHARACTERISTICS ^The

●

denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T = 25°C. V = 4.5V to 5.5V. (See Figure 1) (Note 6).

A

CC

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (V = 4.096V)

FS

SYMBOL PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

●

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

1

4

ns

2

9

ns

3

SCK Low Time

9

ns

4

CS/LD Pulse width

10

7

ns

5

SCK High to CS/LD High

CS/LD Low to SCK High

CS/LD High to SCK Positive Edge

SCK Frequency

ns

6

7

ns

7

ns

10

50% Duty Cycle

50

MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁed maximum operating junction temperature may impair

device reliability.

N

Note 2: Linearity and monotonicity are deﬁned from code k to code 2 –1,

L

N

where N is the resolution and k is given by k = 0.016 • (2 / V ), rounded

Note 5: Digital inputs at 0V or V .

L

FS

CC

to the nearest whole code. For V = 2.5V and N = 12, k = 26 and linearity

FS

L

Note 6: Guaranteed by design and not production tested.

Note 7: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.

Note 8: Temperature coefﬁcient is calculated by dividing the maximum

change in output voltage by the speciﬁed temperature range.

is deﬁned from code 26 to code 4,095. For V = 4.096V and

FS

N = 12, k = 16 and linearity is deﬁned from code 16 to code 4,095.

L

Note 3: Inferred from measurement at code 16 (LTC2630-12), code 4

(LTC2630-10) or code 1 (LTC2630-8).

2630f

7

LTC2630

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2630-LM12/-LZ12 (V = 2.5V)

FS

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

1.0

0.5

V

= 3V

V

= 3V

CC

0

–0.5

–1.0

–0.5

–1.0

2048

3072

0

4095

1024

2048

0

3072

4095

1024

CODE

2630 G01

2630 G02

Full-Scale Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

1.0

0.5

1.0

0.5

2.52

2.51

2.50

2.49

2.48

V

= 3V

V

CC

= 3V

V

= 3V

CC

INL (POS)

DNL (POS)

DNL (NEG)

0

INL (NEG)

–0.5

–1.0

50

100

50

100

50

100

125 150

–50 –25

25

75

125 150

–50 –25

25

75

125 150

–50 –25

25

75

0

TEMPERATURE (°C)

2630 G03

2630 G04

2630 G05

Settling to 1LSB

3/4 SCALE TO 1/4 SCALE STEP

= 3V, V = 2.5V

V

CC

L

FS

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

V

OUT

1LSB/DIV

4.4µs

3.6µs

V

OUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

= 3V, V = 2.5V

V

CC

FS

CS/LD

2V/DIV

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2µs/DIV

2630 G07

2630 G06

2630f

8

LTC2630

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2630-HM12/-HZ12 (V = 4.096V)

FS

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

1.0

0.5

V

= 5V

V

= 5V

CC

0

–0.5

–1.0

–0.5

–1.0

2048

3072

2048

3072

0

4095

0

4095

1024

CODE

2630 G08

2630 G09

Full-Scale Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

4.115

4.105

4.095

4.085

4.075

1.0

0.5

1.0

0.5

V

= 5V

V

= 5V

V

= 5V

CC

INL (POS)

DNL (POS)

DNL (NEG)

0

INL (NEG)

–0.5

–1.0

50

100

125 150

–50 –25

25

75

0

50

100

50

100

125 150

–50 –25

25

75

125 150

–50 –25

25

75

0

TEMPERATURE (°C)

2630 G12

2630 G10

2630 G11

Settling to 1LSB

CS/LD

2V/DIV

V

OUT

1LSB/DIV

4.8µs

4.0µs

V

OUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

= 5V, V = 4.096V

1/4 SCALE TO 3/4 SCALE STEP

V

CC

FS

V

= 5V, V = 4.096V

CS/LD

2V/DIV

CC

FS

R

= 2k, C = 100pF

L

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2µs/DIV

2630 G14

2630 G13

2630f

9

LTC2630

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2630-10

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

V

CC

V

FS

= 5V

= 4.096V

V

= 5V

= 4.096V

CC

FS

0.5

0

–0.5

–1.0

–0.5

–1.0

512

768

0

1023

256

0

512

768

1023

256

CODE

2630 G15

2630 G16

LTC2630-8

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

0.50

0.25

0

V

CC

V

FS

= 3V

= 2.5V

V

CC

V

FS

= 3V

= 2.5V

0

–0.5

–1.0

–0.25

–0.50

128

192

128

192

0

255

0

255

64

CODE

2630 G17

2630 G18

LTC2630

Load Regulation

Current Limiting

Offset Error vs Temperature

0.20

0.15

0.10

0.05

0

10

8

3

2

1

0

V

CC

V

CC

V

CC

= 5V (LTC2630-H)

= 5V (LTC2630-L)

= 3V (LTC2630-L)

V

CC

V

CC

V

CC

= 5V (LTC2630-H)

= 5V (LTC2630-L)

= 3V (LTC2630-L)

6

4

2

0

–2

–4

–6

–8

–10

–0.05

–0.10

–0.15

–0.20

–1

–2

–3

INTERNAL REF.

CODE = MIDSCALE

INTERNAL REF.

CODE = MIDSCALE

–30

–20

–10

0

10 20

30

–30

–20

–10

0

10

20

30

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

2630 G21

I

(mA)

I

(mA)

OUT

2630 G20

2630 G19

2630f

10

LTC2630

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2630

Power-On Reset Glitch

Midscale-Glitch Impulse

Large-Signal Response

LTC2630-L

INTERNAL REF

V

CC

CS/LD

5V/DIV

2V/DIV

LTC2630-H12, V = 5V:

CC

2.4nV-s TYP

0.5V/DIV

V

OUT

ZERO-SCALE

5mV/DIV

V

OUT

LTC2630-L12, V = 3V:

CC

2.0nV-s TYP

2mV/DIV

V

= V = 5V

FS

CC

1/4 SCALE TO 3/4 SCALE

2µs/DIV

200µs/DIV

2µs/DIV

2630 G23

2630 G24

2630 G22

Headroom at Rails vs Output

Current

Noise Voltage vs Frequency

0.1Hz to 10Hz Voltage Noise

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

500

400

300

200

100

0

CODE = MIDSCALE

5V SOURCING

V

= 4V, V = 2.5V

FS

CC

CODE = MIDSCALE

3V (LTC2630-L) SOURCING

LTC2630-H

10µV/DIV

(V = 5V)

CC

LTC2630-L

5V SINKING

(V = 4V)

CC

3V (LTC2630-L) SINKING

0

1

2

3

4

5

6

7

8

1k

10k

100k

1s/DIV

100

1M

2630 G27

I

(mA)

FREQUENCY (Hz)

OUT

2630 G25

2630 G26

Exiting Power-Down to Midscale

Supply Current vs Logic Voltage

1.0

0.8

0.6

0.4

0.2

SWEEP SCK, SDI, CS/LD

BETWEEN 0V AND V

CC

CS/LD

2V/DIV

V

= 5V

CC

V

OUT

V

= 3V

0.5V/DIV

CC

(LTC2630-L)

LTC2630-H

0

1

2

3

4

5

4µs/DIV

2630 G28

LOGIC VOLTAGE (V)

2630 G29

2630f

11

LTC2630

PIN FUNCTIONS

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the speciﬁed command (see Table 1) is

executed.

V

(Pin 4): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V

CC CC

(LTC2630-L) or 4.5V ≤ V ≤ 5.5V (LTC2630-H). Also

CC

used as the reference input when the part is programmed

to operate in supply as reference mode. Bypass to GND

with a 0.1μF capacitor.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

GND (Pin 5): Ground.

V

OUT

(Pin 6): DAC Analog Voltage Output.

SDI (Pin 3): Serial Interface Data Input. Data on SDI

is clocked into the DAC on the rising edge of SCK. The

LTC2630 accepts input word lengths of either 24 or 32

bits.

BLOCK DIAGRAM

V

CC

INTERNAL

REFERENCE

SDI

CONTROL

DECODE LOGIC

RESISTOR

DIVIDER

24-BIT

SHIFT

REGISTER

SCK

DACREF

DAC

CS/LD

V

OUT

INPUT

REGISTER

DAC

REGISTER

GND

2630 BD

2630f

12

LTC2630

TIMING DIAGRAM

t

1

t

6

t

3

t

4

2

SCK

SDI

1

2

3

23

24

t

10

t

7

5

CS/LD

2630 F01

Figure 1. Serial Interface Timing

OPERATION

The LTC2630 is a family of single voltage output DACs in

6-lead SC70 packages. Each DAC can operate rail-to-rail

referenced to the input supply, or with its full-scale volt-

age set by an integrated reference. Twelve combinations

of accuracy (12-, 10-, and 8-bit), power-on reset value

(zero or midscale), and full-scale voltage (2.5V or 4.096V)

are available. The LTC2630 is controlled using a 3-wire

SPI/MICROWIRE compatible interface.

Transfer Function

The digital-to-analog transfer function is

k

⎛

⎝

⎞

⎠

V_{OUT(IDEAL) ⎜}

=

V

_N⎟ REF

2

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and V is either 2.5V

REF

(LTC2630-L) or 4.096V (LTC2630-H) in internal refer-

Power-On Reset

ence mode, and V in Supply as reference mode.

CC

The LTC2630-HZ/-LZ clear the output to zero scale when

power is ﬁrst applied, making system initialization con-

sistent and repeatable.

Table 1. Command Codes

Command*

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2630

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero

scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

Write to Input Register

Update (Power up) DAC Register

Write to and Update (Power up) DAC Register

Power down

Select Internal Reference (Power-on Reset Default)

Select Supply as Reference (V = V

)

CC

REF

*Command codes not shown are reserved and should not be used.

TheLTC2630-HM/-LMprovideanalternativereset,setting

the output to midscale when power is ﬁrst applied.

2630f

13

LTC2630

OPERATION

INPUT WORD (LTC2630-12)

COMMAND

4 DON'T-CARE BITS

DATA (12 BITS + 4 DON'T-CARE BITS)

C3 C2 C1 C0

X

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

MSB

LSB

INPUT WORD (LTC2630-10)

COMMAND

4 DON'T-CARE BITS

DATA (10 BITS + 6 DON'T-CARE BITS)

C3 C2 C1 C0

X

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

X

INPUT WORD (LTC2630-8)

COMMAND

4 DON'T-CARE BITS

DATA (8 BITS + 8 DON'T-CARE BITS)

C3 C2 C1 C0

X

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

X

2630 F02

Figure 2. Command and Data Input Format

Serial Interface

While the minimum input sequence is 24 bits, it may

optionally be extended to 32 bits to accommodate micro-

processors that have a minimum word width of 16 bits

(2bytes).Tousethe32-bitwidth,8don’t-carebitsaretrans-

ferred to the device ﬁrst, followed by the 24-bit sequence

described. Figure 3b shows the 32-bit sequence.

TheCS/LDinputisleveltriggered. Whenthisinputistaken

low, it acts as a chip-select signal, enabling the SDI and

SCK buffers and the input shift register. Data (SDI input)

is transferred at the next 24 rising SCK edges. The 4-bit

command, C3-C0, is loaded ﬁrst; then 4 don’t-care bits;

and ﬁnally the 16-bit data word. The data word comprises

the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, fol-

lowed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and

-8 respectively; see Figure 2). Data can only be transferred

to the device when the CS/LD signal is low, beginning on

the ﬁrst rising edge of SCK. SCK may be high or low at

the falling edge of CS/LD. The rising edge of CS/LD ends

the data transfer and causes the device to execute the

command speciﬁed in the 24-bit input sequence. The

complete sequence is shown in Figure 3a.

The 16-bit data word is ignored for all commands that do

not include a Write operation.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever the

DACoutputisnotneeded.Wheninpower-down,thebuffer

ampliﬁer,biascircuit,andreferencecircuitaredisabledand

draw essentially zero current. The DAC output is put into

a high-impedance state, and the output pin is passively

pulled to ground through a 200kΩ resistor. Input and DAC

register contents are not disturbed during power-down.

The command (C3-C0) assignments are shown in Table 1.

The ﬁrst three commands in the table consist of write and

update operations. A Write operation loads a 16-bit data

word from the 24-bit shift register into the input register.

In an Update operation, the input register is copied to the

DAC register and converted to an analog voltage at the

DAC output. Write to and Update combines the ﬁrst two

commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

The DAC can be put into power-down mode by using

command 0100. The supply current is reduced to 1.5µA

maximum when the DAC is powered down.

Normal operation resumes after executing any command

that includes a DAC update, as shown in Table 1. The DAC

is powered up and its voltage output is updated. Normal

settling is delayed while the bias, reference, and ampliﬁer

circuits are re-enabled. The power up delay time is 18μs

for settling to 12 bits.

2630f

14

LTC2630

OPERATION

Reference Modes

SincetheanalogoutputoftheDACcannotgobelowground,

it may limit for the lowest codes as shown in Figure 4b.

Similarly, limiting can occur near full scale when using the

For applications where an accurate external reference is

notavailable,theLTC2630hasauser-selectable,integrated

reference. The LTC2630-LM and LTC2630-LZ provide a

full-scale output of 2.5V. The LTC2630-HM and LTC2630-

HZ provide a full-scale output of 4.096V.

supply as reference. If V = V and the DAC full-scale

FS

CC

error (FSE) is positive, the output for the highest codes

limits at V , as shown in Figure 4. No full-scale limiting

CC

can occur if V is less than V –FSE.

FS

CC

The internal reference can be useful in applications where

the supply voltage is poorly regulated. Internal Reference

mode can be selected by using command 0110, and is

the power-on default.

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting can

occur.

The DAC can also operate in supply as reference mode us-

Board Layout

ing command 0111. In this mode, V supplies the DAC’s

CC

ThePCboardshouldhaveseparateareasfortheanalogand

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2630 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2630 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

reference voltage and the supply current is reduced.

Voltage Output

TheLTC2630’sintegratedrail-to-railampliﬁerhasguaran-

teed load regulation when sourcing or sinking up to 10mA

at 5V, and 5mA at 3V.

Load regulation is a measure of the ampliﬁer’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The ampliﬁer’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2630 is sinking large currents, this current ﬂows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph “Headroom at Rails

vs. Output Current” in the Typical Performance Charac-

teristics section.

The ampliﬁer is stable driving capacitive loads of up to

500pF.

It is sometimes necessary to interrupt the ground plane

to conﬁne digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

2630f

15

LTC2630

OPERATION

Optoisolated 4mA to 20mA Process Controller

additional current through Q1. Note that at the maximum

loop voltage of 80V, Q1 will dissipate 1.6W when I

20mA and must have an appropriate heat sink.

=

OUT

Figure 5 shows how to use an LTC2630HZ to make an

optoisolated, digitally-controlled 4mA to 20mA transmit-

ter. The transmitter circuitry, including optoisolation, is

powered by the loop voltage which has a wide range of

5.4V to 80V. The 5V output of the LT^®3010-5 is used to

R

and R

are the closest 0.1% values to ideal

OFFSET

GAIN

for controlling a 4mA to 20mA output as the digital input

varies from zero scale to full scale. Alternatively, R

OFFSET

can be a 365k, 1% resistor in series with a 20k trim pot

set the 4mA offset current and V

is used to digitally

OUT

and R

can be a 75.0k, 1% resistor in series with a 5k

control the 0mA to 16mA signal current. The supply cur-

GAIN

trim pot. The optoisolators shown will limit the speed of

the serial bus; the 6N139 is an alternative that will allow

higher data rates.

rent for the regulator, DAC, and op amp is well below

the 4mA budget at zero scale. R senses the total loop

S

current, which includes the quiescent supply current and

CS/LD

SCK

SDI

1

2

3

4

5

6

7

8

9

10

11

12

D8

13

D7

14

D6

15

D5

16

D4

17

D3

18

D2

19

D1

20

D0

21

22

23

24

C3

C2

C1

C0

X

D11 D10 D9

X

2630 F03a

COMMAND WORD

4 DON’T-CARE BITS

DATA WORD

24-BIT INPUT WORD

Figure 3a. 24-Bit Load Sequence (Minimum Input Word)

LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);

LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;

LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits

CS/LD

SCK

1

2

3

4

5

6

7

8

9

10

C2

11

C1

12

C0

13

14

15

16

17

18

19

20

D8

21

D7

22

D6

23

D5

24

D4

25

D3

26

D2

27

D1

28

D0

29

30

31

32

SDI

X

C3

X

D11 D10 D9

X

8 DON’T-CARE BITS

COMMAND WORD

4 DON’T-CARE BITS

DATA WORD

2630 F03b

32-BIT INPUT WORD

Figure 3b. 32-Bit Load Sequence

LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);

LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;

LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits

2630f

16

LTC2630

OPERATION

2630f

17

LTC2630

TYPICAL APPLICATION

12-Bit, 2.7V to 5.5V Single Supply, Voltage Output DAC

2.7V TO 5.5V

0.1µF

V

CC

SDI

OUTPUT

µP

LTC2630-LZ12

GND

SCK

V

0V TO 2.5V OR

OUT

0V TO V

CC

CS/LD

2630 TA01

2630f

18

LTC2630

PACKAGE DESCRIPTION

SC6 Package

6-Lead Plastic SC70

(Reference LTC DWG # 05-08-1638 Rev B)

0.47

MAX

0.65

REF

1.80 – 2.20

(NOTE 4)

1.00 REF

INDEX AREA

(NOTE 6)

1.15 – 1.35

1.80 – 2.40

2.8 BSC 1.8 REF

(NOTE 4)

PIN 1

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.15 – 0.30

6 PLCS (NOTE 3)

0.65 BSC

0.10 – 0.40

0.80 – 1.00

0.00 – 0.10

REF

1.00 MAX

GAUGE PLANE

0.15 BSC

0.26 – 0.46

SC6 SC70 1205 REV B

0.10 – 0.18

(NOTE 3)

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE INDEX AREA

7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70

8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB

2630f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC2630

TYPICAL APPLICATION

V

LOOP

5.4V TO 80V

R

OFFSET

374k

LT3010-5

0.1%

IN

OUT

+

SHDN SENSE

GND

1µF

R

76.8k

0.1%

GAIN

V

CC

SDI

FROM

OPTO-

ISOLATED

INPUTS

LTC2630-HZ

V

SCK

OUT

+

–

1k

Q1

2N3440

LTC2054

CS/LD

3.01k

1000 F

P

10k

R

S

5V

10Ω

I

OPTO-ISOLATORS

OUT

10k

SDI

SCK

2630 F05

CS/LD

4N28

500Ω

SDI

SCK

CS/LD

Figure 5. An Optoisolated 4mA to 20mA Process Controller

RELATED PARTS

PART NUMBER

LTC1660/LTC1665

LTC1663

DESCRIPTION

Octal 10-/8-Bit V

COMMENTS

DACs in 16-Pin Narrow SSOP

V

CC

V

CC

V

CC

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

= 2.7V to 5.5V, 60μA, Internal reference, SMBus Interface

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

Single 10-Bit V

DAC in SOT-23

OUT

LTC1664

Quad 10-Bit V

DAC in 16-Pin Narrow SSOP

OUT

2

LTC1669

Single 10-Bit V

DAC in SOT-23

= 2.7V to 5.5V, 60μA, Internal reference, I C Interface

OUT

LTC1821

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2μs for 10V Step

LTC2600/LTC2610/LTC2620

Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

SPI Serial Interface

LTC2601/LTC2611/LTC2621

LTC2602/LTC2612/LTC2622

LTC2604/LTC2614/LTC2624

LTC2605/LTC2615/LTC2625

LTC2606/LTC2616/LTC2626

LTC2609/LTC2619/LTC2629

Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

SPI Serial Interface

Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

OUT

Quad 16-/14-/12-Bit V

Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

SPI Serial Interface

2

DACs with I C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,

2

I C Interface

2

Single 16-/14-/12-Bit V

DACs with I C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

2

I C Interface

2

Quad 16-/14-/12-Bit V

DACs with I C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output

OUT

with Separate V Pins for Each DAC

REF

2630f

LT 0407 • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2630ACSC6-HM12#TR
厂家：	Linear
描述：	暂无描述
文件：	总20页 (文件大小：342K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2630ACSC6-HM12#TR [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E