LTC2631ACTS8-LZ12 [Linear]
Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference; 单12 / 10 / 8位I2C VOUT DAC,带有为10ppm / ° C参考型号: | LTC2631ACTS8-LZ12 |
厂家: | Linear |
描述: | Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference |
文件: | 总28页 (文件大小:349K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2631
2
Single 12-/10-/8-Bit I C
V DACs with
OUT
10ppm/°C Reference
FEATURES
DESCRIPTION
n
Integrated Precision Reference
The LTC®2631 is a family of 12-, 10-, and 8-bit voltage-
output DACs with an integrated, high accuracy, low-drift
referenceinan8-leadTSOT-23package.Ithasarail-to-rail
output buffer that is guaranteed monotonic.
2.5V Full-Scale 10ppm/°C (LTC2631-L)
4.096V Full-Scale 10ppm/°C (LTC2631-H)
n
Maximum INL Error: 1LSB (LTC2631A-12)
n
Bidirectional Reference: Input or 10ppm/°C Output
The LTC2631-L has a full-scale output of 2.5V, and oper-
ates from a single 2.7V to 5.5V supply. The LTC2631-H
hasafull-scaleoutputof4.096V, andoperatesfroma4.5V
to 5.5V supply. A 10ppm/°C reference output is available
at the REF pin.
2
n
400kHz I C™ Interface
n
Nine Selectable Addresses (LTC2631-Z)
n
Low Noise (0.7mV , 0.1Hz to 200kHz)
P-P
n
n
n
n
n
n
n
n
Guaranteed Monotonic Over Temperature
2.7V to 5.5V Supply Range (LTC2631-L)
Low Power Operation: 180μA at 3V
Power Down to 1.8μA Maximum (C and I Grades)
Power-On Reset to Zero or Mid-Scale Options
Double-Buffered Data Latches
Each DAC can also operate in External Reference mode,
in which a voltage supplied to the REF pin sets the full-
scale output.
2
The LTC2631 DACs use a 2-wire, I C-compatible serial
Guaranteed Operation From –40°C to 125°C (H-Grade)
8-Lead TSOT-23 (ThinSOT™) Package
interface. The LTC2631 operates in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
APPLICATIONS
The LTC2631 incorporates a power-on reset circuit. Op-
tions are available for reset to zero-scale or reset to mid-
scale after power-up.
n
Mobile Communications
n
Process Control and Industrial Automation
n
Automatic Test Equipment
2
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. I C and
n
Portable Equipment
ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5396245, 5859606,
6891433, 6937178 and 7414561.
n
Automotive
n
Optical Networking
(LTC2631-M)
BLOCK DIAGRAM
V
REF
CC
2
Integral Nonlinearity (LTC2631A-LM12)
I C
CA0
ADDRESS
DECODE
INTERNAL
REFERENCE
1.0
REF_SEL
V
V
= 3V
SWITCH
CC
FS
= 2.5V
0.5
CONTROL
DECODE LOGIC
RESISTOR
DIVIDER
SCL
SDA
0
2
I C
INTERFACE
DACREF
DAC
–0.5
–1.0
V
OUT
INPUT
REGISTER
DAC
REGISTER
0
2048
3072
4095
1024
GND
CODE
2631 TA01b
2631 TA01
2631fb
1
LTC2631
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (V ) ...................................–0.3V to 6V
Maximum Junction Temperature........................... 150°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
CC
REF_SEL, SCL, SDA.....................................–0.3V to 6V
V
, CA0, CA1, REF.........–0.3V to Min(V + 0.3V, 6V)
OUT
CC
Operating Temperature Range
LTC2631C ................................................ 0°C to 70°C
LTC2631I..............................................–40°C to 85°C
LTC2631H (Note 3) ............................–40°C to 125°C
PIN CONFIGURATION
LTC2631-Z
LTC2631-M
TOP VIEW
TOP VIEW
CA0 1
SCL 2
SDA 3
GND 4
8 CA1
7 V
6 REF
CA0 1
SCL 2
SDA 3
GND 4
8 REF_SEL
7 V
OUT
OUT
6 REF
5 V
CC
5 V
CC
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
T
= 150°C (NOTE 6), θ = 195°C/W
T
JMAX
= 150°C (NOTE 6), θ = 195°C/W
JMAX
JA
JA
2631fb
2
LTC2631
ORDER INFORMATION
LTC2631
A
C
TS8 –L
M
12
#TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = 1LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2631fb
3
LTC2631
PRODUCT SELECTION GUIDE
V
WITH INTERNAL
POWER-ON RESET
TO CODE
FS
PART NUMBER
LTC2631A-LM12 LTDHF
LTC2631A-LZ12 LTDHG
PART MARKING* REFERENCE
PIN 8
RESOLUTION
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
10-Bit
8-Bit
V
MAXIMUM INL
1LSB
CC
2.5V • (4095/4096)
2.5V • (4095/4096)
4.096V • (4095/4096)
4.096V • (4095/4096)
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Zero
REF_SEL
CA1
2.7V – 5.5V
2.7V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
2.7V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
4.5V – 5.5V
1LSB
LTC2631A-HM12 LTDHH
LTC2631A-HZ12 LTDHJ
Mid-Scale
Zero
REF_SEL
CA1
1LSB
1LSB
LTC2631-LM12
LTC2631-LM10
LTC2631-LM8
LTC2631-LZ12
LTC2631-LZ10
LTC2631-LZ8
LTDHF
LTDHK
LTDHQ
LTDHG
LTDHM
LTDHR
LTDHH
LTDHN
LTDHS
LTDHJ
LTDHP
LTDHT
Mid-Scale
Mid-Scale
Mid-Scale
Zero
REF_SEL
REF_SEL
REF_SEL
CA1
2.5LSB
1LSB
0.5LSB
2.5LSB
1LSB
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
12-Bit
10-Bit
8-Bit
Zero
CA1
Zero
CA1
0.5LSB
2.5LSB
1LSB
LTC2631-HM12
LTC2631-HM10
LTC2631-HM8
LTC2631-HZ12
LTC2631-HZ10
LTC2631-HZ8
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Zero
REF_SEL
REF_SEL
REF_SEL
CA1
12-Bit
10-Bit
8-Bit
0.5LSB
2.5LSB
1LSB
12-Bit
10-Bit
8-Bit
Zero
CA1
Zero
CA1
0.5LSB
*The temperature grade is identified by a label on the shipping container.
2631fb
4
LTC2631
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
LTC2631-8
LTC2631-10
LTC2631-12
LTC2631A-12
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
LSB
Monotonicity
V
V
= 3V, Internal Ref. (Note 4)
= 3V, Internal Ref. (Note 4)
CC
CC
DNL
INL
Differential
0.5
0.5
5
0.5
1
1
2.5
5
1
1
Nonlinearity
l
l
l
Integral
Nonlinearity
V
V
= 3V, Internal Ref. (Note 4)
= 3V, Internal Ref.,
0.05
0.5
0.2
0.5
0.5
10
1
0.5
0.5
10
0.5
0.5
0.5
10
LSB
mV
CC
CC
ZSE
Zero-Scale Error
Offset Error
5
5
Code = 0
V
V
= 3V, Internal Ref.
0.5
5
5
5
5
mV
OS
CC
(Note 5)
V
OSTC
V
Temperature V = 3V, Internal Ref.
10
μV/°C
OS
CC
(Note 5)
Coefficient
l
FSE
Full-Scale Error
V
= 3V, Internal Ref.
0.08
0.4
0.08 0.4
0.08 0.4
0.08 0.4 %FSR
CC
(Note 15)
V = 3V, Internal Ref. (Note 10)
CC
C-Grade
I-Grade
H-Grade
V
Full-Scale
Voltage
Temperature
Coefficient
FSTC
10
10
10
10
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
ppm/°C
Load Regulation Internal Ref., Mid-Scale,
= 3V 10%,
l
l
V
0.009 0.016
0.009 0.016
0.035 0.064
0.035 0.064
0.14 0.256
0.14 0.256
0.14 0.256 LSB/mA
0.14 0.256 LSB/mA
CC
–5mA ≤ I
≤ 5mA,
OUT
V
= 5V 10%,
CC
–10mA ≤ I
≤ 10mA
OUT
R
DC Output
Impedance
Internal Ref., Mid-Scale,
= 3V 10%,
OUT
l
l
V
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
Ω
CC
–5mA ≤ I
≤ 5mA,
OUT
V
= 5V 10%,
CC
–10mA ≤ I
≤ 10mA
OUT
SYMBOL
PARAMETER
DAC Output Span
CONDITIONS
MIN
TYP
MAX
UNITS
V
OUT
External Reference
Internal Reference
0 to V
V
V
REF
0 to 2.5
PSR
Power Supply Rejection
V
CC
= 3V 10% or 5V 10%
–80
dB
I
SC
Short-Circuit Output Current (Note 6)
V
= V = 5.5V
CC
FS
l
Sinking
Zero-Scale; V
shorted to V
27
–28
48
–48
mA
mA
OUT
CC
l
Sourcing
Full-Scale; V
shorted to GND
OUT
Power Supply
l
V
Positive Supply Voltage
Supply Current (Note 7)
For Specified Performance
2.7
5.5
V
CC
l
l
l
l
I
CC
V
CC
V
CC
V
CC
V
CC
= 3V, V = 2.5V, External Reference
150
180
160
190
200
240
210
260
μA
μA
μA
μA
REF
= 3V, Internal Reference
= 5V, V = 2.5V, External Reference
REF
= 5V, Internal Reference
l
l
I
SD
Supply Current in Power-Down Mode
(Note 7)
V
V
= 5V, C-Grade, I-Grade
= 5V, H-Grade
0.6
0.6
1.8
4
μA
μA
CC
CC
2631fb
5
LTC2631
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
l
l
Input Voltage Range
Resistance
0
V
V
kΩ
pF
CC
160
190
7.5
220
Capacitance
l
l
I
Reference Current, Power-Down Mode
DAC Powered Down
0.005
0.1
μA
REF
Reference Output
Output Voltage
1.240
1.250
10
1.260
V
ppm/°C
kΩ
Reference Temperature Coefficient
Output Impedance
0.5
10
Capacitive Load Driving
Short-Circuit Current
μF
V
CC
= 5.5V; REF Shorted to GND
2.5
mA
Digital I/O
l
l
l
V
V
V
Low Level Input Voltage (SDA and SCL) (Note 14)
High Level Input Voltage (SDA and SCL) (Note 11)
–0.5
0.7V
0.3V
V
V
V
IL
CC
IH
CC
Low Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
0.15V
IL(CAn)
CC
l
l
l
l
V
High Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
See Test Circuit 2
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
0.85V
V
kΩ
IH(CAn)
CC
R
R
R
Resistance from CAn (n = 0, 1)
10
10
INH
INL
INF
OL
to V to Set CAn = V
CC
CC
Resistance from CAn (n = 0, 1)
to GND to Set CAn = GND
kΩ
Resistance from CAn (n = 0, 1)
2
0
MΩ
to V or GND to Set CAn = Float
CC
l
l
V
Low Level Output Voltage
Output Fall Time
0.4
V
t
t
I
V = V
B
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 12)
l
Pulse Width of Spikes Suppressed by
Input Filter
0
50
ns
SP
IN
l
l
l
l
Input Leakage
0.1V ≤ V ≤ 0.9V
1
10
μA
pF
pF
pF
CC
IN
CC
C
C
C
I/O Pin Capacitance
(Note 8)
IN
Capacitive Load for Each Bus Line
400
10
B
External Capacitive Load on Address
Pin CAn (n = 0, 1)
CAn
2631fb
6
LTC2631
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
t
S
Settling Time
V
= 3V (Note 9)
CC
0.39% ( 1LSB at 8-Bits)
0.098% ( 1LSB at 10-Bits)
0.024% ( 1LSB at 12-Bits)
3.2
3.8
4.1
μs
μs
μs
Voltage-Output Slew Rate
Capacitance Load Driving
Glitch Impulse
1
V/μs
pF
500
2.1
300
At Mid-Scale Transition
External Reference
nV•s
kHz
Multiplying Bandwidth
Output Voltage Noise Density
e
n
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
20
20
650
670
μV
P-P
μV
P-P
μV
P-P
μV
P-P
C
= 0.33μF
REF
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13).
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
μs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
0.6
HD(STA)
LOW
1.3
μs
0.6
μs
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
0.6
μs
0
0.9
μs
Data Set-Up Time
100
ns
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
(Note 12)
(Note 12)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
B
B
ns
f
μs
SU(STO)
BUF
1.3
μs
2631fb
7
LTC2631
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
LTC2631-8
LTC2631-10
LTC2631-12
LTC2631A-12
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
LSB
Monotonicity
V
V
= 5V, Internal Ref. (Note 4)
= 5V, Internal Ref. (Note 4)
CC
DNL
INL
Differential
0.5
0.5
1
1
1
1
CC
Nonlinearity
l
Integral
Nonlinearity
V
= 5V, Internal Ref. (Note 4)
0.05 0.5
0.2
1
2.5
0.5
LSB
CC
l
l
ZSE
Zero-Scale Error
Offset Error
V
CC
V
CC
V
CC
= 5V, Internal Ref., Code = 0
= 5V, Internal Ref. (Note 5)
= 5V, Internal Ref. (Note 5)
0.5
0.5
10
5
0.5
0.5
10
5
5
0.5
0.5
10
5
5
0.5
0.5
10
5
mV
mV
V
OS
5
5
V
V
OS
Temperature
μV/°C
OSTC
Coefficient
l
FSE
Full-Scale Error
V
V
= 5V, Internal Ref. (Note 15)
= 5V, Internal Ref. (Note 10)
C-Grade
I-Grade
H-Grade
0.08 0.4
0.08 0.4
0.08 0.4
0.08 0.4 %FSR
CC
CC
V
FSTC
Full-Scale
Voltage
Temperature
Coefficient
10
10
10
10
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
ppm/°C
l
l
Load Regulation
V
= 5V 10%, Internal Ref.
0.006 0.01
0.022 0.04
0.09 0.16
0.09 0.16 LSB/mA
CC
Mid-Scale, –10mA ≤ I
≤ 10mA
OUT
R
OUT
DC Output
Impedance
V
= 5V 10%, Internal Ref.
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
CC
Mid-Scale, –10mA ≤ I
≤ 10mA
OUT
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OUT
DAC Output Span
External Reference
Internal Reference
0 to V
V
V
REF
0 to 4.096
PSR
Power Supply Rejection
V
CC
= 5V 10%
–80
dB
I
Short-Circuit Output Current (Note 6)
V
FS
= V = 5.5V
CC
SC
l
l
Sinking
Zero-Scale; V
shorted to V
27
–28
48
–48
mA
mA
OUT
CC
Sourcing
Full-Scale; V
shorted to GND
OUT
Power Supply
l
V
Positive Supply Voltage
Supply Current (Note 7)
For Specified Performance
4.5
5.5
V
CC
l
l
I
CC
V
CC
V
CC
= 5V, V = 4.096V, External Reference
160
200
220
270
μA
μA
REF
= 5V, Internal Reference
l
l
I
Supply Current in Power-Down Mode
(Note 7)
V
CC
V
CC
= 5V, C-Grade, I-Grade
= 5V, H-Grade
0.6
0.6
1.8
4
μA
μA
SD
2631fb
8
LTC2631
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
l
l
Input Voltage Range
Resistance
0
V
V
kΩ
pF
CC
160
190
7.5
220
Capacitance
l
l
I
Reference Current, Power-Down Mode
DAC Powered Down
0.005
0.1
μA
REF
Reference Output
Output Voltage
2.032
2.048
10
2.064
V
ppm/°C
kΩ
Reference Temperature Coefficient
Output Impedance
0.5
10
Capacitive Load Driving
Short-Circuit Current
μF
V
CC
= 5.5V; REF Shorted to GND
4.3
mA
Digital I/O
l
l
l
V
V
V
Low Level Input Voltage (SDA and SCL) (Note 14)
High Level Input Voltage (SDA and SCL) (Note 11)
–0.5
0.7V
0.3V
V
V
V
IL
CC
IH
CC
Low Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
0.15V
IL(CAn)
CC
l
l
l
l
V
High Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
See Test Circuit 2
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
0.85V
V
kΩ
IH(CAn)
CC
R
R
R
Resistance from CAn (n = 0, 1)
10
10
INH
INL
INF
OL
to V to Set CAn = V
CC
CC
Resistance from CAn (n = 0, 1)
to GND to Set CAn = GND
kΩ
Resistance from CAn (n = 0, 1)
2
0
MΩ
to V or GND to Set CAn = Float
CC
l
l
V
Low Level Output Voltage
Output Fall Time
0.4
V
t
t
I
V = V
B
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 12)
l
Pulse Width of Spikes Suppressed by
Input Filter
0
50
ns
SP
IN
l
l
l
l
Input Leakage
0.1V ≤ V ≤ 0.9V
1
10
μA
pF
pF
pF
CC
IN
CC
C
C
C
I/O Pin Capacitance
(Note 8)
IN
Capacitive Load for Each Bus Line
400
10
B
External Capacitive Load on Address
Pin CAn (n = 0, 1)
CAn
2631fb
9
LTC2631
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
t
S
Settling Time
V
= 5V (Note 9)
CC
0.39% ( 1LSB at 8-Bits)
0.098% ( 1LSB at 10-Bits)
0.024% ( 1LSB at 12-Bits)
3.7
4.2
4.6
μs
μs
μs
Voltage-Output Slew Rate
Capacitance Load Driving
Glitch Impulse
1
V/μs
pF
500
3.0
300
At Mid-Scale Transition
External Reference
nV•s
kHz
Multiplying Bandwidth
Output Voltage Noise Density
e
n
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
210
200
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
20
20
650
670
μV
P-P
μV
P-P
μV
P-P
μV
P-P
C
= 0.33μF
REF
2631fb
10
LTC2631
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13).
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
μs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
0.6
HD(STA)
LOW
1.3
μs
0.6
μs
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
0.6
μs
0
0.9
μs
Data Set-Up Time
100
ns
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
(Note 12)
(Note 12)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
B
B
ns
f
μs
SU(STO)
BUF
1.3
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: High temperatures degrade operating lifetimes. Operating lifetime
Note 7: Digital inputs at 0V or V
Note 8: Guaranteed by design and not production tested.
Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 10: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
.
CC
is derated at temperatures greater than 105°C.
Note 11: Maximum V = V
+ 0.5V
CC(MAX)
IH
Note 4: Linearity and monotonicity are defined from code k to code
L
Note 12: C = capacitance of one bus line in pF
B
N
N
2 – 1, where N is the resolution and k is given by k = 0.016 • (2 / V ),
L
L
FS
Note 13: All values refer to V = V
and V = V
levels.
IL(MAX)
IH
IH(MIN)
IL
rounded to the nearest whole code. For V = 2.5V and N = 12, k = 26 and
FS
L
Note 14: Minimum V exceeds the Absolute Maximum rating. This
IL
linearity is defined from code 26 to code 4,095. For V = 4.096V and
FS
condition won’t damage the IC, but could degrade performance.
Note 15: Full-scale error is determined using the reference voltage
measured at the REF pin.
N = 12, k = 16 and linearity is defined from code 16 to code 4,095.
L
Note 5: Inferred from measurement at code 16 (LTC2631-12), code 4
(LTC2631-10) or code 1 (LTC2631-8), and at full-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
2631fb
11
LTC2631
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2631-L12 (Internal Reference, VFS = 2.5V)
Reference Output Voltage
vs Temperature
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.5
1.0
0.5
1.260
1.255
1.250
1.245
1.240
V
CC
= 3V
V
CC
= 3V
V
CC
= 3V
0
0
–0.5
–1.0
–0.5
–1.0
2048
3072
2048
3072
50
100
125 150
0
4095
0
4095
–50 –25
25
75
1024
1024
0
CODE
CODE
TEMPERATURE (°C)
2631 G01
2631 G02
2631 G03
Full-Scale Output Voltage
vs Temperature
INL vs Temperature
DNL vs Temperature
2.52
2.51
2.50
2.49
2.48
1.0
0.5
1.0
0.5
V
CC
= 3V
V
CC
= 3V
V
CC
= 3V
INL (POS)
DNL (POS)
DNL (NEG)
0
0
INL (NEG)
–0.5
–0.5
–1.0
–1.0
50
100
125 150
–50 –25
25
75
50
100
50
100
0
–50 –25
25
75
125 150
–50 –25
25
75
125 150
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2631 G06
2631 G04
2631 G05
Settling to 1LSB
Settling to 1LSB
3/4 SCALE TO 1/4 SCALE STEP
= 3V, V = 2.5V
V
CC
FS
9th CLOCK OF
3rd DATA BYTE
R
= 2k, C = 100pF
L
L
AVERAGE OF 256 EVENTS
SCL
2V/DIV
V
OUT
1LSB/DIV
4.1μs
3.6μs
V
OUT
1LSB/DIV
9th CLOCK OF
3rd DATA BYTE
1/4 SCALE TO 3/4 SCALE STEP
= 3V, V = 2.5V
V
CC
FS
SCL
2V/DIV
R
= 2k, C = 100pF
L
L
AVERAGE OF 256 EVENTS
2μs/DIV
2μs/DIV
2631 G08
2631 G07
2631fb
12
LTC2631
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2631-H12 (Internal Reference, VFS = 4.096V)
Reference Output Voltage
vs Temperature
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
0.5
2.068
2.058
2.048
2.038
2.028
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V
0.5
0
0
–0.5
–1.0
–0.5
–1.0
2048
3072
2048
3072
50
100
125 150
0
4095
0
4095
–50 –25
25
75
1024
1024
0
CODE
CODE
TEMPERATURE (°C)
2631 G09
2631 G10
2631 G11
Full-Scale Output Voltage
vs Temperature
INL vs Temperature
DNL vs Temperature
1.0
0.5
4.115
4.105
4.095
4.085
4.075
1.0
0.5
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V
INL (POS)
DNL (POS)
DNL (NEG)
0
0
INL (NEG)
–0.5
–0.5
–1.0
–1.0
50
100
50
–50 –25
25
75
125 150
–50 –25
25
75 100 125 150
50
100
0
0
–50 –25
25
75
125 150
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2631 G13
2631 G14
2631 G12
Settling to 1LSB
Settling to 1LSB
3/4 SCALE TO 1/4 SCALE STEP
= 5V, V = 4.095V
V
CC
FS
9th CLOCK OF
3rd DATA BYTE
R
= 2k, C = 100pF
L
L
AVERAGE OF 256 EVENTS
SCL
5V/DIV
V
OUT
1LSB/DIV
4.6μs
V
OUT
1LSB/DIV
3.9μs
9th CLOCK OF
3rd DATA BYTE
1/4 SCALE TO 3/4 SCALE STEP
= 5V, V = 4.095V
V
CC
FS
SCL
5V/DIV
R
= 2k, C = 100pF
L
L
AVERAGE OF 256 EVENTS
2μs/DIV
2μs/DIV
2631 G16
2631 G15
2631fb
13
LTC2631
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2631-10
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.5
1.0
0.5
V
CC
V
FS
= 5V
= 4.096V
V
CC
V
FS
= 5V
= 4.096V
INTERNAL REF.
INTERNAL REF.
0
0
–0.5
–1.0
–0.5
–1.0
512
768
512
768
0
1023
0
1023
256
256
CODE
CODE
2631 G17
2631 G18
LTC2631-8
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.5
0.50
0.25
0
V
CC
V
FS
= 3V
= 2.5V
V
CC
V
FS
= 3V
= 2.5V
INTERNAL REF.
INTERNAL REF.
0
–0.5
–1.0
–0.25
–0.50
128
192
128
192
0
255
0
255
64
64
CODE
CODE
2631 G19
2631 G20
LTC2631
Load Regulation
Current Limiting
10
8
0.20
0.15
0.10
0.05
0
V
CC
V
CC
V
CC
= 5V (LTC2631-H)
= 5V (LTC2631-L)
= 3V (LTC2631-L)
V
CC
V
CC
V
CC
= 5V (LTC2631-H)
= 5V (LTC2631-L)
= 3V (LTC2631-L)
6
4
2
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
INTERNAL REF.
INTERNAL REF.
CODE = MIDSCALE
CODE = MIDSCALE
–30
–20
–10
0
10
20
30
–30
–20
–10
0
10
20
30
I
(mA)
I
(mA)
OUT
OUT
2631 G21
2631 G22
2631fb
14
LTC2631
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2631
Offset Error vs Temperature
Gain Error vs VCC
Gain Error vs Temperature
3
2
0.4
0.3
0.4
0.3
EXTERNAL REF.
= 2.5V
EXTERNAL REF.
= 2.5V
V
V
REF
REF
0.2
0.2
1
0.1
0.1
0
0.0
0.0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G23
2.5
3
3.5
4
4.5
5
5.5
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G25
V
(V)
CC
2631 G24
Large-Signal Response
Mid-Scale-Glitch Impulse
Power-On Reset Glitch
LTC2631-L
9th CLOCK OF
3rd DATA BYTE
V
CC
SCL
5V/DIV
2V/DIV
V
OUT
LTC2631-H12, V = 5V:
CC
3.0nV-s TYP
0.5V/DIV
V
OUT
ZERO-SCALE
5mV/DIV
V
OUT
LTC2631-L12, V = 3V:
CC
2.1nV-s TYP
2mV/DIV
V
= V = 5V
FS
CC
1/4 SCALE TO 3/4 SCALE
2μs/DIV
2μs/DIV
200μs/DIV
2631 G26
2631 G27
2631 G28
Headroom at Rails
vs Output Current
Exiting Power-Down to Mid-Scale
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
CS/LD
2V/DIV
3V (LTC2631-L) SOURCING
V
OUT
0.5V/DIV
5V SINKING
3V (LTC2631-L) SINKING
LTC2631-H
4μs/DIV
0
1
2
3
4
5
6
7
8
9
10
2631 G30
I
(mA)
OUT
2631 G29
2631fb
15
LTC2631
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2631
Supply Current
vs REF_SEL Voltage
Supply Current vs Logic Voltage
0.5
0.4
0.3
0.2
0.1
1.2
1.0
0.8
0.6
0.4
0.2
0.0
SWEEP REF_SEL
BETWEEN 0V AND V
SWEEP SCL AND SDA
BETWEEN 0V AND V
CC
CC
V
= 5V
CC
V
= 5V
CC
V
= 3V
(LTC2631-L)
CC
V
= 3V
(LTC2631-L)
CC
0
1
2
3
4
5
0
1
2
3
4
5
REF_SEL VOLTAGE (V)
LOGIC VOLTAGE (V)
2631 G32
2631 G31
Multiplying Bandwidth
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
V
V
V
= 5V
REF(DC)
REF(AC)
CC
= 2V
= 0.2V
P-P
CODE = FULL SCALE
1k
10k
100k
1000k
FREQUENCY (Hz)
2631 G33
0.1Hz to 10Hz Voltage Noise
Noise Voltage vs Frequency
500
400
300
200
100
0
INTERNAL REF.
CODE = MIDSCALE
LTC2631-L, V = 4V
CC
INTERNAL REF.
CODE = MIDSCALE
LTC2631-H
10μV/DIV
(V = 5V)
CC
LTC2631-L
(V = 4V)
CC
1s/DIV
1k
10k
100k
100
1M
2631 G35
FREQUENCY (Hz)
2631 G34
2631fb
16
LTC2631
PIN FUNCTIONS
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to V , GND
REF (Pin 6): Reference Voltage Input or Output. When
CC
2
or leave it floating to select an I C slave address for the
External Reference mode is selected, REF is an input (0V
part (see Tables 1 and 2).
≤ V ≤ V ) where the voltage supplied sets the full-
REF CC
scale voltage. When Internal Reference is selected, the
10ppm/°C 1.25V (LTC2631-L) or 2.048V (LTC2631-H)
internal reference is available at the pin. This output may
be bypassed to GND with up to 10μF (0.33μF is recom-
mended), and must be buffered when driving external DC
load current.
SCL (Pin 2): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to V .
CC
SDA (Pin 3): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open-drain
N-channel output during acknowledgment. SDA requires
V
OUT
(Pin 7): DAC Analog Voltage Output.
CA1 (Pin 8, LTC2631-Z): Chip Address Bit 1. Tie this pin
2
a pull-up resistor or current source to V .
to V , GND or leave it floating to select an I C slave ad-
CC
CC
dress for the part (see Table 1).
GND (Pin 4): Ground.
REF_SEL (Pin 8, LTC2631-M): Selects default Reference
V
(Pin 5): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V
CC
CC
at power up. Tie to V to select the Internal Reference,
CC
(LTC2631-L) or 4.5V ≤ V ≤ 5.5V (LTC2631-H). Bypass
CC
or GND to select an External Reference. After power-up,
the logic state at this pin is ignored and the reference may
be changed only by software command.
to GND with a 0.1μF capacitor.
2631fb
17
LTC2631
BLOCK DIAGRAMS
LTC2631-Z
V
CC
REF
CA1
CA0
2
I C
INTERNAL
REFERENCE
ADDRESS
DECODE
SWITCH
CONTROL
DECODE LOGIC
RESISTOR
DIVIDER
SCL
SDA
2
I C
INTERFACE
DACREF
DAC
V
OUT
INPUT
REGISTER
DAC
REGISTER
GND
LTC2631-M
V
CC
REF
2
I C
CA0
ADDRESS
DECODE
INTERNAL
REFERENCE
REF_SEL
SWITCH
CONTROL
DECODE LOGIC
RESISTOR
DIVIDER
SCL
SDA
2
I C
INTERFACE
DACREF
DAC
V
OUT
INPUT
REGISTER
DAC
REGISTER
GND
2631 BD
2631fb
18
LTC2631
TEST CIRCUITS
Test Circuits for I2C Digital I/O (See Electrical Characteristics)
Test Circuit 1 Test Circuit 2
V
CC
R /R /R
INH INL INF
100ꢀ
/V
CAn
CAn
V
IH(CAn) IL(CAn)
GND
2631 TC
2631fb
19
LTC2631
TIMING DIAGRAMS
2631fb
20
LTC2631
OPERATION
The LTC2631 is a family of single voltage-output DACs in
8-leadThinSOTpackages.EachDACcanoperaterail-to-rail
using an external reference, or with its full-scale voltage
set by an integrated reference. Twelve combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero
or mid-scale), and full-scale voltage (2.5V or 4.096V) are
code,Nistheresolution,andV iseither2.5V(LTC2631-
REF
LM/LTC2631-LZ) or 4.096V (LTC2631-HM/LTC2631-HZ)
when in Internal Reference mode, and the voltage at REF
(Pin 6) when in External Reference mode.
2
I C Serial Interface
2
available. The LTC2631 is controlled using a 2-wire I C
interface.
The LTC2631 communicates with a host using the stan-
2
dard 2-wire I C interface. The Timing Diagrams (Figures 1
and 2) show the timing relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high when
the bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I C specifications. For an I C
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
Power-On Reset
TheLTC2631-HZ/LTC2631-LZcleartheoutputtozero-scale
when power is first applied, making system initialization
consistent and repeatable.
2
2
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2631
containscircuitrytoreducethepower-onglitch:theanalog
output typically rises less than 5mV above zero-scale
during power on if the power supply is ramped to 5V in
1msormore.Ingeneral,theglitchamplitudedecreasesas
the power supply ramp time is increased. See “Power-On
Reset Glitch” in the Typical Performance Characteristics
section.
The LTC2631 is a receive-only (slave) device. The master
can write to the LTC2631. The LTC2631 does not respond
to a read from the master.
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communi-
cationtoaslavedevicebytransmittingaSTARTcondition.
A START conditionis generated by transitioningSDA from
high to low while SCL is high.
The LTC2631-HM/LTC2631-LM provide an alternative
reset, setting the output to mid-scale when power is first
applied.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
Default reference mode selection is described in the Ref-
erence Modes section.
Power Supply Sequencing
2
another I C device.
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-
REF
CC
Acknowledge
ings). Particular care should be taken to observe these
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was properly received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
theAcknowledgeclockpulse.Theslave-receivermustpull
downtheSDAbuslineduringtheAcknowledgeclockpulse
so that it remains a stable LOW during the HIGH period
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at V (Pin 5) is in transition.
CC
Transfer Function
The digital-to-analog transfer function is
k
⎛
⎝
⎞
⎠
VOUT(IDEAL) ⎜
=
V
N ⎟ REF
2
where k is the decimal equivalent of the binary DAC input
of this clock pulse. The LTC2631 responds to a write by a
2631fb
21
LTC2631
OPERATION
master in this manner but does not acknowledge a read
operation; in that case, SDA is retained HIGH during the
period of the Acknowledge clock pulse.
The maximum capacitive load allowed on the CA0/CA1
address pins is 10pF, as these pins are driven during ad-
dress detection to determine if they are floating.
Chip Address
Write Word Protocol
The state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-
LZ) determines the slave address of the part. These pins
The master initiates communication with the LTC2631
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2631 acknowledges by
pulling the SDA pin low at the ninth clock if the 7-bit slave
address matches the address of the part (set by CA0/CA1)
or the global address. The master then transmits 3-bytes
of data. The LTC2631 acknowledges each byte of data by
pulling the SDA line low at the ninth clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2631 executes the command specified in
the 24-bit input word.
can each be set to any one of three states: V , GND or
CC
float. This results in nine (LTC2631-HZ/LTC2631-LZ) or
three (LTC2631-HM/LTC2631-LM) selectable addresses
for the part. The slave address assignments are shown
in Tables 1 and 2.
Table 1. Slave Address Map (LTC2631-Z)
CA1
GND
CA0
GND
A6
0
A5
0
A4
1
A3
0
A2
0
A1
0
A0
0
GND
FLOAT
0
0
1
0
0
0
1
If more than three data bytes are transmitted after a valid
7-bitslaveaddress,theLTC2631doesnotacknowledgethe
extra bytes of data (SDA is high during the 9th clock).
GND
V
0
0
1
0
0
1
0
CC
FLOAT
FLOAT
FLOAT
GND
0
0
1
0
0
1
1
FLOAT
0
1
0
0
0
0
0
TheformatofthethreedatabytesisshowninFigure3.The
first byte of the input word consists of the 4-bit command,
followed by four don’t-cares bits. The next two bytes
contain the 16-bit data word, which consists of the 12-,
10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8
don’t-caresbits(LTC2631-12,LTC2631-10andLTC2631-8
respectively). A typical LTC2631 write transaction is
shown in Figure 4.
V
0
1
0
0
0
0
1
CC
V
CC
V
CC
V
CC
GND
0
1
0
0
0
1
0
FLOAT
0
1
0
0
0
1
1
V
0
1
1
0
0
0
0
CC
GLOBAL ADDRESS
1
1
1
0
0
1
1
Table 2. Slave Address Map (LTC2631-M)
CA0
GND
A6
0
A5
0
A4
1
A3
0
A2
0
A1
0
A0
0
The command bit assignments (C3-C0) are shown in
Table 3. The first four commands in the table consist of
write and update operations. A write operation loads a
16-bit data word from the 32-bit shift register into the
input register. In an update operation, the data word is
copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
FLOAT
0
0
1
0
0
0
1
V
CC
0
0
1
0
0
1
0
GLOBAL ADDRESS
1
1
1
0
0
1
1
Inadditiontotheaddressselectedbytheaddresspins, the
partalsorespondstoaglobaladdress.Thisaddressallows
a common write to all LTC2631 parts to be accomplished
2
using one 3-byte write transaction on the I C bus. The
global address, listed at the end of Tables 1 and 2, is a 7-bit
hardwired address not selectable by CA0/CA1. If another
address is required, please consult the factory.
2631fb
22
LTC2631
OPERATION
Write Word Protocol for LTC2631
W
A
1ST DATA BYTE
A
2ND DATA BYTE
INPUT WORD
A
3RD DATA BYTE
A
P
S
SLAVE ADDRESS
Input Word (LTC2631-12)
C3
C1
X
X
X
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
C2
C0
X
X
X
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
Input Word (LTC2631-10)
C3
C1
X
X
X
X
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2ND DATA BYTE
X
X
X
X
C2
C0
1ST DATA BYTE
3RD DATA BYTE
Input Word (LTC2631-8)
C3
C1
X
X
D7 D6 D5 D4 D3 D2 D1 D0
2ND DATA BYTE
X
X
X
X
X
X
X
C2
C0
2631 F03
1ST DATA BYTE
3RD DATA BYTE
Figure 3. Command and Data Input Format
Table 3. Command Codes
COMMAND*
to the REF pin will improve noise performance; 0.33μF
is recommended, and up to 10μF can be driven without
oscillation. This output must be buffered when driving
external DC load current.
C3
0
C2
0
C1 C0
0
0
1
0
1
1
0
1
1
0
0
1
Write to Input Register
0
0
Update (Power Up) DAC Register
Write to and Update (Power Up) DAC Register
Power Down
Alternatively, the DAC can operate in External Reference
modeusingcommand0111.Inthismode,aninputvoltage
supplied externally to the REF pin provides the reference
0
0
0
1
0
1
Select Internal Reference
(0V ≤ V
≤ V ) and the supply current is reduced.
REF
CC
0
1
Select External Reference
External Reference mode is the power-on default for
LTC2631-HM/LTC2631-LM when REF_SEL is tied low.
*Command codes not shown are reserved and should not be used.
The reference mode of LTC2631-HZ/LTC2631-LZ can be
changed only by software command. The same is true for
LTC2631-HM/LTC2631-LMafterpower-on,afterwhichthe
logic state on REF_SEL is ignored.
Reference Modes
For applications where an accurate external reference is
notavailable,theLTC2631hasauser-selectable,integrated
reference. The LTC2631-LM/LTC2631-LZ provide a full-
scaleoutputof2.5V.TheLTC2631-HM/LTC2631-HZprovide
a full-scale output of 4.096V. The internal reference can be
useful in applications where the supply voltage is poorly
regulated.InternalReferencemodecanbeselectedbyusing
command 0110, and is the power-on default for LTC2631-
HZ/LTC2631-LZ, as well as for LTC2631-HM/LTC2631-LM
when REF_SEL is tied high.
Power-Down Mode
Forpower-constrainedapplications,theLTC2631’spower-
down mode can be used to reduce the supply current
whenever the DAC output is not needed. When in power
down, the buffer amplifier, bias circuit, and reference
circuit are disabled and draw essentially zero current. The
DAC output is put into a high-impedance state, and the
output pin is passively pulled to ground through a 200kΩ
resistor.InputandDACregistercontentsarenotdisturbed
during power down.
The 10ppm/°C, 1.25V (LTC2631-LM/LTC2631-LZ) or
2.048V (LTC2631-HM/LTC2631-HZ) internal reference
is available at the REF pin. Adding bypass capacitance
2631fb
23
LTC2631
OPERATION
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8μA
maximum (C and I grades) and the REF pin becomes high
impedance (typically > 1GΩ).
Similarly, limiting can occur near full-scale when the REF
pin is tied to V . If V = V and the DAC full-scale error
CC
REF
CC
(FSE) is positive, the output for the highest codes limits
at V , as shown in Figure 5c. No full-scale limiting can
CC
occur if V is less than V – FSE.
REF
CC
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 3. The
DAC is powered up and its voltage output is updated.
Normal settling is delayed while the bias, reference, and
amplifier circuits are re-enabled. When the REF pin output
is bypassed to GND with 1nF or less, the power-up delay
time is 20μs for settling to 12-bits. This delay increases
to 200μs for 0.33μF, and 10ms for 10μF.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2631 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω).NotethattheLTC2631isnomoresusceptibletothis
effect than any other parts of this type; on the contrary, it
allows layout-based performance improvements to shine
ratherthanlimitingattainableperformancewithexcessive
internal resistance.
Voltage Output
The LTC2631’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2631 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Charac-
teristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage-output device, the output is lim-
ited to voltages within the supply range.
SincetheanalogoutputoftheDACcannotgobelowground,
it may limit the lowest codes, as shown in Figure 5b.
2631fb
24
LTC2631
OPERATION
2631fb
25
LTC2631
OPERATION
POSITIVE
FSE
V
= V
CC
REF
V
= V
CC
REF
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
2631 F05
(c)
OUTPUT
VOLTAGE
0V
0
2,048
4,095
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2631fb
26
LTC2631
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
2.90 BSC
(NOTE 4)
0.52
MAX
0.65
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0802
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2631fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2631
TYPICAL APPLICATION
Programmable 5V Output
5V
0.1μF
5V
5
4
–
10V
7
1
0.1μF
LTC2054
2
3
8
9
10
+
0.1μF
6
M9
M3
M1
5
6
V
CC
V
CC
REF
1.7k
1.7k
8
3
REF_SEL
LT1991
V
= 5V
OUT
OUT
SDA
7
1
2
3
LTC2631A
-LM12
V
OUT
2
P1
P3
P9
REF
I C BUS
2
1
5
V
SCL
CA0
EE
4
CA0
GND
4
0.1μF
–10V
2631 TA03
RELATED PARTS
PART NUMBER
LTC1663
DESCRIPTION
Single 10-Bit V
Single 10-Bit V
COMMENTS
DAC in SOT-23
DAC in SOT-23
V
CC
CC
= 2.7V to 5.5V, 60μA, Internal Reference, SMBus Interface
OUT
OUT
2
LTC1669
V
= 2.7V to 5.5V, 60μA, Internal Reference, I C Interface
LTC2360-LT2362/
LTC2365-LTC2366
12-Bit SAR ADCs in TSOT23-6/TSOT23-8 Packages 100ksps/250ksps/500ksps/1Msps/3Msps Output Rates
LTC2450/LTC2452
LTC2451/LTC2453
16-Bit Single-Ended/Differential Delta Sigma ADCs
16-Bit Single-Ended/Differential Delta Sigma ADCs
SPI Interface, Tiny DFN Packages, 60Hz Output Rate
2
I C Interface, Tiny DFN and TSOT23-8 Packages, 60Hz Output Rate
LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit V
DACs in 16-Lead SSOP
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2601/LTC2611/LTC2621 Single 16-/14-/12-Bit V
DACs in 10-Lead DFN
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit V
DACs in 8-Lead MSOP
DACs in 16-Lead SSOP
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2604/LTC2614/LTC2624 Quad 16-/14-/12-Bit V
LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit V
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
2
DACs with I C Interface
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
OUT
2
I C Interface
2
LTC2606/LTC2616/LTC2626 Single 16-/14-/12-Bit V
DACs with I C Interface 270μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
OUT
2
I C Interface
2
LTC2609/LTC2619/LTC2629 Quad 16-/14-/12-Bit V
DACs with I C Interface
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output with
OUT
OUT
Separate V Pins for Each DAC
REF
LTC2630
LTC2640
Single 12-/10-/8-Bit V
Reference in SC70
DACs with 10ppm/°C
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output, SPI Interface
Single 12-/10-/8-Bit SPI V
Reference in ThinSOT
DACs with 10ppm/°C 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Selectable External Reference Mode, Rail-to-Rail Output, SPI Interface
OUT
2631fb
LT 1108 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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