LTC2635CMSE-HMX8#TRPBF

LTC2635

2

Quad 12-/10-/8-Bit I C V

OUT

DACs with 10ppm/°C Reference

Features

Description

The LTC^®2635 is a family of quad 12-, 10-, and 8-bit

voltage-output DACs with an integrated, high-accuracy,

low-drift reference in a 16-pin QFN or a 10-lead MSOP

package. It has rail-to-rail output buffers and is guaran-

teed monotonic. The LTC2635-L has a full-scale output

of 2.5V, and operates from a single 2.7V to 5.5V supply.

The LTC2635-H has a full-scale output of 4.096V, and

operates from a 4.5V to 5.5V supply. Each DAC can also

operate with an external reference, which sets the full-

scale output to the external reference voltage.

n

Integrated Precision Reference

2.5V Full-Scale 10ppm/°C (LTC2635-L)

4.096V Full-Scale 10ppm/°C (LTC2635-H)

n

Maximum INL Error: 2.5 LSꢀ (LTC2635-12)

n

Power-On-Reset to Zero-Scale/Mid-Scale/Hi-Z

n

Low Noise: 0.75mV 0.1Hz to 200kHz

P-P

n

Guaranteed Monotonic Over –40°C to 125°C

Automotive Temperature Range

n

Selectable Internal or External Reference

n

2.7V to 5.5V Supply Range (LTC2635-L)

n

Ultralow Crosstalk ꢀetween DACs (3nV•s)

2

These DACs communicate via a 2-wire I C-compatible

serialinterface.TheLTC2635operatesinboththestandard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). The LTC2635 incorporates a power-on reset

circuit. Options are available for reset to zero-scale, reset

tomid-scaleininternalreferencemode,resettomid-scale

in external reference mode, or reset with all DAC outputs

in a high-impedance state after power-up.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6891433,

6937178, 7414561.

n

Low Power: 0.6mA at 3V

Double-ꢀuffered Data Latches

n

Small 16-Pin 3mm × 3mm QFN and 10-Lead MSOP

Packages

applications

n

Mobile Communications

n

Process Control and Industrial Automation

n

Power Supply Margining

Portable Equipment

Automotive

n

Block Diagram

Integral Nonlinerity

2

REF

INTERNAL

REFERENCE

GND

V

= 3V

CC

INTERNAL REF.

SWITCH

V

REF

V

(REFLO)

CC

1

0

V

OUTA

V

OUTD

DAC A

DAC B

DAC D

DAC C

V

REF

V

OUTC

OUTB

–1

–2

(LDAC)

DECODE

POWER-ON

RESET

CA0

0

1024

2048

3072

4095

2

CODE

I C

(CA1)

(CA2)

2635 TA01

ADDRESS

DECODE

SCL

SDA

2

I C INTERFACE

2635 BD

( ) QFN PACKAGE ONLY

2635fb

ꢀ

LTC2635

aBsolute maximum ratings

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

CC

SCL, SDA, REFLO, LDAC.............................. –0.3V to 6V

V

, CA0, CA1, CA2...... –0.3V to Min (V + 0.3V, 6V)

OUTA-D

CC

REF .................................... –0.3V to Min (V + 0.3V, 6V)

MS Package...................................................... 300°C

CC

Operating Temperature Range

LTC2635C ................................................ 0°C to 70°C

LTC2635H (Note 3) ............................ –40°C to 125°C

pin conFiguration

TOP VIEW

16 15 14 13

V

1

2

3

4

5

10 GND

CC

OUTA

V

1

2

3

4

12

11

10

9

V

OUTA

OUTD

V

9

8

7

6

V

OUTD

OUTC

11

GND

OUTB

CA0

SCL

OUTB

OUTC

17

GND

REF

LDAC

REF

CA1

SDA

CA0

MSE PACKAGE

10-LEAD PLASTIC MSOP

5

6

7

8

T

= 150°C, θ = 35°C/W

JA

JMAX

EXPOSED PAD (PIN 11) IS GND, MUST ꢀE SOLDERED TO PCꢀ

UD PACKAGE

16-LEAD (3mm s 3mm) PLASTIC QFN

T

= 150°C, θ = 68°C/W

JA

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST ꢀE SOLDERED TO PCꢀ

2635fb

ꢁ

LTC2635

orDer inFormation

LTC2635

C

UD

–L

Z

12

#TR

PBF

LEAD FREE DESIGNATOR

PꢀF = Lead Free

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

RESOLUTION

12 = 12-ꢀit

10 = 10-ꢀit

8 = 8-ꢀit

POWER-0N RESET

MI = Reset to Mid-Scale in Internal Reference Mode

MX = Reset to Mid-Scale in External Reference Mode (LMX Only)

MO = Reset to Mid-Scale in Internal Reference Mode, DAC Outputs Hi-Z (LMO Only)

Z = Reset to Zero-Scale in Internal Reference Mode

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

UD = 16-Pin QFN

MSE = 10-Lead MSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2635fb

ꢂ

LTC2635

proDuct selection guiDe

PART MARKING*

POWER-ON

REFERENCE

MODE

VFS WITH INTERNAL

POWER-ON

RESET TO CODE

MAXIMUM

INL

PART NUMBER

QFN

MSOP

REFERENCE

RESOLUTION

V

CC

LTC2635-LMI12

LTC2635-LMI10

LTC2635-LMI8

LDZꢀ

LDZJ

LDZR

LTDZY

LTFꢀG

LTFꢀP

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LMX12

LTC2635-LMX10

LTC2635-LMX8

LDYZ

LDZH

LDZQ

LTDZX

LTFꢀF

LTFꢀN

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

External

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LZ12

LTC2635-LZ10

LTC2635-LZ8

LDYY

LDZG

LDZP

LTDZW

LTFꢀD

LTFꢀM

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LMO12**

LTC2635-LMO10**

LTC2635-LMO8**

LFꢀT

LFꢀV

LFꢀW

LTFꢀX

LTFꢀY

LTFꢀZ

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

High Impedance

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-HMI12

LTC2635-HMI10

LTC2635-HMI8

LDZF

LDZN

LDZV

LTFꢀC

LTFꢀK

LTFꢀS

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

4.5V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-HZ12

LTC2635-HZ10

LTC2635-HZ8

LDZC

LDZK

LDZS

LTDZZ

LTFꢀH

LTFꢀQ

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

4.5V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

*Above options are available in a 16-pin QFN package (LTC2635xUD) or 10-lead MSOP package (LTC2635xMSE).

**Contact Linear Technology for other Hi-Z options.

2635fb

ꢃ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

LTC2635-8

LTC2635-10

LTC2635-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN

TYP MAX MIN

TYP

MAX

UNITS

l

8

10

12

ꢀits

Monotonicity

V

= 3V, Internal Ref. (Note 4)

= 3V, Internal Ref., Code=0

= 3V, Internal Ref. (Note 5)

= 3V, Internal Ref.

CC

DNL

INL

Differential Nonlinearity

0.5

5

0.5

1

2.5

5

LSꢀ

mV

Integral Nonlinearity

Zero-Scale Error

Offset Error

0.05

0.5

10

0.2

0.5

10

1

0.5

10

ZSE

5

V

5

mV

OS

V

Temperature

OS

µV/°C

OSTC

Coefficient

l

GE

Gain Error

V

= 3V, Internal Ref.

0.2

0.8

0.2

0.8

0.2

0.8

%FSR

CC

Gain Temperature

Coefficient

= 3V, Internal Ref. (Note 10)

C-Grade

H-Grade

TC

CC

10

ppm/°C

10

Load Regulation

Internal Ref., Mid-Scale,

= 3V 10%,

l

0.009 0.016

0.035 0.064

0.14 0.256 LSꢀ/mA

V

CC

–5mA ≤ I

≤ 5mA

OUT

V

= 5V 10%,

CC

–10mA ≤ I

≤ 10mA

OUT

R

DC Output Impedance

Internal Ref., Mid-Scale,

= 3V 10%,

OUT

l

0.09 0.156

Ω

V

CC

–5mA ≤ I

≤ 5mA

OUT

V

= 5V 10%,

CC

–10mA ≤ I

≤ 10mA

OUT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DAC Output Span

External Reference

Internal Reference

0 to V

V

OUT

REF

0 to 2.5

PSR

Power Supply Rejection

V

= 3V 10% or 5V 10%

–80

dꢀ

CC

I

Short Circuit Output Current (Note 6)

V

= V = 5.5V

CC

SC

FS

l

Sinking

Zero-Scale; V

Shorted to V

27

–28

48

–48

mA

OUT

CC

Sourcing

Full-Scale; V

Shorted to GND

OUT

DAC I

DAC Output Current in High Impedance Mode MO Options Only

SD

l

Sinking

0.05

–0.001

2

–0.1

µA

Sourcing

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Specified Performance

2.7

5.5

V

CC

l

I

CC

V

= 3V, V = 2.5V, External Reference

0.5

0.6

0.7

0.8

0.9

mA

CC

REF

= 3V, Internal Reference

= 5V V = 2.5V, External Reference

REF

= 5V, Internal Reference

l

I

SD

Supply Current in Power-Down Mode

(Note 7)

V

= 5V, C-Grade

= 5V, H-Grade

1

20

30

µA

CC

2635fb

ꢄ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

l

Input Voltage Range

Resistance

1

V

kΩ

pF

CC

120

160

14

200

Capacitance

l

I

Reference Current, Power-Down Mode

DAC Powered Down

0.005

1.5

µA

REF

Reference Output

Output Voltage

1.24

–0.5

1.25

10

1.26

V

ppm/°C

kΩ

Reference Temperature Coefficient

Output Impedance

0.5

10

Capacitive Load Driving

Short Circuit Current

µF

V

CC

= 5.5V, REF Shorted to GND

2.5

mA

Digital I/O

l

V

Low Level Input Voltage

(SDA and SCL)

(Note 14)

0.3V

V

IL

CC

High Level Input Voltage

(SDA and SCL)

(Note 11)

0.7V

CC

IH

Low Level Input Voltage on CAn

(n = 0, 1,2)

See Test Circuit 1

See Test Circuit 2

Sink Current = 3mA

0.15V

V

IL(CAn)

IH(CAn)

CC

High Level Input Voltage on CAn

(n = 0, 1,2)

0.85V

V

CC

R

Resistance from CAn (n = 0, 1,2)

10

kΩ

MΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1,2)

to GND to Set CAn = GND

Resistance from CAn (n = 0, 1,2)

2

0

to V or GND to Set CAn = Float

CC

l

V

Low Level Output Voltage

Output Fall Time

0.4

V

t

I

V = V

ꢀ

to V = V

,

20+0.1C

250

ns

OF

O

IH(MIN)

O

IL(MAX)

ꢀ

C = 10pF to 400pF (Note 12)

l

Pulse Width of Spikes Suppressed

by Input Filter

0

50

ns

SP

IN

l

Input Leakage

0.1V ≤ V ≤ 0.9V

1

µA

pF

CC

IN

CC

C

I/O Pin Capacitance

(Note 8)

10

IN

Capacitive Load for Each ꢀus Line

400

10

ꢀ

External Capacitive Load on Address

Pin CAn (n = 0, 1,2)

CAn

2635fb

ꢅ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC Performance

t

Settling Time

V

= 3V (Note 9)

S

CC

0.39% ( 1LSꢀ at 8 ꢀits)

0.098% ( 1LSꢀ at 10 ꢀits)

0.024% ( 1LSꢀ at 12 ꢀits)

3.5

4.1

4.4

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1

V/µs

pF

500

2.1

2.6

320

At Mid-Scale Transition

nV • s

kHz

DAC-to-DAC Crosstalk

Multiplying ꢀandwidth

Output Voltage Noise Density

1 DAC Held at FS, 1 DAC Switched 0 to FS

External Reference

e

n

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

200

180

nV/√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

35

40

680

730

µV

P-P

µV

P-P

µV

P-P

µV

P-P

C

= 0.1µF

REF

timing characteristics The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V. (See Figure 1) (Note 13)

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

kHz

µs

l

f

t

SCL Clock Frequency

400

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

0.6

HD(STA)

LOW

1.3

µs

0.6

µs

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

µs

0

0.9

µs

Data Set-Up Time

100

ns

Rise Time of ꢀoth SDA and SCL Signals

Fall Time of ꢀoth SDA and SCL Signals

Set-Up Time for Stop Condition

ꢀus Free Time ꢀetween a Stop and Start Condition

(Note 12)

20 + 0.1C

0.6

300

ns

ꢀ

ns

f

ꢀ

µs

SU(STO)

ꢀUF

1.3

µs

th

rd

Falling Edge of 9 Clock of the 3 Input ꢀyte to LDAC

High or Low Transition

400

ns

1

l

t

LDAC Low Pulse Width

20

ns

2

2635fb

ꢆ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

LTC2635-8

LTC2635-10

TYP MAX MIN

LTC2635-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN

TYP

MAX

UNITS

l

8

10

12

ꢀits

Monotonicity

V

= 5V, Internal Ref. (Note 4)

= 5V, Internal Ref., Code=0

= 5V, Internal Ref. (Note 5)

= 5V, Internal Reference

CC

DNL

INL

Differential Nonlinearity

0.5

5

0.5

1

2.5

5

LSꢀ

mV

Integral Nonlinearity

Zero-Scale Error

Offset Error

0.05

0.5

10

0.2

0.5

10

1

0.5

10

ZSE

5

V

5

mV

OS

V

Temperature

OS

µV/°C

OSTC

Coefficient

l

GE

Gain Error

V

= 5V, Internal Reference

0.2

0.8

0.2

0.8

0.2

0.8

%FSR

CC

Gain Temperature

Coefficient

= 5V, Internal Ref. (Note 10)

C-Grade

H-Grade

TC

CC

10

ppm/°C

10

l

Load Regulation

DC Output

Internal Reference, Mid-Scale,

= 5V 10%,

0.006 0.01

0.022 0.04

0.09 0.16 LSꢀ/mA

V

CC

–10mA ≤ I

≤ 10mA

OUT

R

Internal Reference, Mid-Scale,

= 5V 10%,

0.09 0.156

Ω

OUT

V

CC

–10mA ≤ I

≤ 10mA

OUT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0 to V

MAX

UNITS

V

DAC Output Span

External Reference

Internal Reference

V

OUT

REF

0 to 4.096

PSR

Power Supply Rejection

V

= 5V 10%

–80

dꢀ

CC

I

Short Circuit Output Current (Note 6)

Sinking

Sourcing

= V = 5.5V

CC

SC

FS

l

Zero-Scale; V

Shorted to V

27

–28

48

–48

mA

OUT

CC

Full-Scale; V

Shorted to GND

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Specified Performance

4.5

5.5

V

CC

l

I

CC

V

= 3V, V = 4.096V, External Reference

0.6

0.7

0.8

0.9

mA

CC

REF

= 3V, Internal Reference

l

I

Supply Current in Power-Down Mode

(Note 7)

V

= 5V, C-Grade

= 5V, H-Grade

1

20

30

µA

SD

CC

2635fb

ꢇ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

l

Input Voltage Range

Resistance

1

V

kΩ

pF

CC

120

160

14

200

Capacitance

l

I

Reference Current, Power-Down Mode

DAC Powered Down

0.005

1.5

µA

REF

Reference Output

Output Voltage

2.032

2.048

10

2.064

V

ppm/°C

kΩ

Reference Temperature Coefficient

Output Impedance

0.5

10

Capacitive Load Driving

Short Circuit Current

µF

V

= 5.5V, REF Shorted to GND

4

mA

CC

Digital I/O

l

V

Low Level Input Voltage

(SDA and SCL)

(Note 14)

–0.5

0.7V

0.3V

V

IL

CC

High Level Input Voltage

(SDA and SCL)

(Note 11)

IH

CC

Low Level Input Voltage on CAn

(n = 0, 1,2)

See Test Circuit 1

See Test Circuit 2

Sink Current = 3mA

0.15V

V

IL(CAn)

IH(CAn)

CC

High Level Input Voltage on CAn

(n = 0, 1,2)

0.85V

V

CC

R

Resistance from CAn (n = 0, 1,2)

10

kΩ

MΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1,2)

to GND to Set CAn = GND

Resistance from CAn (n = 0, 1,2)

2

0

to V or GND to Set CAn = Float

CC

l

V

Low Level Output Voltage

Output Fall Time

0.4

V

t

I

V = V

O

to V = V

,

20+0.1C

250

ns

OF

IH(MIN)

O

IL(MAX)

ꢀ

C = 10pF to 400pF (Note 12)

ꢀ

l

Pulse Width of Spikes Suppressed

by Input Filter

0

50

ns

SP

IN

l

Input Leakage

0.1V ≤ V ≤ 0.9V

1

µA

pF

CC

IN

CC

C

I/O Pin Capacitance

(Note 8)

10

IN

Capacitive Load for Each ꢀus Line

400

10

ꢀ

External Capacitive Load on Address

Pin CAn (n=0, 1,2)

CAn

2635fb

ꢈ

LTC2635

electrical characteristics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC Performance

t

Settling Time

V

= 5V (Note 9)

S

CC

0.39% ( 1LSꢀ at 8 ꢀits)

0.098% ( 1LSꢀ at 10 ꢀits)

0.024% ( 1LSꢀ at 12 ꢀits)

3.9

4.3

5

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1

500

3

V/µs

pF

At Mid-Scale Transition

nV • s

kHz

DAC-to-DAC Crosstalk

Multiplying ꢀandwidth

Output Voltage Noise Density

1 DAC Held at FS, 1 DAC Switched 0 to FS

External Reference

3

320

e

n

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

250

230

nV/√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

35

50

680

750

µV

P-P

µV

P-P

µV

P-P

µV

P-P

C

= 0.1µF

REF

timing characteristics The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V. (See Figure 1) (Note 13)

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

kHz

µs

l

f

t

SCL Clock Frequency

400

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

0.6

HD(STA)

LOW

1.3

µs

0.6

µs

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

µs

0

0.9

µs

Data Set-Up Time

100

20+0.1C

0.6

ns

Rise Time of ꢀoth SDA and SCL Signals

Fall Time of ꢀoth SDA and SCL Signals

Set-Up Time for Stop Condition

ꢀus Free Time ꢀetween a Stop and Start Condition

(Note 12)

300

ns

ꢀ

ns

f

µs

SU(STO)

ꢀUF

1.3

µs

th

rd

Falling Edge of 9 Clock of the 3 Input ꢀyte to LDAC

High or Low Transition

400

ns

1

l

t

LDAC Low Pulse Width

20

ns

2

2635fb

ꢀ0

LTC2635

electrical characteristics

Note 7. Digital inputs at 0V or V

.

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device reliability

and lifetime.

CC

Note 8. Guaranteed by design and not production tested.

Note 9. Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and

3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.

Note 2. All voltages are with respect to GND.

Note 10. Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 3. High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C. Operating at temperatures

above 90°C and with V > 4V requires V slew rates to be no greater than

Note 11. Maximum V = V

+ 0.5V.

CC(MAX)

CC

IH

73mV/ms.

Note 12. C = capacitance of one bus line in pF.

ꢀ

N

Note 4. Linearity and monotonicity are defined from code k to code 2 – 1,

L

Note 13. All values refer to V = V

and V = V

levels.

N

IH

IH(MIN)

IL

IL(MAX)

where N is the resolution and k is given by k = 0.016 • (2 / V ),

L

FS

rounded to the nearest whole code. For V = 2.5V and N = 12, k = 26

FS

L

Note 14. Minimum V exceeds the Absolute Maximum rating. This condition

IL

and linearity is defined from code 26 to code 4,095. For V = 4.096V and

FS

won’t damage the IC, but could degrade performance.

N = 12, k = 16 and linearity is defined from code 16 to code 4,095.

L

Note 5. Inferred from measurement at code 16 (LTC2635-12), code 4

(LTC2635-10) or code 1 (LTC2635-8), and at full-scale.

Note 6. This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the specified maximum operating junction temperature may impair

device reliability.

2635fb

ꢀꢀ

LTC2635

typical perFormance characteristics ^T_A^{= 25°C, unless otherwise noted.}

LTC2635-L12 (Internal Reference, V_FS= 2.5V)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

1.0

0.5

V

= 3V

V

= 3V

CC

0

–0.5

–1.0

–0.5

–1.0

0

1024

2048

3072

4095

0

1024

2048

3072

4095

CODE

2635 G01

2635 G02

Reference Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

1.0

0.5

1.260

1.255

1.250

1.245

1.240

V

CC

= 3V

V

= 3V

V

= 3V

CC

0.5

0

INL (POS)

DNL (POS)

DNL (NEG)

0

–0.5

INL (NEG)

–1.0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

2635 G04

2635 G03

2635 G05

Settling to 1 LSB Rising

Settling to 1 LSB Falling

9th CLOCK OF 3rd

DATA BYTE

3/4 SCALE TO 1/4 SCALE STEP

= 3V, V = 2.5V

SCL

5V/DIV

V

CC

FS

V

OUT

R = 2k, C = 100pF

L

1 LSB/DIV

AVERAGE OF 256 EVENTS

4.4µs

3.3µs

V

OUT

1/4 SCALE TO 3/4 SCALE STEP

= 3V, V = 2.5V

9th CLOCK OF 3rd

DATA BYTE

1 LSB/DIV

V

CC

FS

SCL

5V/DIV

R = 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2635 G06

2635 G07

2µs/DIV

2635fb

ꢀꢁ

LTC2635

typical perFormance characteristics T_A= 25°C, unless otherwise noted.

LTC2635-H12 (Internal Reference, V_FS= 4.096V)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

V

= 5V

V

= 5V

CC

0.5

0

–0.5

–1.0

–0.5

–1.0

0

1024

2048

3072

4095

0

1024

2048

3072

4095

CODE

2635 G08

2635 G09

Reference Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

1.0

0.5

1.0

2.068

2.058

2.048

2.038

2.028

V

= 5V

V

CC

= 5V

CC

V

= 5V

CC

INL (POS)

0.5

0

DNL (POS)

DNL (NEG)

0

INL (NEG)

–0.5

–1.0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

2635 G10

2635 G11

2635 G12

Settling to 1 LSB Rising

Settling to 1 LSB Falling

3/4 SCALE TO

9th CLOCK OF 3rd

DATA BYTE

1/4 SCALE STEP

SCL

5V/DIV

V

= 5V, V = 4.095V

CC

FS

V

R

L

= 2k, C = 100pF

L

OUT

1 LSB/DIV

AVERAGE OF 256 EVENTS

3.9µs

5µs

9th CLOCK OF 3rd

DATA BYTE

V

SCL

5V/DIV

OUT

1/4 SCALE TO 3/4 SCALE STEP

= 5V, V = 4.095V

1 LSB/DIV

V

CC

FS

R = 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2635 G13

2635 G14

2µs/DIV

2635fb

ꢀꢂ

LTC2635

typical perFormance characteristics ^T_A^{= 25°C, unless otherwise noted.}

LTC2635-10

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

1.0

0.5

V

CC

V

FS

= 3V

= 2.5V

V

CC

V

FS

= 3V

= 2.5V

INTERNAL REF

0

–0.5

–1.0

–0.5

–1.0

0

256

512

768

1023

0

256

512

768

1023

CODE

2635 G15

2635 G16

LTC2635-8

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

0.50

0.25

0

0.50

0.25

0

V

CC

V

FS

= 3V

= 2.5V

V

CC

V

FS

= 3V

= 2.5V

INTERNAL REF

–0.25

–0.50

–0.25

–0.50

0

64

128

192

255

0

64

128

192

255

CODE

2635 G17

2635 G18

LTC2635

Load Regulation

Current Limiting

Offset Error vs Temperature

0.20

0.15

0.10

0.05

0

3

2

10

V

CC

V

CC

V

CC

= 5V (LTC2635-H)

= 5V (LTC2635-L)

= 3V (LTC2635-L)

V

CC

V

CC

V

CC

= 5V (LTC2635-H)

= 5V (LTC2635-L)

= 3V (LTC2635-L)

8

6

4

1

2

0

–2

–4

–6

–8

–10

–0.05

–0.01

–0.15

–0.20

–1

–2

–3

INTERNAL REF.

CODE = MID-SCALE

INTERNAL REF.

CODE = MID-SCALE

–30

–20

–10

0

10 20 30

–50 –25

0

25 50 75 100 125 150

–30

–20

–10

0

10 20 30

I

(mA)

TEMPERATURE (°C)

I

(mA)

OUT

2635 G20

2635 G21

2635 G19

2635fb

ꢀꢃ

LTC2635

typical perFormance characteristics ^T_A^{= 25°C, unless otherwise noted.}

LTC2635

Large-Signal Response

Mid-Scale Glitch Impulse

Power-On Reset Glitch

LTC2635-L

9th CLOCK OF 3rd

DATA BYTE

SCL

5V/DIV

V

CC

2V/DIV

V

OUT

LTC2635-H12, V = 5V

CC

3nV•s TYP

0.5V/DIV

ZERO SCALE

V

OUT

5mV/DIV

LTC2635-L12, V = 3V

CC

2.1nV•s TYP

V

= V = 5V

CC

FS

1/4 SCALE to 3/4 SCALE

2635 G23

2µs/DIV

200µs/DIV

2635 G22

2635 G24

Headroom at Rails vs

Output Current

Exiting Power-Down to Mid-Scale

Power-On Reset to Mid-Scale

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 5V

CC

5V SOURCING

INTERNAL

REFERENCE

V

CC

2V/DIV

SCL

5V/DIV

9th CLOCK OF 3rd

DATA BYTE

3V (LTC2635-L) SOURCING

LTC2635-H

DACs A-C IN

POWER-DOWN

MODE

V

OUT

0.5V/DIV

5V SINKING

3V (LTC2635-L) SINKING

LTC2635-L

V

OUT

0.5V/DIV

LTC2635-H

2635 G26

5µs/DIV

200µs/DIV

0

1

2

3

4

5

6

7

8

9

10

2635 G27

I

(mA)

OUT

2635 G25

Exiting Power-Down for Hi-Z

Option

Supply Current vs Logic Voltage

1.6

1.4

1.2

1.0

0.8

0.6

0.4

SWEEP SDA, SCL

BETWEEN

9th CLOCK OF 3rd

DATA BYTE

0V AND V

CC

SCL

5V/DIV

DAC OUTPUT SET

TO MID-SCALE

HIGH-IMPEDANCE

(POWER-DOWN) MODE

V

= 5V

CC

V

OUT

500mV/DIV

V

= 3V

CC

(LTC2635-L)

2635 G29

2µs/DIV

0

1

2

3

4

5

LTC2635-LMO, V = 3V

CC

LOGIC VOLTAGE (V)

2635 G28

DAC OUTPUT DRIVEN BY

1V SOURCE THROUGH

15k RESISTOR

2635fb

ꢀꢄ

LTC2635

typical perFormance characteristics ^T_A^{= 25°C, unless otherwise noted.}

LTC2635

Mulitplying Bandwidth

Noise Voltage vs Frequency

Gain Error vs Reference Input

2

0

1.0

0.8

500

400

300

200

100

0

V

= 5V

CC

V

= 5.5V

CC

CODE = MID-SCALE

INTERNAL REF

GAIN ERROR OF 4 CHANNELS

–2

0.6

–4

0.4

–6

0.2

–8

0

LTC2635-H

–10

–12

–14

–16

–18

–0.2

–0.4

–0.6

–0.8

–1.0

LTC2635-L

V

= 5V

REF(DC)

REF(AC)

CODE = FULL-SCALE

CC

= 2V

= 0.2V

P-P

1k

10k

100k

1M

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

100

1k

10k

100k

1M

FREQUENCY (Hz)

REFERENCE VOLTAGE (V)

FREQUENCY (Hz)

2635 G31

2635 G33

2634 G32

0.1Hz to 10Hz Voltage Noise

DAC-to-DAC Crosstalk (Dynamic)

Gain Error vs Temperature

1.0

0.5

V

= 5V, V = 2.5V

FS

CC

9th CLOCK OF 3rd

DATA BYTE

CODE = MID-SCALE

INTERNAL REF

SCL

5V/DIV

1 DAC

SWITCH 0-FS

2V/DIV

10µV/DIV

0

V

OUT

–0.5

2mV/DIV

LTC2635-H12, V = 5V

CC

3nV•s TYPICAL C =0.1µF

REF

–1.0

2635 G35

2µs/DIV

1s/DIV

–50 –25

0

25 50 75 100 125 150

2635 G34

TEMPERATURE (°C)

2635 G36

2635fb

ꢀꢅ

LTC2635

pin Functions ^(MSOP/QFN)

V

(Pin 1/Pin 16): Supply Voltage Input. 2.7V ≤ V

≤

REF (Pin 7/Pin 10): Reference Voltage Input or Output.

CC

5.5V (LTC2635-L) or 4.5V ≤ V ≤ 5.5V (LTC2635-H).

When External Reference mode is selected, REF is an

CC

ꢀypass to GND with a 0.1µF capacitor.

input (1V ≤ V

≤ V ) where the voltage supplied sets

REF CC

thefull-scaleDACoutputvoltage.WhenInternalReference

is selected, the 10ppm/°C 1.25V (LTC2635-L) or 2.048V

(LTC2635-H)internalreference(halffull-scale)isavailable

at the pin. This output may be bypassed to GND with up

to 10µF, and must be buffered when driving an external

DC load current.

V

to V

(Pins 2, 3, 8, 9/Pins 1, 2, 11, 12): DAC

OUTA

OUTD

Analog Voltage Outputs.

LDAC (Pin 3, QFN Only): Asynchronous DAC Update. A

falling edge on this input after four bytes (slave address

byte plus three data bytes) have been written into the part

immediately updates the DAC registers with the contents

of the input registers (similar to a software update). A

low on this input without a complete 32-bit (four bytes

including the slave address) data write transfer to the part

does not update the DAC output. A low on the LDAC pin

powers up the DACs. A software power down command

is ignored if LDAC is low.

DNC (Pins 6, 15, QFN Only): Do Not Connect These

Pins.

CA2 (Pin 7, QFN Only): Chip Address ꢀit 2. Tie this pin to

2

V , GND or leave it ﬂoating to select an I C slave address

CC

for the part (see Table 1).

CA1 (Pin 9, QFN Only): Chip Address ꢀit 1. Tie this pin to

2

CA0 (Pin 4/Pin 4): Chip Address ꢀit 0. Tie this pin to V ,

V , GND or leave it ﬂoating to select an I C slave address

CC

2

GND or leave it ﬂoating to select an I C slave address for

for the part (see Table 1).

the part (see Tables 1 and 2).

GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad

Pin 17): Ground. Must be soldered to PCꢀ ground.

SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted

into the SDA pin at the rising edges of the clock. This

high-impedance pin requires a pull-up resistor or current

REFLO (Pin 13, QFN Only): Reference Low Pin. The volt-

age at this pin sets the zero-scale voltage of all DACs. This

pin must be tied to GND.

source to V .

CC

SDA (Pin 6/Pin 8): Serial Data ꢀidirectional Pin. Data is

shifted into the SDA pin and acknowledged by the SDA

pin. This pin is high impedance while data is shifted in.

OpendrainN-channeloutputduringacknowledgment.SDA

requires a pull-up resistor or current source to V .

CC

2635fb

ꢀꢆ

LTC2635

Block Diagram

REF

INTERNAL

REFERENCE

GND

SWITCH

V

REF

V

(REFLO)

CC

V

OUTA

OUTD

DAC A

DAC B

DAC D

DAC C

V

REF

V

REF

V

OUTC

OUTB

(LDAC)

DECODE

POWER-ON

RESET

CA0

2

I C

ADDRESS

DECODE

(CA1)

(CA2)

SCL

SDA

2

I C INTERFACE

2635 BD

( ) QFN PACKAGE ONLY

2635fb

ꢀꢇ

LTC2635

test circuits

Test Circuits for I²C Digital I/O (See Electrical Characteristics)

Test Circuit 1

Test Circuit 2

V

DD

100Ω

/V

CAn

R

/R /R

INH INL INF

CAn

V

IH(CAn) IL(CAn)

2635 TC01

2635 TC02

GND

timing Diagrams

SDA

t

SU(DAT)

t

BUF

t

f

t

SP

t

r

t

LOW

t

r

HD(STA)

r

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

S

HIGH

Sr

P

S

t

HD(DAT)

2635 F01

ALL VOLTAGE LEVELS REFER TO V

AND V

LEVELS

IH(MIN)

IL(MAX)

Figure 1. I²C Timing

2635fb

ꢀꢈ

LTC2635

timing Diagrams

SLAVE ADDRESS

START

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

SDA

SCL

X

5

X

7

X

8

A6 A5 A4 A3 A2 A1 A0

W

ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK

ACK

9

ACK

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

1

2

3

4

6

t

1

t

2

LDAC

2635 F02a

Figure 2a. Typical LTC2635 Write Transaction

9TH CLOCK

OF 3RD

DATA BYTE

SCL

t

1

LDAC

2635 F02b

Figure 2b. LTC2635 LDAC Timing (QFN Package Only)

2635fb

ꢁ0

LTC2635

operation

The LTC2635 is a family of quad voltage output DACs in

16-pin QFN and 10-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10-, and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), DAC

power-down output load (high impedance or 200kΩ),

and full-scale voltage (2.5V or 4.096V) are available. The

taken to observe these limits during power supply turn-

on and turn-off sequences, when the voltage at V is in

CC

transition.

Transfer Function

The digital-to-analog transfer function is





^N

k

V_OUT(IDEAL)

=

V_REF– V_REFLO+ V



REFLO

(

)





2

LTC2635 is controlled using a 2-wire I C interface.

where k is the decimal equivalent of the binary DAC input

Power-On Reset

code,Nistheresolution,andV iseither2.5V(LTC2635-

REF

The LTC2635-HZ/-LZ clear the output to zero-scale when

power is ﬁrst applied, making system initialization con-

sistent and repeatable.

LMI/-LMX/-LMO/-LZ)or4.096V(LTC2635-HMI/-HZ)when

in Internal Reference mode, and the voltage at REF when

in External Reference mode.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2635

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

2

I C Serial Interface

The LTC2635 communicates with a host using the stan-

dard 2-wire I C interface. The timing diagrams (Figures

2

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

these pull-up resistors is dependent on the power supply

andcanbeobtainedfromtheI Cspeciﬁcations. ForanI C

bus operating in the fast mode, an active pull-up will be

necessary if the bus capacitance is greater than 200pF.

2

The LTC2635-HMI/-LMI/-LMX provide an alternative

reset, setting the output to mid-scale when power is ﬁrst

applied. The LTC2635-LMI and LTC2635-HMI power

up in internal reference mode, with the output set to a

mid-scale voltage of 1.25V and 2.048V, respectively. The

LTC2635-LMX power-up in external reference mode, with

the output set to mid-scale of the external reference. The

LTC2635-LMO powers up in internal reference mode with

all the DAC channels placed in the high-impedance state

(powered-down). Input and DAC registers are set to the

mid-scalecode,andonlytheinternalreferenceispowered

up, causing supply current to be typically 100µA upon

power up. Default reference mode selection is described

in the Reference Modes section.

The LTC2635 is a receive-only (slave) device. The master

can write to the LTC2635. The LTC2635 will not acknowl-

edge (NAK) a read request from the master.

START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

ASTARTconditionisgeneratedbytransitioningSDAfrom

high to low while SCL is high.

When the master has ﬁnished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

Power Supply Sequencing

The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must

2

be kept within the range –0.3V ≤ V

≤ V + 0.3V (see

REF

CC

another I C device.

Absolute Maximum Ratings). Particular care should be

2635fb

ꢁꢀ

LTC2635

operation

Acknowledge

Table 1. Slave Address Map (QFN Package)

CA2

CA1

CA0

A6

0

1

A5

0

1

0

1

A4

1

0

1

0

1

0

1

A3

0

A2

0

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

The Acknowledge (ACK) signal is used for handshaking

between the master and the slave. An ACK (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was properly received. The ACK

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the ACK clock pulse.

The slave-receiver must pull down the SDA bus line dur-

ing the ACK clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse. The LTC2635

responds to a write by a master in this manner but does

not acknowledge a read operation; in that case, SDA is

retained HIGH during the period of the ACK clock pulse.

GND

GND FLOAT

GND

V

CC

FLOAT GND

FLOAT FLOAT

FLOAT

V

CC

V

CC

GND

V

FLOAT

CC

V

CC

V

CC

FLOAT GND

GND

FLOAT GND FLOAT

FLOAT GND

V

CC

Chip Address

FLOAT FLOAT GND

FLOAT FLOAT FLOAT

The state of pins CA0, CA1 and CA2 (CA1 and CA2 are

only available on the QFN package) determines the slave

address of the part. These pins can be each set to any

FLOAT FLOAT

V

CC

FLOAT

V

CC

V

CC

V

CC

GND

FLOAT

one of three states: V , GND or ﬂoat. This results in 27

CC

(QFNPackage)or3(MSOPPackage)selectableaddresses

for the part. The slave address assignments are shown

in Tables 1 and 2.

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND

GND FLOAT

GND

V

CC

In addition to the address selected by the address pins,

the part also responds to a global address. This address

allows a common write to all LTC2635 parts to be ac-

complished using one 3-byte write transaction on the

FLOAT GND

FLOAT FLOAT

FLOAT

V

CC

2

V

CC

V

CC

V

CC

GND

I C bus. The global address, listed at the end of Tables

FLOAT

1 and 2, is a 7-bit hardwired address not selectable by

CA0, CA1 or CA2. If another address is required, please

consult the factory.

V

CC

GLOꢀAL ADDRESS

Themaximumcapacitiveloadallowedontheaddresspins

(CA0,CA1andCA2)is10pF,asthesepinsaredrivenduring

address detection to determine if they are ﬂoating.

Table 2. Slave Address Map (MSOP Package)

CA0

GND

A6

0

A5

0

A4

1

A3

0

A2

A1

A0

0

1

FLOAT

0

1

0

1

V

0

1

0

CC

GLOꢀAL ADDRESS

1

0

1

2635fb

ꢁꢁ

LTC2635

operation

Write Word Protocol

Table 3. Command Codes

COMMAND*

The master initiates communication with the LTC2635

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2635 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

or CA2) or the global address. The master then transmits

threebytesofdata. TheLTC2635acknowledgeseachbyte

of data by pulling the SDA line low at the 9th clock of each

data byte transmission. After receiving three complete

bytes of data, the LTC2635 executes the command speci-

ﬁed in the 24-bit input word.

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All

Write to and Update (Power Up) DAC Register n

Power Down n

Power Down Chip (All DAC’s and Reference)

Select Internal Reference (Power Up Reference)

Select External Reference (Power Down Internal

Reference)

1

No Operation

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2635 does not acknowledge

(NAK) the extra bytes of data (SDA is high during the 9th

clock).

*Command codes not shown are reserved and should not be used.

Table 4. Address Codes

ADDRESS (n)*

TheformatofthethreedatabytesisshowninFigure3.The

ﬁrstbyteoftheinputwordconsistsofthe4-bitcommand,

followed by the 4-bit DAC address. The next two bytes

contain the 16-bit data word, which consists of the 12-,

10- or 8-bit input code, MSꢀ to LSꢀ, followed by 4, 6 or 8

don’t-care bits (LTC2635-12, -10 and -8, respectively). A

typical LTC2635 write transaction is shown in Figure 4.

A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

DAC A

DAC ꢀ

DAC C

DAC D

ALL DACs

* Address codes not shown are reserved and should not be used.

The command bit assignments (C3-C0) and address (A3-

A0) assignments are shown in Tables 3 and 4. The ﬁrst

four commands in the table consist of write and update

operations. A write operation loads a 16-bit data word

from the 32-bit shift register into the input register. In an

update operation, the data word is copied from the input

register to the DAC register. Once copied into the DAC

register, the data word becomes the active 12-, 10-, or

8-bit input code, and is converted to an analog voltage at

the DAC output. Write to and Update combines the ﬁrst

two commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the ꢀlock Diagram.

Reference Modes

For applications where an accurate external reference is

either not available, or not desirable due to limited space,

the LTC2635 has a user-selectable, integrated reference.

The integrated reference voltage is internally ampliﬁed by

2x to provide the full-scale DAC output voltage range. The

LTC2635-LMI/-LMX/-LMO/-LZprovidesafull-scaleoutput

of2.5V.TheLTC2635-HMI/-HZprovidesafull-scaleoutput

of 4.096V. The internal reference can be useful in applica-

tionswherethesupplyvoltageispoorlyregulated.Internal

Referencemodecanbeselectedbyusingcommand0110b,

and is the power-on default for LTC2635-HZ/-LZ, as well

as for LTC2635-HMI/-LMI/-LMO.

2635fb

ꢁꢂ

LTC2635

operation

Write Word Protocol for LTC2635

S

W

ACK

A1

1STDATABYTE

ACK

2NDDATABYTE

INPUT WORD

ACK

D5

3RDDATABYTE

ACK

D1

X

P

SLAVE ADDRESS

Input Word (LTC2635-12)

C3

A3

A2

A0

D8

C1

D7

D6

D4

D2

D4

D11 D10 D9

D3

D1

X

D2

D0

X

D0

X

C2

C0

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2635-10)

X

A3

C0

A2

D6

C3

C2

A1

D5

D3

D1

D2

D0

D9

D7

D8

D6

D7

D5

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2635-8)

A3

C0

D4

X

C3

C2

D3

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

2635 F03

Figure 3. Command and Data Input Format

The10ppm/°C,1.25V(LTC2635-LMI/-LMX/-LMO/-LZ)or

2.048V(LTC2635-HMI/-HZ)internalreferenceisavailable

at the REF pin. Adding bypass capacitance to the REF pin

will improve noise performance; and up to 10µF can be

driven without oscillation. This output must be buffered

when driving an external DC load current.

Power-Down Mode

Forpower-constrainedapplications,power-downmodecan

be used to reduce the supply current whenever less than

four DAC outputs are needed. When in power-down, the

buffer ampliﬁers, bias circuits, and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC ampliﬁer outputs are put into a high-impedance

state, and the output pins are passively pulled to ground

through individual 200k resistors (LTC2635-LMI/-LMX/

-LZ/-HMI/-HZ). For the LTC2635-LMO options, the out-

put pins are not passively pulled to ground, but are also

placed in a high-impedance state (open-circuited state)

during power-down, typically drawing less than 0.1µA.

TheLTC2635-LMOoptionspower-upwithallDACoutputs

in this high-impedance state. They remain that way until

given a software or hardware update command. For all

LTC2635 options, input- and DAC-register contents are

not disturbed during power-down.

Alternatively, the DAC can operate in External Reference

modeusingcommand0111b.Inthismode,aninputvoltage

supplied externally to the REF pin provides the reference

(1V ≤ V ≤ V ) and the supply current is reduced. The

REF

CC

externalreferencevoltagesuppliedsetsthefull-scaleDAC

output voltage. External Reference mode is the power-on

default for LTC2635-LMX.

ThereferencemodeofLTC2635-HZ/-LZ/-HMI/-LMI/-LMO

(Internal Reference power-on default), can be changed by

software command after power up. The same is true for

LTC2635-LMX (External Reference power-on default).

2635fb

ꢁꢃ

LTC2635

operation

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combi-

nation with the appropriate DAC address, (n). The supply

current is reduced approximately 20% for each DAC

powered down. The integrated reference is automatically

powered down when external reference is selected using

command 0111b. In addition, all the DAC channels and the

integrated reference together can be put into power-down

modeusingPowerDownChipcommand0101b. Whenthe

integrated reference is in power-down mode, the REF pin

becomeshighimpedance (typically > 1GΩ). Forall power-

down commands the 16-bit data word is ignored.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change

in units from LSꢀ/mA to Ω. The ampliﬁer’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph Headroom at Rails

vs. Output Current in the Typical Performance Charac-

teristics section.

Normal operation resumes after executing any command

that includes a DAC update, (as shown in Table 1) or pull-

ing the asynchronous LDAC pin low (QFN package only).

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state

is powered up and updated, normal settling is delayed. If

less than four DACs are in a powered-down state prior to

the update command, the power-up delay time is 10µs.

However, if all four DACs and the integrated reference are

powereddown,thenthemainbiasgenerationcircuitblock

has been automatically shut down in addition to the DAC

ampliﬁersandreferencebuffers.Inthiscase,thepowerup

delay time is 12µs. The power-up of the integrated refer-

ence depends on the command that powered it down. If

the reference is powered down using the Select External

Reference Command (0111b), then it can only be powered

backupusingSelectInternalReferenceCommand(0110b).

However, if the reference was powered down using Power

Down Chip Command (0101b), then in addition to Select

Internal Reference Command (0110b), any command (in

software or using the LDAC pin) that powers up the DACs

will also power up the integrated reference.

The ampliﬁer is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is lim-

ited to voltages within the supply range.

SincetheanalogoutputoftheDACcannotgobelowground,

it may limit for the lowest codes as shown in Figure 5b.

Similarly, limiting can occur near full-scale when the REF

. If V = V and the DAC full-scale error

pin is tied to V

CC

REF

CC

(FSE) is positive, the output for the highest codes limits

at V , as shown in Figure 5c. No full-scale limiting can

CC

occur if V

is less than V – FSE.

REF

CC

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting can

occur.

Board Layout

ThePCboardshouldhaveseparateareasfortheanalogand

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2635 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2635 is no more susceptible to

Voltage Output

The LTC2635’s integrated rail-to-rail ampliﬁer has guar-

anteed load regulation when sourcing or sinking up to

10mA at 5V, and 5mA at 3V.

Load regulation is a measure of the ampliﬁer’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSꢀ/mA.

2635fb

ꢁꢄ

LTC2635

operation

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

analog ground, digital ground, and power ground. When

the LTC2635 is sinking large currents, this current ﬂows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

It is sometimes necessary to interrupt the ground plane

to conﬁne digital ground currents to the digital portion

of the plane. When doing this, make the gap in the plane

only as long as it needs to be to serve its purpose and

ensure that no traces cross over the gap.

SLAVE ADDRESS

COMMAND/ADDRESS

MS DATA

LS DATA

A6 A5 A4 A3 A2 A1 A0

W

C3 C2 C1 C0 A3 A2 A1 A0

D11 D10 D9 D8 D7 D6 D5 D4

D3 D2 D1 D0

X

6

X

7

X

8

STOP

START

SDA

SCL

A6 A5 A4 A3 A2 A1 A0

W

ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK

ACK

9

ACK

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

1

2

3

4

5

FULL-SCALE

VOLTAGE

V

OUT

ZERO-SCALE

VOLTAGE

X = DON’T CARE

2635 F04

Figure 4. Typical LTC2635 Input Waveform—Programming DAC Output for Full-Scale

2635fb

ꢁꢅ

LTC2635

operation

POSITIVE

FSE

V

REF

= V

CC

V

= V

CC

REF

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

2635 F05

OUTPUT

VOLTAGE

(c)

0V

0

2,048

4,095

INPUT CODE

(a)

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

Figure 5. Effects of Rail-to-Rail On a DAC Transfer Curve (Shown for 12 Bits).

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

2635fb

ꢁꢆ

LTC2635

application inFormation

Voltage Margining Application with LTC3850 (1.2V 5%) –LTC2635– LMO Option Only

V

IN

6.5V TO 14V

0.1µF

4.7µF

2.2Ω

100k

0.1µF

INTV

PGOOD

V

CC

IN

I

TG1

LIM

0.1µF

10k

BOOST1

SW1

FREQ

2.2µH

0.008Ω

V

OUT

1.2V 5ꢀ

LTC3850EUF

3.32k

1nF

BG1

PGND

10Ω

I

TH1

+

SENSE

RUN1

1nF

500kHz

MODE/PLLIN

TK/SS1

1nF

100pF

–

SENSE

10k

10nF

V

FB1

SGND

15pF

63.4k

5V

2635 TA02

20k

DAC D

OUTPUT DAC CODE

1

9

7

REF

V

CC

V

OUT

0.1µF

LTC2635CMSE-LMOI2

1.26V

1.2V

1.14V

0.5V

0.8V

1.1V

819

1311

1802

10k

15k

0.22µF

2

3

DAC A

DAC B

DAC D

DAC C

8

10

4

5

6

CAO

SCL

SDA

GND

2

TO I C

BUS

2635 TA02

2635fb

ꢁꢇ

LTC2635

package Description

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

0.70 p0.05

3.50 p 0.05

2.10 p 0.05

1.45 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 p0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 s 45o CHAMFER

R = 0.115

TYP

0.75 p 0.05

3.00 p 0.10

(4 SIDES)

15 16

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

1.45 p 0.10

(4-SIDES)

(UD16) QFN 0904

0.200 REF

0.25 p 0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

2635fb

ꢁꢈ

LTC2635

package Description

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev D)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1.88 p 0.102

(.074 p .004)

0.889 p 0.127

(.035 p .005)

1

0.29

REF

1.68

(.066)

0.05 REF

5.23

(.206)

MIN

1.68 p 0.102 3.20 – 3.45

(.066 p .004) (.126 – .136)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

10

NO MEASUREMENT PURPOSE

0.50

(.0197)

BSC

0.305 p 0.038

(.0120 p .0015)

TYP

3.00 p 0.102

(.118 p .004)

(NOTE 3)

0.497 p 0.076

(.0196 p .003)

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

REF

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

DETAIL “A”

0.254

(.010)

0o – 6o TYP

1

2

3

4 5

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 p 0.0508

(.004 p .002)

0.50

(.0197)

BSC

MSOP (MSE) 0210 REV D

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

2635fb

ꢂ0

LTC2635

revision history

REV

DATE

12/09 Revise QFN pin names

Minor text edit in Operations section

DESCRIPTION

PAGE NUMBER

A

2, 17

21, 24

11

ꢀ

06/10 Revised Note 3 in the Electrical Characteristics section

Added Typical Application drawing and revised Related Parts List

32

2635fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-

tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

ꢂꢀ

LTC2635

typical application

Voltage Margining Application with LTC3850 (1.2V 5%) –LTC2635– LMO Option Only

V

IN

6.5V TO 14V

0.1µF

4.7µF

2.2Ω

100k

0.1µF

INTV

PGOOD

V

CC

TG1

IN

I

LIM

0.1µF

10k

FREQ

BOOST1

SW1

2.2µH

0.008Ω

V

OUT

1.2V 5ꢀ

3.32k

1nF

BG1

LTC3850EUF

PGND

10Ω

+

SENSE

I

TH1

RUN1

1nF

–

1nF

10k

SENSE

500kHz

MODE/PLLIN

TK/SS1

100pF

V

FB1

SGND

10nF

15pF

63.4k

5V

1

9

7

REF

V

CC

LTC2635CMSE-LMOI2

0.1µF

2635 TA02

20k

10k

15k

0.22µF

DAC D

OUTPUT DAC CODE

2

3

DAC A

DAC B

DAC D

DAC C

V

OUT

1.26V

1.2V

1.14V

0.5V

0.8V

1.1V

819

1311

1802

8

10

4

5

6

CAO

SCL

SDA

GND

2

TO I C

BUS

2635 TA03

relateD parts

PART NUMBER

DESCRIPTION

COMMENTS

2

LTC2654/LTC2655 Quad 16-/12 ꢀit, SPI/I C V

Maximum Reference

DACs with 10ppm/°C

4LSꢀ INL Maximum at 16 ꢀits and 2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages

OUT

2

LTC2609/LTC2619/ Quad 16-/14-/12-ꢀit V

LTC2629

DACs with I C Interface

250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with

OUT

Separate V Pins for Each DAC

REF

LTC2604/LTC2614/ Quad 16-/14-/12-ꢀit, SPI V

DACs with External

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead

SSOP Package

OUT

LTC2624

LTC2634

Reference

Quad 12-/10-/8-ꢀit SPI V

Reference

DACs with 10ppm/°C

125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP

Packages

OUT

2

LTC2656/LTC2657 Octal 16-/12 ꢀit, SPI/I C V

DACs with 10ppm/°C

4LSꢀ INL Maximum at 16 ꢀits and 2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages

125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead

MSOP Packages

OUT

Maximum Reference

2

LTC2636/LTC2637 Octal 12-/10-/8-ꢀit, SPI/I C V

10ppm/°C Reference

DACs with

OUT

2

LTC2630/LTC2631 Single 12-/10-/8-ꢀit, SPI/ I C V

10ppm/°C Reference

DACs with

180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Rail-to-Rail Output, SC70 (LTC2630)/ThinSOT™ (LTC2631) Packages

OUT

LTC2640

Single 12-/10-/8-ꢀit, SPI V

Reference

DACs with 10ppm/°C 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, ThinSOT Package

OUT

LTC1664

Quad 10-ꢀit, Serial V

DAC

V

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output, 16-Pin Narrow SSOP

CC

OUT

2635fb

LT 0610 REV B • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

ꢂꢁ

●

 LINEAR TECHNOLOGY CORPORATION 2009

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2635CMSE-HMX8#TRPBF
厂家：	Linear
描述：	D/A Converter, 1 Func, Serial Input Loading, 3.9us Settling Time, PDSO10 光电二极管
文件：	总32页 (文件大小：521K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2635CMSE-HMX8#TRPBF [Linear]

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