LTC2641CDD-14#PBF [Linear]
LTC2641 - 16-/14-/12-Bit VOUT DACs in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC2641CDD-14#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2641 - 16-/14-/12-Bit VOUT DACs in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2641/LTC2642
16-/14-/12-Bit V DACs in
OUT
3mm × 3mm DFN
FEATURES
DESCRIPTION
The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit
unbufferedvoltageoutputDACs.TheseDACsoperatefrom
a single 2.7V to 5.5V supply and are guaranteed mono-
tonic over temperature. The LTC2641A-16/LTC2642A-16
provide 16-bit performance ( 1LSB INL and 1LSB DNL)
over temperature. Unbuffered DAC outputs result in low
supply current of 120µA and a low offset error of 1LSB.
n
Tiny 3mm × 3mm 8-Pin DFN Package
n
Maximum 16-Bit INL Error: 1LSB over Temperature
n
Low 120µA Supply Current
n
Guaranteed Monotonic over Temperature
n
Low 0.5nV•sec Glitch Impulse
n
2.7V to 5.5V Single Supply Operation
n
Fast 1µs Settling Time to 16 Bits
n
Unbuffered Voltage Output Directly Drives 60k Loads
Both the LTC2641 and LTC2642 feature a reference input
n
50MHz SPI/QSPI/MICROWIRE Compatible
range of 2V to V . V
swings from 0V to V . For
DD OUT
REF
Serial Interface
bipolar operation, the LTC2642 includes matched scaling
n
Power-On Reset Clears DAC Output to Zero Scale
resistors for use with an external precision op amp (such
(LTC2641) or Midscale (LTC2642)
as the LT1678), generating a V output swing at R .
REF
FB
n
Schmitt-Trigger Inputs for Direct Optocoupler
The LTC2641/LTC2642 use a simple SPI/MICROWIRE
compatible 3-wire serial interface which can be operated
at clock rates up to 50MHz and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the LTC2641’s DAC output
to zero scale and the LTC2642’s DAC output to midscale
when power is initially applied. A logic low on the CLR pin
asynchronously clears the DAC to zero scale (LTC2641)
or midscale (LTC2642). These DACs are all specified over
the commercial and industrial ranges.
Interface
Asynchronous CLR Pin
n
n
8-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2641)
n
10-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2642)
APPLICATIONS
n
High Resolution Offset and Gain Adjustment
n
Process Control and Industrial Automation
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
n
Automatic Test Equipment
Data Acquisition Systems
n
TYPICAL APPLICATION
Bipolar 16-Bit DAC
LTC2642-16 Integral Nonlinearity
V
REF
2.7V TO 5.5V
2V TO V
DD
0.1µF
1µF
0.1µF
1.0
V
V
= 5V
DD
REF
2.5V RANꢀE
0.8
0.6
= 2.5V
R
FB
REF
V
DD
LTC2642
5pF
–
INV
0.4
0.2
BIPOLAR V
REF
OUT
TO V
1/2 LT1678
+
–V
REF
V
OUT
0
16-BIT DAC
POWER-ON
RESET
–0.2
–0.4
–0.6
–0.8
–1.0
INL 25°C
INL 90°C
INL –45°C
CS
16-BIT DATA LATCH
SCLK
DIN
CLR
CONTROL
LOGIC
0
32768
CODE
49152
16-BIT SHIFT REGISTER
16384
65535
GND
26412 TA01a
26412 TA01b
26412fd
1
For more information www.linear.com/LTC2641
LTC2641/LTC2642
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
V
to GND.................................................. –0.3V to 6V
DD
LTC2641C/LTC2642C............................... 0°C to 70°C
LTC2641I/LTC2642I .............................–40°C to 85°C
Maximum Junction Temperature (Note 2) ............ 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
CS, SCLK, DIN,
CLR to GND.........................–0.3V to (V + 0.3V) or 6V
DD
REF, V , INV to GND........–0.3V to (V + 0.3V) or 6V
OUT
DD
R
R
to INV....................................................... –6V to 6V
to GND ..................................................... –6V to 6V
FB
FB
GND to GND (S8 Package) OBSOLETE .... –0.3V to 0.3V
PIN CONFIGURATION
LTC2641
LTC2641
LTC2641
TOP VIEW
TOP VIEW
V
1
2
3
4
8
7
6
5
V
DD
OUT
TOP VIEW
REF
CS
1
2
3
4
8
7
6
5
GND
GND
REF
CS
GND
DIN
REF
CS
SCLK
DIN
1
2
3
4
8 GND
V
V
DD
7 V
6 V
OUT
9
DD
SCLK
DIN
OUT
5 CLR
SCLK
CLR
MS8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC SO
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C (NOTE 2), θ = 120°C/W
JMAX
JA
T
= 125°C, θ = 110°C/W
JA
JMAX
T
= 125°C (NOTE 2), θ = 43°C/W
JA
JMAX
OBSOLETE PACKAGE
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
LTC2642
LTC2642
TOP VIEW
TOP VIEW
10 GND
REF
CS
1
2
3
4
5
10 GND
REF
CS
SCLK
DIN
CLR
1
2
3
4
5
9
8
7
6
V
DD
9
8
7
6
V
DD
11
SCLK
DIN
R
FB
R
FB
INV
INV
OUT
V
CLR
V
OUT
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
= 125°C (NOTE 2), θ = 120°C/W
JA
T
= 125°C (NOTE 2), θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
26412fd
2
For more information www.linear.com/LTC2641
LTC2641/LTC2642
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LCZP
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2641ACDD-16#PBF
LTC2641CDD-16#PBF
LTC2641CDD-14#PBF
LTC2641CDD-12#PBF
LTC2641AIDD-16#PBF
LTC2641IDD-16#PBF
LTC2641IDD-14#PBF
LTC2641IDD-12#PBF
LTC2641ACMS8-16#PBF
LTC2641CMS8-16#PBF
LTC2641CMS8-14#PBF
LTC2641CMS8-12#PBF
LTC2641AIMS8-16#PBF
LTC2641IMS8-16#PBF
LTC2641IMS8-14#PBF
LTC2641IMS8-12#PBF
LTC2642ACDD-16#PBF
LTC2642CDD-16#PBF
LTC2642CDD-14#PBF
LTC2642CDD-12#PBF
LTC2642AIDD-16#PBF
LTC2642IDD-16#PBF
LTC2642IDD-14#PBF
LTC2642IDD-12#PBF
LTC2642ACMS-16#PBF
LTC2642CMS-16#PBF
LTC2642CMS-14#PBF
LTC2642CMS-12#PBF
LTC2642AIMS-16#PBF
LTC2642IMS-16#PBF
LTC2642IMS-14#PBF
LTC2642IMS-12#PBF
LTC2641ACDD-16#TRPBF
LTC2641CDD-16#TRPBF
LTC2641CDD-14#TRPBF
LTC2641CDD-12#TRPBF
LTC2641AIDD-16#TRPBF
LTC2641IDD-16#TRPBF
LTC2641IDD-14#TRPBF
LTC2641IDD-12#TRPBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LCZP
0°C to 70°C
LCZN
0°C to 70°C
LCZM
0°C to 70°C
LCZP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LCZP
LCZN
LCZM
LTC2641ACMS8-16#TRPBF LTCZS
LTC2641CMS8-16#TRPBF LTCZS
LTC2641CMS8-14#TRPBF LTCZR
LTC2641CMS8-12#TRPBF LTCZQ
LTC2641AIMS8-16#TRPBF LTCZS
8-Lead Plastic MSOP
0°C to 70°C
8-Lead Plastic MSOP
0°C to 70°C
8-Lead Plastic MSOP
0°C to 70°C
8-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC2641IMS8-16#TRPBF
LTC2641IMS8-14#TRPBF
LTC2641IMS8-12#TRPBF
LTC2642ACDD-16#TRPBF
LTC2642CDD-16#TRPBF
LTC2642CDD-14#TRPBF
LTC2642CDD-12#TRPBF
LTC2642AIDD-16#TRPBF
LTC2642IDD-16#TRPBF
LTC2642IDD-14#TRPBF
LTC2642IDD-12#TRPBF
LTCZS
LTCZR
LTCZQ
LCZW
LCZW
LCZV
LCZT
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
LCZW
LCZW
LCZV
LCZT
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC2642ACMS-16#TRPBF LTCZZ
LTC2642CMS-16#TRPBF
LTC2642CMS-14#TRPBF
LTC2642CMS-12#TRPBF
LTC2642AIMS-16#TRPBF
LTC2642IMS-16#TRPBF
LTC2642IMS-14#TRPBF
LTC2642IMS-12#TRPBF
LTCZZ
LTCZY
LTCZX
LTCZZ
LTCZZ
LTCZY
LTCZX
10-Lead Plastic MSOP
0°C to 70°C
10-Lead Plastic MSOP
0°C to 70°C
10-Lead Plastic MSOP
0°C to 70°C
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
OBSOLETE
LTC2641CS8-16#PBF
LTC2641IS8-16#PBF
LTC2641CS8-16#TRPBF
LTC2641IS8-16#TRPBF
264116
264116
8-Lead Plastic SO
8-Lead Plastic SO
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
26412fd
3
For more information www.linear.com/LTC2641
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
LTC2641-12
LTC2642-12
LTC2641-14
LTC2642-14
LTC2641-16
LTC2642-16
LTC2641A-16
LTC2642A-16
SYMBOL PARAMETER
Static Performance
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
l
l
N
Resolution
12
12
14
14
16
16
16
16
Bits
Bits
Monotonicity
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
Zero Code Offset Error
Zero Code Tempco
Gain Error
(Note 3)
(Note 3)
Code = 0
0.5
0.5
1
0.5
0.5
1
1
0.5
0.5
1
2
0.5
0.5
1
1
LSB
LSB
ZSE
2
2
2
LSB
ZS
0.05
0.5
0.1
6.2
1
0.05
1
0.05
2
0.05
2
ppm/°C
LSB
TC
l
GE
GE
2
4
5
5
Gain Error Tempco
DAC Output Resistance
0.1
6.2
1
0.1
6.2
1
0.1
6.2
1
ppm/°C
kΩ
TC
R
(Note 4)
OUT
Bipolar Resistor Matching (LTC2642) R /R
FB INV
l
l
Ratio Error (Note 7)
(LTC2642)
0.1
2
0.03
4
0.015
5
0.015
5
%
LSB
BZE
BZS
Bipolar Zero Offset Error
Bipolar Zero Tempco
0.5
0.1
0.5
0.1
2
2
(LTC2642)
0.1
0.1
ppm/°C
LSB
TC
l
PSR
Power Supply Rejection
ΔV
=
10%
0.5
0.5
1
1
DD
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
l
V
REF
Reference Input Range
2.0
V
V
DD
l
l
R
Reference Input Resistance (Note 5)
Unipolar Mode (LTC2641)
Bipolar Mode (LTC2642)
11
8.5
14.8
11.4
kΩ
kΩ
REF
Dynamic Performance—V
OUT
SR
Voltage Output Slew Rate
Output Settling Time
DAC Glitch Impulse
Digital Feedthrough
Measured from 10% to 90%
To 0.5LSB of FS
15
1
V/µs
µs
Major Carry Transition
0.5
0.2
nV•s
nV•s
Code = 0000hex; NCS = V
;
DD
SCLK, DIN 0V to V Levels
DD
Output Voltage Noise Density
10
nV/√Hz
Dynamic Performance—Reference Input
BW
Reference –3dB Bandwidth
Code = FFFFhex
1.3
1
MHz
Reference Feedthrough
Signal-to-Noise Ratio
Code = 0000hex, V = 1V at 100kHz
mV
P-P
REF
P-P
SNR
92
dB
C
Reference Input Capacitance
Code = 0000hex
Code = FFFFhex
75
120
pF
pF
IN(REF)
Digital Inputs
l
l
V
Digital Input High Voltage
V
CC
V
CC
= 3.6V to 5.5V
= 2.7V to 3.6V
2.4
2.0
V
V
IH
26412fd
4
For more information www.linear.com/LTC2641
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
IL
Digital Input Low Voltage
V
CC
V
CC
= 4.5V to 5.5V
= 2.7V to 4.5V
0.8
0.6
V
V
l
l
I
Digital Input Current
Digital Input Capacitance
Hysteresis Voltage
V
= GND to V
DD
1
µA
pF
V
IN
IN
C
V
(Note 6)
3
10
IN
0.15
H
Power Supply
l
l
V
Supply Voltage
2.7
5.5
V
DD
D
I
Supply Current, V
Digital Inputs = 0V or V
DD
120
200
µA
DD
DD
P
Power Dissipation
Digital Inputs = 0V or V , V = 5V
0.60
0.36
mW
mW
DD DD
Digital Inputs = 0V or V , V = 3V
DD DD
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
10
0
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
f
DIN Valid to SCLK Setup Time
DIN Valid to SCLK Hold Time
SCLK Pulse Width High
SCLK Pulse Width Low
CS Pulse High Width
1
ns
2
9
ns
3
9
ns
4
10
8
ns
5
LSB SCLK High to CS High
CS Low to SCLK High
CS High to SCLK Positive Edge
CLR Pulse Width Low
SCLK Frequency
ns
6
8
ns
7
8
ns
8
15
ns
9
50% Duty Cycle
50
MHz
µs
SCLK
V
DD
High to CS Low (Power-Up Delay)
30
Note 4: R
tolerance is typically 20%.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
OUT
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
Note 3: LTC2641-16/LTC2642-16 1LSB = 0.0015% = 15.3ppm of full
scale. LTC2641-14/LTC2642-14 1LSB = 0.006% = 61ppm of full scale.
LTC2641-12/LTC2642-12 1LSB = 0.024% = 244ppm of full scale.
tested.
26412fd
5
For more information www.linear.com/LTC2641
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
Integral Nonlinearity (INL)
INL vs VREF
vs Supply (VDD
)
1.0
0.8
1.0
0.8
1.0
0.8
V
= 2.5V
V
DD
= 5.5V
REF
LTC2642-16
V
V
= 2.5V
REF
= 5V
DD
0.6
0.6
0.6
+INL
+INL
–INL
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–INL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
4
6
0
16384
32768
CODE
49152
65535
2
3
5
2
3
4
5
6
V
(V)
V
(V)
DD
REF
26412 G02
26412 G01
26412 G03
Differential Nonlinearity (DNL)
vs Supply (VDD
)
Differential Nonlinearity (DNL)
DNL vs VREF
1.0
0.8
1.0
0.8
1.0
0.8
V
REF
= 2.5V
V
DD
= 5.5V
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
+DNL
–DNL
+DNL
–DNL
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
4
6
2
3
4
6
0
16384
32768
CODE
49152
65535
2
3
5
5
V
(V)
V
(V)
REF
DD
26412 G05
26412 G06
26412 G04
INL vs Temperature
DNL vs Temperature
Bipolar Zero Error vs Temperature
5
4
1.0
0.8
1.0
0.8
V
V
= 2.5V
REF
= 5V
DD
V
V
= 2.5V
REF
= 5V
DD
V = 2.5V
REF
V = 5V
DD
3
0.6
0.6
+INL
–INL
2
0.4
0.4
1
0.2
0.2
+DNL
–DNL
0
0
0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
TEMPERATURE (°C)
35
60
85
–40
TEMPERATURE (°C)
TEMPERATURE (°C)
26412 G09
26412 G07
26412 G08
26412fd
6
For more information www.linear.com/LTC2641
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Unbuffered Zero Scale Error vs
Temperature (LTC2641-16)
Unbuffered Full-Scale Error vs
Temperature (LTC2641-16)
1.0
Bipolar Gain Error vs Temperature
5
4
1.0
0.8
V
V
= 2.5V
REF
= 5V
DD
0.8
0.6
0.4
0.2
0
3
0.6
2
0.4
1
0.2
0
0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
26412 G10
26412 G11
26412 G12
14-Bit Integral Nonlinearity (INL)
(LTC2642-14)
14-Bit Differential Nonlinearity
(DNL) (LTC2642-14)
IREF vs Code (Unipolar LTC2641)
1.0
0.8
1.0
0.8
250
200
150
100
50
LTC2642-14
V
V
= 2.5V
REF
= 5V
DD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
8192
16383
0
4096
8192
16384
32768
CODE
49152
0
4096
12288
12288
16383
0
65535
CODE
CODE
26412 G15
26412 G13
26412 G14
12-Bit Integral Nonlinearity (INL)
(LTC2642-12)
12-Bit Differential Nonlinearity
(DNL) (LTC2642-12)
IREF vs Code (Bipolar LTC2642)
1.0
0.8
1.0
0.8
250
200
150
100
50
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32768
CODE
49152
0
1024
2048
3072
4095
0
1024
2048
3072
4095
0
16384
65535
CODE
CODE
26412 G18
26412 G16
26412 G17
26412fd
7
For more information www.linear.com/LTC2641
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current (IDD) vs
Temperature
Supply Current (IDD) vs Supply
Voltage (VDD
Supply Current (IDD) vs Digital
Input Voltage
)
900
800
700
600
500
400
300
200
100
0
150
125
150
125
100
75
V
= 2.5V
V
REF
= 2.5V
REF
V
V
= 5V
= 3V
DD
DD
V
= 5V
DD
100
75
50
25
0
50
V
= 3V
DD
25
0
–40
–15
10
35
60
85
2.5
3.5
4
4.5
5
5.5
3
0
0.5
1
1.5
2
2.5
5
3
3.5 4 4.5
TEMPERATURE (°C)
V
(V)
DIGITAL INPUT VOLTAGE (V)
DD
26412 G19
26412 G20
26412 G21
Supply Current (IDD) vs VREF
VDD = 5V
,
Supply Current (IDD) vs VREF
VDD = 3V
,
Midscale Glitch Impulse
150
125
100
75
150
125
100
75
CS
V
= 5V
V
DD
= 3V
DD
5V/DIV
CODE
32767
CODE
32768
CODE
32767
V
OUT
20mV/DIV
50
50
25
25
26412 G24
LTC2641-16
500ns/DIV
UNBUFFERED
C
= 10pF
L
0
0
3.5
4
2.5
1
1.5
2
2.5
3
4.5
5
1
1.5
2
3
V
(V)
V
(V)
REF
REF
26412 G22
26412 G23
V
OUT vs VDD = 0V to 5.5V
Full-Scale Transition
Full-Scale Settling (Zoomed In)
(POR Function) LTC2641
CS
CS
5V/DIV
V
= V
REF
DD
5V/DIV
0V TO 5.5V
2V/DIV
SETTLE
RESIDUE
250µV/DIV
V
OUT
V
OUT
1V/DIV
10mV/DIV
26412 G25
26412 G26
26412 G27
LTC2641-16
= 2.5V
CONSULT FACTORY FOR
MEASUREMENT CIRCUIT
500ns/DIV
LTC2641-16
500ns/DIV
LTC2641-16
50ms/DIV
V
UNBUFFERED
REF
UNBUFFERED
C
V
V
= 10pF
C
= 10pF
L
L
= 2.5V
REF
= 5V
DD
26412fd
8
For more information www.linear.com/LTC2641
LTC2641/LTC2642
PIN FUNCTIONS
LTC2641 – MSOP, DFN Packages
GND (Pin 7): Circuit Ground Pin. Must be connected to
Pin 2 (GND).
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and V .
V
DD
(Pin 8): Supply Voltage. Set between 2.7V and 5.5V.
DD
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
LTC2642 – MSOP, DFN Packages
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and V .
DD
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to code 0.
DIN (Pin 4): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
V
(Pin 6): DAC Output Voltage. The output range is
REF
OUT
0V to V
.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to midscale.
V
DD
(Pin 7): Supply Voltage. Set between 2.7V and 5.5V.
GND (Pin 8): Circuit Ground.
V
(Pin 6): DAC Output Voltage. The output range is
REF
OUT
0V to V
.
Exposed Pad (DFN Pin 9): Circuit Ground. Must be sol-
dered to PCB ground.
INV (Pin 7): Center Tap of Internal Scaling Resistors.
Connect to an external amplifier’s inverting input in bi-
polar mode.
LTC2641 – SO Package OBSOLETE
V
(Pin 1): DAC Output Voltage. The output range is
REF
OUT
0V to V
R
(Pin 8): Feedback Resistor. Connect to an external
FB
.
amplifier’s output in bipolar mode. The bipolar output
GND (Pin 2): Circuit Ground.
range is –V to V
.
REF
REF
REF (Pin 3): Reference Voltage Input. Apply an external
V
(Pin 9): Supply Voltage. Set between 2.7V and 5.5V.
DD
reference at REF between 2V and V .
DD
GND (Pin 10): Circuit Ground.
CS (Pin 4): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
Exposed Pad (DFN Pin 11): Circuit Ground. Must be
soldered to PCB ground.
SCLK (Pin 5): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 6): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
26412fd
9
For more information www.linear.com/LTC2641
LTC2641/LTC2642
BLOCK DIAGRAMS
LTC2641 - MSOP, DFN
LTC2641 - SO
OBSOLETE PACKAGE
7
1
8
3
REF
V
REF
V
DD
DD
LTC2641-16
LTC2641-14
LTC2641-12
LTC2641-16
V
V
POWER-ON
RESET
OUT
POWER-ON
RESET
OUT
16-/14-/12-BIT DAC
6
16-/14-/12-BIT DAC
1
CS
CS
2
3
4
5
4
5
6
7
SCLK
DIN
CLR
SCLK
DIN
CONTROL
LOGIC
CONTROL
LOGIC
16-BIT DATA LATCH
16-BIT DATA LATCH
GND
16-BIT SHIFT REGISTER
16-BIT SHIFT REGISTER
GND
8
GND
2
2641 BD01a
2641 BD01b
LTC2642
9
1
REF
V
DD
R
FB
8
7
LTC2642-16
LTC2642-14
LTC2642-12
INV
OUT
V
POWER-ON
RESET
16-/14-/12-BIT DAC
6
CS
2
3
4
5
SCLK
DIN
CLR
CONTROL
LOGIC
16-BIT DATA LATCH
16-BIT SHIFT REGISTER
GND
10
2642 BD
26412fd
10
For more information www.linear.com/LTC2641
LTC2641/LTC2642
TIMING DIAGRAM
t
1
t
t
3
t
4
t
6
2
1
2
3
15
16
SCK
SDI
t
8
t
t
7
5
26412 TD
CS/LD
OPERATION
General Description
The digital-to-analog transfer function at the V
pin is:
OUT
N
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
1LSB integral linearity error and less than 1LSB differ-
ential linearity error, guaranteeing monotonic operation.
They operate from a single supply ranging from 2.7V to
5.5V, consuming 120µA (typical). An external voltage
k
VOUT(IDEAL)
=
V
REF
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V is between 2.0V and
REF
V
(see Tables 1a, 1b and 1c).
DD
reference of 2V to V determines the DAC’s full-scale
DD
The LTC2642 includes matched resistors that are tied
to an external amplifier to provide bipolar output swing
(Figure 2). The bipolar transfer function at the RFB pin is:
outputvoltage.A3-wireserialinterfaceallowstheLTC2641/
LTC2642 to fit into a small 8-/10-pin MSOP or DFN 3mm
× 3mm package.
k
N–1
V
OUT_BIPOLAR(IDEAL) = VREF
– 1
Digital-to-Analog Architecture
2
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOS
switches.TheLTC2641/LTC2642DACresistorladdersare
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
chip select input (CS) controls and frames the loading of
serial data from the data input (DIN). Following a CS high-
to-low transition, the data on DIN is loaded, MSB first, into
the shift register on each rising edge of the serial clock
impulse is very low at 500pV•sec, C = 10pF, ten times
L
lower than previous DACs of this type.
26412fd
11
For more information www.linear.com/LTC2641
LTC2641/LTC2642
OPERATION
input (SCLK). After 16 data bits have been loaded into the
serial input register, a low-to-high transition on CS trans-
fers the data to the 16-bit DAC latch, updating the DAC
output (see Figures 1a, 1b, 1c). While CS remains high,
the serial input shift register is disabled. If there are less
than16low-to-hightransitionsonSCLKwhileCSremains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while CS remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
Power-On Reset
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC output comes up in a known
state. When V is first applied, the power-on reset cir-
DD
cuit sets the output of the LTC2641 to zero-scale (code
0). The LTC2642 powers up to midscale (bipolar zero).
Depending on the DAC number of bits, the midscale code
is: 32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048
(LTC2642-12).
Clearing the DAC
A low pulse meeting the t (minimum) specification on
9
the CLR pin asynchronously clears the DAC latch to code
zero (LTC2641) or to midscale (LTC2642).
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
26412 F01a
DATA (16 BITS)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
26412 F01b
MSB
LSB
DATA (14 BITS + 2 DON’T-CARE BITS)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
CS
SCLK
DIN
DAC
UPDATED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
X
X
26412 F01c
DATA (12 BITS + 4 DON’T-CARE BITS)
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
26412fd
12
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
Unipolar Configuration
The external amplifier provides a unity-gain buffer. The
LTC2642 can also be used in unipolar configuration by
Figure 2 shows a typical unipolar DAC application for
the LTC2641. Tables 1a, 1b and 1c show the unipolar
binary code tables for 16-bit, 14-bit and 12-bit operation.
tying R and INV to REF. This provides power-up and
FB
clear to midscale.
V
REF
2.5V
OUT
LT®1019CS8-2.5
IN
5V
0.1µF
4.7µF
Table 1a. 16-Bit Unipolar Binary Code Table
(LTC2641-16)
5V/3V
7
GND
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
0.1µF
ANALOG OUTPUT
(V
5V/3V
0.1µF
1
REF
)
OUT
V
DD
MSB
LSB
–
LTC2641-16
1111 1111 1111 1111 V (65,535/65,536)
UNIPOLAR V
REF
OUT
1/2 LTC6078
0V TO 2.5V
V
6
OUT
+
1000 0000 0000 0000 V (32,768/65,536) = V /2
REF
REF
2
3
4
5
16-BIT DAC
CS
0000 0000 0000 0001 V (1/65,536)
REF
SCLK
DIN
0000 0000 0000 0000 0V
CLR
GND
8
26412 F02
Figure 2. 16-Bit Unipolar Output (LTC2641-16) Unipolar VOUT = 0V to VREF
Table 1b. 14-Bit Unipolar Binary Code Table
(LTC2641-14)
Table 1c. 12-Bit Unipolar Binary Code Table
(LTC2641-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
)
)
OUT
OUT
MSB
LSB
MSB
LSB
1111 1111 1111 11xx V (16,383/16,384)
1111 1111 1111 xxxx
1000 0000 0000 xxxx
0000 0000 0001 xxxx
V
REF
V
REF
V
REF
(4,095/4,096)
REF
1000 0000 0000 00xx V (8,192/16,384) = V /2
(2,048/4,096) = V /2
REF
REF
REF
0000 0000 0000 01xx V (1/16,384)
(1/4,096)
REF
0000 0000 0000 00xx 0V
0000 0000 0000 xxxx 0V
26412fd
13
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
Bipolar Configuration
The amplifier circuit provides a gain of +2 from the V
OUT
pin, and gain of –1 from V . Tables 2a, 2b and 2c show
REF
Figure 3 shows a typical bipolar DAC application for the
the bipolar offset binary code tables for 16-bit, 14-bit and
12-bit operation.
LTC2642. The on-chip bipolar offset/gain resistors, R
FB
andR ,areconnectedtoanexternalamplifiertoproduce
INV
a bipolar output swing from –V to V at the R pin.
REF
REF
FB
V
REF
2.5V
5V/3V
OUT
LT1019CS8-2.5
GND
IN
5V
0.1µF
4.7µF
0.1µF
9
1
REF
V
DD
R
FB
8
5V
0.1µF
0.1µF
LTC2642-16
C1
10pF
–
INV
OUT
7
6
BIPOLAR V
OUT
1/2 LT1678
–2.5V TO 2.5V
V
+
2
3
4
5
16-BIT DAC
CS
SCLK
DIN
–5V
CLR
GND
10
26412 F02
Figure 3. 16-Bit Bipolar Output (LTC2642-16) VOUT = –VREF to VREF
Table 2a. 16-Bit Bipolar Offset Binary
Code Table (LTC2642-16)
Table 2b. 14-Bit Bipolar Offset Binary
Code Table (LTC2642-14)
Table 2c. 12-Bit Bipolar Offset Binary
Code Table (LTC2642-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
)
)
)
OUT
OUT
OUT
MSB
LSB
MSB
LSB
MSB
LSB
1111 1111 1111 1111 V (32,767/32,768)
1111 1111 1111 11xx V (8,191/8,192)
1111 1111 1111 xxxx
1000 0000 0001 xxxx
V
V
(2,047/2,048)
(1/2,048)
REF
REF
REF
1000 0000 0000 0001 V (1/32,768)
1000 0000 0000 01xx V (1/8,192)
REF
REF
REF
1000 0000 0000 0000 0V
1000 0000 0000 00xx 0V
1000 0000 0000 xxxx 0V
0111 1111 1111 xxxx –V (1/2048)
0111 1111 1111 1111 –V (1/32,768)
0111 1111 1111 11xx –V (1/8,192)
REF
REF
REF
0000 0000 0000 0000 –V
0000 0000 0000 00xx –V
0000 0000 0000 xxxx –V
REF
REF
REF
26412fd
14
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
Unbuffered Operation and V
Loading
Unbuffered V
Settling Time
OUT
OUT
The DAC output is available directly at the V
pin, which
The settling time at the V
pin can be closely approxi-
OUT
OUT
swings from GND to V . Unbuffered operation provides
mated by a single-pole response where:
REF
the lowest possible offset, full-scale and linearity errors,
thefastestsettlingtimeandminimumpowerconsumption.
t = R • (C + C )
OUT
OUT
L
(Figure 4). Settling to 1/2LSB at 16-bits requires about
12 time constants (ln(2 • 65,536)). The typical settling
time of 1µs corresponds to a time constant of 83ns, and
However, unbuffered operation requires that appropriate
loading be maintained on the V
pin. The LTC2641/
OUT
LTC2642 V
can be modeled as an ideal voltage source
OUT
a total (C
+ C ) of about 83ns/6.2k = 13pF. The internal
OUT
L
OUT
in series with a source resistance of R , typically 6.2k
OUT
capacitance, C
3pF corresponds to 1µs settling to 1/2LSB.
is typically 10pF, so an external C of
L
(Figure 4). The DAC’s linear output impedance allows it to
drive medium loads (R > 60k) without degrading INL or
L
DNL; only the gain error is increased. The gain error (GE)
V
REF
caused by a load resistance, R , (relative to full scale) is:
L
REF
R
LTC2641
LTC2642
–1
V
OUT
OUT
GE =
V
OUT
+
–
0V TO V
REF
R
OUT
CODE
C
OUT
R
L
C
I
L
1+
V
L
REF
(
N
)
2
RL
26412 F04
GND
In 16-bit LSBs:
–65536
Figure 4. VOUT Pin Equivalent Circuit
GE =
LSB
R
1+
OUT
Op Amp Selection
RL
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
R
has a low tempco (typically < 50ppm/°C), and is
OUT
independent of DAC code. The variation of R , part-to-
OUT
part, is typically less than 20%.
Note on LSB units:
For the following error descriptions, “LSB” means 16-bit
LSB and 65,536 is rounded to 66k.
To convert to 14-bit LSBs (LTC2641-14/LTC2642-14)
divide by 4.
In bipolar mode (LTC2642 only), the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. In this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
To convert to 12-bit LSBs (LTC2641-12/LTC2642-12)
divide by 16.
Aconstantcurrent,I ,loadingV willproduceanoffsetof:
L
OUT
V
output range (Figure 3).
REF
V
= –I • R
L OUT
OFFSET
In unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applica-
tions a precision, rail-to-rail input, single supply op amp
For V
38µV. Since R
= 2.5V, a 16-bit LSB equals 2.5V/65,536, or
REF
is 6.2k, an I of 6nA produces an offset
OUT
L
of 1LSB. Therefore, to avoid degrading DAC performance,
it is critical to protect the V
leakage current.
pin from any sources of
OUT
26412fd
15
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
such as the LTC6078 is suitable, if the application does
notrequirelinearoperationveryneartoGND, orzeroscale
(Figure 2). The LTC6078 typically swings to within 1mV of
GND if it is not required to sink any load current. For an
LSB size of 38µV, 1mV represents 26 missing codes near
zero scale. Linearity will be degraded over a somewhat
larger range of codes above GND. It is also unavoidable
that settling time and transient performance will degrade
whenever a single supply amplifier is operated very close
to GND, or to the positive supply rail.
voltage temperature coefficient (referenced to 25°C) of
0.6μV/°C will add 1LSB of zero-scale error. Also, I and
BIAS
the V
error it causes, will typically show significant
OFFSET
relative variation over temperature.
Op amp open-loop gain, A , contributes to DAC gain
VOL
error (GE):
66k
AVOL
GE =
LSB
[
]
Op amp input common mode rejection ratio (CMRR) is an
input-referred error that corresponds to a combination of
gain error (GE) and INL, depending on the op amp archi-
tecture and operating conditions. A conservative estimate
of total CMRR error is:
The small LSB size of a 16-bit DAC, coupled with the tight
accuracyspecifications on theLTC2641/LTC2642, means
that the accuracy and input specifications for the external
op amp are critical for overall DAC performance.
Op Amp Specifications and Unipolar DAC Accuracy
CMRR
20
VCMRR_RANGE
Error = 10
•
• 66k LSB
Most op amp accuracy specifications convert easily to
DAC accuracy.
VREF
Op amp input bias current on the noninverting (+) input is
equivalent to an I loading the DAC V
pin and therefore
where V
is the voltage range that CMRR (in
L
OUT
CMRR_RANGE
produces a DAC zero-scale error (ZSE) (see Unbuffered
dB) is specified over. Op amp Typical Performance Char-
acteristicsgraphsareusefultopredicttheimpactofCMRR
errors on DAC performance. Typically, a precision op amp
will exhibit a fairly linear CMRR behavior (corresponding
to DAC gain error only) over most of the common mode
input range (CMR), and become nonlinear and produce
significant errors near the edge of the CMR.
Operation):
ZSE = –I (IN+) • R
[Volts]
B
OUT
In 16-bit LSBs:
66k
ZSE = –I IN+ • 6.2k •
LSB
B
V
REF
Rail-to-rail input op amps are a special case, because they
have 2 distinct input stages, one with CMR to GND and
the other with CMR to V . This results in a “crossover”
CM input region where operation switches between the
two input stages.
Op amp input impedance, R , is equivalent to an R
IN
L
+
loading the LTC2641/LTC2642 V
a gain error of:
pin, and produces
OUT
–66k
GE =
LSB
The LTC6078 rail-to-rail input op amp typically exhibits
remarkably low crossover linearity error, as shown in the
6.2k
1+
R
IN
V
vs V Typical Performance Characteristics graphs
OS
CM
(see the LTC6078 data sheet). Crossover occurs at CM
Op amp offset voltage, V , corresponds directly to DAC
+
OS
inputs about 1V below V , and an LTC6078 operating as
zero code offset error, ZSE:
+
a unipolar DAC buffer with V = 2.5V and V = 5V will
REF
typically add only about 1LSB of GE and almost no INL
66k
VREF
ZSE = VOS
•
LSB
[
]
error due to CMRR. Even in a full rail-to-rail application,
+
with V = V = 5V, a typical LTC6078 will add only about
REF
Temperature effects also must be considered. Over the
–40°C to 85°C industrial temperature range, an offset
1LSB of INL at 16-bits.
26412fd
16
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
Op Amp Specifications and Bipolar DAC Accuracy
will introduce a feedback loop pole with a time constant
of (C • 28k/2). A small feedback capacitor, C1, should be
P
TheopampcontributionstounipolarDACerrordiscussed
above apply equally to bipolar operation. The bipolar ap-
plication circuit gains up the DAC span, and all errors, by
a factor of 2. Since the LSB size also doubles, the errors
in LSBs are identical in unipolar and bipolar modes.
included, to introduce a zero that will partially cancel this
pole. C1 should nominally be <C , typically in the range
P
of 5pF to 10pF. This will restore the phase margin and
improve coarse settling time, but a pole-zero doublet will
unavoidably leave a slower settling tail, with a time con-
–
One added error in bipolar mode comes from I (IN ),
stant of roughly (C + C1) • 28k/2, which will limit 16-bit
B
P
which flows through R to generate an offset. The full
settling time to be greater than 2µs.
FB
bias current offset error becomes:
Reference and GND Input
–
+
V
= (I (IN ) • R – I (IN ) • R • 2) [Volts]
OUT
OFFSET
B
FB
B
TheLTC2641/LTC2642operateswithexternalvoltagerefer-
So:
ences from 2V to V , and linearity, offset and gain errors
DD
33k
are virtually unchanged vs V . Full 16-bit performance
VOFFSET = I (IN–)• 28k –I (IN+)•12.4k •
[LSB]
VREF
REF
B
B
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typ-
ical, corresponds to less than 0.5LSB variation over the
–40°C to 85°C temperature range. In practice, this means
thattheoverallgainerrortempcowillbedeterminedalmost
entirely by the external reference tempco.
Settling Time with Op Amp Buffer
When using an external op amp, the output settling time
will still include the single pole settling on the LTC2641/
LTC2642 V
L
node, with time constant R
• (C
+
OUT
OUT
OUT
C ) (see Unbuffered V
Settling Time). C will include
OUT
L
The DAC voltage-switching mode “inverted” resistor lad-
der architecture used in the LTC2641/LTC2642 exhibits a
the buffer input capacitance and PC board interconnect
capacitance.
reference input resistance (R ) that is code dependent
REF
Theexternalbufferamplifieraddsanotherpoletotheoutput
(see the Typical Performance curves I vs Input Code).
REF
response, with a time constant equal to (fbandwidth/2π).
In unipolar mode, the minimum R
is 14.8k (at code
For example, assume that C is maintained at the same
REF
L
871Chex, 34,588 decimal) and the the maximum R is
value as above, so that the V
node time constant is
REF
OUT
300k at code 0000hex (zero scale). The maximum change
83ns = 1μs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2π • 83ns) = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
root square sum of the individual time constants, or √2
• 83ns = 117ns, and 1/2 LSB settling time will be ~12 •
117ns = 1.4μs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. In practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1μs.
in I for a 2.5V reference is 160µA. Since the maximum
REF
occursnearmidscale, theINLerrorisaboutonehalfofthe
change on V , so maintaining an INL error of <0.1LSB
REF
requiresareferenceloadregulationof(1.53ppm•2/160µA)
=19[ppm/mA].Thisimpliesareferenceoutputimpedance
of 48mΩ, including series wiring resistance.
To prevent output glitches from occurring when resistor
ladder branches switch from GND to V , the reference
REF
inputmustmaintainlowimpedanceathigherfrequencies.
A 0.1μF ceramic capacitor with short leads between REF
and GND provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1μF between REF
and GND provides low frequency bypassing. The circuit
The output settling time for bipolar applications (Fig-
ure 3) will be somewhat increased due to the feedback
resistor network R and R (each 28k nominal). The
FB
INV
parasitic capacitance, C , on the op amp (–) input node
P
26412fd
17
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
will benefit from even higher bypass capacitance, as long
as the external reference remains stable with the added
capacitive loading.
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane.
Digital Inputs and Interface Logic
All of the digital inputs include Schmitt-trigger buffers to
accept slow transition interfaces. This means that opto-
cuplers can interface directly to the LTC2641/LTC2642
without additional external logic. Digital input hysteresis
is typically 150mV.
A “star ground” area should be established by attaching
the LTC2641/LTC2642 GND pin, V
GND and the DAC
REF
V
OUT
GND reference terminal to the same area on the
GND plane. Care should be taken to ensure that no large
GND return current paths flow through the “star GND”
area. In particular, the resistance from the LTC2641 GND
The digital inputs are compatible with TTL/CMOS-logic
levels. However, rail-to-rail (CMOS) logic swings are
preferred, because operating the logic inputs away from
pin to the point where the V input source connects to
REF
the ground plane should be as low as possible. Excessive
resistance here will be multiplied by the code dependent
the supply rails generates additional I and GND current,
DD
I
current to produce an INL error similar to the error
REF
(see Typical Performance Characteristic graph Supply
produced by V source resistance. For the LTC2641 in
REF
Current vs Logic Input Voltage).
the S8 package both GND pins, Pin 2 and Pin 7 should
be tied to the same GND plane.
Digital feedthrough is only 0.2nV•s typical, but it is always
preferredtokeepalllogicinputsstaticexceptwhenloading
a new code into the DAC.
Sourcesofgroundreturncurrentintheanalogareainclude
op amp power supply bypass capacitors and the GND
connection for single supply amps. A useful technique
for minimizing errors is to use a separate board layer for
powergroundreturnconnections,andreserveoneground
plane layer for low current “signal” GND connections.
The “signal”, or “star” GND plane must connected to the
“power” GND plane at a single point, which should be
located near the LTC2641/LTC2642 GND pin.
Board Layout for Precision
Even a small amount of board leakage can degrade
accuracy. The 6nA leakage current into V
needed to
OUT
generate1LSBoffseterrorcorrespondsto833MΩleakage
resistance from a 5V supply.
The V
node is relatively sensitive to capacitive noise
OUT
coupling, so minimum trace length, appropriate shielding
and clean board layout are imperative here.
Ifseparateanaloganddigitalgroundareasexistitisneces-
sary to connect them at a single location, which should be
fairly close to the DAC for digital signal integrity. In some
systems, large GND return currents can flow between the
digital and analog GNDs, especially if different PC boards
are involved. In such cases the digital and analog ground
connection point should not be made right at the “star”
GND area, so the highly sensitive analog signals are not
corrupted.Ifforcedtochoose,alwaysplaceanalogground
quality ahead of digital signal ground. (A few mV of noise
Temperature differences at the DAC, op amp or reference
pins can easily generate tens of microvolts of thermocou-
ple voltages. Analog signal traces should be short, close
together and away from heat dissipating components. Air
currentsacrosstheboardcanalsogeneratethermocouples.
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
26412fd
18
For more information www.linear.com/LTC2641
LTC2641/LTC2642
APPLICATIONS INFORMATION
on the digital inputs is imperceptible, thanks to the digital
input hysteresis)
Caution: if a GND plane gap is improperly placed, so that
it interrupts a significant GND return path, or if a signal
traces crosses over the gap, then adding the gap may
greatly degrade performance! In this case, the GND and
signal return currents are forced to flow the long way
around the gap, and then are typically channeled directly
into the most sensitive area of the analog GND plane.
Just by maintaining separate areas on the GND plane
where analog and digital return currents naturally flow,
good results are generally achieved. Only after this has
been done, it is sometimes useful to interrupt the ground
planewithstrategicallyplaced“slots”,topreventthedigital
ground currents from fringing into the analog portion of
the plane. When doing this, the gap in the plane should
be only as long as it needs to be to serve its purpose.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
R = 0.125
0.40 ±0.10
TYP
5
8
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10 1.65 ±0.10
(4 SIDES) (2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 0509 REV C
4
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.25 ±0.05
0.50 BSC
0.50
BSC
2.38 ±0.10
2.38 ±0.05
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
26412fd
19
For more information www.linear.com/LTC2641
LTC2641/LTC2642
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
26412fd
20
For more information www.linear.com/LTC2641
LTC2641/LTC2642
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
SO8 REV G 0212
OBSOLETE PACKAGE
26412fd
21
For more information www.linear.com/LTC2641
LTC2641/LTC2642
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1ꢀꢀ0 Rev G)
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 ꢀ 5
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .00ꢀ)
DETAIL “A”
0.254
0.889 0.127
(.035 .005)
(.010)
0° – ꢀ° TYP
GAUGE PLANE
1
2
3
4
5.10
3.20 – 3.45
(.201)
0.53 0.152
(.021 .00ꢀ)
(.12ꢀ – .13ꢀ)
MIN
1.10
(.043)
MAX
0.8ꢀ
(.034)
REF
DETAIL “A”
0.18
0.ꢀ5
(.025ꢀ)
BSC
(.007)
0.42 0.038
(.01ꢀ5 .0015)
TYP
SEATING
PLANE
0.22 – 0.38
0.101ꢀ 0.0508
RECOMMENDED SOLDER PAD LAYOUT
(.009 – .015)
(.004 .002)
0.ꢀ5
(.025ꢀ)
BSC
TYP
MSOP (MS8) 0213 REV G
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1ꢀꢀ1 Rev F)
3.00 0.102
(.118 .004)
(NOTE 3)
0.497 0.07ꢀ
(.019ꢀ .003)
REF
10 9
8
7 ꢀ
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .00ꢀ)
DETAIL “A”
0.254
0.889 0.127
(.035 .005)
(.010)
0° – ꢀ° TYP
GAUGE PLANE
1
2
3
4 5
5.10
(.201)
MIN
0.53 0.152
(.021 .00ꢀ)
3.20 – 3.45
(.12ꢀ – .13ꢀ)
0.8ꢀ
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
0.50
(.0197)
BSC
0.305 0.038
(.0120 .0015)
TYP
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.101ꢀ 0.0508
(.004 .002)
RECOMMENDED SOLDER PAD LAYOUT
0.50
(.0197)
BSC
NOTE:
MSOP (MS) 0213 REV F
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
26412fd
22
For more information www.linear.com/LTC2641
LTC2641/LTC2642
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
12/13 Marked S8 package as Obsolete
2, 3, 9, 10, 18, 21
D
10/14 Added output voltage noise density specifications
Updated text under Clearing the DAC section
4
12
26412fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation
cr on
that the interconnectio its rc it s d ibed ert i ring existing patent rights.
23
n of ci u s a es h ein will no nf e
LTC2641/LTC2642
TYPICAL APPLICATION
Wide Range Current Load Sinks 0A to 2.5A
V
REF
2.5V
OUT
LT1019CS8-2.5
IN
5V
5V
0.1µF
0.1µF
4.7µF
GND
7
1
REF
V
DD
10V
0.1µF
LTC2641-16
I
SINK
0A TO 2.5A
V
OUT
6
+
2
3
4
5
16-BIT DAC
CS
1k
SCLK
DIN
IRLZ44
LTC2054HV
–
CLR
0.033µF
10k
GND
8
1Ω
10W
26412 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
DACs
LTC1588/LTC1589 12-/14-/16-Bit SoftSpanTM Current Output DACs
LTC1592
Software Programmable Output Ranges up to 10V
LTC1595/LTC1596 Serial 16-Bit Current Output DACs
Low Glitch, 1LSB Maximum INL, DNL
1LSB Max INL, DNL, 10V Output
LTC1591/LTC1597 Parallel 14-/16-Bit Current Output DACs
LTC1599
LTC1650
16-Bit Current Output DAC
16-Bit Voltage Output DAC
1LSB Max INL, DNL, 10V Output
2nV•s Glitch Impulse, 30nV/√Hz Noise
Single DACs, Single Supply, 0V to 5V Outputs in DFN10
LTC2621/LTC2611 12-/14-/16-Bit Serial Voltage Output DACs
LTC2601
LTC2704-12
LTC2704-14
LTC2704-16
12-/14-/16-Bit Quad Voltage Output DACs
Software Programmable Output Ranges up to 10V, Serial I/O
Op Amps
LT®1678
LTC2054
LT6010
Dual Low Noise Rail-to-Rail Precision Op Amp
Micropower Zero Drift Op Amp
3.9nV/√Hz at 1MHz
3µV Maximum Offset
150µA 8nV/√Hz Rail-to-Rail Output Precision Op Amp
Dual CMOS Rail-to-Rail Input/Output Amplifier
Micropower
LTC6078
References
LT1019
54µA per Amp, 16nV/√Hz Input Noise Voltage
Precision Bandgap Reference
0.005% Max, 5ppm/°C Max
26412fd
LT 1014 REV D • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2007
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2641
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