LTC2641IDD-12PBF [Linear]
16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN; 采用3mm 16位/ 14位/ 12位DAC的VOUT 】 3mm DFN封装
| 型号： | LTC2641IDD-12PBF |
| 厂家： | 
Linear |
| 描述： | 16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN |
| 文件： | 总20页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2641/LTC2642
16-/14-/12-Bit V DACs in
OUT
3mm × 3mm DFN
FEATURES
DESCRIPTION
The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit
unbufferedvoltageoutputDACs.TheseDACsoperatefrom
asingle2.7Vto5.5Vsupplyandareguaranteedmonotonic
over temperature. The LTC2641-16/LTC2642-16 provide
16-bit performance ( 2LꢀS ꢁIL and 1LꢀS DILN over
temperature. UnbufferedDACoutputsresultinlowsupply
current of 120μA and a low offset error of 1LꢀS.
■
Tiny 3mm × 3mm 8-Pin DFN Package
■
Maximum 16-Bit INL Error: ±±LꢀB oꢁer Temperature
■
Low 1±0μA ꢀupply Current
■
Guaranteed Monotonic oꢁer Temperature
■
Low 0.5nV•sec Glitch Impulse
■
2.7V to 5.5V ꢀingle ꢀupply Operation
■
Fast 1μs ꢀettling Time to 16 Sits
■
Unbuffered Voltage Output Directly Drives 60k Loads
Soth the LTC2641 and LTC2642 feature a reference input
50MHz ꢀPꢁTM/QꢀPꢁTM/MꢁCROWꢁRETM Compatible
■
range of 2V to V . V
swings from 0V to V . For
DD OUT
REF
ꢀerial ꢁnterface
bipolar operation, the LTC2642 includes matched scaling
■
Power-On Reset Clears DAC Output to Zero ꢀcale
resistors for use with an external precision op amp (such
(LTC2641N or Midscale (LTC2642N
as the LT1678N, generating a V output swing at R .
REF
FS
■
ꢀchmitt-Trigger ꢁnputs for Direct Optocoupler
The LTC2641/LTC2642 use a simple ꢀPꢁ/MꢁCROWꢁRE
compatible 3-wire serial interface which can be operated
at clock rates up to 50MHz and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the LTC2641’s DAC output
to zero scale and the LTC2642’s DAC output to midscale
when power is initially applied. A logic low on the CLR pin
asynchronously clears the DAC to zero scale (LTC2641N
or midscale (LTC2642N. These DACs are all specified over
the commercial and industrial ranges.
ꢁnterface
Asynchronous CLR Pin
■
⎯
⎯
⎯
■
8-Lead MꢀOP and 3mm × 3mm DFI Packages
(LTC2641N
10-Lead MꢀOP and 3mm × 3mm DFI Packages
(LTC2642N
■
⎯
⎯
⎯
APPLICATIONS
■
High Resolution Offset and Gain Adjustment
■
Process Control and ꢁndustrial Automation
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Automatic Test Equipment
Data Aquisition ꢀystems
■
TYPICAL APPLICATION
Bipolar 16-Bit DAC
LTC±64±-16 Integral Nonlinearity
V
REF
2.7V TO 5.5V
2V TO V
DD
0.1μF
1μF
0.1μF
1.0
V
V
= 5V
REF
DD
0.8
0.6
= 2.5V
R
REF
V
FB
DD
LTC2642
2.5V RANGE
5pF
–
0.4
INV
0.2
BIPOLAR V
OUT
REF
1/2 LT1678
+
–V
TO V
REF
V
0
OUT
16-BIT DAC
POWER-ON
RESET
–0.2
–0.4
–0.6
–0.8
–1.0
INL 25°C
INL 90°C
INL –45°C
CS
16-BIT DATA LATCH
SCLK
DIN
CLR
CONTROL
LOGIC
0
32768
CODE
49152
16384
65535
16-BIT SHIFT REGISTER
GND
26412 TA01a
LT1372 • G10
26412f
1
LTC2641/LTC2642
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
V
to GID.................................................. –0.3V to 6V
DD
⎯
⎯
LTC2641C/LTC2642C............................... 0°C to 70°C
LTC2641ꢁ/LTC2642ꢁ............................. –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
ꢀtorage Temperature Range................... –65°C to 150°C
Lead Temperature (ꢀoldering, 10 secN .................. 300°C
Cꢀ, ꢀCLK, DꢁI,
⎯
⎯
⎯
CLR to GID ........................–0.3V to (V + 0.3VN or 6V
DD
REF, V , ꢁIV to GID ........–0.3V to (V + 0.3VN or 6V
OUT
DD
R
R
to ꢁIV....................................................... –6V to 6V
to GID ..................................................... –6V to 6V
FS
FS
PIN CONFIGURATION
LTC±641
TOP VIEW
TOP VIEW
REF
CS
1
2
3
4
8
7
6
5
GND
REF
CS
SCLK
DIN
1
2
3
4
8 GND
V
V
DD
7 V
6 V
OUT
5 CLR
9
DD
SCLK
DIN
OUT
CLR
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C (IOTE 2N, θ = 200°C/W
JMAX
JA
T
= 125°C (IOTE 2N, θ = 43°C/W
JMAX
JA
EXPOꢀED PAD (PꢁI 9N ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS
LTC±64±
TOP VIEW
TOP VIEW
REF
CS
1
2
3
4
5
10 GND
REF
CS
SCLK
DIN
CLR
1
2
3
4
5
10 GND
9
8
7
6
V
DD
9
8
7
6
V
DD
11
SCLK
DIN
R
FB
R
FB
INV
INV
V
OUT
CLR
V
OUT
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C (IOTE 2N, θ = 120°C/W
JA
JMAX
T
= 125°C (IOTE 2N, θ = 43°C/W
JA
JMAX
EXPOꢀED PAD (PꢁI 11N ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS
26412f
2
LTC2641/LTC2642
ORDER INFORMATION
LTC±641
LEAD FREE FINIꢀH
TAPE AND REEL
PART MARKING*
PACKAGE DEꢀCRIPTION
TEMPERATURE RANGE
LTC2641CDD-16#PSF
LTC2641CDD-14#PSF
LTC2641CDD-12#PSF
LTC2641CDD-16#TRPSF
LTC2641CDD-14#TRPSF
LTC2641CDD-12#TRPSF
LCZP
LCZI
LCZM
8-Lead (3mm × 3mmN Plastic DFI
8-Lead (3mm × 3mmN Plastic DFI
8-Lead (3mm × 3mmN Plastic DFI
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2641ꢁDD-16#PSF
LTC2641ꢁDD-14#PSF
LTC2641ꢁDD-12#PSF
LTC2641ꢁDD-16#TRPSF
LTC2641ꢁDD-14#TRPSF
LTC2641ꢁDD-12#TRPSF
LCZP
LCZI
LCZM
8-Lead (3mm × 3mmN Plastic DFI
8-Lead (3mm × 3mmN Plastic DFI
8-Lead (3mm × 3mmN Plastic DFI
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2641CMꢀ8-16#PSF
LTC2641CMꢀ8-14#PSF
LTC2641CMꢀ8-12#PSF
LTC2641CMꢀ8-16#TRPSF
LTC2641CMꢀ8-14#TRPSF
LTC2641CMꢀ8-12#TRPSF
LTCZꢀ
LTCZR
LTCZQ
8-Lead Plastic MꢀOP
8-Lead Plastic MꢀOP
8-Lead Plastic MꢀOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2641ꢁMꢀ8-16#PSF
LTC2641ꢁMꢀ8-14#PSF
LTC2641ꢁMꢀ8-12#PSF
LTC2641ꢁMꢀ8-16#TRPSF
LTC2641ꢁMꢀ8-14#TRPSF
LTC2641ꢁMꢀ8-12#TRPSF
LTCZꢀ
LTCZR
LTCZQ
8-Lead Plastic MꢀOP
8-Lead Plastic MꢀOP
8-Lead Plastic MꢀOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC±64±
LTC2642CDD-16#PSF
LTC2642CDD-14#PSF
LTC2642CDD-12#PSF
LTC2642CDD-16#TRPSF
LTC2642CDD-14#TRPSF
LTC2642CDD-12#TRPSF
LCZW
LCZV
LCZT
10-Lead (3mm × 3mmN Plastic DFI
10-Lead (3mm × 3mmN Plastic DFI
10-Lead (3mm × 3mmN Plastic DFI
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2642ꢁDD-16#PSF
LTC2642ꢁDD-14#PSF
LTC2642ꢁDD-12#PSF
LTC2642ꢁDD-16#TRPSF
LTC2642ꢁDD-14#TRPSF
LTC2642ꢁDD-12#TRPSF
LCZW
LCZV
LCZT
10-Lead (3mm × 3mmN Plastic DFI
10-Lead (3mm × 3mmN Plastic DFI
10-Lead (3mm × 3mmN Plastic DFI
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2642CMꢀ-16#PSF
LTC2642CMꢀ-14#PSF
LTC2642CMꢀ-12#PSF
LTC2642CMꢀ-16#TRPSF
LTC2642CMꢀ-14#TRPSF
LTC2642CMꢀ-12#TRPSF
LTCZZ
LTCZY
LTCZX
10-Lead Plastic MꢀOP
10-Lead Plastic MꢀOP
10-Lead Plastic MꢀOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2642ꢁMꢀ-16#PSF
LTC2642ꢁMꢀ-14#PSF
LTC2642ꢁMꢀ-12#PSF
LTC2642ꢁMꢀ-16#TRPSF
LTC2642ꢁMꢀ-14#TRPSF
LTC2642ꢁMꢀ-12#TRPSF
LTCZZ
LTCZY
LTCZX
10-Lead Plastic MꢀOP
10-Lead Plastic MꢀOP
10-Lead Plastic MꢀOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
26412f
3
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply oꢁer the full operating
temperature range, otherwise specifications are at TA = ±5°C. VDD = 3V or 5V, VREF = ±.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
LTC±641-1±
LTC±64±-1±
LTC±641-14
LTC±64±-14
LTC±641-16
LTC±64±-16
ꢀYMBOL PARAMETER
ꢀtatic Peformance
CONDITIONꢀ
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITꢀ
●
●
●
●
●
I
Resolution
12
12
14
14
16
16
Sits
Sits
Monotonicity
DIL
ꢁIL
Differential Ionlinearity
ꢁntegral Ionlinearity
Zero Code Offset Error
Zero Code Tempco
Gain Error
(Iote 2N
(Iote 2N
Code = 0
0.5
0.5
1
0.5
0.5
1
1
0.5
0.5
1
2
LꢀS
LꢀS
ZꢀE
2
2
LꢀS
Zꢀ
0.05
0.5
0.1
6.2
1
0.05
1
0.05
2
ppm/°C
LꢀS
TC
●
GE
GE
2
4
5
Gain Error Tempco
DAC Output Resistance
0.1
6.2
1
0.1
6.2
1
ppm/°C
kΩ
TC
R
(Iote 4N
OUT
Sipolar Resistor Matching (LTC2642N R /R
FS ꢁIV
●
●
Ratio Error (Iote 7N
(LTC2642N
0.1
2
0.03
4
0.015
5
%
LꢀS
SZE
SZꢀ
Sipolar Zero Offset Error
Sipolar Zero Tempco
0.5
0.1
0.5
0.1
2
(LTC2642N
0.1
ppm/°C
LꢀS
TC
●
PꢀR
Power ꢀupply Rejection
ΔV = 10%
DD
0.5
0.5
1
The ● denotes the specifications which apply oꢁer the full operating temperature range, otherwise specifications are at TA = ±5°C.
VDD = 3V or 5V, VREF = ±.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
ꢀYMBOL
PARAMETER
CONDITIONꢀ
MIN
TYP
MAX
UNITꢀ
Reference Input
●
V
Reference ꢁnput Range
2.0
V
V
REF
DD
●
●
R
REF
Reference ꢁnput Resistance (Iote 5N
Unipolar Mode (LTC2641N
Sipolar Mode (LTC2642N
11
8.5
14.8
11.4
kΩ
kΩ
Dynamic Performance—V
OUT
ꢀR
Voltage Output ꢀlew Rate
Output ꢀettling Time
DAC Glitch ꢁmpulse
Digital Feedthrough
Measured from 10% to 90%
To 0.5LꢀS of Fꢀ
15
1
V/μs
μs
Major Carry Transition
0.5
0.2
nV•s
nV•s
Code = 0000hex; ICꢀ = V
;
DD
ꢀCLK, DꢁI 0V to V Levels
DD
Dynamic Performance—Reference Input
SW
Reference –3dS Sandwidth
Code = FFFFhex
1.3
1
MHz
Reference Feedthrough
ꢀignal-to-Ioise Ratio
Code = 0000hex, V = 1V at 100kHz
mV
P-P
REF
P-P
ꢀIR
92
dS
C
Reference ꢁnput Capacitance
Code = 0000hex
Code = FFFFhex
75
120
pF
pF
ꢁI(REFN
Digital Inputs
●
●
V
Digital ꢁnput High Voltage
Digital ꢁnput Low Voltage
V
V
= 3.6V to 5.5V
= 2.7V to 3.6V
2.4
2.0
V
V
ꢁH
CC
CC
●
●
V
V
CC
V
CC
= 4.5V to 5.5V
= 2.7V to 4.5V
0.8
0.6
V
V
ꢁL
26412f
4
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply oꢁer the full operating
temperature range, otherwise specifications are at TA = ±5°C. VDD = 3V or 5V, VREF = ±.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
ꢀYMBOL
PARAMETER
CONDITIONꢀ
= GID to V
CC
MIN
TYP
MAX
1
UNITꢀ
μA
●
●
ꢁ
ꢁI
Digital ꢁnput Current
Digital ꢁnput Capacitance
Hysteresis Voltage
V
ꢁI
C
V
(Iote 6N
3
10
pF
ꢁI
H
0.15
V
Power ꢀupply
●
●
V
ꢀupply Voltage
2.7
5.5
V
DD
D
ꢁ
ꢀupply Current, V
Digital ꢁnputs = 0V or V
DD
120
200
μA
DD
DD
P
Power Dissipation
Digital ꢁnputs = 0V or V , V = 5V
0.60
0.36
mW
mW
DD DD
Digital ꢁnputs = 0V or V , V = 3V
DD DD
TIMING CHARACTERISTICS The ● denotes the specifications which apply oꢁer the full operating temperature
range, otherwise specifications are at TA = ±5°C. VDD = 3V or 5V, VREF = ±.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
ꢀYMBOL
PARAMETER
CONDITIONꢀ
MIN
10
0
TYP
MAX
UNITꢀ
ns
●
●
●
●
●
●
●
●
●
●
t
t
t
t
t
t
t
t
t
f
DꢁI Valid to ꢀCLK ꢀetup Time
DꢁI Valid to ꢀCLK Hold Time
ꢀCLK Pulse Width High
ꢀCLK Pulse Width Low
1
ns
2
9
ns
3
9
ns
4
⎯
⎯
Cꢀ Pulse High Width
10
8
ns
5
⎯
⎯
LꢀS ꢀCLK High to Cꢀ High
ns
6
⎯
⎯
Cꢀ Low to ꢀCLK High
8
ns
7
⎯
⎯
Cꢀ High to ꢀCLK Positive Edge
8
ns
8
⎯
⎯
⎯
CLR Pulse Width Low
ꢀCLK Frequency
15
ns
9
50% Duty Cycle
50
MHz
μs
ꢀCLK
⎯
⎯
V
DD
High to Cꢀ Low (Power-Up DelayN
30
Note 4: R
tolerance is typically 20%.
Note 1: ꢀtresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
OUT
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588N in unipolar mode and at 671Chex (26, 396N in bipolar
mode.
Note ±: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
Note 3: LTC2641-16/LTC2642-16 1LꢀS = 0.0015% = 15.3ppm of full
scale. LTC2641-14/LTC2642-14 1LꢀS = 0.006% = 61ppm of full scale.
LTC2641-12/LTC2642-12 1LꢀS = 0.024% = 244ppm of full scale.
tested.
26412f
5
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
Integral Nonlinearity (INL)
INL ꢁs VREF
ꢁs ꢀupply (VDD
)
1.0
0.8
1.0
0.8
1.0
0.8
V
= 2.5V
V
= 5.5V
REF
LTC2642-16
DD
V
V
= 2.5V
REF
= 5V
DD
0.6
0.6
0.6
+INL
+INL
–INL
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–INL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2
3
4
5
6
2
3
4
5
6
V
(V)
V
(V)
DD
REF
26412 G01
26412 G02
26412 G03
Differential Nonlinearity (DNL)
ꢁs ꢀupply (VDD
)
Differential Nonlinearity (DNL)
DNL ꢁs VREF
1.0
0.8
1.0
0.8
1.0
0.8
V
= 2.5V
V
= 5.5V
DD
REF
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
+DNL
–DNL
+DNL
–DNL
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
2
3
4
5
6
2
3
4
5
6
0
16384
32768
CODE
49152
65535
V
(V)
V
(V)
REF
DD
26412 G05
26412 G06
26412 G04
INL ꢁs Temperature
DNL ꢁs Temperature
Bipolar Zero Error ꢁs Temperature
1.0
0.8
5
4
1.0
0.8
V
V
= 2.5V
REF
= 5V
DD
V
V
= 2.5V
REF
= 5V
DD
V
V
= 2.5V
REF
= 5V
DD
0.6
0.6
3
+INL
–INL
0.4
0.4
2
0.2
0.2
+DNL
–DNL
1
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
26412 G07
26412 G08
26412 G09
26412f
6
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Unbuffered Zero ꢀcale Error ꢁs
Temperature (LTC±641-16)
Unbuffered Full-ꢀcale Error ꢁs
Temperature (LTC±641-16)
1.0
Bipolar Gain Error ꢁs Temperature
5
4
1.0
0.8
V
V
= 2.5V
REF
= 5V
DD
0.8
0.6
0.4
0.2
0
3
0.6
2
0.4
1
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
26412 G10
26412 G12
26412 G11
14-Bit Integral Nonlinearity (INL)
(LTC±64±-14)
14-Bit Differential Nonlinearity
(DNL) (LTC±64±-14)
IREF ꢁs Code (Unipolar LTC±641)
1.0
0.8
1.0
0.8
250
200
150
100
50
V
= 2.5V
REF
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
4096
8192
12288
16383
32768
CODE
0
4096
8192
12288
16383
0
16384
49152
65535
CODE
CODE
26412 G14
26412 G13
26412 G15
1±-Bit Integral Nonlinearity (INL)
(LTC±64±-1±)
1±-Bit Differential Nonlinearity
(DNL) (LTC±64±-1±)
IREF ꢁs Code (Bipolar LTC±64±)
1.0
0.8
1.0
0.8
250
200
150
100
50
V
= 2.5V
REF
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32768
CODE
49152
0
16384
0
1024
2048
3072
4095
0
1024
2048
3072
4095
65535
CODE
CODE
26412 G18
26412 G16
26412 G17
26412f
7
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
ꢀupply Current (IDD) ꢁs
Temperature
ꢀupply Current (IDD) ꢁs ꢀupply
Voltage (VDD
ꢀupply Current (IDD) ꢁs Digital
Input Voltage
)
150
125
150
125
100
75
900
800
700
600
500
400
300
200
100
0
V
= 2.5V
V
= 2.5V
REF
REF
V
V
= 5V
= 3V
DD
DD
V
= 5V
DD
100
75
50
25
0
50
V
= 3V
DD
25
0
–40
–15
10
35
60
85
2.5
3.5
4
4.5
5
5.5
3
0
0.5
1
1.5
2
2.5
5
3
3.5 4 4.5
TEMPERATURE (°C)
V
(V)
DIGITAL INPUT VOLTAGE (V)
DD
26412 G19
26412 G20
26412 G21
ꢀupply Current (IDD) ꢁs VREF
,
ꢀupply Current (IDD) ꢁs VREF
,
Midscale Glitch Impulse
VDD = 5V
VDD = 3V
150
125
100
75
150
125
100
75
CS
5V/DIV
V
= 5V
V
= 3V
DD
DD
CODE
32767
CODE
32768
CODE
32767
V
OUT
20mV/DIV
50
50
26412 G24
25
25
LTC2641-16
500ns/DIV
UNBUFFERED
C
= 10pF
L
0
0
3.5
4
2.5
1
1.5
2
2.5
3
4.5
5
1
1.5
2
3
V
(V)
V
REF
(V)
REF
26412 G22
26412 G23
VOUT ꢁs VDD = 0V to 5.5V
(POR Function) LTC±641
Full-ꢀcale Transition
Full-ꢀcale ꢀettling (Zoomed In)
CS
CS
V
= V
REF
5V/DIV
DD
5V/DIV
0V TO 5.5V
2V/DIV
SETTLE
RESIDUE
250μV/DIV
V
OUT
V
OUT
1V/DIV
10mV/DIV
26412 G27
26412 G25
26412 G26
LTC2641-16
= 2.5V
CONSULT FACTORY FOR
MEASUREMENT CIRCUIT
500ns/DIV
LTC2641-16
50ms/DIV
LTC2641-16
500ns/DIV
V
UNBUFFERED
UNBUFFERED
REF
C
= 10pF
C
V
V
= 10pF
L
L
= 2.5V
REF
= 5V
DD
26412f
8
LTC2641/LTC2642
PIN FUNCTIONS
LTC±641
LTC±64±
REF (Pin 1): Reference Voltage ꢁnput. Apply an external
REF (Pin 1): Reference Voltage ꢁnput. Apply an external
reference at REF between 2V and V .
reference at REF between 2V and V .
DD
DD
⎯
⎯
⎯
⎯
⎯
⎯
Cꢀ (Pin ±): ꢀerial ꢁnterface Chip ꢀelect/Load ꢁnput. When
Cꢀ (Pin ±): ꢀerial ꢁnterface Chip ꢀelect/Load ꢁnput. When
⎯
⎯
Cꢀ is low, ꢀCLK is enabled for shifting in data on DꢁI.
Cꢀ is low, ꢀCLK is enabled for shifting in data on DꢁI.
⎯
⎯
⎯
⎯
When Cꢀ is taken high, ꢀCLK is disabled, the 16-bit input
word is latched and the DAC is updated
When Cꢀ is taken high, ꢀCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
ꢀCLK (Pin 3): ꢀerial ꢁnterface Clock ꢁnput. CMOꢀ and
TTL compatible.
ꢀCLK (Pin 3): ꢀerial ꢁnterface Clock ꢁnput. CMOꢀ and
TTL compatible.
DIN (Pin 4): ꢀerial ꢁnterface Data ꢁnput. Data is applied
to DꢁI for transfer to the device at the rising edge of
ꢀCLK.
DIN (Pin 4): ꢀerial ꢁnterface Data ꢁnput. Data is applied
to DꢁI for transfer to the device at the rising edge of
ꢀCLK.
⎯
⎯
⎯
⎯
⎯
⎯
CLR (Pin 5): Asynchronous Clear ꢁnput. A logic low clears
CLR (Pin 5): Asynchronous Clear ꢁnput. A logic low clears
the DAC to midscale.
the DAC to code 0.
V
(Pin 6): DAC Output Voltage. The output range is
REF
V
(Pin 6): DAC Output Voltage. The output range is
REF
OUT
0V to V
OUT
0V to V
.
.
INV (Pin 7): Center Tap of ꢁnternal ꢀcaling Resistors.
Connecttoanexternalamplifier’sinvertinginputinbipolar
mode.
V
(Pin 7): ꢀupply Voltage. ꢀet between 2.7V and
DD
5.5V.
GND (Pin 8): Circuit Ground.
R
(Pin 8): Feedback Resistor. Connect to an external
FB
Exposed Pad (DFN Pin 9): Circuit Ground. Must be sol-
dered to PCS ground.
amplifier’s output in bipolar mode. The bipolar output
range is –V to V
.
REF
REF
V
(Pin 9): ꢀupply Voltage. ꢀet between 2.7V and
DD
5.5V.
GND (Pin 10): Circuit Ground.
Exposed Pad (DFN Pin 11): Circuit Ground. Must be
soldered to PCS ground.
26412f
9
LTC2641/LTC2642
BLOCK DIAGRAMS
LTC±641
LTC±64±
7
1
9
1
REF
REF
V
V
DD
DD
R
FB
8
7
LTC2641-16
LTC2641-14
LTC2641-12
LTC2642-16
LTC2642-14
LTC2642-12
INV
V
OUT
V
OUT
POWER-ON
RESET
POWER-ON
RESET
16-/14-/12-BIT DAC
6
16-/14-/12-BIT DAC
6
CS
CS
2
3
4
5
2
3
4
5
SCLK
DIN
CLR
SCLK
DIN
CLR
CONTROL
LOGIC
CONTROL
LOGIC
16-BIT DATA LATCH
16-BIT DATA LATCH
16-BIT SHIFT REGISTER
16-BIT SHIFT REGISTER
GND
8
GND
10
2641 BD
2642 BD
TIMING DIAGRAM
t
1
t
t
t
t
6
2
3
4
1
2
3
15
16
SCK
SDI
t
8
t
5
t
7
26412 TD
CS/LD
OPERATION
General Description
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOꢀ
switches. TheLTC2641/LTC2642DACresistorladdersare
composed of a proprietary arrangement of matched DAC
sections. The four MꢀSs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
2LꢀSintegrallinearityerrorandlessthan 1LꢀSdifferen-
tiallinearityerror,guaranteeingmonotonicoperation.They
operate from a single supply ranging from 2.7V to 5.5V,
consuming 120μA (typicalN. An external voltage reference
of 2V to V determines the DAC’s full-scale output volt-
DD
impulse is very low at 500pV•sec, C = 10pF, ten times
age.A3-wireserialinterfaceallowstheLTC2641/LTC2642
to fit into a small 8-/10-pin MꢀOP or DFI 3mm × 3mm
package.
L
lower than previous DACs of this type.
26412f
10
LTC2641/LTC2642
OPERATION
The digital-to-analog transfer function at the V
is:
⎯
⎯
pin
chip select input (CꢀN controls and frames the loading
OUT
⎯
⎯
of serial data from the data input (DꢁIN. Following a Cꢀ
high-to-low transition, the data on DꢁI is loaded, MꢀS
first, into the shift register on each rising edge of the serial
clock input (ꢀCLKN. After 16 data bits have been loaded
intotheserialinputregister, alow-to-hightransitiononCꢀ
transfersthedatatothe16-bitDAClatch,updatingtheDAC
output (see Figures 1a, 1b, 1cN. While Cꢀ remains high,
the serial input shift register is disabled. ꢁf there are less
than16low-to-hightransitionsonꢀCLKwhileCꢀremains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on ꢀCLK while Cꢀ remains low, only the last 16 data bits
loaded from DꢁI will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14N, the MꢀS
remains in the same (left-justifiedN position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LꢀS, to make up the required 16 data
bits (Figure 1bN. ꢀimilarly, for the 12-bit family members
(LTC2641-12/LTC2642-12N four “don’t-care” bits must
follow the LꢀS (Figure 1cN.
k
⎛
⎞
⎠
VOUT(IDEAL)
=
V
⎜
⎝
N⎟ REF
2
⎯
⎯
where k is the decimal equivalent of the binary DAC input
code, I is the resolution, and V is between 2.0V and
REF
⎯
⎯
V
(see Tables 1a, 1b and 1cN.
DD
The LTC2642 includes matched resistors that are tied to
an external amplifier to provide bipolar output swing (Fig-
ure 2N. The bipolar transfer function at the RFS pin is:
⎯
⎯
⎯
⎯
k
N–1
⎛
⎞
⎠
VOUT _BIPOLAR(IDEAL) = VREF ⎜
– 1
⎟
⎝
2
(see Tables 2a, 2b and 2cN.
ꢀerial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire ꢀPꢁ/QꢀPꢁ/MꢁCROWꢁRE compatible interface. The
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
26412 F01a
DATA (16 BITS)
Figure 1a. 16-Bit Timing Diagram (LTC±641-16/LTC±64±-16)
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
26412 F01b
DATA (14 BITS + 2 DON’T-CARE BITS)
Figure 1b. 14-Bit Timing Diagram (LTC±641-14/LTC±64±-14)
CS
SCLK
DIN
DAC
UPDATED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
X
X
26412 F01c
DATA (12 BITS + 4 DON’T-CARE BITS)
Figure 1c. 1±-Bit Timing Diagram (LTC±641-1±/LTC±64±-1±)
26412f
11
LTC2641/LTC2642
OPERATION
Power-On Reset
32,768 (LTC2642-16N; 8,192 (LTC2642-14N; or 2,048
(LTC2642-12N.
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC ouput comes up in a known state.
Clearing the DAC
When V is first applied, the power-on reset circuit sets
DD
⎯
⎯
⎯
A 10ns (minimumN low pulse on the CLR pin asynchro-
nously clears the DAC latch to code zero (LTC2641N or to
midscale (LTC2642N.
the output of the LTC2641 to zero-scale (code 0N. The
LTC2642 powers up to midscale (bipolar zeroN. Depend-
ing on the DAC number of bits, the midscale code is:
APPLICATIONS INFORMATION
Unipolar Configuration
The external amplifier provides a unity-gain buffer. The
LTC2642 can also be used in unipolar configuration by
Figure 2 shows a typical unipolar DAC application for
the LTC2641. Tables 1a, 1b and 1c show the unipolar
binary code tables for 16-bit, 14-bit and 12-bit operation.
tying R and ꢁIV to REF. This provides power-up and
FS
clear to midscale.
V
REF
2.5V
OUT
LT®1019CS8-2.5
IN
5V
0.1μF
4.7μF
Table 1a. 16-Bit Unipolar Binary Code Table
(LTC±641-16)
5V/3V
7
GND
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
0.1μF
ANALOG OUTPUT
(V
5V/3V
0.1μF
1
REF
)
OUT
V
DD
MꢀS
LꢀS
–
LTC2641-16
1111 1111 1111 1111 V (65,535/65,536N
UNIPOLAR V
0V TO 2.5V
REF
OUT
1/2 LTC6078
V
6
OUT
+
1000 0000 0000 0000 V (32,768/65,536N = V /2
REF
REF
2
3
4
5
16-BIT DAC
CS
0000 0000 0000 0001 V (1/65,536N
REF
SCLK
DIN
CLR
0000 0000 0000 0000 0V
GND
8
26412 F02
Figure ±. 16-Bit Unipolar Output (LTC±641-16) Unipolar VOUT = 0V to VREF
Table 1b. 14-Bit Unipolar Binary Code Table
(LTC±641-14)
Table 1c. 1±-Bit Unipolar Binary Code Table
(LTC±641-1±)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
)
)
OUT
OUT
MꢀS
LꢀS
MꢀS
LꢀS
1111 1111 1111 11xx V (16,383/16,384N
1111 1111 1111 xxxx
1000 0000 0000 xxxx
0000 0000 0001 xxxx
V
REF
V
REF
V
REF
(4,095/4,096N
REF
1000 0000 0000 00xx V (8,192/16,384N = V /2
(2,048/4,096N = V /2
REF
REF
REF
0000 0000 0000 01xx V (1/16,384N
(1/4,096N
REF
0000 0000 0000 00xx 0V
0000 0000 0000 xxxx 0V
26412f
12
LTC2641/LTC2642
APPLICATIONS INFORMATION
Bipolar Configuration
The amplifier circuit provides a gain of +2 from the V
OUT
pin, and gain of –1 from V . Tables 2a, 2b and 2c show
REF
Figure 3 shows a typical bipolar DAC application for the
the bipolar offset binary code tables for 16-bit, 14-bit and
12-bit operation.
LTC2642. The on-chip bipolar offset/gain resistors, R
FS
andR ,areconnectedtoanexternalamplifiertoproduce
ꢁIV
a bipolar output swing from –V to V at the R pin.
REF
REF
FS
V
REF
2.5V
5V/3V
OUT
LT1019CS8-2.5
GND
IN
5V
0.1μF
4.7μF
0.1μF
9
1
REF
V
DD
R
FB
8
5V
0.1μF
0.1μF
LTC2642-16
C1
10pF
–
INV
OUT
7
6
BIPOLAR V
OUT
1/2 LT1678
–2.5V TO 2.5V
V
+
2
3
4
5
16-BIT DAC
CS
SCLK
DIN
CLR
–5V
GND
10
26412 F02
Figure 3. 16-Bit Bipolar Output (LTC±64±-16) VOUT = –VREF to VREF
Table ±a. 16-Bit Bipolar Offset Binary
Code Table (LTC±64±-16)
Table ±b. 14-Bit Bipolar Offset Binary
Code Table (LTC±64±-14)
Table ±c. 1±-Bit Bipolar Offset Binary
Code Table (LTC±64±-1±)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
ANALOG OUTPUT
(V
)
)
)
OUT
OUT
OUT
MꢀS
LꢀS
MꢀS
LꢀS
MꢀS
LꢀS
1111 1111 1111 1111 V (32,767/32,768N
1111 1111 1111 11xx V (8,191/8,192N
1111 1111 1111 xxxx
1000 0000 0001 xxxx
V
V
(2,047/2,048N
(1/2,048N
REF
REF
REF
1000 0000 0000 0001 V (1/32,768N
1000 0000 0000 01xx V (1/8,192N
REF
REF
REF
1000 0000 0000 0000 0V
1000 0000 0000 00xx 0V
1000 0000 0000 xxxx 0V
0111 1111 1111 xxxx –V (1/2048N
0111 1111 1111 1111 –V (1/32,768N
0111 1111 1111 11xx –V (1/8,192N
REF
REF
REF
0000 0000 0000 0000 –V
0000 0000 0000 00xx –V
0000 0000 0000 xxxx –V
REF
REF
REF
26412f
13
LTC2641/LTC2642
APPLICATIONS INFORMATION
Unbuffered Operation and V
Loading
it is critical to protect the V
leakage current.
pin from any sources of
OUT
OUT
The DAC output is available directly at the V
pin, which
OUT
swings from GID to V . Unbuffered operation provides
REF
Unbuffered V
ꢀettling Time
OUT
thelowestpossibleoffset,full-scaleandlinearityerrors,the
fastest settling time and minimum power consumption.
The settling time at the V
pin can be closely approxi-
OUT
mated by a single-pole response where:
However, unbuffered operation requires that appropriate
τ = R • (C + C N
loading be maintained on the V
pin. The LTC2641/
OUT
OUT
L
OUT
LTC2642 V
can be modeled as an ideal voltage source
OUT
(Figure 4N. ꢀettling to 1/2LꢀS at 16-bits requires about
12 time constants (ln(2 • 65,536NN. The typical settling
time of 1μs corresponds to a time constant of 83ns, and
in series with a source resistance of R , typically 6.2k
OUT
(Figure 4N. The DAC’s linear output impedance allows
it to drive medium loads (R > 60kN without degrading
L
a total (C
+ C N of about 83ns/6.2k = 13pF. The internal
OUT
OUT
L
ꢁIL or DIL; only the gain error is increased. The gain
capacitance, C
is typically 10pF, so an external C of
L
error (GEN caused by a load resistance, R , (relative to
L
3pF corresponds to 1μs settling to 1/2LꢀS.
full scaleN is:
V
REF
–1
GE =
⎛
⎝
⎞
⎠
ROUT
RL
REF
R
LTC2641
LTC2642
1+
V
OUT
OUT
⎜
⎟
V
OUT
+
–
0V TO V
REF
CODE
C
OUT
R
C
I
L
V
L
L
REF
(
N
)
2
ꢁn 16-bit LꢀSs:
–65536
26412 F04
GND
GE =
LSB
[
]
⎛
⎞
ROUT
RL
Figure 4. VOUT Pin Equiꢁalent Circuit
1+
⎜
⎟
⎝
⎠
Op Amp ꢀelection
R
has a low tempco (typically < 50ppm/°CN, and is
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
OUT
independent of DAC code. The variation of R , part-to-
OUT
part, is typically less than 20%.
Iote on LꢀS units:
For the following error descriptions, “LꢀS” means 16-bit
LꢀS and 65,536 is rounded to 66k.
To convert to 14-bit LꢀSs (LTC2641-14/LTC2642-14N
divide by 4.
ꢁn bipolar mode (LTC2642 onlyN, the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. ꢁn this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
To convert to 12-bit LꢀSs (LTC2641-12/LTC2642-12N
divide by 16.
A constant current, ꢁ , loading V
will produce an offset
L
OUT
of:
V
output range (Figure 3N.
REF
V
= –ꢁ • R
L OUT
OFFꢀET
ꢁn unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applica-
tions a precision, rail-to-rail input, single supply op amp
ForV =2.5V, a16-bitLꢀSequals2.5V/65,536, or38μV.
REF
ꢀince R
is 6.2k, an ꢁ of 6nA produces an offset of
OUT
L
1LꢀS. Therefore, to avoid degrading DAC performance,
26412f
14
LTC2641/LTC2642
APPLICATIONS INFORMATION
suchastheLTC6078issuitable, iftheapplicationdoesnot
require linear operation very near to GID, or zero scale
(Figure 2N. The LTC6078 typically swings to within 1mV
of GID if it is not required to sink any load current. For an
LꢀS size of 38μV, 1mV represents 26 missing codes near
zero scale. Linearity will be degraded over a somewhat
larger range of codes above GID. ꢁt is also unavoidable
that settling time and transient performance will degrade
whenever a single supply amplifier is operated very close
to GID, or to the positive supply rail.
voltage temperature coefficient (referenced to 25°CN of
0.6ꢂV/°C will add 1LꢀS of zero-scale error. Also, ꢁ
and
SꢁAꢀ
the V
error it causes, will typically show significant
OFFꢀET
relative variation over temperature.
Op amp open-loop gain, A , contributes to DAC gain
VOL
error (GEN:
66k
AVOL
GE =
LSB
[
]
Op amp input common mode rejection ratio (CMRRN is an
input-referred error that corresponds to a combination of
gain error (GEN and ꢁIL, depending on the op amp archi-
tecture and operating conditions. A conservative estimate
of total CMRR error is:
The small LꢀS size of a 16-bit DAC, coupled with the tight
accuracy specifications on the LTC2641/LTC2642, means
that the accuracy and input specifications for the external
op amp are critical for overall DAC performance.
Op Amp ꢀpecifications and Unipolar DAC Accuracy
CMRR
20
⎛
⎞
⎛
⎞
⎟
⎜
⎝
⎟
⎠
V
⎛
⎞
CMRR_RANGE
⎜
Most op amp accuracy specifications convert easily to
DAC accuracy.
Error = 10
•
• 66k LSB
[
]
⎜
⎟
⎜
⎝
⎟
⎠
VREF
⎝
⎠
Op amp input bias current on the noninverting (+N input is
where V
is the voltage range that CMRR (in
CMRR_RAIGE
equivalent to an ꢁ loading the DAC V
pin and therefore
L
OUT
dSNisspecifiedover.OpampTypicalPerformanceCharac-
teristics graphs are useful to predict the impact of CMRR
errors on DAC performance. Typically, a precision op amp
will exhibit a fairly linear CMRR behavior (corresponding
to DAC gain error onlyN over most of the common mode
input range (CMRN, and become nonlinear and produce
significant errors near the edge of the CMR.
produces a DAC zero-scale error (ZꢀEN (see Unbuffered
OperationN:
ZꢀE = –ꢁ (ꢁI+N • R
[Volts]
S
OUT
ꢁn 16-bit LꢀSs:
⎛
⎞
66k
ZSE = –I IN+ • 6.2k •
LSB
[
]
(
)
B
⎜
⎟
V
⎝
⎠
REF
Rail-to-rail input op amps are a special case, because they
have 2 distinct input stages, one with CMR to GID and
the other with CMR to V . This results in a “crossover”
CM input region where operation switches between the
two input stages.
Op amp input impedance, R , is equivalent to an R
ꢁI
L
+
loading the LTC2641/LTC2642 V
gain error of:
pin, and produces a
OUT
–66k
The LTC6078 rail-to-rail input op amp typically exhibits
remarkably low crossover linearity error, as shown in the
GE =
LSB
[
]
⎛
⎞
⎠
6.2k
1+
⎜
⎟
R
V
vs V Typical Performance Characteristics graphs
⎝
Oꢀ
CM
IN
(see the LTC6078 data sheetN. Crossover occurs at CM
+
Op amp offset voltage, V , corresponds directly to DAC
inputs about 1V below V , and an LTC6078 operating as
Oꢀ
+
zero code offset error, ZꢀE:
a unipolar DAC buffer with V = 2.5V and V = 5V will
REF
typically add only about 1LꢀS of GE and almost no ꢁIL
66k
VREF
ZSE = VOS
•
LSB
error due to CMRR. Even in a full rail-to-rail application,
[
]
+
with V = V = 5V, a typical LTC6078 will add only about
REF
1LꢀS of ꢁIL at 16-bits.
Temperature effects also must be considered. Over the
–40°C to 85°C industrial temperature range, an offset
26412f
15
LTC2641/LTC2642
APPLICATIONS INFORMATION
Op Amp ꢀpecifications and Bipolar DAC Accuracy
introduce a zero that will partially cancel this pole. C1
should nominally be <C , typically in the range of 5pF
P
TheopampcontributionstounipolarDACerrordiscussed
above apply equally to bipolar operation. The bipolar ap-
plication circuit gains up the DAC span, and all errors, by
a factor of 2. ꢀince the LꢀS size also doubles, the errors
in LꢀSs are identical in unipolar and bipolar modes.
to 10pF. This will restore the phase margin and improve
coarse settling time, but a pole-zero doublet will unavoid-
ably leave a slower settling tail, with a time constant of
roughly (C + C1N • 28k/2, which will limit 16-bit settling
P
time to be greater than 2μs.
–
One added error in bipolar mode comes from ꢁ (ꢁI N,
S
Reference and GND Input
which flows through R to generate an offset. The full
FS
bias current offset error becomes:
TheLTC2641/LTC2642operateswithexternalvoltagerefer-
–
+
ences from 2V to V , and linearity, offset and gain errors
V
= (ꢁ (ꢁI N • R – ꢁ (ꢁI N • R • 2N [Volts]
OUT
DD
OFFꢀET
S
FS
S
are virtually unchanged vs V . Full 16-bit performance
REF
ꢀo:
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typi-
cal, corresponds to less than 0.5LꢀS variation over the
–40°C to 85°C temperature range. ꢁn practice, this means
thattheoverallgainerrortempcowillbedeterminedalmost
entirely by the external reference tempco.
33k
VOFFSET = I (IN–)• 28k –I (IN+)•12.4k •
[LSB]
VREF
(
)
B
B
ꢀettling Time with Op Amp Buffer
Whenusinganexternalopamp,theoutputsettlingtimewill
stillincludethesinglepolesettlingontheLTC2641/LTC2642
V
node, with time constant R • (C
+ C N (see Un-
TheDACvoltage-switchingmode“inverted”resistorladder
architectureusedintheLTC2641/LTC2642exhibitsarefer-
OUT
OUT
OUT L
bufferedV ꢀettlingTimeN.C willincludethebufferinput
OUT
L
capacitance and PC board interconnect capacitance.
ence input resistance (R N that is code dependent (see
REF
the Typical Performance curves ꢁ vs ꢁnput CodeN.
REF
Theexternalbufferamplifieraddsanotherpoletotheoutput
response, with a time constant equal to (fbandwidth/2πN.
ꢁn unipolar mode, the minimum R
is 14.8k (at code
REF
For example, assume that C is maintained at the same
871Chex, 34,588 decimalN and the the maximum R is
L
REF
value as above, so that the V
node time constant is
300k at code 0000hex (zero scaleN. The maximum change
OUT
83ns = 1ꢂs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2π • 83nsN = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
in ꢁ for a 2.5V reference is 160μA. ꢀince the maximum
REF
occursnearmidscale, theꢁILerrorisaboutonehalfofthe
change on V , so maintaining an ꢁIL error of <0.1LꢀS
REF
requiresareferenceloadregulationof(1.53ppm•2/160μAN
=19[ppm/mA].Thisimpliesareferenceoutputimpedance
of 48mΩ, including series wiring resistance.
⎯
root square sum of the individual time constants, or √2
• 83ns = 117ns, and 1/2 LꢀS settling time will be ~12 •
117ns = 1.4ꢂs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. ꢁn practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1ꢂs.
To prevent output glitches from occuring when resistor
ladder branches switch from GID to V , the reference
REF
inputmustmaintainlowimpedanceathigherfrequencies.
A 0.1ꢂF ceramic capacitor with short leads between REF
and GID provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1ꢂF between REF
and GID provides low frequency bypassing. The circuit
will benefit from even higher bypass capacitance, as long
as the external reference remains stable with the added
The output settling time for bipolar applications (Figure 3N
will be somewhat increased due to the feedback resistor
network R and R (each 28k nominalN. The parasitic
FS
ꢁIV
capacitance,C ,ontheopamp(–Ninputnodewillintroduce
P
a feedback loop pole with a time constant of (C • 28k/2N.
P
A small feedback capacitor, C1, should be included, to
capacative loading.
26412f
16
LTC2641/LTC2642
APPLICATIONS INFORMATION
Digital Inputs and Interface Logic
return current paths flow through the “star GID” area. ꢁn
particular, theresistancefromtheLTC2641GIDpintothe
All of the digital inputs include ꢀchmitt-trigger buffers
to accept slow transition interfaces. This means that op-
tocuplers can interface directly to the LTC2641/LTC2642
without additional external logic. Digital input hysteresis
is typically 150mV.
point where the V input source connects to the ground
REF
plane should be as low as possible. Excessive resistance
here will be multiplied by the code dependent ꢁ current
REF
to produce an ꢁIL error similar to the error produced by
V
REF
source resistance.
The digital inputs are compatible with TTL/CMOꢀ-logic
levels. However, rail-to-rail (CMOꢀN logic swings are
preferred, because operating the logic inputs away from
ꢀourcesofgroundreturncurrentintheanalogareainclude
op amp power supply bypass capacitors and the GID
connection for single supply amps. A useful technique
for minimizing errors is to use a separate board layer
for power ground return connections, and reserve one
ground plane layer for low current “signal” GID connec-
tions. The “signal”, or “star” GID plane must connected
to the “power” GID plane at a single point, which should
be located near the LTC2641/LTC2642 GID pin.
the supply rails generates additional ꢁ and GID current,
DD
(see Typical Performance Characteristic graph ꢀupply
Current vs Logic ꢁnput VoltageN.
Digital feedthrough is only 0.2nV•s typical, but it is always
preferredtokeepalllogicinputsstaticexceptwhenloading
a new code into the DAC.
ꢁfseparateanaloganddigitalgroundareasexistitisneces-
sary to connect them at a single location, which should be
fairly close to the DAC for digital signal integrity. ꢁn some
systems, large GID return currents can flow between the
digital and analog GIDs, especially if different PC boards
are involved. ꢁn such cases the digital and analog ground
connection point should not be made right at the “star”
GID area, so the highly sensitive analog signals are not
corrupted.ꢁfforcedtochoose,alwaysplaceanalogground
quality ahead of digital signal ground. (A few mV of noise
on the digital inputs is imperceptible, thanks to the digital
input hysteresisN
Board Layout for Precision
Even a small amount of board leakage can degrade ac-
curacy. The 6nA leakage current into V
needed to
OUT
generate1LꢀSoffseterrorcorrespondsto833MΩleakage
resistance from a 5V supply.
The V
node is relatively sensitive to capacitive noise
OUT
coupling, so minimum trace length, appropriate shielding
and clean board layout are imperative here.
Temperature differences at the DAC, op amp or reference
pins can easily generate tens of microvolts of thermo-
couple voltages. Analog signal traces should be short,
close together and away from heat dissipating compo-
nents. Air currents across the board can also generate
thermocouples.
Just by maintaining separate areas on the GID plane
where analog and digital return currents naturally flow,
good results are generally achieved. Only after this has
been done, it is sometimes useful to interrupt the ground
planewithstrategicallyplaced“slots”,topreventthedigital
ground currents from fringing into the analog portion of
the plane. When doing this, the gap in the plane should be
only as long as it needs to be to serve its purpose.
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane.
Caution: if a GID plane gap is improperly placed, so that
it interrupts a significant GID return path, or if a signal
traces crosses over the gap, then adding the gap may
greatly degrade performance! ꢁn this case, the GID and
signal return currents are forced to flow the long way
around the gap, and then are typically channeled directly
A “star ground” area should be established by attaching
the LTC2641/LTC2642 GID pin, V
GID and the DAC
REF
V
GID reference terminal to the same area on the GID
OUT
plane. Care should be taken to ensure that no large GID
into the most sensitive area of the analog GID plane.
26412f
17
LTC2641/LTC2642
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698N
R = 0.115
0.38 0.10
TYP
5
8
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699N
R = 0.115
0.38 0.10
TYP
6
10
0.675 0.05
3.50 0.05
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
2.15 0.05 (2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.10
(2 SIDES)
2.38 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
26412f
18
LTC2641/LTC2642
PACKAGE DESCRIPTION
Mꢀ8 Package
8-Lead Plastic MꢀOP
(Reference LTC DWG # 05-08-1660 Rev FN
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6
5
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
0.889 0.127
(.035 .005)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
1
2
3
4
0.53 0.152
(.021 .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
SEATING
PLANE
0.22 – 0.38
RECOMMENDED SOLDER PAD LAYOUT
0.1016 0.0508
(.009 – .015)
(.004 .002)
NOTE:
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Mꢀ Package
10-Lead Plastic MꢀOP
(Reference LTC DWG # 05-08-1661 Rev EN
3.00 0.102
(.118 .004)
(NOTE 3)
0.497 0.076
(.0196 .003)
REF
10 9
8
7 6
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.254
0.889 0.127
(.035 .005)
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.53 0.152
(.021 .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
0.50
(.0197)
BSC
0.305 0.038
(.0120 .0015)
TYP
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
RECOMMENDED SOLDER PAD LAYOUT
0.50
(.0197)
BSC
NOTE:
MSOP (MS) 0307 REV E
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
26412f
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2641/LTC2642
TYPICAL APPLICATION
Wide Range Current Load ꢀinks 0A to ±.5A
V
REF
2.5V
OUT
IN
5V
5V
0.1μF
0.1μF
4.7μF
LT1019CS8-2.5
GND
10V
7
1
REF
V
DD
0.1μF
LTC2641-16
I
SINK
0A TO 2.5A
V
6
OUT
+
2
3
4
5
16-BIT DAC
CS
1k
SCLK
DIN
CLR
IRLZ44
LTC2054HV
–
0.033μF
GND
8
10k
1Ω
10W
26412 TA02
RELATED PARTS
PART NUMBER
DEꢀCRIPTION
COMMENTꢀ
DACs
LTC1588/LTC1589 12-/14-/16-Sit ꢀoftꢀpanTM Current Output DACs
LTC1592
ꢀoftware Programmable Output Ranges up to 10V
LTC1595/LTC1596 ꢀerial 16-Sit Current Output DACs
Low Glitch, 1LꢀS Maximum ꢁIL, DIL
1LꢀS Max ꢁIL, DIL, 10V Output
LTC1591/LTC1597 Parallel 14-/16-Sit Current Output DACs
LTC1599
LTC1650
16-Sit Current Output DAC
16-Sit Voltage Output DAC
1LꢀS Max ꢁIL, DIL, 10V Output
2nV•s Glitch ꢁmpulse, 30nV/√Hz Ioise
ꢀingle DACs, ꢀingle ꢀupply, 0V to 5V Outputs in DFI10
LTC2621/LTC2611 12-/14-/16-Sit ꢀerial Voltage Output DACs
LTC2601
LTC2704-12
LTC2704-14
LTC2704-16
12-/14-/16-Sit Quad Voltage Output DACs
ꢀoftware Programmable Output Ranges up to 10V, ꢀerial ꢁ/O
Op Amps
LT®1678
LTC2054
LT6010
Dual Low Ioise Rail-to-Rail Precision Op Amp
Micropower Zero Drift Op Amp
3.9nV/√Hz at 1MHz
3μV Maximum Offset
150μA 8nV/√Hz Rail-to-Rail Output Precision Op Amp
Dual CMOꢀ Rail-to-Rail ꢁnput/Output Amplifier
Micropower
LTC6078
References
LT1019
54μA per Amp, 16nV/√Hz ꢁnput Ioise Voltage
Precision Sandgap Reference
0.005% Max, 5ppm/°C Max
ꢀoftꢀpan is a trademark of Linear Technology Corporation.
26412f
LT 0707 • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Slvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408N 432-1900 FAX: (408N 434-0507 www.linear.com
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