LTC2751AIUHF-16#TRPBF

LTC2751

Current Output

12-/14-/16-Bit SoftSpan

DACs with Parallel I/O

FeaTures

DescripTion

The LTC^®2751 is a family of 12-, 14-, and 16-bit multi-

plying parallel-input, current-output DACs. They operate

from a single 2.7V to 5.5V supply. All parts are guaranteed

monotonic over temperature. The LTC2751A-16 provides

16-bitperformance( 1LSBINLandDNL)overtemperature

withoutanyadjustments.TheseSoftSpan™DACsoffersix

outputranges—twounipolarandfourbipolar—thatcanbe

programmedthroughtheparallelinterface,orpinstrapped

for operation in a single range.

n

Six Programmable Output Ranges

Unipolar: 0V to 5V, 0V to 10V

Bipolar: 5V, 10V, ꢀꢁ5V, ꢂꢀꢁ5V to ꢃꢁ5V

n

Maximum 16-Bit INL Error: 1 LSB over Temperature

n

Low 1µA (Maximum) Supply Current

n

Guaranteed Monotonic over Temperature

n

Low Glitch Impulse 1nV • s

n

2.7V to 5.5V Single Supply Operation

n

2µs Settling Time to 1 LSB

Reference Input: 15V

n

These parts use a bidirectional input/output parallel in-

terface that allows readback of any on-chip register. A

power-oncircuitresetstheDACoutputto0Vwhenpoweris

initiallyapplied.AlogiclowontheCLRpinasynchronously

clears the DAC to 0V in any output range.

n

Parallel Interface with Readback of All Registers

Asynchronous CLR Pin Clears DAC Output to 0V in

Any Output Range

Power-On Reset to 0V

38-Pin 5mm × 7mm QFN Package

n

The parts are specified over commercial and industrial

temperature ranges.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

applicaTions

n

High Resolution Offset and Gain Adjustment

n

Process Control and Industrial Automation

n

Automatic Test Equipment

Data Acquisition Systems

n

Typical applicaTion

16-Bit DAC with Software Selectable Ranges

LTCꢀꢃ51-16 Integral Nonlinearity

REF

5V

1.0

V

= 5V

REF

10V RANꢀE

DD

+

0.8

0.6

= 5V

1/2 LT^®1469

C2

150pF

–

0.4

0.2

0.0

R

COM

R

FB

OFS

REF

R

IN

R1

C1

R2

–0.2

–0.4

–0.6

–0.8

–1.0

15pF

LTC2751-16

I

–

OUT1

25°C

90°C

–45°C

WR

UPD

READ

D/S

WR

UPD

V

OUT

16-BIT DAC WITH SPAN SELECT

1/2 LT1469

+

OUT2

GND

READ

D/S

0

16384

32768

CODE

49152

65535

CLR

3

16

2751 TA01b

5V

V

DD

MSPAN

R

VOS

C3

0.1µF

2751 TA01

SPAN I/O

S2-S0

DATA I/O

D15-D0

2751fa

1

LTC2751

absoluTe MaxiMuM raTings

(Notes 1, ꢀ)

Operating Temperature Range

I

, I

, R

to GND..................................... 0.3V

OUT1 OUT2 COM

R , R , R , REF, R

DD

LTC2751C..................................................... 0°C to 70°C

LTC2751I..................................................–40°C to 85°C

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range .................. –65°C to 150°C

to GND........................... 15V

FB OFS IN

VOS

V

to GND.................................................. –0.3V to 7V

S2, S1, S0, D15-D0, MSPAN, READ, D/S,WR,

UPD, CLR to GND........ –0.3V to V + 0.3V (7V Max)

DD

pin conFiguraTion

TOP VIEW

38 37 36 35 34 33 32

R

I

1

2

3

4

5

6

7

8

9

31 WR

COM

R

1

2

3

4

5

6

7

8

9

31 WR

R

I

1

2

3

4

5

6

7

8

9

31 WR

COM

R

30 UPD

IN

R

IN

30 UPD

R

30 UPD

IN

S2

READ

29

28

S2

READ

S2

READ

29

28

29

28

D/S

OUT2

NC

I

D/S

OUT2

NC

OUT2

NC

27 NC

NC

27 NC

NC

27 NC

26

NC

D15

D14

D13

D12

26

D11

D10

D9

D13

D12

D11

D10

26

39

25 D0

24 D1

23 D2

22 D3

21 D4

25 NC

24 NC

23 NC

22 NC

21 D0

25 NC

24 NC

23 D0

22 D1

21 D2

D8

D11 10

D10 11

D9 12

D7 10

D6 11

D5 12

D9 10

D8 11

D7 12

20

D5

20

D3

D1

13 14 15 16 17 18 19

LTC2751-16 UHF PACKAGE

13 14 15 16 17 18 19

LTC2751-12 UHF PACKAGE

13 14 15 16 17 18 19

LTC2751-14 UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W

T

= 125°C, θ = 34°C/W

JMAX JA

JMAX

JA

T

= 125°C, θ = 34°C/W

JMAX JA

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

275112

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2751CUHF-12#PBF

LTC2751IUHF-12#PBF

LTC2751CUHF-14#PBF

LTC2751IUHF-14#PBF

LTC2751BCUHF-16#PBF

LTC2751BIUHF-16#PBF

LTC2751ACUHF-16#PBF

LTC2751AIUHF-16#PBF

LTC2751CUHF-12#TRPBF

LTC2751IUHF-12#TRPBF

LTC2751CUHF-14#TRPBF

LTC2751IUHF-14#TRPBF

LTC2751BCUHF-16#TRPBF

LTC2751BIUHF-16#TRPBF

LTC2751ACUHF-16#TRPBF

LTC2751AIUHF-16#TRPBF

38-Lead (5mm × 7mm) Plastic QFN

275112

–40°C to 85°C

0°C to 70°C

275114

–40°C to 85°C

0°C to 70°C

275116

–40°C to 85°C

0°C to 70°C

275116

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

2751fa

2

LTC2751

elecTrical characTerisTics ^V_DD= 5V, V_REF= 5V unless otherwise specifiedꢁ The l denotes the

specifications which apply over the full operating temperature range, otherwise specifications are at T_A= ꢀ5°Cꢁ

LTCꢀꢃ51-1ꢀ LTCꢀꢃ51-14 LTCꢀꢃ51B-16 LTCꢀꢃ51A-16

MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

SYMBOL PARAMETER

Static Performance

Resolution

CONDITIONS

MIN TYP

l

12

14

16

Bits

LSB

Monotonicity

DNL

INL

GE

Differential

1

2

1

5

1

2

0.2

0.4

4

1

Nonlinearity

l

Integral

Nonlinearity

LSB

Gain Error

All Output

Ranges

0.5

0.6

0.2

0.5

1.5

0.6

0.5

20

14

GE

Gain Error Temp-

erature Coefficient

0.6

0.5

0.6

2

ppm/°C

LSB

DGain/DTemp

TC

l

BZE

BZS

Bipolar Zero Error All Bipolar

Ranges

1

3

12

8

Bipolar Zero Temp-

erature Coefficient

0.5

ppm/°C

LSB/V

nA

TC

l

PSR

Power Supply

Rejection

V

= 5V, 10ꢀ

= 3V, 10ꢀ

0.025

0.06

0.1

0.25

0.4

1

0.03

0.1

0.2

0.5

DD

I

Leakage

T = 25°C

0.05

2

5

0.05

2

5

0.05

2

5

0.05

2

5

LKG

OUT1

A

l

Current

T

to T

MIN MAX

C

Output

Capacitance

Full-Scale

Zero Scale

75

45

75

45

75

45

75

45

pF

IOUT1

V_DD= 5V, V_REF= 5V unless otherwise specifiedꢁ The l denotes specifications that apply over the full operating temperature range,

otherwise specifications are at T_A= ꢀ5°Cꢁ

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resistances (Note 3)

R1/R2

l

Reference Inverting Resistors

DAC Input Resistance

Feedback Resistor

(Note 4)

16

8

20

10

kW

R

REF

R

(Note 3)

8

10

FB

R

Bipolar Offset Resistor

Offset Adjust Resistor

16

800

20

OFS

R

1000

VOS

Dynamic Performance

Output Settling Time

0V to 10V Range, 10V Step. To 0.0015ꢀ FS

(Note 5)

2

μs

Glitch Impulse

(Note 6)

(Note 7)

1

nV•s

mV

Digital-to-Analog Glitch Impulse

Multiplying Feedthrough Error

0V to 10V Range, V

Sine Wave

=

10V, 10kHꢁ

0.5

REF

THD

Total Harmonic Distortion

(Note 8) Multiplying

(Note 9) at I

–110

13

dB

Output Noise Voltage Density

nV/√Hz

OUT1

Power Supply

l

V

Supply Voltage

2.7

5.5

1

V

DD

I

Supply Current, V

Digital Inputs = 0V or V

0.5

μA

DD

2751fa

3

LTC2751

elecTrical characTerisTics ^V_DD= 5V, V_REF= 5V unless otherwise specifiedꢁ The l denotes the

specifications which apply over the full operating temperature range, otherwise specifications are at T_A= ꢀ5°Cꢁ

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Inputs

l

V

Digital Input High Voltage

Digital Input Low Voltage

3.3V ≤ V ≤ 5.5V

2.4

2

V

IH

DD

2.7V ≤ V < 3.3V

DD

l

V

4.5V < V ≤ 5.5V

0.8

0.6

V

IL

DD

2.7V ≤ V ≤ 4.5V

DD

l

I

Digital Input Current

V

= GND to V

DD

1

6

µA

pF

IN

C

Digital Input Capacitance

= 0V (Note 10)

IN

Digital Outputs

l

V

I

= 200µA

V – 0.4

DD

V

OH

OL

OH

OL

0.4

TiMing characTerisTics ^V_DD= 5V, V_REF= 5V unless otherwise specifiedꢁ The l denotes specifications that

apply over the full operating temperature range, otherwise specifications are at T_A= ꢀ5°Cꢁ

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

= 4ꢁ5V to 5ꢁ5V

Write and Update Timing

l

t

I/O Valid to WR Rising Edge Set-Up

I/O Valid to WR Rising Edge Hold

WR Pulse Width

9

ns

1

2

3

4

5

6

7

8

20

0

UPD Pulse Width

UPD Falling Edge to WR Falling Edge

WR Rising Edge to UPD Rising Edge

D/S Valid to WR Falling Edge Set-Up Time

WR Rising Edge to D/S Valid Hold Time

No Data Shoot-Through

(Note 10)

0

9

Readback Timing

l

t

13

t

14

t

15

t

17

t

18

t

19

t

20

t

22

t

23

t

24

WR Rising Edge to READ Rising Edge

READ Falling Edge to WR Falling Edge

READ Rising Edge to I/O Propagation Delay

UPD Valid to I/O Propagation Delay

D/S Valid to READ Rising Edge

9

ns

(Note 10)

20

C = 10pF

L

30

C = 10pF

L

(Note 10)

No Update

(Note 10)

9

READ Rising Edge to UPD Rising Edge

UPD Falling Edge to READ Falling Edge

READ Falling Edge to UPD Rising Edge

I/O Bus Hi-Z to READ Rising Edge

READ Falling Edge to I/O Bus Active

9

0

20

CLR Timing

l

t

CLR Pulse Width Low

20

ns

25

2751fa

4

LTC2751

TiMing characTerisTics ^V_DD= 5V, V_REF= 5V unless otherwise specifiedꢁ The l denotes specifications that

apply over the full operating temperature range, otherwise specifications are at T_A= ꢀ5°Cꢁ

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

= ꢀꢁꢃV to 3ꢁ3V

Write and Update Timing

l

t

I/O Valid to WR Rising Edge Set-Up

I/O Valid to WR Rising Edge Hold

WR Pulse Width

18

30

0

ns

1

2

3

4

5

6

7

8

UPD Pulse Width

UPD Falling Edge to WR Falling Edge

WR Rising Edge to UPD Rising Edge

D/S Valid to WR Falling Edge Set-Up Time

WR Rising Edge to D/S Valid Hold Time

No Data Shoot-Through

(Note 10)

0

18

Readback Timing

l

t

13

t

14

t

15

t

17

t

18

t

19

t

20

t

22

t

23

t

24

WR Rising Edge to Read Rising Edge

Read Falling Edge to WR Falling Edge

Read Rising Edge to I/O Propagation Delay

UPD Valid to I/O Propagation Delay

D/S Valid to Read Rising Edge

18

40

ns

(Note 10)

C = 10pF

L

40

C = 10pF

L

(Note 10)

No Update

(Note 10)

18

9

Read Rising Edge to UPD Rising Edge

UPD Falling Edge to Read Falling Edge

READ Falling Edge to UPD Rising Edge

I/O Bus Hi-Z to Read Rising Edge

9

18

0

Read Falling Edge to I/O Bus Active

40

CLR Timing

l

t

CLR Pulse Width Low

30

ns

25

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

basis. See Application Note 74, “Component and Measurement Advances

Ensure 16-Bit DAC Settling Time.”

Note 6: Measured at the major carry transition, 0V to 5V range. Output

amplifier: LT1469; C = 27pF.

FB

Note ꢀ: Continuous operation above the specified maximum operating

junction temperature may impair device reliability.

Note 3: Because of the proprietary SoftSpan switching architecture, the

measured resistance looking into each of the specified pins is constant for

Note ꢃꢁ Full-scale transition; REF = 0V.

Note 8ꢁ REF = 6V

at 1kHꢁ. 0V to 5V range. DAC code = FS. Output

RMS

amplifier = LT1469.

Note 9ꢁ Calculation from V = √4kTRB, where k = 1.38E-23 J/°K

n

all output ranges if the I

and I

pins are held at ground.

OUT1

OUT2

(Boltꢁmann constant), R = resistance (W), T = temperature (°K), and B =

bandwidth (Hꢁ).

Note 10ꢁ Guaranteed by design. Not production tested.

Note 4: R1 is measured from R to R

; R2 is measured from REF to

IN

COM

R

COM

.

Note 5: Using LT1469 with C

= 15pF. A 0.0015ꢀ settling time

FEEDBACK

of 1.7μs can be achieved by optimiꢁing the time constant on an individual

2751fa

5

LTC2751

Typical perForMance characTerisTics ^T_A^{= ꢀ5°C, unless otherwise notedꢁ}

LTCꢀꢃ51-16

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

V

= 5V

REF

10V RꢀNGE

V

= 5V

DD

REF

10V RꢀNGE

DD

= 5V

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

2751 G01

2751 G02

INL vs Temperature

DNL vs Temperature

Bipolar Zero vs Temperature

1.0

0.8

1.0

8

V

= 5V

V

= 5V

V

= 5V

DD

REF

DD

REF

DD

REF

0.8

0.6

6

4

2

0

2

4

6

8

10V RAꢀGE

10V RANGE

0.6

0.4

+INL

–INL

0.5ppm/°C (TYP)

0.2

+DNL

–DNL

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

20

TEMPERATURE (°C)

40

80

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–40

–20

0

60

TEMPERATURE (°C)

2751 G06

2751 G04

2751 G05

Gain Error vs Temperature

INL vs V_REF

DNL vs V_REF

16

12

8

1.0

0.8

1.0

0.8

V

= 5V

REF

10V RAꢀGE

V

= 5V

V

= 5V

DD

= 5V

5V RꢀAGE

0.6

0.4

+IAL

0.6ppm/°C (TYP)

4

+IAL

–IAL

0.2

+DAL

–DAL

+DAL

–DAL

0

0.0

–IAL

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–4

–8

–12

–16

–40

–20

0

20

TEMPERATURE (°C)

40

60

80

–10 –8

–6

4

2

V

0

2

4

6

8

10

–10 –8 –6

4

2

0

2

4

6

8

10

(V)

V

REF

(V)

REF

2751 G07

2751 G08

2751 G09

2751fa

6

LTC2751

Typical perForMance characTerisTics ^T_A^{= ꢀ5°C, unless otherwise notedꢁ}

LTCꢀꢃ51-16

INL vs V_DD

Settling 0V to 10V

1.0

0.8

UPD

0.6

5V/DIV

0.4

+INL

–INL

0.2

GATED

SETTLING

WAVEFORM

250µV/DIV

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

2751 G10

500ns/DIV

USING LT1469 AMP

= 12pF

C

FEEDBACK

2.5

3

3.5

4

4.5

5

5.5

0V TO 10V STEP

V

DD

(V)

2751 G09b

LTCꢀꢃ51-14

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

V

= 5V

REF

10V RꢀNGE

V

= 5V

DD

REF

10V RꢀNGE

DD

= 5V

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

4096

8192

12288

16383

0

4096

8192

12288

16383

CODE

2751 G11

2751 G12

LTCꢀꢃ51-1ꢀ

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

V

= 5V

REF

10V RꢀNGE

V

= 5V

DD

REF

10V RꢀNGE

DD

= 5V

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1024

2048

3072

4095

0

1024

2048

3072

4095

CODE

2751 G13

2751 G14

2751fa

7

LTC2751

Typical perForMance characTerisTics ^T_A^{= ꢀ5°C, unless otherwise notedꢁ}

LTCꢀꢃ51-1ꢀ, LTCꢀꢃ51-14, LTCꢀꢃ51-16

Supply Current vs

Logic Input Voltage

Midscale Glitch

12

10

UPD

5V/DIV

8

6

1nV•s (TYP)

V

DD

= 5V

V

OUT

2mV/DIV

4

2

0

2751 G15

500ns/DIV

V

= 3V

DD

V

= 5V

REF

0V TO 5V RANGE

USING AN LT1469

DD

= 5V

C

= 27pF

FEEDBACK

0

1

2

3

4

5

LOGIC VOLTAGE (V)

2751 G16

ALL DIGITAL PINS TIED TOGETHER

(EXCEPT READ TIED TO GND)

Logic Threshold

vs Supply Voltage

Supply Current

vs Update Frequency

2

1.75

1.5

1000

100

10

RISING

1.25

1

FALLING

1

V

= 5V

= 3V

DD

0.75

0.5

DD

0.1

2.5

3.5

4

4.5

5

5.5

10

100

10k

UPD FREQUENCY (Hz)

100k

1M

3

1k

V

(V)

DD

2751 G18

2751 G17

ALTERNATING ZERO-SCALE/FULL-SCALE

(LTC2751-16)

2751fa

8

LTC2751

pin FuncTions

R

(Pin 1): Center Tap Point of R and REF. Normally

tied to the negative input of the external reference invert-

MSPAN must be connected either directly to GND (Soft-

COM

IN

Span configuration) or V (single-span configuration).

DD

ing amplifier.

D0-Dꢀ(Pins19-ꢀ1):LTCꢀꢃ51-1ꢀOnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

R (Pinꢀ):InputResistorforExternalReferenceInverting

IN

Amplifier. Normally tied to the external reference voltage

V

andtoR (Pin37).Typically5V;acceptsupto 15V.

REF

OFS

D0-D4(Pins19-ꢀ3):LTCꢀꢃ51-14OnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

Sꢀ (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used

to program and to read back the output range of the DAC.

D0-D6(Pins19-ꢀ5):LTCꢀꢃ51-16OnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

I

(Pin 4): DAC Current Output Complement. Tie I

OUT2

OUTꢀ

to GND.

NC (Pin 5): No Connection. Must be tied to GND, provides

necessary shielding for I

NC (Pins ꢀꢀ-ꢀꢃ): LTCꢀꢃ51-1ꢀ Onlyꢁ No Connection.

NC (Pins ꢀ4-ꢀꢃ): LTCꢀꢃ51-14 Onlyꢁ No Connection.

NC (Pins ꢀ6, ꢀꢃ): LTCꢀꢃ51-16 Onlyꢁ No Connection.

.

OUT2

D3-D11(Pins6-14):LTCꢀꢃ51-1ꢀOnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D11 is the MSB.

D/S (Pin ꢀ8): Data/Span Select. This pin is used to select

activation of the data or span I/O pins (D0 to D15 or S0

to S2, respectively), along with their respective dedicated

registers, for write or read operations. Update operations

ignore D/S, since all updates affect both data and span

registers. For single-span operation, tie D/S to GND.

D5-D13(Pins6-14):LTCꢀꢃ51-14OnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D13 is the MSB.

Dꢃ-D15(Pins6-14):LTCꢀꢃ51-16OnlyꢁDACInput/Output

Data Bits. These I/O pins set and read back the DAC code.

D15 is the MSB.

READ(Pinꢀ9):ReadPin.WhenREADisassertedhigh,the

dataI/Opins(D0-D15)orspanI/Opins(S0-S2)outputthe

contents of the selected register (see Table 1). For single-

span operation, readback of the span I/O pins is disabled.

V

(Pin 15): Positive Supply Input 2.7V ≤ V ≤ 5.5V.

DD

Requires a 0.1µF bypass capacitor to GND.

GND (Pin 16): Ground. Tie to ground.

UPD (Pin 30): Update and Buffer Select Pin. When READ

is held low and UPD is asserted high, the contents of the

input registers (both data and span) are copied into their

respectiveDACregisters.TheoutputoftheDACisupdated,

reflecting the new DAC register values.

CLR (Pin 1ꢃ): Asynchronous Clear. When CLR is taken

to a logic low, the data registers are reset to the ꢁero-volt

code for the present output range (V

= 0V).

OUT

MSPAN(Pin18):ManualSpanControlPin.MSPANisused

to configure the LTC2751 for operation in a single, fixed

output range. When configured for single-span operation,

the output range is set via hardware pin strapping. The

span input and DAC registers are transparent and do not

respond to write or update commands.

When READ is held high, the update function is disabled

and the UPD pin functions as a buffer selector—logic low

to select the input register, high for the DAC register. See

Readback in the Operation section.

WR (Pin 31): Active Low Write Pin. A Write operation

copies the data present on the data or span I/O pins (D0-

D15 or S0-S2, respectively) into the input register. When

READ is high, the Write function is disabled.

To configure the part for single-span use, tie MSPAN

directly to V . If MSPAN is instead connected to GND

DD

(SoftSpan configuration), the output ranges are set and

verified by using write, update and read operations. See

Manual Span Configuration in the Operation section.

S0 (Pin 3ꢀ): Span I/O Bit 0. Pins S0, S1 and S2 are used

to program and to read back the output range of the DAC.

2751fa

9

LTC2751

pin FuncTions

S1 (Pin 33): Span I/O Bit 1. Pins S0, S1 and S2 are used

to program and to read back the output range of the DAC.

R

(Pin 3ꢃ): Bipolar Offset Network. This pin provides

OFS

the translation of the output voltage range for bipolar

spans. Accepts up to 15V; normally tied to the positive

reference voltage at R (Pin 2).

R

(Pin 34): DAC Offset Adjust. Nominal input range is

VOS

IN

5V. If not used, R

should be shorted to I

.

VOS

OUT2

REF(Pin38):FeedbackResistorfortheReferenceInverting

Amplifier, and Reference Input for the DAC. Normally tied

to the output of the reference inverting amplifier. Typically

–5V. Accepts up to 15V.

I

(Pin 35): DAC current output; normally tied to the

OUT1

negative input of the I/V converter amplifier.

R

(Pin 36): DAC Feedback Resistor; normally tied to

FB

the output of the I/V converter amplifier. The DAC output

Exposed Pad (Pin 39): Ground. The Exposed Pad must

be soldered to the PCB.

current from I

flows through the feedback resistor

OUT1

to the R pin.

FB

2751fa

10

LTC2751

block DiagraM

1

38

REF

37

36

R

COM

R

FB

R

OFS

R

IN

R1

R2

2

I

OUT1

OUT2

35

4

READ

29

WR

31

UPD

30

D/S

28

CLR

17

MSPAN

18

16-BIT DAC WITH SPAN SELECT

3

16

DAC

REGISTER

DAC

REGISTER

CONTROL

LOGIC

3

16

INPUT

REGISTER

INPUT

REGISTER

I/O

PORT

I/O

PORT

3

16

2751 BD

3, 32, 33

SPAN I/O

6-14, 19-25

DATA I/O

D15-D0

S2-S0

2751fa

11

LTC2751

TiMing DiagraMs

Write, Update and Clear Timing

t

3

t

1

t

2

WR

I/O

INPUT

t

5

t

6

UPD

t

4

t

7

t

8

D/S

t

25

CLR

2751 TD01

Readback Timing

READ

t

14

24

13

WR

t

23

I/O

INPUT

t

15

I/O

OUTPUT

t

17

t

20

t

19

22

UPD

t

18

D/S

2751 TD02

operaTion

Output Ranges

Digital Section

The LTC2751 is a current-output, parallel-input precision

multiplying DAC with software-programmable output

ranges. SoftSpan provides two unipolar output ranges

(0V to 5V and 0V to 10V), and four bipolar ranges ( 2.5V,

5V, 10V and –2.5V to 7.5V). These ranges are obtained

when an external precision 5V reference is used. When

a reference voltage of 2V is used, the SoftSpan ranges

become: 0V to 2V, 0V to 4V, 1V, 2V, 4V and –1V to

3V. The output ranges are linearly scaled for references

other than 2V and 5V.

The LTC2751 family has four internal interface registers

(see Block Diagram). Two of these—one input and one

DAC register—are dedicated to the data I/O port, and two

to the span I/O port. Each port is thus double-buffered.

The double-buffered feature provides the capability to

simultaneously update the span and code, which allows

smooth voltage transitions when changing output ranges.

ItalsopermitsthesimultaneousupdatingofmultipleDACs.

2751fa

12

LTC2751

operaTion

Write and Update Operations

Table 1 shows the functions of the LTC2751.

The data input register is loaded directly from a 16-bit

microprocessor bus by holding the D/S pin low and then

pulsing the WR pin low. The second register (DAC regis-

ter) is loaded by pulsing the UPD pin high, which copies

the data held in the input register into the DAC register.

Note that updates always include both data and span; but

the DAC register values will not change unless the input

register values have been changed by writing.

Table 1ꢁ Write, Update and Read Functions

READ D/S WR UPD

SPAN I/O

DATA I/O

0

1

-

Write to Input Register

Write/Update

(Transparent)

0

1

0

1

0

1

-

Update DAC Register Update DAC Register

Write to Input Register

-

Write/Update

(Transparent)

Loadingthespaninputregisterisaccomplishedinasimilar

manner, by holding the D/S pin high and then bringing

the WR pin low. The span and data register structures

are the same except for the number of parallel bits—the

span registers have three bits, while the data registers

have 12, 14, or 16 bits.

0

1

0

1

X

0

1

0

1

0

1

-

Update DAC register Update DAC Register

-

Read Input Register

-

Read DAC Register

Read Input Register

Read DAC Register

-

To make both registers transparent for flowthrough mode,

tie WR low and UPD high. However, this defeats the de-

glitcher operation and output glitch impulse may increase.

ThedeglitcherisactivatedontherisingedgeoftheUPDpin.

X = Don’t Care

Manual Span Configuration

The interface also allows the use of the input and DAC

registers in a master-slave, or edge-triggered, configura-

tion. This mode of operation occurs when WR and UPD

are tied together and driven by a single clock signal. The

data bits are loaded into the input register on the falling

edge of the clock and then loaded into the DAC register

on the rising edge.

Multipleoutputrangesarenotneededinsomeapplications.

To configuretheLTC2751forsingle-spanoperation,tiethe

MSPAN pin to V and the D/S pin to GND. The desired

DD

output range is then specified by the span I/O pins (S0, S1

and S2) as usual, but the pins are programmed by tying

directly to GND or V (see Figure 1 and Table 2). In this

DD

configuration, the part will initialiꢁe to the chosen output

The separation of data and span for write and read opera-

tions makes it possible to control both data and span on

one 16-bit wide data bus by allowing span pins S2 to S0

to share bus lines with the data LSBs (D2 to D0). Since

no write or read operation includes both span and data,

there cannot be a conflict.

range at power-up, with V

= 0V.

OUT

When configured for manual span operation, span pin

readback is disabled.

V

DD

The asynchronous clear pin resets the LTC2751 to 0V

(ꢁero-, half- or quarter-scale code) in any output range.

CLR resets both the input and DAC data registers, while

leaving the span registers undisturbed.

V

MSPAN

S2

DD

LTC2751-16

S1

S0

WR UPD READ

D/S

These devices also have a power-on reset. If configured

for SoftSpan operation, the part initialiꢁes to ꢁero scale in

the 0V to 5V output range. If configured for single-span

operation, the part initialiꢁes to the ꢁero-volt code in the

chosen output range.

16

2751 F01

DATA I/O

Figure 1ꢁ Configuring the LTCꢀꢃ51 for

Single-Span Operation ( 10V Range)

2751fa

13

LTC2751

operaTion

Table ꢀꢁ Span Codes

isatwo-functionpin.Theupdatefunctionisdisabledwhen

READ is high, and the UPD pin instead selects the input

or DAC register for readback. Table 1 shows the readback

functions for the LTC2751.

Sꢀ

0

S1

0

S0

0

SPAN

Unipolar 0V to 5V

Unipolar 0V to 10V

Bipolar –5V to 5V

Bipolar –10V to 10V

Bipolar –2.5V to 2.5V

Bipolar –2.5V to 7.5V

0

1

0

1

0

The most common readback task is to check the contents

of an input register after writing to it, before updating the

new data to the DAC register. To do this, bring READ high

whileholdingUPDlow. Thecontentsoftheselectedport’s

input register are output by the data or span I/O pins.

0

1

0

1

0

1

Codes not shown are reserved and should not be used.

To read back the contents of a DAC register, bring READ

high, then bring UPD high. The contents of the selected

data or span DAC register are output by the data or span

I/O pins. Note: if no update is desired after the readback

operation, UPD must be returned low before bringing

READ low, otherwise the UPD pin will revert to its primary

function and update the DAC.

Readback

The contents of any one of the four interface registers can

be read back by using the READ pin in conjunction with

the D/S and UPD pins.

AreadbackoperationisinitiatedbybringingREADtologic

high.TheI/Opins,whicharehigh-impedancedigitalinputs

when READ is low, selectively change to low-impedance

logic outputs during readback.

System Offset Adjustment

Many systems require compensation for overall system

offset. The R

offset adjustment pin is provided for this

VOS

The I/O pins comprise two ports, data and span. The data

I/O port consists of pins D0-D11, D0-D13 or D0-D15

(LTC2751-12,LTC2751-14orLTC2751-16,respectively).

The span I/O port consists of pins S0, S1 and S2 for all

parts.

purpose. For noise immunity and ease of adjustment, the

control voltage is attenuated to the DAC output:

V

OS

V

OS

= –0.01 • V(R ) [0V to 5V, 2.5V spansꢂ

VOS

= –0.02 • V(R ) [0V to 10V, 5V,

VOS

Each I/O port has one dedicated input register and one

dedicated DAC register. The register structure is shown

in the Block Diagram.

–2.5V to 7.5V spansꢂ

= –0.04 • V(R ) [ 10V spanꢂ

V

OS

VOS

The D/S pin is used to select which I/O port (data or span)

isconfiguredtoreadbackthecontentsofitsregisters. The

unselected I/O port’s pins remain high-impedance inputs.

The nominal input range of this pin is 5V; other refer-

ence voltages of up to 15V may be used if needed. The

R

pin has an input impedance of 1MW. To preserve the

VOS

Once the I/O port is selected, its input or DAC register is

selected for readback by using the UPD pin. Note that UPD

settling performance of the LTC2751, this pin should be

driven with a Thevenin-equivalent impedance of 10kW or

less. If not used, R

should be shorted to I

.

VOS

OUT2

2751fa

14

LTC2751

operaTion—exaMples

1. Load 5V range with the output at 0V. Note that since span and code are updated together, the output, if started at

0V, will stay there.

WR

SPAN I/O

INPUT

010

DATA I/O

INPUT

8000

H

UPD

UPDATE

(5V RANGE, V

= 0V)

OUT

D/S

READ = LOW

2751 TD03

2. Load 10V range with the output at 5V, changing to –5V.

WR

SPAN I/O

INPUT

011

DATA I/O

INPUT

C000

4000

H

UPD

UPDATE (5V)

UPDATE (–5V)

D/S

READ = LOW

2751 TD04

3. Write and update mid-scale code in 0V to 5V range (V

and DAC registers before updating.

= 2.5V) using readback to check the contents of the input

OUT

WR

HI-Z

DATA I/O

INPUT

8000

H

HI-Z

DATA I/O

OUTPUT

8000

0000

H

INPUT REGISTER

DAC REGISTER

UPD

UPDATE (2.5V)

D/S

READ

2751 TD05

2751fa

15

LTC2751

applicaTions inForMaTion

Op Amp Selection

when programmed in a unipolar or bipolar output range.

These are the changes the op amp can cause to the INL,

DNL, unipolar offset, unipolar gain error, bipolar ꢁero

and bipolar gain error. Tables 3 and 4 can also be used

to determine the effects of op amp parameters on the

LTC2751-14 and the LTC2751-12. However, the results

obtained from Tables 3 and 4 are in 16-bit LSBs. Divide

these results by 4 (LTC2751-14) and 16 (LTC2751-12) to

obtain the correct LSB siꢁing.

Because of the extremely high accuracy of the 16-bit

LTC2751-16, careful thought should be given to op amp

selection in order to achieve the exceptional performance

of which the part is capable. Fortunately, the sensitivity of

INL and DNL to op amp offset has been greatly reduced

compared to previous generations of multiplying DACs.

Tables 3 and 4 contain equations for evaluating the ef-

fects of op amp parameters on the LTC2751’s accuracy

Table 5 contains a partial list of LTC precision op amps

recommended for use with the LTC2751. The easy-to-use

designequationssimplifytheselectionofopampstomeet

the system’s specified error budget. Select the amplifier

from Table 5 and insert the specified op amp parameters

in Table 4. Add up all the errors for each category to de-

termine the effect the op amp has on the accuracy of the

part.Arithmeticsummationgivesan(unlikely)worst-case

effect. A root-sum-square (RMS) summation produces a

more realistic estimate.

Table 3ꢁ Variables for Each Output Range That Adjust the

Equations in Table 4

OUTPUT RANGE

A1

1.1

2.2

2

Aꢀ

A3

A4

A5

1

5V

10V

2

1

3

0.5

1

1.5

2.5

1

5V

2

1

10V

4

0.83

1.4

0.7

2.5V

1

–2.5V to 7.5V

1.9

3

0.5

1.5

Table 4ꢁ Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1)ꢁ Subscript 1

Refers to Output Amp, Subscript ꢀ Refers to Reference Inverting Ampꢁ

UNIPOLAR

OFFSET (LSB)

BIPOLAR ZERO

ERROR (LSB)

UNIPOLAR GAIN

ERROR (LSB)

BIPOLAR GAIN

ERROR (LSB)

OP AMP

INL (LSB)

DNL (LSB)

5V

REF

5V

REF

5V

REF

5V

REF

5V

REF

5V

REF

V

(mV)

V

• 3.2 •

V

• 0.82 •

A3 • V

OS1

• 13.2 •

A3 • V

• 19.8 •

V

• 13.2 •

V

• 13.2 •

OS1

)

⁽V

OS1

5V

I

(nA)

I

• 0.0003 •

I

• 0.00008 •

I

• 0.13 •

I

• 0.13 •

0

I

B1

• 0.0018 •

I

B1

• 0.0018 •

⁽V

B1

)

⁽V

)

REF

16.5k

VOL1

1.5k

VOL1

131k

VOL1

131k

VOL1

A

VOL1

(V/V)

(mV)

A1 •

A2 •

0

A5 •

)

⁽A

)

⁽A

5V

V

0

A4 • V

• 13.1 •

V

• 26.2 •

V

• 26.2 •

OS2

⁽V

)

⁽V

(

))

)

REF

5V

REF

5V

REF

I

(mV)

A4 • I • 0.13 •

I

• 0.26 •

I

B2

• 0.26 •

131k

B2

(

))

⁽V

REF

⁽V

)

⁽V

66k

VOL2

131k

A

VOL2

(V/V)

A4 •

⁽A

)

⁽A

)

VOL2

Table 5ꢁ Partial List of LTC Precision Amplifiers Recommended for Use with the LTCꢀꢃ51 with Relevant Specifications

AMPLIFIER SPECIFICATIONS

t

SETTLING

VOLTAGE CURRENT

SLEW

RATE

V/µs

GAIN BANDWIDTH

PRODUCT

MHz

with

POWER

V

I

A

VOL

NOISE

LTCꢀꢃ51

µs

DISSIPATION

mW

OS

B

AMPLIFIER

LT1001

µV

nA

V/mV

nV/√Hz

pA/√Hz

25

2

800

10

14

2.7

5

0.12

0.008

0.3

0.25

0.2

0.16

4.5

22

0.8

0.7

120

115

19

2

46

11

LT1097

50

0.35

0.25

20

1000

1500

4000

5000

2000

LT1112 (Dual)

LT1124 (Dual)

LT1468

60

0.75

12.5

90

10.5/Op Amp

69/Op Amp

117

70

75

10

0.6

LT1469 (Dual)

125

10

5

0.6

22

90

2

123/Op Amp

2751fa

16

LTC2751

applicaTions inForMaTion

Op amp offset will contribute mostly to output offset and

gain error and has minimal effect on INL and DNL. For

the LTC2751-16, a 250µV op amp offset will cause about

0.8LSB INL degradation and 0.2LSB DNL degradation

with a 5V reference. For the LTC2751 programmed in 5V

unipolar mode, the same 250µV op amp offset will cause

a 3.3LSB ꢁero-scale error and a 3.3LSB gain error.

be very dependent on ambient conditions. Minimiꢁing

the error due to reference temperature coefficient can be

achieved by choosing a precision reference with a low

output voltage temperature coefficient and/or tightly con-

trolling the ambient temperature of the circuit to minimiꢁe

temperature gradients.

As precision DAC applications move to 16-bit and higher

performance, referenceoutputvoltage noise may contrib-

ute a dominant share of the system’s noise floor. This in

turn can degrade system dynamic range and signal-to-

noise ratio. Care should be exercised in selecting a voltage

reference with as low an output noise voltage as practi-

cal for the system resolution desired. Precision voltage

references, like the LT1236, produce low output noise in

the 0.1Hꢁ to 10Hꢁ region, well below the 16-bit LSB level

in 5V or 10V full-scale systems. However, as the circuit

bandwidths increase, filtering the output of the reference

may be required to minimiꢁe output noise.

While not directly addressed by the simple equations in

Tables 3 and 4, temperature effects can be handled just

as easily for unipolar and bipolar applications. First, con-

sult an op amp’s data sheet to find the worst-case V

OS

and I over temperature. Then, plug these numbers in

the V and I equations from Table 4 and calculate the

B

OS

B

temperature-induced effects.

For applications where fast settling time is important,

Application Note 74, “Component and Measurement

Advances Ensure 16-Bit DAC Settling Time,” offers a

thorough discussion of 16-bit DAC settling time and op

amp selection.

Table 6ꢁ Partial List of LTC Precision References Recommended

for Use with the LTCꢀꢃ51 with Relevant Specifications

Precision Voltage Reference Considerations

INITIAL

TOLERANCE

TEMPERATURE

DRIFT

0ꢁ1Hz to 10Hz

NOISE

REFERENCE

Much in the same way selecting an operational amplifier

for use with the LTC2751 is critical to the performance of

the system, selecting a precision voltage reference also

requiresduediligence.TheoutputvoltageoftheLTC2751is

directlyaffectedbythevoltagereference;thus,anyvoltage

reference error will appear as a DAC output voltage error.

LT1019A-5,

LT1019A-10

0.05ꢀ

0.075ꢀ

0.05ꢀ

5ppm/°C

10ppm/°C

12µV

P-P

LT1236A-5,

LT1236A-10

3µV

P-P

LT1460A-5,

LT1460A-10

20µV

P-P

LT1790A-2.5

12µV

There are three primary error sources to consider when

selecting a precision voltage reference for 16-bit appli-

cations: output voltage initial tolerance, output voltage

temperature coefficient and output voltage noise.

Grounding

As with any high resolution converter, clean grounding is

important. A low impedance analog ground plane and star

grounding techniques should be used. I

to the star ground with as low a resistance as possible.

When it is not possible to locate star ground close to

Initial reference output voltage tolerance, if uncorrected,

generates a full-scale error term. Choosing a reference

with low output voltage initial tolerance, like the LT1236

( 0.05ꢀ), minimiꢁes the gain error caused by the refer-

ence; however, a calibration sequence that corrects for

system ꢁero- and full-scale error is always recommended.

must be tied

OUT2

I

, a low resistance trace should be used to route this

OUT2

pin to star ground. This minimiꢁes the voltage drop from

this pin to ground caused by the code dependent current

flowing to ground. When the resistance of this circuit

board trace becomes greater than 1W, a force/sense am-

plified configuration should be used to drive this pin (see

Figure 2). This preserves the excellent accuracy (1LSB

INL and DNL) of the LTC2751-16.

Areference’soutputvoltagetemperaturecoefficientaffects

notonlythefull-scaleerror, butcanalsoaffectthecircuit’s

INL and DNL performance. If a reference is chosen with

a loose output voltage temperature coefficient, then the

DAC output voltage along its transfer characteristic will

2751fa

17

LTC2751

applicaTions inForMaTion

ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE

6

I

OUT2

200Ω

–

2

6

1000pF

LT1468

1

2

+ ³

–

+

2

3

ZETEX

BAT54S

6

I

LT1001

OUT2

3

1

2

REF

5V

ZETEX*

BAT54S

5

+

3

7

1/2 LT^®1469

6

C2**

150pF

–

*SCHOTTKY BARRIER DIODE

2

R

1

R

38 37

REF

36

C1

15pF

R

FB

OFS

R

IN

COM

R1

R2

0.1µF

15V

LTC2751-16

8

–

I

35

OUT1

2

3

31

30

29

28

17

18

WR

UPD

READ

D/S

WR

UPD

1

V

OUT

16-BIT DAC WITH SPAN SELECT

1/2 LT1469

+

4

OUT2

GND

READ

D/S

0.1µF

16

4

CLR

–15V

3

16

15

V

DD

5V

MSPAN

C3

R

VOS

0.1µF

3, 33, 32

SPAN I/O

S2-S0

**FOR MULTIPLYING APPLICATIONS C2 = 15pF

6-14, 19-25

34

DATA I/O

D15-D0

2751 F02

Figure ꢀꢁ Basic Connections for SoftSpan V_OUTDAC with Two Optional Circuits

for Driving I_OUTꢀfrom GND with a Force/Sense Amplifier

2751fa

18

LTC2751

Typical applicaTions

16-Bit DAC with Software-Selectable Ranges

REF

5V

5

+

7

1/2 LT1469

6

C2**

150pF

–

2

R

1

R

38 37

REF

36

R

IN

COM

FB

OFS

C1

15pF

R1

R2

0.1µF

15V

LTC2751-16

8

I

–

35

OUT1

2

31

30

29

28

17

18

WR

UPD

READ

D/S

WR

UPD

1

V

OUT

16-BIT DAC WITH SPAN SELECT

1/2 LT1469

4

OUT2

GND

³+

READ

D/S

16

4

–15V

5V

CLR

0.1µF

3

16

15

V

DD

MSPAN

C3

0.1µF

R

VOS

3, 33, 32

SPAN I/O

S2-S0

6-14, 19-25

34

2751 TA02

DATA I/O

D15-D0

**FOR MULTIPLYING APPLICATIONS C2 = 15pF

2751fa

19

LTC2751

package DescripTion

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)

0.70 0.05

5.50 0.05

4.ꢀ0 0.05

3.00 REF

5.ꢀ5 0.05

3.ꢀ5 0.05

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

5.5 REF

6.ꢀ0 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 0.05

0.00 – 0.05

3.00 REF

5.00 0.ꢀ0

37 38

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

(SEE NOTE 6)

ꢀ

2

5.ꢀ5 0.ꢀ0

5.50 REF

7.00 0.ꢀ0

3.ꢀ5 0.ꢀ0

(UH) QFN REF C ꢀꢀ07

0.200 REF 0.25 0.05

0.50 BSC

R = 0.ꢀ25

TYP

R = 0.ꢀ0

TYP

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

2751fa

20

LTC2751

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

11/12 Correction made in the Typical Application diagram.

1, 18

2751fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

21

LTC2751

Typical applicaTion

Offset and Gain Trim Circuitsꢁ Powering V_DDfrom LT10ꢀꢃ Ensures Quiet Supply

+

V

IN

OUT

U3

LT1027

+

2

6

5

2

1

V

C13

8

2

3

2

10µF

TRIM

R2

10k

–

3

R1

10k

C20

10µF

GND

4

U2A

1

GND

LT^®1469

1

C23

0.1µF

+

C22

0.001µF

4

–

V

GND

C1

30pF

15

2

1

38

37 36

6

7

8

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

V

R

REF

R R

OFS FB

DD

IN

COM

–

35

9

6

5

I

OUT1

10

11

12

13

14

19

20

21

22

23

24

25

U2B

LT1469

7

V

OUT

4

+

OUT2

U1

LTC2751-16

34

DATA I/O

R

VOS

GND

D4

D3

D2

D1

D0

3

33

32

S2

S1

SPAN I/O

S0 D/S READ UPD WR CLR

MSPAN NC GND GND

2751 TA03

28 29 30 31 17

18

5

16

39

D/S READ UPD WR CLR

GND

relaTeD parTs

PART NUMBER

LT1027

DESCRIPTION

COMMENTS

Precision Reference

2ppm/°C Maximum Drift

LT1236A-5

LT1468

0.05ꢀ Maximum Tolerance, 1ppm 0.1Hꢁ to 10Hꢁ Noise

90MHꢁ GBW, 22V/µs Slew Rate

16-Bit Accurate Op-Amp

LT1469

Dual 16-Bit Accurate Op-Amp

90MHꢁ GBW, 22V/µs Slew Rate

LTC1588/LTC1589/ Serial 12-/14-/16-Bit I

LTC1592

Single DACs

Software-Selectable (SoftSpan) Ranges, 1LSB INL, DNL, 16-Lead SSOP Package

OUT

LTC1591/LTC1597 Parallel 14-/16-Bit I

Single DAC

Integrated 4-Quadrant Resistors

OUT

LTC1821

Parallel 16-Bit V

Single DAC

1LSB INL, DNL, 0V to 10V, 0V to –10V, 10V Output Ranges

OUT

LTC2601/LTC2611/ Serial 12-/14-/16-Bit V

LTC2621

Single DACs

Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

DFN-10 Package

OUT

2

LTC2606/LTC2616/ Serial 12-/14-/16-Bit V

LTC2626

Single DACs

Single DACs, I C-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

OUT

DFN-10 Package

LTC2641/LTC2642 Serial 12-/14-/16-Bit Unbuffered V

DACs

Single

2LSB INL, 1LSB DNL, 1µs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10

Packages

OUT

LTC2704

Serial 12-/14-/16-Bit V

Quad DACs

Software-Selectable (SoftSpan) Ranges, Integrated Amplifiers

OUT

2751fa

LT 1112 REV A • PRINTED IN USA

22 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2007

(408)432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2751AIUHF-16#TRPBF
厂家：	Linear
描述：	LTC2751 - Current Output 12-/14-/16-Bit SoftSpan DACs with Parallel I/O; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C 转换器
文件：	总22页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2751AIUHF-16#TRPBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E