LTC2751BIUHF-16#TRPBF [Linear]
暂无描述;型号: | LTC2751BIUHF-16#TRPBF |
厂家: | Linear |
描述: | 暂无描述 |
文件: | 总20页 (文件大小:311K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2751
Current Output
TM
12-/14-/16-Bit SoftSpan
DACs with Parallel I/O
FEATURES
DESCRIPTION
The LTC®2751 is a family of 12-, 14-, and 16-bit multi-
plying parallel-input, current-output DACs. They operate
from a single 2.7V to 5.5V supply. All parts are guaranteed
monotonic over temperature. The LTC2751A-16 provides
16-bitperformance( 1LꢀSꢁILandDILꢂovertemperature
withoutanyadjustments.Theseꢀoftꢀpan™DACsoffersix
outputranges—twounipolarandfourbipolar—thatcanbe
programmedthroughtheparallelinterface,orpinstrapped
for operation in a single range.
■
Six Programmable Output Ranges
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±±25V, –±25V to 725V
■
Maximum 16-Bit INL Error: ±1 LSB oꢀer ꢁemperature
■
Low 1µA (Maximum) Supply Current
■
Guaranteed Monotonic oꢀer ꢁemperature
■
Low Glitch Impulse 1nV • s
■
■
■
■
■
2.7V to 5.5V ꢀingle ꢀupply Operation
2µs ꢀettling Time to 1 LꢀS
Reference ꢁnput: 15V
These parts use a bidirectional input/output parallel
interface that allows readback of any on-chip register. A
power-oncircuitresetstheDACoutputto0Vwhenpoweris
initiallyapplied.AlogiclowontheCLRpinasynchronously
clears the DAC to 0V in any output range.
Parallel ꢁnterface with Readback of All Registers
Asynchronous CLR Pin Clears DAC Output to 0V in
Any Output Range
Power-On Reset to 0V
38-Pin 5mm × 7mm QFI Package
■
■
The parts are specified over commercial and industrial
temperature ranges.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
APPLICATIONS
■
High Resolution Offset and Gain Adjustment
■
Process Control and ꢁndustrial Automation
■
Automatic Test Equipment
Data Acquisition ꢀystems
■
TYPICAL APPLICATION
16-Bit DAC with Software Selectable Ranges
LꢁC±751-16 Integral Nonlinearity
REF
5V
1.0
V
V
= 5V
REF
DD
–
0.8
0.6
= 5V
1/2 LT®1469
±10V RANGE
C2
150pF
+
0.4
0.2
2
R
1
R
38 37
REF
36
R
R
OFS
IN
R1
COM
FB
0.0
C1
R2
15pF
–0.2
–0.4
–0.6
–0.8
–1.0
LTC2751-16
I
I
–
OUT1 35
31
30
29
28
17
18
WR
UPD
READ
D/S
WR
UPD
16-BIT DAC WITH SPAN SELECT
V
OUT
25°C
90°C
–45°C
1/2 LT1469
+
OUT2
GND
4
READ
D/S
16
CLR
CLR
0
16384
32768
CODE
49152
65535
3
16
15
5V
V
DD
MSPAN
C3
0.1μF
R
VOS
2751 TA01b
3, 32, 33
SPAN I/O
S2-S0
6-14, 19-25
34
2751 TA01
DATA I/O
D15-D0
2751f
1
LTC2751
ABSOLUTE MAXIMUM RATINGS
(Notes 1, ±)
Operating Temperature Range
ꢁ
, ꢁ
, R
to GID..................................... 0.3V
OUT1 OUT2 COM
R , R , R , REF, R
DD
LTC2751C .................................................... 0°C to 70°C
LTC2751ꢁ ................................................. –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
ꢀtorage Temperature Range................... –65°C to 150°C
to GID........................... 15V
VOꢀ
FS OFꢀ ꢁI
V
to GID.................................................. –0.3V to 7V
ꢀ2, ꢀ1, ꢀ0, D15-D0, MꢀPAI, READ, D/ꢀ,WR,
UPD, CLR to GID........–0.3V to V + 0.3V (7V Maxꢂ
DD
PIN CONFIGURATION
TOP VIEW
TOP VIEW
TOP VIEW
38 37 36 35 34 33 32
38 37 36 35 34 33 32
38 37 36 35 34 33 32
R
I
1
2
3
4
5
6
7
8
9
31 WR
R
I
1
2
3
4
5
6
7
8
9
31 WR
R
1
2
3
4
5
6
7
8
9
31 WR
COM
COM
COM
R
IN
30 UPD
R
IN
30 UPD
R
IN
30 UPD
S2
READ
D/S
S2
READ
D/S
29
28
S2
READ
D/S
29
28
29
28
I
OUT2
NC
OUT2
NC
OUT2
NC
27 NC
26
NC
27 NC
26
NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 D0
D15
D14
D13
D12
D13
D12
D11
D10
D11
D10
D9
39
39
39
25 D0
24 D1
23 D2
22 D3
21 D4
25 NC
24 NC
23 D0
22 D1
21 D2
D8
D11 10
D10 11
D9 12
D9 10
D8 11
D7 12
D7 10
D6 11
D5 12
20
20
D5
20
D3
D1
13 14 15 16 17 18 19
LTC2751-16 UHF PACKAGE
13 14 15 16 17 18 19
LTC2751-14 UHF PACKAGE
13 14 15 16 17 18 19
LTC2751-12 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
38-LEAD (5mm × 7mm) PLASTIC QFN
38-LEAD (5mm × 7mm) PLASTIC QFN
T
= 125°C, θ = 34°C/W
T
= 125°C, θ = 34°C/W
JMAX JA
JMAX
JA
T
= 125°C, θ = 34°C/W
JA
JMAX
EXPOꢀED PAD (PꢁI 39ꢂ ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS EXPOꢀED PAD (PꢁI 39ꢂ ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS
EXPOꢀED PAD (PꢁI 39ꢂ ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS
ORDER INFORMATION
LEAD FREE FINISH
LTC2751CUHF-12#PSF LTC2751CUHF-12#TRPSF
LTC2751ꢁUHF-12#PSF LTC2751ꢁUHF-12#TRPSF
LTC2751CUHF-14#PSF LTC2751CUHF-14#TRPSF
LTC2751ꢁUHF-14#PSF LTC2751ꢁUHF-14#TRPSF
ꢁAPE AND REEL
PARꢁ MARKING*
275112
PACKAGE DESCRIPꢁION
ꢁEMPERAꢁURE RANGE
0°C to 70°C
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
38-Lead (5mm × 7mmꢂ Plastic QFI
275112
–40°C to 85°C
0°C to 70°C
275114
275114
–40°C to 85°C
0°C to 70°C
LTC2751SCUHF-16#PSF LTC2751SCUHF-16#TRPSF
LTC2751SꢁUHF-16#PSF LTC2751SꢁUHF-16#TRPSF
LTC2751ACUHF-16#PSF LTC2751ACUHF-16#TRPSF
LTC2751AꢁUHF-16#PSF LTC2751AꢁUHF-16#TRPSF
275116
275116
–40°C to 85°C
0°C to 70°C
275116
275116
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2751f
2
LTC2751
ELECTRICAL CHARACTERISTICS
V
= 5V, V
= 5V unless otherwise specified2 ꢁhe
REF
●
denotes the
DD
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at ꢁ = ±5°C2
A
LꢁC±751-1±
LꢁC±751-14
LꢁC±751B-16
LꢁC±751A-16
SYMBOL PARAMEꢁER
Static Performance
Resolution
CONDIꢁIONS
MIN ꢁYP
MAX MIN ꢁYP MAX MIN ꢁYP MAX MIN ꢁYP MAX UNIꢁS
●
●
●
12
12
14
14
16
16
16
16
Sits
Sits
LꢀS
Monotonicity
DIL
ꢁIL
GE
Differential
1
1
2
1
1
5
1
2
0.2
0.4
4
1
1
Ionlinearity
●
●
ꢁntegral
Ionlinearity
LꢀS
LꢀS
Gain Error
All Output
Ranges
0.5
0.6
0.2
0.5
1.5
0.6
0.6
0.5
20
14
GE
Gain Error Temp-
erature Coefficient
ΔGain/ΔTemp
0.6
0.5
0.6
2
ppm/°C
LꢀS
TC
●
SZE
SZꢀ
Sipolar Zero Error All Sipolar
Ranges
1
3
12
8
Sipolar Zero Temp-
erature Coefficient
0.5
ppm/°C
LꢀS/V
nA
TC
●
●
PꢀR
Power ꢀupply
Rejection
V
V
= 5V, 10ꢃ
= 3V, 10ꢃ
0.025
0.06
0.1
0.25
0.4
1
0.03
0.1
0.2
0.5
DD
DD
ꢁ
ꢁ
Leakage
T = 25°C
0.05
2
5
0.05
2
5
0.05
2
5
0.05
2
5
LKG
OUT1
A
●
Current
T
to T
MꢁI MAX
C
ꢁOUT1
Output
Capacitance
Full-ꢀcale
Zero ꢀcale
75
45
75
45
75
45
75
45
pF
pF
V
= 5V, V
= 5V unless otherwise specified2 ꢁhe
●
denotes specifications that apply oꢀer the full operating temperature range,
DD
REF
otherwise specifications are at ꢁ = ±5°C2
A
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
Resistances (Note 3)
R1/R2
●
●
●
●
●
Reference ꢁnverting Resistors
DAC ꢁnput Resistance
Feedback Resistor
(Iote 4ꢂ
16
8
20
10
kΩ
kΩ
kΩ
kΩ
kΩ
R
R
R
R
REF
FS
(Iote 3ꢂ
(Iote 3ꢂ
8
10
Sipolar Offset Resistor
Offset Adjust Resistor
16
800
20
OFꢀ
VOꢀ
1000
Dynamic Performance
Output ꢀettling Time
0V to 10V Range, 10V ꢀtep. To 0.0015ꢃ Fꢀ
(Iote 5ꢂ
2
μs
Glitch ꢁmpulse
(Iote 6ꢂ
(Iote 7ꢂ
1
1
nV•s
nV•s
mV
Digital-to-Analog Glitch ꢁmpulse
Multiplying Feedthrough Error
0V to 10V Range, V
ꢀine Wave
=
10V, 10kHz
0.5
REF
THD
Total Harmonic Distortion
(Iote 8ꢂ Multiplying
(Iote 9ꢂ at ꢁ
–110
13
dS
Output Ioise Voltage Density
nV/√Hz
OUT1
Power Supply
●
●
V
ꢀupply Voltage
2.7
5.5
1
V
DD
ꢁ
DD
ꢀupply Current, V
Digital ꢁnputs = 0V or V
0.5
μA
DD
DD
2751f
3
LTC2751
ELECTRICAL CHARACTERISTICS
V
= 5V, V
= 5V unless otherwise specified2 ꢁhe
●
denotes the
DD
REF
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at ꢁ = ±5°C2
A
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
Digital Inputs
●
●
V
Digital ꢁnput High Voltage
Digital ꢁnput Low Voltage
3.3V ≤ V ≤ 5.5V
2.4
2
V
V
ꢁH
DD
2.7V ≤ V < 3.3V
DD
●
●
V
4.5V < V ≤ 5.5V
0.8
0.6
V
V
ꢁL
DD
2.7V ≤ V ≤ 4.5V
DD
●
●
ꢁ
Digital ꢁnput Current
V
= GID to V
DD
1
6
µA
pF
ꢁI
ꢁI
ꢁI
C
Digital ꢁnput Capacitance
V
= 0V (Iote 10ꢂ
ꢁI
Digital Outputs
●
●
V
OH
V
OL
ꢁ
ꢁ
= 200µA
= 200µA
V – 0.4
DD
V
V
OH
OL
0.4
TIMING CHARACTERISTICS
V
= 5V, V
= 5V unless otherwise specified2 ꢁhe
REF
●
denotes specifications that
DD
apply oꢀer the full operating temperature range, otherwise specifications are at ꢁ = ±5°C2
A
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
V
= 425V to 525V
DD
Write and Update ꢁiming
●
●
●
●
●
●
●
●
t
t
t
t
t
t
t
t
ꢁ/O Valid to WR Rising Edge ꢀet-Up
ꢁ/O Valid to WR Rising Edge Hold
WR Pulse Width
9
9
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
20
20
0
UPD Pulse Width
UPD Falling Edge to WR Falling Edge
WR Rising Edge to UPD Rising Edge
D/ꢀ Valid to WR Falling Edge ꢀet-Up Time
WR Rising Edge to D/ꢀ Valid Hold Time
Io Data ꢀhoot-Through
(Iote 10ꢂ
0
9
9
Readback ꢁiming
●
●
●
●
●
●
●
●
●
●
t
13
t
14
t
15
t
17
t
18
t
19
t
20
t
22
t
23
t
24
WR Rising Edge to READ Rising Edge
READ Falling Edge to WR Falling Edge
READ Rising Edge to ꢁ/O Propagation Delay
UPD Valid to ꢁ/O Propagation Delay
D/ꢀ Valid to READ Rising Edge
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Iote 10ꢂ
20
C = 10pF
L
30
30
C = 10pF
L
(Iote 10ꢂ
Io Update
Io Update
(Iote 10ꢂ
(Iote 10ꢂ
(Iote 10ꢂ
9
9
READ Rising Edge to UPD Rising Edge
UPD Falling Edge to READ Falling Edge
READ Falling Edge to UPD Rising Edge
ꢁ/O Sus Hi-Z to READ Rising Edge
READ Falling Edge to ꢁ/O Sus Active
9
9
0
20
CLR ꢁiming
●
t
CLR Pulse Width Low
20
ns
25
2751f
4
LTC2751
TIMING CHARACTERISTICS
V
= 5V, V
= 5V unless otherwise specified2 ꢁhe
REF
●
denotes specifications that
DD
apply oꢀer the full operating temperature range, otherwise specifications are at ꢁ = ±5°C2
A
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
V
= ±27V to 323V
DD
Write and Update ꢁiming
●
●
●
●
●
●
●
●
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
ꢁ/O Valid to WR Rising Edge ꢀet-Up
ꢁ/O Valid to WR Rising Edge Hold
WR Pulse Width
18
18
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
UPD Pulse Width
UPD Falling Edge to WR Falling Edge
WR Rising Edge to UPD Rising Edge
D/ꢀ Valid to WR Falling Edge ꢀet-Up Time
WR Rising Edge to D/ꢀ Valid Hold Time
Io Data ꢀhoot-Through
(Iote 10ꢂ
0
18
18
Readback ꢁiming
●
●
●
●
●
●
●
●
●
●
t
13
t
14
t
15
t
17
t
18
t
19
t
20
t
22
t
23
t
24
WR Rising Edge to Read Rising Edge
Read Falling Edge to WR Falling Edge
Read Rising Edge to ꢁ/O Propagation Delay
UPD Valid to ꢁ/O Propagation Delay
D/ꢀ Valid to Read Rising Edge
18
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Iote 10ꢂ
C = 10pF
L
40
40
C = 10pF
L
(Iote 10ꢂ
Io Update
Io Update
(Iote 10ꢂ
(Iote 10ꢂ
(Iote 10ꢂ
18
9
Read Rising Edge to UPD Rising Edge
UPD Falling Edge to Read Falling Edge
READ Falling Edge to UPD Rising Edge
ꢁ/O Sus Hi-Z to Read Rising Edge
9
18
0
Read Falling Edge to ꢁ/O Sus Active
40
CLR ꢁiming
●
t
CLR Pulse Width Low
30
ns
25
Note 1: ꢀtresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
basis. ꢀee Application Iote 74, “Component and Measurement Advances
Ensure 16-Sit DAC ꢀettling Time.”
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1469; C = 27pF.
FS
Note ±: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Secause of the proprietary ꢀoftꢀpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
Note 72 Full-scale transition; REF = 0V.
Note 82 REF = 6V
at 1kHz. 0V to 5V range. DAC code = Fꢀ. Output
RMꢀ
amplifier = LT1469.
Note 92 Calculation from V = √4kTRS, where k = 1.38E-23 J/°K
n
all output ranges if the ꢁ
and ꢁ
pins are held at ground.
OUT1
OUT2
(Soltzmann constantꢂ, R = resistance (Ωꢂ, T = temperature (°Kꢂ, and S =
bandwidth (Hzꢂ.
Note 102 Guaranteed by design. Iot production tested.
Note 4: R1 is measured from R to R
; R2 is measured from REF to
ꢁI
COM
R
COM
.
Note 5: Using LT1469 with C
= 15pF. A 0.0015ꢃ settling time
FEEDSACK
of 1.7μs can be achieved by optimizing the time constant on an individual
2751f
5
LTC2751
TYPICAL PERFORMANCE CHARACTERISTICS ꢁ = ±5°C, unless otherwise noted2
A
LꢁC±751-16
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.8
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
DD
REF
DD
= 5V
= 5V
±10V RANGE
±10V RANGE
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
2751 G01
2751 G02
INL ꢀs ꢁemperature
DNL ꢀs ꢁemperature
Bipolar Zero ꢀs ꢁemperature
1.0
0.8
1.0
8
V
V
= 5V
= 5V
V
V
= 5V
= 5V
V
V
= 5V
= 5V
DD
REF
DD
REF
DD
REF
0.8
0.6
6
4
2
0
2
4
6
8
±10V RANGE
±10V RANGE
±10V RANGE
0.6
0.4
0.4
+INL
–INL
0.5ppm/°C (TYP)
0.2
0.2
+DNL
–DNL
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2751 G04
2751 G05
2751 G06
Gain Error ꢀs ꢁemperature
INL ꢀs V
DNL ꢀs V
REF
REF
16
12
8
1.0
0.8
1.0
0.8
V
V
= 5V
REF
V
= 5V
V
= 5V
DD
DD
DD
= 5V
±5V RANGE
±5V RANGE
±10V RANGE
0.6
0.6
0.4
0.4
+INL
–INL
0.6ppm/°C (TYP)
4
+INL
–INL
0.2
0.2
+DNL
–DNL
+DNL
–DNL
0
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–4
–8
–12
–16
0
20
TEMPERATURE (°C)
40
–10 –8
–6
0
2
4
6
10
–10 –8 –6
4
2
V
0
2
4
6
10
–40
–20
60
80
4
2
V
8
8
(V)
(V)
REF
REF
2751 G07
2751 G08
2751 G09
2751f
6
LTC2751
TYPICAL PERFORMANCE CHARACTERISTICS ꢁ = ±5°C, unless otherwise noted2
A
LꢁC±751-16
INL ꢀs V
DD
Settling 0V to 10V
1.0
0.8
UPD
0.6
5V/DIV
0.4
+INL
–INL
0.2
GATED
SETTLING
WAVEFORM
250μV/DIV
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
2751 G10
500ns/DIV
USING LT1469 AMP
= 12pF
C
FEEDBACK
2.5
3
3.5
4
4.5
5
5.5
0V TO 10V STEP
V
(V)
DD
2751 G09b
LꢁC±751-14
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.8
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
DD
REF
DD
= 5V
= 5V
±10V RANGE
±10V RANGE
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
12288
16383
0
4096
8192
12288
16383
CODE
CODE
2751 G11
2751 G12
LꢁC±751-1±
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.8
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
DD
REF
DD
= 5V
= 5V
±10V RANGE
±10V RANGE
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
4095
0
1024
2048
3072
4095
CODE
CODE
2751 G13
2751 G14
2751f
7
LTC2751
TYPICAL PERFORMANCE CHARACTERISTICS ꢁ = ±5°C, unless otherwise noted2
A
LꢁC±751-1±, LꢁC±751-14, LꢁC±751-16
Supply Current ꢀs
Logic Input Voltage
Midscale Glitch
12
10
UPD
5V/DIV
8
6
1nV•s (TYP)
V
= 5V
DD
V
OUT
2mV/DIV
4
2
0
2751 G15
500ns/DIV
USING AN LT1469
= 27pF
V
= 3V
DD
V
V
= 5V
REF
0V TO 5V RANGE
DD
= 5V
C
FEEDBACK
0
1
2
3
4
5
LOGIC VOLTAGE (V)
2751 G16
ALL DIGITAL PINS TIED TOGETHER
(EXCEPT READ TIED TO GND)
Logic ꢁhreshold
ꢀs Supply Voltage
Supply Current
ꢀs Update Frequency
1000
100
10
2
1.75
1.5
RISING
1.25
1
FALLING
1
V
V
= 5V
= 3V
DD
0.75
0.5
DD
0.1
10
100
1k
10k
100k
1M
2.5
3.5
4
4.5
5
5.5
3
V
(V)
UPD FREQUENCY (Hz)
DD
2751 G18
2751 G17
ALTERNATING ZERO-SCALE/FULL-SCALE
(LTC2751-16)
2751f
8
LTC2751
PIN FUNCTIONS
R
(Pin 1): Center Tap Point of R and REF. Iormally
tied to the negative input of the external reference invert-
MꢀPAI must be connected either directly to GID (ꢀoft-
COM
ꢁI
ꢀpan configurationꢂ or V (single-span configurationꢂ.
DD
ing amplifier.
D0-D±(Pins19-±1):LꢁC±751-1±Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D0 is the LꢀS.
R (Pin±):ꢁnputResistorforExternalReferenceꢁnverting
IN
Amplifier. Iormally tied to the external reference voltage
V
15V.
and to R
(Pin 37ꢂ. Typically 5V; accepts up to
REF
OFꢀ
D0-D4(Pins19-±3):LꢁC±751-14Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D0 is the LꢀS.
S± (Pin 3): ꢀpan ꢁ/O Sit 2. Pins ꢀ0, ꢀ1 and ꢀ2 are used to
program and to read back the output range of the DAC.
D0-D6(Pins19-±5):LꢁC±751-16Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D0 is the LꢀS.
I
(Pin 4): DAC Current Output Complement. Tie ꢁ
OUT2
OUꢁ±
to GID.
NC (Pin 5): Io Connection. Must be tied to GID, provides
necessary shielding for ꢁ
NC (Pins ±±-±7): LꢁC±751-1± Only2 Io Connection.
NC (Pins ±4-±7): LꢁC±751-14 Only2 Io Connection.
NC (Pins ±6, ±7): LꢁC±751-16 Only2 Io Connection.
.
OUT2
D3-D11(Pins6-14):LꢁC±751-1±Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D11 is the MꢀS.
D/S (Pin ±8): Data/ꢀpan ꢀelect. This pin is used to select
activation of the data or span ꢁ/O pins (D0 to D15 or ꢀ0
to ꢀ2, respectivelyꢂ, along with their respective dedicated
registers, for write or read operations. Update operations
ignore D/ꢀ, since all updates affect both data and span
registers. For single-span operation, tie D/ꢀ to GID.
D5-D13(Pins6-14):LꢁC±751-14Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D13 is the MꢀS.
D7-D15(Pins6-14):LꢁC±751-16Only2DACꢁnput/Output
Data Sits. These ꢁ/O pins set and read back the DAC code.
D15 is the MꢀS.
READ (Pin ±9): Read Pin. When READ is asserted high,
the data ꢁ/O pins (D0-D15ꢂ or span ꢁ/O pins (ꢀ0-ꢀ2ꢂ
output the contents of the selected register (see Table 1ꢂ.
For single-span operation, readback of the span ꢁ/O pins
is disabled.
V
(Pin 15): Positive ꢀupply ꢁnput 2.7V ≤ V ≤ 5.5V.
DD
DD
Requires a 0.1µF bypass capacitor to GID.
GND (Pin 16): Ground. Tie to ground.
UPD (Pin 30): Update and Suffer ꢀelect Pin. When READ
is held low and UPD is asserted high, the contents of the
input registers (both data and spanꢂ are copied into their
respectiveDACregisters.TheoutputoftheDACisupdated,
reflecting the new DAC register values.
CLR (Pin 17): Asynchronous Clear. When CLR is taken
to a logic low, the data registers are reset to the zero-volt
code for the present output range (V
= 0Vꢂ.
OUT
MSPAN(Pin18):ManualꢀpanControlPin.MꢀPAIisused
to configure the LTC2751 for operation in a single, fixed
output range. When configured for single-span operation,
the output range is set via hardware pin strapping. The
span input and DAC registers are transparent and do not
respond to write or update commands.
When READ is held high, the update function is disabled
and the UPD pin functions as a buffer selector—logic low
to select the input register, high for the DAC register. ꢀee
Readback in the Operation section.
WR (Pin 31): Active Low Write Pin. A Write operation
copies the data present on the data or span ꢁ/O pins (D0-
D15 or ꢀ0-ꢀ2, respectivelyꢂ into the input register. When
READ is high, the Write function is disabled.
To configure the part for single-span use, tie MꢀPAI
directly to V . ꢁf MꢀPAI is instead connected to GID
DD
(ꢀoftꢀpan configurationꢂ, the output ranges are set and
verified by using write, update and read operations. ꢀee
Manual ꢀpan Configuration in the Operation section.
S0 (Pin 3±): ꢀpan ꢁ/O Sit 0. Pins ꢀ0, ꢀ1 and ꢀ2 are used to
program and to read back the output range of the DAC.
2751f
9
LTC2751
PIN FUNCTIONS
S1 (Pin 33): ꢀpan ꢁ/O Sit 1. Pins ꢀ0, ꢀ1 and ꢀ2 are used to
program and to read back the output range of the DAC.
R
(Pin 37): Sipolar Offset Ietwork. This pin provides
OFS
the translation of the output voltage range for bipolar
spans. Accepts up to 15V; normally tied to the positive
reference voltage at R (Pin 2ꢂ.
R
(Pin 34): DAC Offset Adjust. Iominal input range is
VOS
ꢁI
5V. ꢁf not used, R
should be shorted to ꢁ
.
VOꢀ
OUT2
REF(Pin38):FeedbackResistorfortheReferenceꢁnverting
Amplifier, and Reference ꢁnput for the DAC. Iormally tied
to the output of the reference inverting amplifier. Typically
–5V. Accepts up to 15V.
I
(Pin 35): DAC current output; normally tied to the
OUꢁ1
negative input of the ꢁ/V converter amplifier.
R
(Pin 36): DAC Feedback Resistor; normally tied to
FB
the output of the ꢁ/V converter amplifier. The DAC output
Exposed Pad (Pin 39): Ground. The Exposed Pad must
be soldered to the PCS.
current from ꢁ
to the R pin.
flows through the feedback resistor
OUT1
FS
2751f
10
LTC2751
BLOCK DIAGRAM
1
38
REF
37
36
R
COM
R
FB
R
OFS
R
IN
R1
R2
2
I
I
OUT1
35
4
READ
29
WR
31
UPD
30
D/S
28
CLR
17
MSPAN
18
16-BIT DAC WITH SPAN SELECT
OUT2
3
16
DAC
REGISTER
DAC
REGISTER
CONTROL
LOGIC
3
16
INPUT
REGISTER
INPUT
REGISTER
I/O
PORT
I/O
PORT
3
16
2751 BD
3, 32, 33
SPAN I/O
6-14, 19-25
DATA I/O
D15-D0
S2-S0
2751f
11
LTC2751
TIMING DIAGRAMS
Write, Update and Clear ꢁiming
t
3
t
1
t
2
WR
I/O
INPUT
t
5
t
6
UPD
t
4
t
7
t
8
D/S
t
25
CLR
2751 TD01
Readback ꢁiming
READ
WR
t
t
t
14
24
13
t
23
I/O
INPUT
t
15
I/O
OUTPUT
t
17
t
20
t
t
22
19
UPD
D/S
t
18
2751 TD02
OPERATION
Output Ranges
Digital Section
The LTC2751 is a current-output, parallel-input precision
multiplying DAC with software-programmable output
ranges. ꢀoftꢀpan provides two unipolar output ranges
(0V to 5V and 0V to 10Vꢂ, and four bipolar ranges ( 2.5V,
5V, 10V and –2.5V to 7.5Vꢂ. These ranges are obtained
when an external precision 5V reference is used. When
a reference voltage of 2V is used, the ꢀoftꢀpan ranges
become: 0V to 2V, 0V to 4V, 1V, 2V, 4V and –1V to
3V. The output ranges are linearly scaled for references
other than 2V and 5V.
The LTC2751 family has four internal interface registers
(see Slock Diagramꢂ. Two of these—one input and one
DAC register—are dedicated to the data ꢁ/O port, and two
tothespanꢁ/Oport. Eachportisthusdouble-buffered. The
double-bufferedfeatureprovidesthecapabilitytosimulta-
neously update the span and code, which allows smooth
voltage transitions when changing output ranges. ꢁt also
permits the simultaneous updating of multiple DACs.
2751f
12
LTC2751
OPERATION
Write and Update Operations
Table 1 shows the functions of the LTC2751.
The data input register is loaded directly from a 16-bit
microprocessor bus by holding the D/ꢀ pin low and then
pulsing the WR pin low. The second register (DAC regis-
terꢂ is loaded by pulsing the UPD pin high, which copies
the data held in the input register into the DAC register.
Iote that updates always include both data and span; but
the DAC register values will not change unless the input
register values have been changed by writing.
ꢁable 12 Write, Update and Read Functions
READ D/S WR UPD
SPAN I/O
DAꢁA I/O
0
0
0
0
0
0
0
1
-
-
Write to ꢁnput Register
Write/Update
(Transparentꢂ
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
-
-
Update DAC Register Update DAC Register
Write to ꢁnput Register
-
-
Write/Update
(Transparentꢂ
Loadingthespaninputregisterisaccomplishedinasimilar
manner, by holding the D/ꢀ pin high and then bringing the
WR pin low. The span and data register structures are the
same except for the number of parallel bits—the span
registers have three bits, while the data registers have
12, 14, or 16 bits.
0
0
1
1
1
1
1
1
0
0
1
1
1
1
X
X
X
X
0
1
0
1
0
1
-
-
Update DAC register Update DAC Register
-
Read ꢁnput Register
-
Read DAC Register
Read ꢁnput Register
Read DAC Register
-
-
To make both registers transparent for flowthrough
mode, tie WR low and UPD high. However, this defeats
the deglitcher operation and output glitch impulse may
increase. The deglitcher is activated on the rising edge
of the UPD pin.
X = Don’t Care
Manual Span Configuration
Multipleoutputrangesarenotneededinsomeapplications.
ToconfiguretheLTC2751forsingle-spanoperation,tiethe
The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, configura-
tion. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
MꢀPAI pin to V and the D/ꢀ pin to GID. The desired
DD
output range is then specified by the span ꢁ/O pins (ꢀ0, ꢀ1
and ꢀ2ꢂ as usual, but the pins are programmed by tying
directly to GID or V (see Figure 1 and Table 2ꢂ. ꢁn this
DD
configuration, the part will initialize to the chosen output
range at power-up, with V
= 0V.
OUT
The separation of data and span for write and read opera-
tions makes it possible to control both data and span on
one 16-bit wide data bus by allowing span pins ꢀ2 to ꢀ0
to share bus lines with the data LꢀSs (D2 to D0ꢂ. ꢀince
no write or read operation includes both span and data,
there cannot be a conflict.
When configured for manual span operation, span pin
readback is disabled.
V
DD
V
MSPAN
S2
DD
LTC2751-16
The asynchronous clear pin resets the LTC2751 to 0V
(zero-, half- or quarter-scale codeꢂ in any output range.
CLR resets both the input and DAC data registers, while
leaving the span registers undisturbed.
S1
S0
WR UPD READ
D/S
16
These devices also have a power-on reset. ꢁf configured
for ꢀoftꢀpan operation, the part initializes to zero scale in
the 0V to 5V output range. ꢁf configured for single-span
operation, the part initializes to the zero-volt code in the
chosen output range.
2751 F01
DATA I/O
Figure 12 Configuring the LꢁC±751 for
Single-Span Operation (±10V Range)
2751f
13
LTC2751
OPERATION
ꢁable ±2 Span Codes
isatwo-functionpin.Theupdatefunctionisdisabledwhen
READ is high, and the UPD pin instead selects the input
or DAC register for readback. Table 1 shows the readback
functions for the LTC2751.
S±
0
S1
0
S0
0
SPAN
Unipolar 0V to 5V
Unipolar 0V to 10V
Sipolar –5V to 5V
Sipolar –10V to 10V
Sipolar –2.5V to 2.5V
Sipolar –2.5V to 7.5V
0
0
1
0
1
0
The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, bring READ high
while holding UPD low. The contents of the selected port’s
input register are output by the data or span ꢁ/O pins.
0
1
1
1
0
0
1
0
1
Codes not shown are reserved and should not be used.
To read back the contents of a DAC register, bring READ
high, then bring UPD high. The contents of the selected
data or span DAC register are output by the data or span
ꢁ/O pins. Iote: if no update is desired after the readback
operation, UPD must be returned low before bringing
READ low, otherwise the UPD pin will revert to its primary
function and update the DAC.
Readback
The contents of any one of the four interface registers can
be read back by using the READ pin in conjunction with
the D/ꢀ and UPD pins.
AreadbackoperationisinitiatedbybringingREADtologic
high.Theꢁ/Opins,whicharehigh-impedancedigitalinputs
when READ is low, selectively change to low-impedance
logic outputs during readback.
System Offset Adjustment
Many systems require compensation for overall system
The ꢁ/O pins comprise two ports, data and span. The data
ꢁ/O port consists of pins D0-D11, D0-D13 or D0-D15
(LTC2751-12, LTC2751-14 or LTC2751-16, respectivelyꢂ.
The span ꢁ/O port consists of pins ꢀ0, ꢀ1 and ꢀ2 for all
parts.
offset. The R
offset adjustment pin is provided for this
VOꢀ
purpose. For noise immunity and ease of adjustment, the
control voltage is attenuated to the DAC output:
V
V
= –0.01 • V(R ꢂ [0V to 5V, 2.5V spansꢄ
Oꢀ
VOꢀ
= –0.02 • V(R ꢂ [0V to 10V, 5V,
Each ꢁ/O port has one dedicated input register and one
dedicated DAC register. The register structure is shown
in the Slock Diagram.
Oꢀ
VOꢀ
–2.5V to 7.5V spansꢄ
V
Oꢀ
= –0.04 • V(R ꢂ [ 10V spanꢄ
VOꢀ
The D/ꢀ pin is used to select which ꢁ/O port (data or spanꢂ
is configured to read back the contents of its registers.
The unselected ꢁ/O port’s pins remain high-impedance
inputs.
The nominal input range of this pin is 5V; other refer-
ence voltages of up to 15V may be used if needed. The
VOꢀ
R
pin has an input impedance of 1MΩ. To preserve the
settling performance of the LTC2751, this pin should be
driven with a Thevenin-equivalent impedance of 10kΩ or
Once the ꢁ/O port is selected, its input or DAC register is
selected for readback by using the UPD pin. Iote that UPD
less. ꢁf not used, R
should be shorted to ꢁ
.
VOꢀ
OUT2
2751f
14
LTC2751
OPERATION—EXAMPLES
1. Load 5V range with the output at 0V. Iote that since span and code are updated together, the output, if started at
0V, will stay there.
WR
SPAN I/O
INPUT
010
DATA I/O
INPUT
8000
H
UPD
UPDATE
(±5V RANGE, V
= 0V)
OUT
D/S
READ = LOW
2751 TD03
2. Load 10V range with the output at 5V, changing to –5V.
WR
SPAN I/O
INPUT
011
DATA I/O
INPUT
C000
4000
H
H
UPD
UPDATE (5V)
UPDATE (–5V)
D/S
READ = LOW
2751 TD04
3. Write and update midscale code in 0V to 5V range (V
and DAC registers before updating.
= 2.5Vꢂ using readback to check the contents of the input
OUT
WR
HI-Z
DATA I/O
INPUT
8000
H
HI-Z
DATA I/O
OUTPUT
8000
0000
H
H
INPUT REGISTER
DAC REGISTER
UPD
D/S
UPDATE (2.5V)
READ
2751 TD05
2751f
15
LTC2751
APPLICATIONS INFORMATION
Op Amp Selection
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the ꢁIL, DIL,
unipolaroffset,unipolargainerror,bipolarzeroandbipolar
gain error. Tables 3 and 4 can also be used to determine
the effects of op amp parameters on the LTC2751-14
and the LTC2751-12. However, the results obtained from
Tables 3 and 4 are in 16-bit LꢀSs. Divide these results
by 4 (LTC2751-14ꢂ and 16 (LTC2751-12ꢂ to obtain the
correct LꢀS sizing.
Secause of the extremely high accuracy of the 16-bit
LTC2751-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
ꢁIL and DIL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 3 and 4 contain equations for evaluating the effects
of op amp parameters on the LTC2751’s accuracy when
Table 5 contains a partial list of LTC precision op amps
recommended for use with the LTC2751. The easy-to-use
designequationssimplifytheselectionofopampstomeet
the system’s specified error budget. ꢀelect the amplifier
from Table 5 and insert the specified op amp parameters
in Table 4. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part.Arithmeticsummationgivesan(unlikelyꢂworst-case
effect. A root-sum-square (RMꢀꢂ summation produces a
more realistic estimate.
ꢁable 32 Variables for Each Output Range ꢁhat Adjust the
Equations in ꢁable 4
OUꢁPUꢁ RANGE
A1
1.1
2.2
2
A±
2
A3
1
A4
A5
1
5V
10V
3
0.5
1
1.5
1.5
2.5
1
5V
2
1
1
10V
4
4
0.83
1.4
0.7
2.5V
1
1
1
–2.5V to 7.5V
1.9
3
0.5
1.5
ꢁable 42 Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1)2 Subscript 1
Refers to Output Amp, Subscript ± Refers to Reference Inꢀerting Amp2
UNIPOLAR
OFFSET (LSB)
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
BIPOLAR GAIN
ERROR (LSB)
OP AMP
INL (LSB)
DNL (LSB)
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
V
(mV)
V
• 3.2 •
V
• 0.82 •
A3 • V
OS1
• 13.2 •
A3 • V
• 19.8 •
V
• 13.2 •
V
I
• 13.2 •
OS1
)
)
)
)
)
)
)
)
(V
(V
(V
(V
(V
(V
OS1
OS1
OS1
OS1
OS1
5V
5V
5V
5V
5V
5V
I
(nA)
I
• 0.0003 •
I
• 0.00008 •
I
• 0.13 •
I
• 0.13 •
0
I
B1
• 0.0018 •
• 0.0018 •
(V
(V
B1
B1
B1
B1
B1
B1
)
(V
(V
(V
(V
)
)
)
REF
REF
REF
REF
REF
REF
( 16.5k)
1.5k
VOL1
131k
VOL1
131k
VOL1
A
VOL1
(V/V)
(mV)
A1 •
A2 •
0
0
0
0
A5 •
A5 •
)
A
(A
)
)
(A
(A
VOL1
5V
5V
5V
V
0
0
0
0
0
0
A4 • V
• 13.1 •
V
• 26.2 •
V
• 26.2 •
OS2
OS2
OS2
OS2
(V
)
(V
(V
(
))
))
)
REF
REF
REF
5V
5V
REF
5V
(V
I
(mV)
A4 • I • 0.13 •
I
• 0.26 •
I
B2
• 0.26 •
131k
B2
B2
B2
(
(V
REF
)
)
(V
REF
66k
VOL2
131k
(A
A
VOL2
(V/V)
A4 •
(A
)
(A
)
)
VOL2
VOL2
ꢁable 52 Partial List of LꢁC Precision Amplifiers Recommended for Use with the LꢁC±751 with Releꢀant Specifications
AMPLIFIER SPECIFICAꢁIONS
VOLꢁAGE CURRENꢁ
SLEW
RAꢁE
V/µs
GAIN BANDWIDꢁH
PRODUCꢁ
MHz
t
POWER
SEꢁꢁLING
V
I
A
VOL
NOISE
NOISE
with LꢁC±751 DISSIPAꢁION
OS
B
AMPLIFIER
LT1001
µV
nA
V/mV
nV/√Hz
pA/√Hz
µs
120
120
115
19
mW
46
25
2
800
10
14
14
2.7
5
0.12
0.008
0.008
0.3
0.25
0.2
0.16
4.5
22
0.8
0.7
0.75
12.5
90
LT1097
50
0.35
0.25
20
1000
1500
4000
5000
2000
11
LT1112 (Dualꢂ
LT1124 (Dualꢂ
LT1468
60
10.5/Op Amp
69/Op Amp
117
70
75
10
0.6
2
LT1469 (Dualꢂ
125
10
5
0.6
22
90
2
123/Op Amp
2751f
16
LTC2751
APPLICATIONS INFORMATION
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on ꢁIL and DIL. For
the LTC2751-16, a 250µV op amp offset will cause about
0.8LꢀS ꢁIL degradation and 0.2LꢀS DIL degradation
with a 5V reference. For the LTC2751 programmed in 5V
unipolar mode, the same 250µV op amp offset will cause
a 3.3LꢀS zero-scale error and a 3.3LꢀS gain error.
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coefficient can be
achieved by choosing a precision reference with a low
output voltage temperature coefficient and/or tightly con-
trolling the ambient temperature of the circuit to minimize
temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, referenceoutputvoltagenoisemaycontrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practi-
cal for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LꢀS level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
While not directly addressed by the simple equations in
Tables 3 and 4, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case V and ꢁ
Oꢀ
S
over temperature. Then, plug these numbers in the V
Oꢀ
and ꢁ equations from Table 4 and calculate the tempera-
S
ture-induced effects.
For applications where fast settling time is important,
Application Iote 74, “Component and Measurement
Advances Ensure 16-Sit DAC ꢀettling Time,” offers a
thorough discussion of 16-bit DAC settling time and op
amp selection.
ꢁable 62 Partial List of LꢁC Precision References Recommended
for Use with the LꢁC±751 with Releꢀant Specifications
Precision Voltage Reference Considerations
INIꢁIAL
ꢁOLERANCE
ꢁEMPERAꢁURE
DRIFꢁ
021Hz to 10Hz
NOISE
REFERENCE
Much in the same way selecting an operational amplifier
for use with the LTC2751 is critical to the performance
of the system, selecting a precision voltage reference
also requires due diligence. The output voltage of the
LTC2751 is directly affected by the voltage reference;
thus, any voltage reference error will appear as a DAC
output voltage error.
LT1019A-5,
LT1019A-10
0.05ꢃ
0.05ꢃ
0.075ꢃ
0.05ꢃ
5ppm/°C
5ppm/°C
10ppm/°C
10ppm/°C
12µV
P-P
LT1236A-5,
LT1236A-10
3µV
P-P
LT1460A-5,
LT1460A-10
20µV
P-P
P-P
LT1790A-2.5
12µV
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit appli-
cations: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. ꢁ
must be tied
OUT2
ꢁnitial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
( 0.05ꢃꢂ,minimizesthegainerrorcausedbythereference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to
ꢁ
, a low resistance trace should be used to route this
OUT2
pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code dependent current
flowing to ground. When the resistance of this circuit
board trace becomes greater than 1Ω, a force/sense am-
plified configuration should be used to drive this pin (see
Figure 2ꢂ. This preserves the excellent accuracy (1LꢀS
Areference’soutputvoltagetemperaturecoefficientaffects
not only the full-scale error, but can also affect the circuit’s
ꢁIL and DIL performance. ꢁf a reference is chosen with
a loose output voltage temperature coefficient, then the
ꢁIL and DILꢂ of the LTC2751-16.
2751f
17
LTC2751
APPLICATIONS INFORMATION
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
I
OUT2
200
200
–
2
6
1000pF
LT1468
1
2
+ 3
–
+
2
3
ZETEX
BAT54S
6
I
LT1001
OUT2
3
1
2
REF
5V
ZETEX*
BAT54S
5
–
3
7
1/2 LT®1469
6
C2**
150pF
+
*SCHOTTKY BARRIER DIODE
2
R
1
R
38 37
REF
36
C1
R
FB
OFS
15pF
R
IN
R1
COM
R2
15V 0.1
F
LTC2751-16
8
–
I
I
OUT1 35
2
3
31
30
29
28
17
18
WR
UPD
READ
D/S
WR
UPD
1
16-BIT DAC WITH SPAN SELECT
V
OUT
1/2 LT1469
+
OUT2
GND
4
READ
D/S
0.1
F
16
4
CLR
CLR
3
16
–15V
15
V
5V
DD
MSPAN
C3
R
VOS
34
0.1
F
3, 33, 32
SPAN I/O
S2-S0
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
6-14, 19-25
DATA I/O
D15-D0
2751 F02
Figure ±2 Basic Connections for SoftSpan V
DAC with ꢁwo Optional Circuits
OUꢁ
for Driꢀing I
from GND with a Force/Sense Amplifier
OUꢁ±
TYPICAL APPLICATIONS
16-Bit DAC with Software-Selectable Ranges
REF
5V
5
–
7
1/2 LT1469
6
C2**
150pF
+
2
R
1
38 37
REF
36
R
R
COM
R
IN
FB
OFS
C1
15pF
R1
R2
0.1
F
F
15V
8
LTC2751-16
I
I
–
OUT1 35
2
31
WR
UPD
READ
D/S
WR
1
30
29
28
17
18
16-BIT DAC WITH SPAN SELECT
V
OUT
1/2 LT1469
UPD
READ
D/S
OUT2
GND
4
3 +
16
4
–15V
5V
CLR
CLR
0.1
3
16
15
V
DD
MSPAN
C3
0.1
R
VOS
F
3, 33, 32
SPAN I/O
S2-S0
6-14, 19-25
34
2751 TA02
DATA I/O
D15-D0
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
2751f
18
LTC2751
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701ꢂ
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.15 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.15 ± 0.10
(2 SIDES)
0.75 ± 0.05
5.00 ± 0.10
(2 SIDES)
37 38
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.40 ± 0.10
0.200 REF 0.25 ± 0.05
R = 0.115
TYP
(UH) QFN 0205
0.50 BSC
0.200 REF
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
2751f
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2751
TYPICAL APPLICATION
Offset and Gain ꢁrim Circuits2 Powering V from Lꢁ10±7 Ensures Quiet Supply
DD
+
V
IN
OUT
U3
LT1027
+
2
6
5
2
1
V
C13
8
2
3
2
10 F
TRIM
R2
10k
–
3
R1
10k
C20
10 F
GND
4
U2A
1
GND
LT®1469
1
C23
0.1 F
+
C22
0.001 F
4
–
V
GND
GND
GND
C1
30pF
15
2
1
38
37 36
6
7
8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
V
R
R
REF
R R
OFS FB
DD
IN
COM
–
35
9
6
5
I
I
OUT1
OUT2
10
11
12
13
14
19
20
21
22
23
24
25
U2B
LT1469
7
V
OUT
4
+
U1
LTC2751-16
34
DATA I/O
R
VOS
GND
D4
D3
D2
D1
D0
3
33
32
S2
S1
SPAN I/O
S0 D/S READ UPD WR CLR
MSPAN NC GND GND
2751 TA03
28 29 30 31 17
18
5
16
39
D/S READ UPD WR CLR
GND
RELATED PARTS
PARꢁ NUMBER
LT1027
DESCRIPꢁION
COMMENꢁS
Precision Reference
Precision Reference
1ppm/°C Maximum Drift
LT1236A-5
LT1468
0.05ꢃ Maximum Tolerance, 1ppm 0.1Hz to 10Hz Ioise
90MHz GSW, 22V/µs ꢀlew Rate
16-Sit Accurate Op-Amp
LT1469
Dual 16-Sit Accurate Op-Amp
90MHz GSW, 22V/µs ꢀlew Rate
LTC1588/LTC1589/ ꢀerial 12-/14-/16-Sit ꢁ
LTC1592
ꢀingle DACs
ꢀoftware-ꢀelectable (ꢀoftꢀpanꢂ Ranges, 1LꢀS ꢁIL, DIL, 16-Lead ꢀꢀOP Package
OUT
LTC1591/LTC1597 Parallel 14-/16-Sit ꢁ
ꢀingle DAC
ꢁntegrated 4-Quadrant Resistors
OUT
LTC1821
Parallel 16-Sit V
ꢀingle DAC
1LꢀS ꢁIL, DIL, 0V to 10V, 0V to –10V, 10V Output Ranges
OUT
LTC2601/LTC2611/ ꢀerial 12-/14-/16-Sit V
LTC2621
ꢀingle DACs
ꢀingle DACs, ꢀPꢁ-Compatible, ꢀingle ꢀupply, 0V to 5V Outputs in 3mm × 3mm
DFI-10 Package
OUT
2
LTC2606/LTC2616/ ꢀerial 12-/14-/16-Sit V
LTC2626
ꢀingle DACs
ꢀingle DACs, ꢁ C-Compatible, ꢀingle ꢀupply, 0V to 5V Outputs in 3mm × 3mm
OUT
DFI-10 Package
LTC2641/LTC2642 ꢀerial 12-/14-/16-Sit Unbuffered V
DACs
ꢀingle
2LꢀS ꢁIL, 1LꢀS DIL, 1µs ꢀettling, Tiny MꢀOP-10, 3mm × 3mm DFI-10
Packages
OUT
LTC2704
ꢀerial 12-/14-/16-Sit V
Quad DACs
ꢀoftware-ꢀelectable (ꢀoftꢀpanꢂ Ranges, ꢁntegrated Amplifiers
OUT
2751f
LT 0907 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Slvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408ꢂ 432-1900 FAX: (408ꢂ 434-0507 www.linear.com
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