LTC2925IGN#TR [Linear]
LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC2925IGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总24页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2925
Multiple Power Supply
Tracking Controller with
Power Good Timeout
FEATURES
DESCRIPTION
The LTC®2925 provides a simple solution to power supply
tracking and sequencing requirements. By selecting a few
resistors, the supplies can be configured to ramp-up and
ramp-down together or with voltage offsets, time delays
or different ramp rates.
n
Flexible Power Supply Tracking Up and Down
n
Power Supply Sequencing
n
Supply Stability Is Not Affected
n
Controls Three Supplies Without Series FETs
n
Controls an Optional Fourth Supply with a
Series FET
Electronic Circuit Breaker
The LTC2925 controls the outputs of three independent
supplies without inserting any pass element losses. For
systems that require a fourth supply, or when a supply
does not allow direct access to its feedback resistors, one
supply can be controlled with a series FET. When the FET
is used, an internal remote sense switch compensates for
thevoltagedropacrosstheFETandcurrentsenseresistor,
and an electronic circuit breaker provides protection from
short-circuit conditions.
n
n
Remote Sense Switch Compensates for Voltage
Drop Across a Series FET
n
Supply Shutdown Outputs
n
FAULT Output
n
Adjustable Power Good Timeout
n
Available in Narrow 24-Lead SSOP and Tiny 24-Lead
QFN Packages
The LTC2925 also includes a power good timeout feature
that turns off the supplies if an external supply monitor
fails to indicate that the supplies have entered regulation
within an adjustable timeout period.
APPLICATIONS
n
V
and V Supply Tracking
Microprocessor, DSP and FPGA Supplies
Servers
CORE
I/O
n
n
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Communication Systems
TYPICAL APPLICATION
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1μF
0.1μF
10Ω
SUPPLY
3.3V
2.5V
1.8V
1.5V
MONITOR
138k
100k
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
1V/DIV
3.3V
IN
SD1
RUN/SS
DC/DC
REMOTE
STATUS
FB1
FB = 1.235V OUT
1.8V
V
V
IN
SLAVE1
10k
10k
2925 TA02a
16.5k
35.7k
10ms/DIV
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
IN
FB2
OUT
2.5V
SLAVE2
FAULT
RAMPBUF
3.3V
1.65k
13k
88.7k
41.2k
2.5V
1.8V
1.5V
1V/DIV
TRACK1
TRACK2
3.3V
IN
88.7k
41.2k
SD3
RUN/SS
DC/DC
FB = 0.8V
86.6k
100k
FB3
OUT
1.5V
SLAVE3
TRACK3
GND SCTMR
SDTMR
0.082μF
PGTMR
0.82μF
86.6k
2925 TA02b
100k
10ms/DIV
0.47μF
2925 TA01
2925fc
1
LTC2925
(Notes 1, 2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ................................. –0.3V to 10V
GATE (Note 3)..................................... –0.3V to 11.5V
Average Current
TRACK1, TRACK2, TRACK3.................................5mA
FB1, FB2, FB3 ......................................................5mA
Operating Temperature Range
CC
Input Voltages
ON, PGI, SENSEP, SENSEN ................... –0.3V to 10V
TRACK1, TRACK2, TRACK3.........–0.3V to V + 0.3V
CC
SCTMR, SDTMR, PGTMR............–0.3V to V + 0.3V
CC
Output Voltages
LTC2925C ................................................ 0°C to 70°C
LTC2925I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FAULT, SD1, SD2, SD3,
FB1, FB2, FB3, STATUS.......................... –0.3V to 10V
RAMPBUF, REMOTE.....................–0.3V to V + 0.3V
CC
CC
RAMP .............................................–0.3V to V + 1V
MS Package...................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
SCTMR
PGTMR
PGI
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
SENSEP
SENSEN
ON
24 23 22 21 20 19
3
ON
SDTMR
SD1
1
2
3
4
5
6
18 STATUS
4
STATUS
FAULT
GATE
FAULT
17
16
5
SDTMR
SD1
GATE
25
6
SD2
15 RAMP
7
RAMP
REMOTE
FB1
SD2
SD3
REMOTE
14
8
SD3
RAMPBUF
13 FB1
9
RAMPBUF
GND
7
8
9 10 11 12
10
11
12
TRACK1
TRACK2
FB2
FB3
TRACK3
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
EXPOSED PAD (PIN 25) INTERNALLY CONNECTED
TO GND (PCB CONNECTION OPTIONAL)
T
= 125°C, θ = 85°C/W
JA
JMAX
T
= 125°C, θ = 37°C/W
JA
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC2925CGN#PBF
LTC2925IGN#PBF
LTC2925CUF#PBF
LTC2925IUF#PBF
LEAD BASED FINISH
LTC2925CGN
TAPE AND REEL
PART MARKING*
LTC2925CGN
LTC2925IGN
2925
PACKAGE DESCRIPTION
24-Lead Plastic SSOP
24-Lead Plastic SSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
PACKAGE DESCRIPTION
24-Lead Plastic SSOP
24-Lead Plastic SSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
LTC2925CGN#TRPBF
LTC2925IGN#TRPBF
LTC2925CUF#TRPBF
LTC2925IUF#TRPBF
TAPE AND REEL
2925
PART MARKING*
LTC2925CGN
LTC2925IGN
2925
LTC2925CGN#TR
LTC2925IGN#TR
LTC2925IGN
LTC2925CUF
LTC2925IUF
LTC2925CUF#TR
LTC2925IUF #TR
2925
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2925fc
2
LTC2925
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
3
UNITS
V
l
l
l
V
Input Supply Range
Input Supply Current
2.9
CC
I
CC
I
= 0, I
= 0, I = 0
RAMPBUF
1.5
mA
mA
FBx
TRACKx
I
I
= –1mA, I
RAMPBUF
= –1mA,
10.5
15
FBx
TRACKx
= –3mA
l
V
Input Supply Undervoltage Lockout
V
Rising
CC
2.3
2.5
25
2.7
V
mV
V
CC(UVL)
Input Supply Undervoltage Lockout Hysteresis
ΔV
ΔV
CC(UVL, HYST)
l
l
l
l
External N-Channel Gate Drive (V
GATE Pin Current
– V
)
CC
I
= –1μA
5
–7
7
5.5
–10
10
6
GATE
GATE
GATE
I
Gate On, V
Gate Off, V
Gate Off, V
= 0V, No Faults
= 5V, No Faults
–13
13
μA
μA
mA
GATE
GATE
GATE
GATE
= 5V, Short-Circuit or
5
20
50
Power Good Timeout
l
l
l
l
V
ON Pin Threshold Voltage
ON Pin Hysteresis
V
Rising
1.214
30
1.232
75
1.250
150
0.5
V
mV
V
ON(TH)
ON
ΔV
ON(HYST)
V
ON Pin Fault Clear Threshold Voltage
ON Pin Input Current
0.3
0.4
0
ON(FC)
I
V
ON
= 1.2V, V = 5.5V
100
nA
ON(IN)
CC
l
l
ΔV
Sense Resistor Overcurrent Voltage Threshold 1V < V
< V
CC
40
30
50
50
60
70
mV
mV
RS-SENSE(TH)
SENSEP
< 1V
SENSEP
(V
– V
)
SENSEN
0V < V
0V < V
0V < V
SENSEP
l
l
l
l
l
l
l
l
l
I
I
SENSEN Pin Input Current
SENSEP Pin Input Current
< V
< V
–1
–1
5
5
10
10
μA
μA
mV
V
SENSEN
SENSEP
SENSEN
SENSEP
CC
CC
V
V
V
V
Ramp Buffer Offset (V
– V
)
V
= V /2, I = 0A
RAMPBUF
–30
0
30
OS
RAMPBUF
RAMP
RAMPBUF
CC
FAULT Output Low Voltage
SDx Output Low Voltage
STATUS Output Low Voltage
RAMP Pin Input Current
RAMPBUF Low Voltage
I
I
I
= 3mA
0.2
0.2
0.2
0
0.4
0.4
0.4
1
FAULT(OL)
SDx(OL)
STATUS(OL)
RAMP
FAULT
= 1mA, V = 2.3
V
SDx
CC
= 3mA
V
STATUS
I
0V < RAMP < V , V = 5.5V
μA
mV
mV
CC CC
V
V
I
I
= 3mA
90
100
150
200
RAMPBUF(OL)
RAMPBUF(OH)
ERROR(%)
RAMPBUF
RAMPBUF
RAMPBUF High Voltage (V – V
)
RAMPBUF
= –3mA
CC
l
l
I
I
I
to I
ERROR(%)
Current Mismatch
FBx
I
I
= –10μA
= –1mA
0
0
5
5
%
%
FBx
TRACKx
TRACKx
TRACKx
= (I – I
)/I
TRACKx TRACKx
l
l
V
TRACK Pin Voltage
I
I
= –10μA
= –1mA
0.78
0.78
0.8
0.8
0.82
0.82
V
V
TRACKx
TRACKx
TRACKx
l
l
l
l
l
l
l
l
l
l
l
l
I
I
Leakage Current
Clamp Voltage
V
= 1.5V, V = 5.5V
10
2.5
30
nA
V
FB(LEAK)
FB
FB
CC
V
V
1μA < I < 1mA
1.6
2.1
15
FB(CLAMP)
FB
FB
R
REMOTE Feedback Switch Resistance
Short-Circuit Timer Pull-Up Current
Short-Circuit Timer Pull-Down Current
Short-Circuit Timer Threshold Voltage
Shutdown Timer Pull-Up Current
2V < V
< V
CC
Ω
μA
μA
V
REMOTE
REMOTE
I
I
V
V
= 1V
= 1V
–35
1
–50
2
–65
3
SCTMR(UP)
SCTMR(DN)
SCTMR
SCTMR
V
1.1
–7
1.23
–10
1.23
–10
1.4
–13
1.4
–15
1.4
–14
1.4
SCTMR(TH)
SDTMR(UP)
I
V
V
V
= 1V
μA
V
SDTMR
V
Shutdown Timer Threshold Voltage
Power Good Input Pull-Up Current
Power Good Input Threshold Voltage
Power Good Timer Pull-Up Current
Power Good Timer Threshold Voltage
1.1
–5
SDTMR(TH)
PGI(UP)
I
= 0V
μA
V
PGI
V
0.8
–8
PGI(TH)
I
= 1V
–10
μA
V
PGTMR(UP)
PGTMR
V
1.1
1.23
PGTMR(TH)
2925fc
3
LTC2925
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into the device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 3: The GATE pin is internally limited to a minimum of 11.5V. Driving
this pin to voltages beyond the clamp may damage the part.
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at TA = 25°C
ICC vs VCC
VGATE vs VCC
VGATE vs IGATE
12
11
10
9
15
10
5
12
10
8
I
= I = 1mA
RAMPBUF
TRACKx FBx
V
V
= 5.5V
= 2.9V
CC
I
= 3mA
CC
6
4
I
= I = 0mA
TRACKx FBx
I
= 0mA
RAMPBUF
2
8
0
0
2
3
4
5
6
0
5
10
2.5
3.5
4
4.5
5
5.5
3
15
V
(V)
I
(μA)
GATE
V
(V)
CC
CC
2925 G02
2925 G03
2925 G01
IGATE Fast Pull-Down vs
Temperature
VRAMPBUF(OL) vs Temperature
VRAMPBUF(OH) vs Temperature
50
45
40
35
30
25
110
100
90
70
65
60
55
50
45
40
35
30
V
= 5V
GATE
V
= 2.9V
CC
V
= 2.9V
CC
80
V
= 5.5V
CC
70
V
= 2.9V
CC
V
= 5.5V
60
CC
V
= 5.5V
CC
50
40
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
–50
–25
0
25
50
75
100
–25
0
50
–50
75
100
25
TEMPERATURE (°C)
TEMPERATURE (°C)
2925 G06
2925 G04
2925 G05
2925fc
4
LTC2925
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at TA = 25°C
V
SDx(OL) vs VCC
VTRACK vs Temperature
Tracking Cell Error vs ITRACKx
1.0
0.8
0.6
0.4
0.805
0.800
0.795
0.790
5
4
3
V
= 5.5V
CC
I
= 10μA
TRACKx
V
= 5.5V
= 1mA
CC
TRACKx
I
V
= 2.9V
CC
I
= 1mA
TRACKx
2
1
0
V
= 2.9V
I
= 5mA
CC
SDx
I
= 10μA
TRACKx
0.2
0
I
= 10μA
3
SDx
0
2
4
5
–50
–25
0
25
50
75
100
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
(V)
TEMPERATURE (°C)
I
(mA)
CC
TRACKx
2925 G07
2925 G08
2925 G09
PIN FUNCTIONS GN/UF Packages
divider connected to V drives the ON pin, the supplies will
V
(Pin 1/Pin 22): Positive Supply Input. The operating
CC
CC
automatically start up when V is fully powered.
supplyinputrangeis2.9Vto5.5V.Anundervoltagelockout
CC
circuit resets the part when the supply is below 2.5V. V
should be bypassed to GND with a 0.1μF capacitor.
CC
SDTMR (Pin 5/Pin 2): Shutdown Timer. A capacitor from
SDTMR to GND sets the delay time between the ON pin tran-
sitioninghigh(whichreleasestheSDxpins)andthesupplies
beginning to ramp-up. Float SDTMR when it is unused.
SENSEP (Pin 2/Pin 23): Circuit Breaker Positive Sense
Input. SENSEP and SENSEN measure the voltage across
the sense resistor and trigger the circuit breaker function
when the current exceeds the level programmed by the
senseresistorforlongerthanashort-circuittimercycle(see
SD1, SD2, SD3 (Pins 6, 7, 8/Pins 3, 4, 5): Outputs for
Slave Supply Shutdowns. The SDx pins are open-drain
outputsthatholdtheshutdown(RUN/SS)pinsoftheslave
supplies low until the ON pin is pulled above 1.23V. The
SDxpinswillbepulledlowagainwhenRAMP<100mVand
ON <1.23V. If a slave supply is capable of operating with
an input supply that is lower than the LTC2925’s minimum
operating voltage of 2.9V, the SDx pins can be used to hold
off the slave supplies. Each SDx pin is capable of sinking
greater than 1mA with supplies as low as 2.3V.
SCTMR). If unused, tie SENSEN and SENSEP to V .
CC
SENSEN (Pin 3/Pin 24): Circuit Breaker Negative Sense
Input. SENSEN connects to the low side of the current
sense resistor. SENSEP and SENSEN monitor the current
through the external FET by measuring the voltage across
the sense resistor. The circuit breaker turns off the FET
when the sense voltage exceeds 50mV for longer than a
short circuit timer cycle (see SCTMR). If the short-circuit
timer times out, the GATE pin will be pulled low im-
mediately to protect the FET. If unused, tie SENSEN and
RAMPBUF (Pin 9/Pin 6): Ramp Buffer Output. Provides a
lowimpedancebufferedversionofthesignalontheRAMP
pin. This buffered output drives the resistive dividers that
connect to the TRACKx pins. Limit the capacitance at the
RAMPBUF pin to less than 100pF.
SENSEP to V .
CC
ON (Pin 4/Pin 1): On Control Input. The ON pin has a
threshold of 1.23V with 75mV of hysteresis. An active high
will cause 10μA to flow from the GATE pin, ramping up the
supplies.Anactivelowpulls10μAfromtheGATEpin,ramp-
ing the supplies down. Pulling the ON pin below 0.4V resets
the electronic circuit breaker in the LTC2925. If a resistive
GND (Pin 10/Pins 7, 25): Circuit Ground.
TRACK1,TRACK2,TRACK3(Pins15,14,12/Pins12,11,
9): Tracking Control Input Pin. A resistive divider between
RAMPBUF, TRACKx and GND determines the tracking
2925fc
5
LTC2925
PIN FUNCTIONS GN/UF Packages
GATE (Pin 19/Pin 16): Gate Drive for External N-Channel
FET. When the ON pin is high, an internal 10μA current
sourcechargesthegateoftheexternalN-channelMOSFET.
A capacitor connected from GATE to GND sets the ramp
rate. It is a good practice to add a 10Ω resistor between
this capacitor and the FET’s gate to prevent high frequency
FET oscillations. An internal charge pump guarantees that
profile of OUTx (see Applications Information). TRACKx
pulls up to 0.8V and the current supplied at TRACKx is
mirrored at FBx. The TRACKx pin is capable of supply-
ing at least 1mA when VCC = 2.9V. It may be capable of
supplying up to 30mA when the supply is at 5.5V, so care
should be taken not to short this pin for extended periods.
Limit the capacitance at the TRACKx pin to less than 25pF.
Float the TRACKx pins if unused.
GATE will pull up to 5V above V ensuring that logic-level
CC
N-channel FETs are fully enhanced. When the ON pin is
pulled low, the GATE pin is pulled to GND with a 10μA
current source. Under a short-circuit condition, the elec-
tronic circuit breaker in the LTC2925 pulls the GATE low
immediately with 20mA. Tie GATE to GND if unused.
FB1, FB2, FB3 (Pins 16, 13, 11/Pins 13, 10, 8): Feed-
back Control Output. FBx connects to the feedback node
of slave supplies. Tracking is achieved by mirroring the
current from TRACKx into FBx. If the appropriate resistive
divider connects RAMPBUF and TRACKx, the FBx current
will force OUTx to track RAMP. The LTC2925 is capable of
controllingslavesupplieswithfeedbackvoltagesbetween
0V and 1.6V. To prevent damage to the slave supply, the
FBx pin will not force the slave’s feedback node above
2.5V. In addition, it will not actively sink current from this
node even when the LTC2925 is unpowered. Float the FBx
pins if unused.
FAULT (Pin 20/Pin 17): Circuit Breaker and Power Good
Timer Fault Output. FAULT is an open-drain output that
pullslowwhentheelectroniccircuitbreakerisactivatedor
a power good timeout fault is detected. FAULT is reset by
pulling ON below 0.4V. To allow retry, tie FAULT to ON.
STATUS(Pin21/Pin18):PowerGoodStatusIndicator.The
STATUS pin is an open-drain output that pulls low until
GATE has been fully charged at which time all supplies
will have reached their final operating voltage.
REMOTE (Pin 17/Pin 14): Remote Sense Switch. A 15Ω
switch connects REMOTE to RAMP when the GATE is fully
enhanced (GATE > RAMP + 4.9V). Otherwise, it presents
a high impedance. When the slave supplies track the
master supply, REMOTE can be used to compensate for
the voltage drop across the external sense resistor and
N-channelFET.Aresistorbetweentheoutputandthesense
nodes of the master supply provides feedback before the
external FET is fully enhanced. If an external FET is not
used, float REMOTE.
PGI (Pin 22/Pin 19): Power Good Timer Input. PGI con-
nects to the RST pin of the downstream supply monitor.
If PGI has not transitioned high within a power good timer
cycle (see PGTMR), the FAULT pin will be pulled low and
the supplies will be turned off by pulling the GATE pin
low with 20mA. PGI is pulled up with 10μA. An internal
Schottky diode allows PGI to be pulled safely above V .
CC
Float PGI when it is unused.
RAMP(Pin18/Pin15):RampBufferInput.WhentheRAMP
pin is connected to the source of the external N-channel
FET, the slave supplies track the FET’s source as it ramps
up and down. Alternatively, when no external FET is used,
the RAMP pin can be tied directly to the GATE pin. In this
configuration,thesuppliestrackthecapacitorontheGATE
pin as it is charged and discharged by the 10μA current
source controlled by the ON pin. When the GATE is fully
enhanced (GATE > RAMP + 4.9V) the open-drain STATUS
pin goes high impedance and the remote sense switch
connects the RAMP pin to the REMOTE pin.
PGTMR (Pin 23/Pin 20): Power Good Timer. A capacitor
from PGTMR to GND sets the power good timer duration.
While ON > 1.23V, the PGTMR pin will pull up to V with
CC
10μA. Otherwise, it pulls to GND. If the voltage on the
PGTMR pin exceeds 1.23V and PGI is still low, FAULT will
be pulled low and the GATE will be pulled to ground with
20mA until the power good timer fault is cleared by pull-
ing ON below 0.4V. If FAULT is tied back to ON the system
will automatically retry after a FAULT. In this mode, verify
that the slave supplies’ current limits provide sufficient
protection under short-circuit conditions. Tie PGTMR to
GND when it is unused.
2925fc
6
LTC2925
PIN FUNCTIONS GN/UF Packages
SCTMR(Pin24/Pin21):CircuitBreakerTimer. Acapacitor
from SCTMR to GND programs the maximum time that a
short circuit can be sustained before GATE is pulled low.
When (SENSEP – SENSEN) > 50mV, SCTMR will pull up
with 50μA, otherwise it pulls down with 2μA. When the
voltage at SCTMR exceeds 1.23V, the GATE will be pulled
to ground with 20mA and the FAULT pin will be pulled low.
The circuit breaker function is reset by pulling ON below
0.4V. The GATE pin will not rise again until SCTMR has
been pulled below 100mV by the 2μA current source. If
FAULT is tied back to ON the system will automatically
retry after a fault. Tie SCTMR to GND if the circuit breaker
is not used.
BLOCK DIAGRAM Pin numbers in parentheses are for the UF package.
(22)
1
V
CC
V
CC
FB3
FB2
FB1
TRACK3
TRACK2
TRACK1
11 (8)
(9) 12
(11) 14
(12) 15
0.8V
+
–
13 (10)
16 (13)
V
CC
SENSEP > SENSEN + 50mV
SENSEP
50μA
2μA
(23)
(24)
2
3
SCTMR
(21) 24
50mV
SENSEN
FAULT
(17)
20
+
–
1.2V
1.2V
GATE
PGI
(16)
19
(19) 22
(20) 23
V
CC
CHARGE
PUMP
–
+
10μA
PGTMR
10μA
–
+
1.2V
ONSIG
10μA
SCTMR
0.1V
–
+
S
R
Q
V
CC
+
–
0.4V
10μA
S
R
Q
ON
SDTMR
(1)
4
(2)
5
+
–
SDx
1.2V
+
–
0.1V
V
–
+
CC
2.6V
RAMP
RAMPBUF
(15)
(6)
1×
18
9
REMOTE
STATUS
+
–
(14) 17
(18) 21
V
CC
4.9V
GATE
GATE > RAMP + 4.9V
GND
2925 FBD
10
(7, 25)
2925fc
7
LTC2925
APPLICATIONS INFORMATION
Power Supply Tracking and Sequencing
Certain applications require one supply to come up after
another.Forexample,asystemclockmayneedtostartbefore
a block of logic. In this case, the supplies are sequenced
as in Figure 4 where the 1.8V supply ramps up completely
followed by the 2.5V supply and then the 1.5V supply.
The LTC2925 handles a variety of power-up profiles to
satisfy the requirements of digital logic circuits including
FPGAs, PLDs, DSPs and microprocessors. These require-
mentsfallintooneofthefourgeneralcategoriesillustrated
in Figures 1 to 4.
Operation
Some applications require that the potential difference
between two power supplies must never exceed a speci-
fied voltage. This requirement applies during power-up
and power-down as well as during steady-state operation,
often to prevent destructive latch-up in a dual supply IC.
Typically, this is achieved by ramping the supplies up and
down together (Figure 1). In other applications it is desir-
able to have the supplies ramp up and down with fixed
voltage offsets between them (Figure 2) or to have them
ramp up and down ratiometrically (Figure 3).
The LTC2925 provides a simple solution to all of the power
supply tracking and sequencing profiles shown in Figures
1 to 4. A single LTC2925 controls up to four supplies with
three “slave” supplies that track a “master” signal. With
just two resistors, a slave supply is configured to ramp up
as a function of the master signal. This master signal can
be a fourth supply that is ramped up through an external
FET, whose ramp rate is set with a single capacitor, or it
can be a signal generated by tying the GATE and RAMP
pins to an external capacitor.
MASTER
SLAVE1
SLAVE2
SLAVE3
MASTER
SLAVE1
SLAVE2
SLAVE3
1V/DIV
1V/DIV
2925 F01
2925 F02
10ms/DIV
10ms/DIV
Figure 1. Coincident Tracking
Figure 2. Offset Tracking
MASTER
SLAVE1
SLAVE2
SLAVE3
SLAVE1
SLAVE2
SLAVE3
2V/DIV
2V/DIV
2925 F03
2925 F04
10ms/DIV
10ms/DIV
Figure 3. Ratiometric Tracking
Figure 4. Supply Sequencing
2925fc
8
LTC2925
APPLICATIONS INFORMATION
Tracking Cell
In a properly designed system, when the master signal
has reached its maximum voltage the current from the
TRACK1 pin is zero. In this case, there is no current from
the FB1 pin and the LTC2925 has no effect on the output
voltage accuracy, transient response or stability of the
slave supply.
The LTC2925’s operation is based on the tracking cell
shown in Figure 5, which uses a proprietary wide-range
current mirror. The tracking cell shown in Figure 5 servos
the TRACK pin at 0.8V. The current supplied by the TRACK
pin is mirrored at the FB pin to establish a voltage at the
output of the slave supply. The slave output voltage varies
with the master signal, enabling the slave supply to be
controlled as a function of the master signal with terms
set by R and R . By selecting appropriate values of
When the ON pin falls below V
– ΔV
, typi-
ON(HYST)
ON(TH)
cally 1.225V, the GATE pin pulls down with 10μA and the
master signal and the slave supplies will fall at the same
rate as they rose previously.
TA
TB
R
TA
and R , it is possible to generate any of the profiles
TB
The ON pin can be controlled by a digital I/O pin or it
can be used to monitor an input supply. By connecting a
resistive divider from an input supply to the ON pin, the
supplies will ramp up only after the monitored supply has
reached a preset voltage.
in Figures 1 to 4.
V
CC
V
+
–
CC
+
MASTER
0.8V
–
R
TB
DC/DC
SENSEP – SENSEN > 50mV
FB
TRACK
FB OUT
SLAVE
50μA
2μA
SENSEP
R
TA
SCTMR
R
50mV
FB
R
FA
SENSEN
2925 F05
Figure 5. Simplified Tracking Cell
+
–
Controlling the Ramp-Up and Ramp-Down Behavior
1.2V
ON
R
R
ONB
ONA
TheoperationoftheLTC2925ismosteasilyunderstoodby
referring to the simplified functional diagram in Figure 6.
When the ON pin is low, the GATE pin is pulled to ground
causing the master signal to remain low. Since the current
10μA
10μA
+
–
GATE
Q1
1.2V
C
GATE
through R is at its maximum when the master signal is
RAMP
RAMPBUF
TB1
1s
MASTER
V
CC
low, the current from FB1 is also at its maximum. This cur-
rent drives the slave’s output to its minimum voltage.
WhentheONpinrisesabove1.23V, themastersignalrises
and the slave supply tracks the master signal. The ramp
rateissetbyanexternalcapacitordrivenbya10μAcurrent
source from an internal charge pump. If no external FET
is used, the ramp rate is set by tying the RAMP and GATE
pins together at one terminal of the external capacitor (see
the Ratiometric Tracking Example).
0.8V
+
–
R
R
TB1
TA1
FB1
TRACK1
SLAVE1
DC/DC
R
FB1
R
FA1
2925 F06
Figure 6. Simplified Functional Block Diagram
2925fc
9
LTC2925
APPLICATIONS INFORMATION
Optional External FET
The short-circuit timer duration is configured by a capaci-
tor tied between SCTMR and GND. SCTMR will pull up
with 50μA when SENSEP – SENSEN > 50mV. Otherwise, it
pulls down with 2μA. When the voltage at SCTMR exceeds
1.23V,theGATEwillbepulledtogroundwith20mAandthe
Figure 7 illustrates how an optional external N-channel
FET can ramp up a single supply that becomes the mas-
ter signal. When used, the FET’s gate is tied to the GATE
pin and its source is tied to the RAMP pin. Under normal
operation, the GATE pin sources or sinks 10μA to ramp
the FET’s gate up or down at a rate set by the external
capacitor connected to the GATE pin.
FAULT pin will be pulled low. Thus, the capacitor, C
,
SCTMR
required to configure the short-circuit timer duration,
t
is determined from:
SCTMR
50μA • tSCTMR
The series FET easily controls any supply with an output
CSCTMR
=
1.23V
voltage between 0V and V . See the Typical Applications
CC
section for examples.
Because the slave supplies track the RAMP pin which is
driven by the external FET, they are pulled low by the track-
ing circuit when a short-circuit fault occurs. Following a
short-circuitfault,theFETislatchedoffandFAULT ispulled
low until the fault is cleared by pulling the ON pin below
0.4V. Note that the supplies will not be allowed to ramp up
againuntilSCTMRhasbeenpulledbelowabout100mVby
the 2μA pull-down current source. The electronic circuit
R
Q1
SENSE
V
IN
MASTER
0.1μF
C
GATE
10Ω
SUPPLY
MONITOR
R
R
ONB
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
3.3V
IN
ONA
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
V
V
IN
IN
SLAVE1
breaker supports any supply voltage between 0V and V .
CC
10k
10k
R
FB1
Although it is normally used to monitor current through
the optional series FET, it is capable of monitoring other
currents, including the current from a slave supply. The
Typical Applications section shows one such example.
R
FA1
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
FB2
OUT
2.5V
SLAVE2
FAULT
RAMPBUF
R
R
TB1
R
FB2
R
FA2
If the electronic circuit breaker is not used, tie SENSEP
TRACK1
TRACK2
3.3V
IN
R
TB2
and SENSEN to V and SCTMR to GND.
TA1
CC
SD3
RUN/SS
DC/DC
FB = 0.8V
R
R
TB3
TA2
FB3
OUT
1.5V
SLAVE3
TRACK3
Power Good Timeout
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
C
C
C
PGTMR
SCTMR
SDTMR
R
FA3
The power good timeout circuit turns off the supplies if an
external supply monitor, connected to the PGI pin, fails to
indicate that all supplies have entered regulation in time
after power up begins. After power up is complete, it turns
off the supplies if any supply exits regulation.
2925 F07
Figure 7. Typical Application with External FET
Electronic Circuit Breaker
The power good timer duration is configured by a capaci-
tor tied between PGTMR and GND. PGTMR will pull up
the CPGTMR capacitor with 10μA starting when the ON
pin is driven above 1.23V. Once the voltage at the PGTMR
exceeds 1.23V, a fault will trip if the PGI pin is low. When
the power good timeout circuit detects a fault, the GATE
TheLTC2925featuresanelectroniccircuitbreakerfunction
that protects the optional series FET against short circuits.
An external sense resistor is used to measure the current
flowing in the FET. If the voltage across the sense resistor
exceeds50mVformorethanashort-circuittimercycle,the
gate of the FET is pulled low with 20mA, turning it off.
2925fc
10
LTC2925
APPLICATIONS INFORMATION
V
IN
C
0.1μF
GATE
pin is pulled low, the supplies are latched off, and the
FAULT pin is held low until the fault is cleared by taking
the ON pin below 0.4V.
SUPPLY
MONITOR
V
SENSEP SENSEN GATE
RAMP
R
R
CC
ONB
ONA
RST
ON
V
PGI
IN
ThePGIpin, whichisnormallyconnectedtotheRSTpinof
SD1
RUN/SS
DC/DC
IN
anexternalsupplymonitor, ispulledupwith10μAthrough
REMOTE
STATUS
FB1
FB
OUT
SLAVE1
V
V
IN
a Schottky diode allowing it to be pulled safely above V .
CC
R
FB1
Since, PGTMR pulls up with a 10μA current source, the
R
FA1
V
IN
IN
OUT
IN
capacitor, C
, required to configure the power good
PGTMR
PGTMR
timeout duration, t
LTC2925
SD2
RUN/SS
DC/DC
, is determined from:
FB2
FB
SLAVE2
SLAVE3
FAULT
RAMPBUF
10μA • tPGTMR
1.23V
R
R
TB1
TA1
R
FB2
CPGTMR
=
R
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
SD3
RUN/SS
DC/DC
If the power good timeout circuit is unused, tie PGTMR
low and float PGI.
R
R
TB3
TA2
FB3
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
C
C
PGTMR
SDTMR
R
FA3
The Ramp Buffer
2925 F08
The RAMPBUF pin provides a buffered version of the
RAMP pin voltage that drives the resistive dividers on the
TRACKx pins. When there is no external FET, it provides
up to 3mA to drive the resistors even though the GATE
pin only supplies 10μA (Figure 8). The RAMPBUF pin
also proves useful in systems with an external FET. Since
Figure 8. Typical Application Without External FET
and 8). The SDx pins are released when the ON pin rises
above 1.23V, V is above the 2.6V undervoltage lockout
CC
condition, and there are no faults latched. The shutdown
timer begins at the same time, and the supplies begin to
ramp up after the shutdown timer cycle completes. The
duration of the timer cycle is configured by a capacitor
tied between SDTMR and GND. The capacitor voltage is
ramped up by a 10μA current source and the SDTMR
cycle completes when its voltage reaches 1.23V. Thus, the
the track cell drives 0.8V on the TRACKx pins, if R is
TBx
connected directly to the FET’s source, the TRACKx pin
could potentially pull up the FET’s source towards 0.8V
when the FET is off. RAMPBUF blocks this path.
Shutdown Outputs
capacitor, C
, required for a given shutdown timer
SDTMR
, is determined from:
In some applications it might be necessary to control
the shutdown or RUN/SS pins of the slave supplies. The
LTC2925maynotbeabletosupplytherated1mAofcurrent
cycle, t
SDTMR
10μA • tSDTMR
1.23V
CSDTMR
=
from the FB1, FB2, and FB3 pins when V is below 2.9V.
CC
If the slave power supplies are capable of operating at low
input voltages, use the open-drain SDx outputs to drive
the SHDN or RUN/SS pins of the slave supplies (Figures 7
The SDx pins pull low again when the ON pin is pulled
below 1.23V and the RAMP pin is below about 100mV.
2925fc
11
LTC2925
APPLICATIONS INFORMATION
Status Output
Retry on Fault
The STATUS pin provides an indication that the supplies
are finished ramping up. This pin is an open-drain output
that pulls low until the GATE has been fully charged.
Since the GATE pin drives the gate of the external FET, or
the RAMP pin directly when no FET is used, the supplies
are completely ramped up when the GATE pin is fully
charged. The STATUS pin will go low again when the
GATE pin is pulled low, either because of a short-circuit
fault, a power good timeout fault, or because the ON pin
has been pulled low.
TheLTC2925continuouslyattemptstorampuptheoutputs
after a fault if the FAULT pin is tied to the ON pin (Figure 9).
If a short-circuit fault occurs in this configuration, the
SCTMRpinrampsuptheC
capacitorwith50μAuntil
SCTMR
it reaches 1.23V. Then, GATE is pulled low turning off the
shorted FET. At the same time, the FAULT pin’s open-drain
output pulls ON low. The C
capacitor is pulled down
SCTMR
with 2μA until it reaches about 100mV. After the C
SCTMR
capacitor reaches 100mV, the shutdown timer begins and
uponcompletingashutdowntimercycle,thesuppliesstart
ramping up again. If there is no short-circuit this time, the
supplies will come up normally. Otherwise the retry cycle
will repeat. If a longer off time is required between retry
Fault Output
The FAULT pin is an open-drain output that pulls low
when the electronic circuit breaker is activated due to a
short-circuit or power good timeout fault. FAULT is reset
by pulling ON below 0.4V. The supplies will not be allowed
to ramp up again until the SCTMR, PGTMR and SDTMR
pins are below about 100mV, and the ON pin is pulled
above 1.23V.
attempts, the C
capacitor value can be increased,
SDTMR
providing a greater delay before the FET’s GATE ramps up
on each cycle. Note that tying FAULT to ON also causes the
LTC2925 to retry on Power Good Timeout faults. In this
mode, verify that the slave supplies’ current limits provide
sufficient protection under short-circuit conditions.
R
SENSE
Q1
V
IN
MASTER
0.1μF
C
GATE
10Ω
SUPPLY
MONITOR
R
R
ONB
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
V
IN
IN
OUT
ONA
SD1
RUN/SS
DC/DC
REMOTE
STATUS
FB1
FB
SLAVE1
V
IN
10k
R
FB1
R
FA1
V
IN
IN
OUT
LTC2925
SD2
RUN/SS
DC/DC
SLAVE2
SLAVE3
FB2
FB
FAULT
RAMPBUF
R
R
TB1
TA1
R
FB2
R
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
SD3
RUN/SS
DC/DC
R
R
TB3
TA2
FB3
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
C
C
C
PGTMR
SCTMR
SDTMR
R
FA3
2925 F09
Figure 9. Retry on Fault
2925fc
12
LTC2925
APPLICATIONS INFORMATION
3-Step Design Procedure
Choose a ramp rate for the slave supply, S . If the slave
S
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish ramping
beforethemastersupplyhasreacheditsfinalsupplyvalue.
If not, the slave supply will be held below the intended
regulation value by the master supply. Use the following
formulas to determine the resistor values for the desired
Thefollowing3-stepdesignprocedureallowsonetochoose
theTRACKresistors,R andR ,andthegatecapacitor,
TAx
TBx
C
GATE
, that give any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic four supply application
circuit is shown in Figure 10.
1. Set the ramp rate of the master signal.
Solve for the value of C , the capacitor on the GATE
GATE
ramp rate, where R and R are the feedback resistors in
FB
FA
pin, based on the desired ramp rate (V/s) of the master
supply, S :
the slave supply and V is the feedback reference voltage
FB
M
of the slave supply:
IGATE
SM
CGATE
=
whereIGATE ≈ 10μA
(1)
SM
SS
RTB = RFB •
(2)
(3)
If the external FET has a gate capacitance comparable to
VTRACK
C
,thentheexternalcapacitor’svalueshouldbereduced
GATE
RTA ′ =
V
V
FB
RFB RFA
VTRACK
RTB
to compensate for the FET’s gate capacitance.
FB
+
–
If no external FET is used, tie the GATE and RAMP pins
where V
≈ 0.8V.
together, connect SENSEN and SENSEP to V , and con-
TRACK
CC
nect SCTMR to GND.
Note that large ratios of slave ramp rate to master ramp
rate, S /S , may result in negative values for R ´. If a
2. Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
S
M
TA
sufficiently large delay is used in step 3, R will be posi-
TA
tive, otherwise S /S must be reduced.
S
M
R
Q1
SENSE
V
IN
MASTER
3. Choose R to obtain the desired delay.
TA
0.1μF
C
GATE
10Ω
If no delay is required, such as in coincident and ratio-
SUPPLY
MONITOR
metric tracking, then simply set R = R ´. If a delay
TA
TA
R
ONB
138k
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
is desired, as in offset tracking and supply sequencing,
V
IN
IN
OUT
R
ONA
calculate R ´´ to determine the value of R where t is
100k
TA
TA
D
SD1
RUN/SS
DC/DC
the desired delay.
REMOTE
STATUS
FB1
FB
SLAVE1
V
V
IN
IN
VTRACK •RTB
10k
10k
R
FB1
RTA ′′ =
(4)
(5)
R
FA1
V
tD • SM
IN
LTC2925
SD2
RUN/SS
IN
DC/DC
RTA = RTA ′ ||RTA ′′
FB2
FB
OUT
SLAVE2
SLAVE3
FAULT
RAMPBUF
R
R
TB1
R
the parallel combination of R ´ and R ´´.
FB2
R
TA
TA
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
TA1
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in se-
quencing) may result in solutions with negative values for
SD3
RUN/SS
DC/DC
R
R
TB3
TA2
FB3
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
R . In such cases, either the delay must be increased or
R
FA3
TA
the ratio of slave ramp rate to master ramp rate must be
2925 F10
reduced.
Figure 10. Four Supply Application
2925fc
13
LTC2925
APPLICATIONS INFORMATION
MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
2925 F11
10ms/DIV
10ms/DIV
Figure 11. Coincident Tracking from Figure 12
Coincident Tracking Example
In this example, all supplies remain low while the ON pin
is held below 1.23V. When the ON pin rises above 1.23V,
10μA pulls up CGATE and the gate of the FET at 100V/s.
As the gate of the FET rises, the source follows and pulls
up the output to 3.3V at 100V/s. This output serves as
the master signal and is buffered from the RAMP pin
to the RAMPBUF pin. As this output and the RAMPBUF
pin rise, the current from the TRACKx pins is reduced.
Consequently, the voltages at the slave supplies’ outputs
increase, and the slave supplies track the master supply.
When the ON pin is again pulled below 1.23V, 10μA will
A typical four supply application is shown in Figure 12.
The master signal is a 3.3V module. The slave 1 supply
is a 1.8V switching power supply, the slave 2 supply is a
2.5V switching power supply, and the slave 3 supply is
a 1.5V supply. All three slave supplies track coincidently
with the 3.3V supply that is controlled with an external
FET. The ramp rate of the supplies is 100V/s. The 3-step
design procedure detailed previously can be used to
determine component values. Only the slave 1 supply
is considered here as the procedure is the same for the
other supplies.
pull down C
and the gate of the FET at 100V/s. If the
GATE
loads on the outputs are sufficient, all outputs will track
1. Set the ramp rate of the master signal.
down coincidently at 100V/s.
Q1
From Equation 1:
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1μF
10μA
100V/s
C
GATE
0.1μF
10Ω
CGATE
=
= 0.1μF
SUPPLY
MONITOR
R
ONB
138k
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
From Equation 2:
FB1
1.8V
V
V
IN
IN
SLAVE1
10k
10k
R
R
FB1
16.5k
FA1
35.7k
100V/s
100V/s
RTB = 16.5k •
= 16.5k
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
FB2
OUT
2.5V
SLAVE2
From Equation 3:
FAULT
RAMPBUF
R
TB1
R
41.2k
R
FB2
88.7k
FA2
16.5k
0.8V
1.235V 1.235V 0.8V
TRACK1
TRACK2
RTA ′ =
≈ 13k
3.3V
IN
R
TB2
88.7k
R
TA1
13k
SD3
RUN/SS
DC/DC
FB = 0.8V
+
–
R
TB3
86.6k
R
41.2k
16.5k
3. Choose RTA to obtain the desired delay.
Since no delay is desired, R = R ´.
35.7k 16.5k
TA2
FB3
OUT
1.5V
SLAVE3
TRACK3
R
TA3
100k
GND SCTMR
SDTMR
PGTMR
R
86.6k
FB3
R
100k
FA3
C
C
C
SCTMR
0.47μF
SDTMR
0.082μF
PGTMR
0.82μF
TA
TA
2925 F12
Figure 12. Coincident Tracking Example
2925fc
14
LTC2925
APPLICATIONS INFORMATION
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
2925 F13
10ms/DIV
10ms/DIV
Figure 13. Ratiometric Tracking from Figure 14
From Equation 3:
Ratiometric Tracking Example
0.8V
1.235V 1.235V 0.8V
This example converts the coincident tracking example to
the ratiometric tracking profile shown in Figure 13, using
three supplies without an external FET. The ramp rate of
the master signal remains unchanged (step 1) and there
is no delay in ratiometric tracking (step 3), so only the
result of step 2 in the 3-step design procedure needs to
be considered. In this example, the ramp rate of the 1.8V
slave 1 supply ramps up at 60V/s, the 2.5V slave 2 supply
ramps up at 85V/s, and the 1.5V slave 3 supply ramps up
at 50V/s. Always verify that the chosen ramp rate will al-
low the supplies to ramp-up completely before RAMPBUF
RTA ′ =
≈ 10k
+
–
16.5k
35.7k 27.5k
Step 3 is unnecessary because there is no delay, so
R
= R ´.
TA
TA
3.3V V
IN
C
GATE
0.1μF
0.1μF
SUPPLY
MONITOR
R
ONB
138k
V
SENSEP SENSEN GATE
RAMP
CC
RST
ON
3.3V
IN
PGI
R
ONA
reaches V . If the 1.8V supply were to ramp-up at 50V/s
100k
CC
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
it would only reach 1.65V because the RAMPBUF signal
REMOTE
STATUS
FB1
1.8V
V
V
IN
IN
would reach its final value of V = 3.3V before the slave
SLAVE1
CC
10k
10k
R
FB1
16.5k
R
FA1
35.7k
supply reached 1.8V.
3.3V
IN
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
FB2
OUT
2.5V
SLAVE2
FAULT
RAMPBUF
R
TB1
27.4k
From Equation 2:
R
R
FB2
88.7k
FA2
41.2k
TRACK1
TRACK2
3.3V
IN
R
TB2
100k
R
TA1
10k
100V/s
60V/s
SD3
RUN/SS
DC/DC
FB = 0.8V
RTB = 16.5k •
≈ 27.4k
R
TB3
174k
R
TA2
38.3k
FB3
OUT
1.5V
SLAVE3
TRACK3
R
TA3
63.4k
GND SCTMR
SDTMR
C
PGTMR
C
R
FB3
86.6k
R
FA3
C
SCTMR
SDTMR
PGTMR
0.82μF
100k
0.41μF
0.082μF
2925 F14
Figure 14. Ratiometric Tracking Example
2925fc
15
LTC2925
APPLICATIONS INFORMATION
MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
2925 F15
10ms/DIV
10ms/DIV
Figure 15. Offset Tracking from Figure 16
Q1
Offset Tracking Example
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
Converting the circuit in the coincident tracking example
to the offset tracking shown in Figure 15 is relatively
simple. Here the 1.8V slave 1 supply ramps up 1V below
the master. The ramp rate remains the same (100V/s), so
there are no changes necessary to steps 1 and 2 of the
3-step design procedure. Only step 3 must be considered.
Be sure to verify that the chosen voltage offsets will allow
the slave supplies to ramp up completely. In this example,
if the voltage offset were 2V, the slave supply would only
ramp up to 3.3V – 2V = 1.3V.
0.1μF
C
GATE
0.1μF
10Ω
SUPPLY
MONITOR
R
ONB
138k
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
V
V
IN
IN
SLAVE1
10k
10k
R
FB1
16.5k
R
FA1
35.7k
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
FB2
OUT
2.5V
SLAVE2
FAULT
RAMPBUF
3. Choose R to obtain the desired delay.
TA
R
TB1
R
R
FB2
88.7k
FA2
16.5k
41.2k
TRACK1
TRACK2
First, convert the desired voltage offset, V , to a delay,
3.3V
IN
OS
R
TB2
88.7k
R
TA1
6.65k
t , using the ramp rate:
D
SD3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
86.6k
R
TA2
31.6k
FB3
OUT
1.5V
SLAVE3
TRACK3
VOS
SS 100V/s
1V
R
TA3
31.6k
tD =
=
= 10ms
(6)
GND SCTMR
SDTMR
PGTMR
R
FB3
86.6k
R
100k
FA3
C
C
C
SCTMR
0.41μF
SDTMR
0.082μF
PGTMR
0.82μF
2925 F16
From Equation 4:
0.8V •16.5k
1ms •100V/s
From Equation 5:
RTA = 13.1k ||13.2k ≈ 6.65k
Figure 16. Offset Tracking Example
″
RTA
=
= 13.2k
2925fc
16
LTC2925
APPLICATIONS INFORMATION
MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
2925 F17
10ms/DIV
10ms/DIV
Figure 17. Supply Sequencing from Figure 18
3. Choose R to obtain the desired delay.
Supply Sequencing Example
TA
From Equation 4:
In Figure 17, the three slave supplies are sequenced in-
stead of tracking. As in the coincident tracking example,
the 3.3V master supply ramps up at 100V/s through an
external FET, so step 1 remains the same. The 1.8V slave
1 supply ramps up at 1000V/s beginning 10ms after the
master signal starts to ramp up. The 2.5V slave 2 supply
ramps up at 1000V/s beginning 20ms after the master
signal begins to ramp up. The 1.5V slave 3 supply ramps
up at 1000V/s beginning 25ms after the master signal
begins to ramp up. Note that not every combination of
ramp rates and delays is possible. Small delays and large
ratios of slave ramp rate to master ramp rate may result
in solutions that require negative resistors. In such cases,
either the delay must be increased or the ratio of slave
ramp rate to master ramp rate must be reduced. In this
example, solving for the slave 1 supply yields:
0.8V •1.65k
10ms •100V/s
″
RTA
=
= 1.32k
From Equation 5:
RTA = –2.13k ||1.32k ≈ 3.48k
Q1
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1μF
C
GATE
0.1μF
10Ω
SUPPLY
MONITOR
R
ONB
138k
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
SLAVE1
V
V
IN
IN
10k
10k
R
FB1
16.5k
R
FA1
35.7k
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
From Equation 2:
2.5V
FB2
OUT
FAULT
RAMPBUF
SLAVE2
R
TB1
R
R
FA2
FB2
88.7k
1.65k
100V/s
1000V/s
41.2k
TRACK1
TRACK2
3.3V
IN
RTB = 16.5k •
≈ 1.65k
R
TB2
8.87k
R
TA1
3.48k
SD3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
8.66k
R
TA2
4.87k
FB3
OUT
1.5V
SLAVE3
From Equation 3:
TRACK3
R
TA3
3.74k
GND SCTMR
SDTMR
C
PGTMR
C
PGTMR
R
FB3
86.6k
R
FA3
C
0.8V
SCTMR
SDTMR
100k
0.41μF
0.082μF
0.82μF
RTA ′ =
≈ –2.13k
1.235V 1.235V 0.8V
2925 F18
+
–
16.5k
35.7k 1.65k
Figure 18. Supply Sequencing Example
2925fc
17
LTC2925
APPLICATIONS INFORMATION
Final Sanity Checks
Caution with Boost Regulators and Linear Regulators
The collection of equations below is useful for identifying
unrealizable solutions.
Note that the LTC2925’s tracking cell is not able to control
the outputs of all types of power supplies. If it is necessary
to control a supply, where the output is not controllable
through its feedback node, the series FET can be used to
controlitsoutput.Forexample,boostregulatorscommonly
contain an inductor and diode between the input supply
and the output supply providing a DC current path when
the output voltage falls below the input voltage. Therefore,
the LTC2925’s tracking cell will not effectively drive the
supply’s output below the input.
As stated in step 2, the slave supply must finish ramping
before the master signal has reached its final voltage. This
can be verified by the following equation:
⎛
⎝
⎞
RTB
RTA
VTRACK 1+
< V
MASTER
⎜
⎟
⎠
Here,V
=0.8V.V
isthefinalvoltageofthemas-
TRACK
MASTER
tersignal, eitherthesupplyvoltagerampedupthroughthe
Special caution should be taken when considering the use
of linear regulators. Three-terminal linear regulators have
a reference voltage that is referred to the output supply
rather than to ground. In this case, driving current into
the regulator’s feedback node will cause its output to rise
rather than fall. Even linear regulators that have their ref-
erence voltage referred to ground, including low-dropout
regulators (LDOs), may be problematic. Linear regulators
commonly contain circuitry that prevents driving their
outputs below their reference voltage. This may not be
obvious from the datasheets, so lab testing is recom-
mended whenever the LTC2925’s tracking cell is used to
control linear regulators.
optional external FET or V when no FET is present.
CC
It is possible to choose resistor values that require the
LTC2925 to supply more current than the Electrical Char-
acteristicstableguarantees. Toavoidthiscondition, check
that I
does not exceed 1mA and I
does not
TRACKx
exceed 3mA.
RAMPBUF
To confirm that I
< 1mA, the TRACKx pin(s) maxi-
TRACKx
mum guaranteed current, verify that:
VTRACK
< 1mA
RTA RTB
Finally, check that the RAMPBUF pin will not be forced to
sink more than 3mA when it is at 0V or be forced to source
more than 3mA when it is at V
.
MASTER
VTRACK VTRACK VTRACK
+
+
< 3mA and
VMASTER
RTB1
VMASTER
RTB2
RTB3
VMASTER
+
+
< 3mA
RTA1+RTB1 RTA2 +RTB2 RTA3 +RTB3
2925fc
18
LTC2925
APPLICATIONS INFORMATION
Load Requirements
Start-Up Delays
Often power supplies do not start-up immediatley when
their input supplies are applied. If the LTC2925 tries to
ramp-up these power supplies as soon as the input sup-
ply is present, the start-up of the outputs may be delayed
defeating the tracking circuit (Figure 20). Often this delay
is intentionally configured by a soft-start capacacitor. This
canberemediedeitherbyreducingthesoft-startcapacitor
on the slave supply or by increasing the shutdown timer
When the supplies are ramped down quickly, either the
loadorthesupplyitselfmustbecapableofsinkingenough
current to support the ramp rate. For example, if there
is a large output capacitance on the supply and a weak
resistive load, supplies that do not sink current will have
their falling ramp rate limited by the RC time constant of
the load and the output capacitance. Figure 19 shows the
case when the 2.5V supply does not track the 1.8V and
3.3V supplies near ground.
cycle configured by C
.
SDTMR
MASTER
SLAVE2
SLAVE1
1V/DIV
2925 F19
1ms/DIV
Figure 19. Weak Resistive Load
MASTER
SLAVE1
SLAVE2
1V/DIV
ON
2925 F20
1ms/DIV
Figure 20. Power Supply Start-Ups Delayed
2925fc
19
LTC2925
APPLICATIONS INFORMATION
Layout Considerations
This resistor is most effective if there is already a
capacitor at the feedback node of the slave supply (often
a compensation component). Increasing the capacitance
on a slave supply’s feedback node will further improve the
noise immunity, but could affect the stability and transient
response of the supply.
Be sure to place a 0.1μF bypass capacitor as near as pos-
sible to the supply pin of the LTC2925.
To minimize the noise on the slave supplies’ outputs,
keep the traces connecting the FBx pins of the LTC2925
and the feedback nodes of the slave supplies as short as
possible. In addition, do not route those traces next to
signals with fast transition times. In some circumstances
it might be advantageous to add a resistor near the feed-
back node of the slave supply in series with the FBx pin
of the LTC2925.
For proper circuit breaker operation, Kelvin-sense PCB
connectionsbetweenthesenseresistorandtheLTC2925’s
SENSEP and SENSEN pins are strongly recommended.
The drawing in Figure 22 illustrates the correct way of
making connections between the LTC2925 and the sense
resistor.PCBlayoutshouldbebalancedandsymmetricalto
minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
This resistor must not exceed:
⎛
⎞
1.6V – VFB
IMAX
1.6V
VFB
RSERIES
=
=
– 1 R ||R
(
FA
⎟
)
FB
⎜
⎝
⎠
Thepowerratingofthesenseresistorshouldaccommodate
steady-state fault current levels so that the component is
not damaged before the circuit breaker trips.
V
CC
LTC2925
R
DC/DC
FB OUT
SERIES
FB1
MINIMIZE
TRACE
LENGTH
GND
R
FB
R
FA
0.1μF
2925 F21
Figure 21. Layout Considerations
IRC-TT SENSE RESISTOR
LR251201R010F
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
OR EQUIVALENT
0.01Ω, 1%, 1W
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
2925 F22
TO TO
SENSEP SENSEN
Figure 22. Making PCB Connections to the Sense Resistor
2925fc
20
LTC2925
TYPICAL APPLICATION
External FET Controls 1V Supply
Q1
0.015Ω
Si4412ADY
1V
MASTER
0.1μF
C
GATE
0.1μF
10Ω
3.3V
SUPPLY
MONITOR
R
ONB
V
SENSEP SENSEN GATE
RAMP
PGI
CC
RST
138k
ON
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
SLAVE1
V
V
IN
IN
10k
10k
R
R
FB1
FA1
16.5k
35.7k
3.3V
IN
LTC2925
SD2
RUN/SS
DC/DC
FB = 0.8V
2.5V
FB2
OUT
FAULT
SLAVE2
RAMPBUF
R
TB1
R
R
FA2
FB2
8.66k
41.2k
88.7k
TRACK1
TRACK2
3.3V
IN
R
TB2
R
48.7k
TA1
32.4k
SD3
RUN/SS
DC/DC
FB = 0.8V
R
53.6k
TB3
R
215k
TA2
FB3
OUT
1.5V
SLAVE3
TRACK3
R
348k
TA3
GND SCTMR
SDTMR
PGTMR
R
FB3
R
100k
FA3
C
C
C
PGTMR
0.82μF
SCTMR
SDTMR
86.6k
0.41μF
0.082μF
2925 TA03a
2925fc
21
LTC2925
PACKAGE DESCRIPTION
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 .005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
(0.38 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2925fc
22
LTC2925
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.10 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
2.45 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2925fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2925
TYPICAL APPLICATION
Electronic Circuit Breaker Monitors Slave Output
Q1
Si4412ADY
MASTER
V
IN
0.1μF
C
GATE
0.1μF
10Ω
SUPPLY
MONITOR
R
ONB
V
GATE
RAMP
PGI
CC
RST
138k
ON
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235VOUT
REMOTE
FB1
1.8V
V
V
IN
SLAVE1
10k
10k
R
R
FB1
FA1
16.5k
35.7k
STATUS
3.3V
IN
IN
SD2
RUN/SS
DC/DC
FB = 0.8V OUT
2.5V
SLAVE2
FB2
FAULT
RAMPBUF
LTC2925
R
TB1
R
R
FA2
FB2
16.5k
41.2k
88.7k
TRACK1
TRACK2
TRACK3
3.3V
IN
R
TB2
R
13k
TA1
88.7k
SD3
RUN/SS
DC/DC
FB = 0.8V OUT
R
86.6k
TB3
R
41.2k
TA2
0.015W
FB3
1.5V
SLAVE3
R
100k
TA3
R
FB3
R
FA3
86.6k
100k
SENSEP
SENSEN
PGTMR
GND SCTMR
SDTMR
2925 TA03b
C
C
C
PGTMR
0.82μF
SCTMR
SDTMR
0.41μF
0.082μF
RELATED PARTS
PART NUMBER
LTC2900
DESCRIPTION
COMMENTS
Quad Voltage Monitor in MSOP and DFN
Quad Voltage Monitor with Watchdog
Quad Voltage Monitor with Adjustable Reset
Power Supply Margining Controller
16 User Selectable Combinations, 1.5% Threshold Accuracy
16 User Selectable Combinations, Adjustable Timers
LTC2901
LTC2902
5%, 2.5%, 10% and 12.5% Selectable Supply Tolerances
Single or Dual, Symmetric/Asymmetric High and Low Margining
Includes Three (LTC2921) or Five (LTC2922) Remote Sense Switches
Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages
LTC2920
LTC2921/LTC2922
LTC2923
Power Supply Tracker with Input Monitors
Power Supply Sequencing/Tracking Controller
2925fc
LT 1207 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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