LTC2933CGN#TRPBF [Linear]
LTC2933 - Programmable Hex Voltage Supervisor with EEPROM; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC2933CGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC2933 - Programmable Hex Voltage Supervisor with EEPROM; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总34页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2933
Programmable Hex Voltage
Supervisor with EEPROM
FeaTures
DescripTion
The LTC®2933 is an EEPROM configurable voltage super-
visor which can simultaneously monitor up to six power
supply voltage inputs. Each voltage detector offers I C
programmable over/undervoltage thresholds in various
ranges and increments.
n
Supervises 6 Power Supplies
2
n
I C Adjustable UV and OV Trip Points
2
n
Guaranteed Threshold Accuracy: ±±1
2
n
I C/SMBus Interface
n
Internal EEPROM
n
256 Programmable Thresholds per Channel
Two general purpose inputs (GPI) can be configured as
programmable manual reset (MR), UV disable (UVDIS),
margin (MARG) or auxiliary comparator (AUXC) inputs.
Three general purpose pins (GPIO) can be configured for
input or output operation. When configured as an input, a
GPIO pin can be mapped to any other GPIO configured as
output. The GPIO pins can also be configured as ALERT
or fault outputs. Faults can be configured with program-
mable delay-on-release times. Output type and polarity
are also configurable.
n
Up to Three Range Settings per Channel
n
Two General Purpose Inputs
n
Three General Purpose Inputs/Outputs
n
Programmable Output Delays
n
Supply Voltage Range: 3.4V to 13.9V
n
Supply Voltage Power Sharing from V1 to V4
n
16-Pin 5mm × 4mm DFN and SSOP Packages
applicaTions
n
High Availability Computer Systems
Status and history registers log faults and can be polled
n
Network Servers
2
via the I C interface. A fault snapshot is also backed up
n
Telecom Equipment
Data Storage Systems
in internal EEPROM. All parameters are programmable
n
2
via the I C interface. Configuration EEPROM supports
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
autonomous operation without additional software.
Typical applicaTion
Precision Multiple Power Supply Supervisor
V± to V6 Threshold Error
vs Temperature
1
0.5
0
12V
5V
3.3V
2.5V
1.8V
DC/DC
CONVERTERS
1.5V
100nF
SYSTEM
V1 V2 V3 V4 V5 V6
GPIO1
RST
OV
220nF
V
–0.5
DD33
GPIO2
LTC2933
MR
ALERT
GPI1
GPI2
GPIO3
SDA
–1
–50
–25
0
25
50
75
100
GND
ASEL
SCL
TEMPERATURE (°C)
2933 TA01b
2933 TA01a
2933fa
1
For more information www.linear.com/LTC2933
LTC2933
absoluTe MaxiMuM raTings (Notes ±, 2)
Supply Voltages:
Operating Temperature Range:
V1.......................................................... –0.3V to 14V
V2, V3, V4................................................ –0.3V to 6V
Input/Output Voltages:
LTC2933C................................................ 0°C to 70°C
LTC2933I.............................................–40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C*
Maximum Junction Temperature ........................ 125°C*
Lead Temperature Range (Soldering, 10 sec):
SDA, SCL, GPI1, GPI2, V5, V6.................. –0.3V to 6V
GPIO1, GPIO2, GPIO3 ............................ –0.3V to 14V
V
.................................................... –0.3V to 3.6V
SSOP Package..................................................300°C
DD33
ASEL...................................................–0.3V to V
DD33
* See Applications Information section for detailed EEPROM derating
information for junction temperatures in excess of 85°C.
pin conFiguraTion
TOP VIEW
TOP VIEW
V4
V3
V2
V1
1
2
3
4
5
6
7
8
16 V5
1
2
3
4
5
6
7
8
V4
V3
V2
V1
16 V5
15 V6
15 V6
14 GPI1
13 GPI2
12 SCL
11 SDA
10 GPIO1
14 GPI1
13 GPI2
12 SCL
11 SDA
10 GPIO1
17
V
DD33
GND
V
DD33
GND
GPIO3
ASEL
GPIO3
ASEL
9
GPIO2
9
GPIO2
DHD16 PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
GN PACKAGE
16-LEAD PLASTIC SSOP NARROW
T
= 125°C, θ = 41.7°C/W, θ
= 4.3°C/W
JMAX
JA
JCbottom
T
= 125°C, θ = 110°C/W, θ = 40°C/W
JCtop
JMAX
JA
EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL
http://www.linear.com/product/LTC2933#orderinfo
orDer inForMaTion
LEAD FREE FINISH
LTC2933CDHD#PBF
LTC2933IDHD#PBF
LTC2933CGN#PBF
LTC2933IGN#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2933CDHD#TRPBF
LTC2933IDHD#TRPBF
LTC2933CGN#TRPBF
LTC2933IGN#TRPBF
2933
2933
2933
2933
16-Lead (5mm × 4mm) Plastic DFN
16-Lead (5mm × 4mm) Plastic DFN
16-Lead Plastic SSOP
–40°C to 85°C
0°C to 70°C
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2933fa
2
For more information www.linear.com/LTC2933
LTC2933
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V± = ±2V. (Note 2)
SYMBOL
Power Supply Characteristics
Vn Supply Voltage Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
V1
3.4
3.4
13.9
5.8
V
V
V2 to V4
V
V
V
Regulator Output Voltage
Regulator Current Limit
I
= –1mA
= 0V
DD33
3.22
–5.5
3.3
3.37
V
DD33
DD33
DD33
VDD33
I
DD
V
mA
In
V1 to V4 Supply Current
Highest Voltage Supplies Current
Writing to EEPROM
0.7
1.5
mA
mA
SUP
Voltage Supervisor Characteristics
l
l
l
l
l
V1
V1 Monitoring Range
Medium Range
High Range
1
5.8
13.9
1.2
3
V
V
RANGE
2.5
0.2
0.5
1
V2
RANGE
V6
RANGE
to
V2 to V6 Monitoring Range
Precision Range
Low Range
V
V
Medium Range
5.8
V
V1
V1 Threshold Programming Step (LSB) Medium Range
High Range
20
50
4
mV
mV
mV
mV
mV
STEP
V2
V6
to
V2 to V6 Threshold Programming Step
(LSB)
Precision Range
Low Range
STEP
STEP
10
20
Medium Range
l
l
V1
V1 Threshold Accuracy
Medium Range, 3V < V1 < 5.8V
Medium Range, 1V < V1 < 3V
1.5
45
%
mV
ERR
l
l
High Range, 7.5V < V1 < 13.9V
High Range, 2.5V < V1 < 7.5V
1.5
112.5
%
mV
l
l
V2
ERR
V6
ERR
to
V2 to V6 Threshold Accuracy
Precision Range, 0.6V < Vn < 1.2V
Precision Range, 0.2V < Vn < 0.6V
1
6
%
mV
l
l
Low Range, 1.5V < Vn < 3 V
Low Range, 0.5V < Vn < 1.5V
1
15
%
mV
l
l
Medium Range, 3V < Vn < 5.8V
Medium Range, 1V < Vn < 3V
1
30
%
mV
l
R
Vn Input Impedance
Vn Input Current
Low, Medium and High Range
200
kΩ
IN
l
l
I
IN
Precision Range, V2 to V4 = 1.2V
Precision Range, V5 to V6 = 1.2V
2
10
µA
nA
t
Vn Comparator Response Time
2LSB of Overdrive
20LSB of Overdrive
100
25
µs
µs
RT
l
l
40
Manual Reset Characteristics
t
t
Input Pulse Width
Glitch Rejection
Active Low
5
µs
µs
MRI
1
1
MRR
GPIn Characteristics
l
l
l
V
Input Threshold Voltage
Leakage Current
0.6
–5
1.4
2
V
µA
µA
ITH
LEAK
PU
I
I
V
V
= 6V
= 2V
GPI
GPI
Internal Pull-Up Current
–15
–30
2933fa
3
For more information www.linear.com/LTC2933
LTC2933
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V± = ±2V. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.5
9
MAX
UNITS
Auxiliary Comparator Characteristics
l
l
V
Input Threshold Voltage
Input Current
0.49
0.51
20
V
nA
µs
ACIN
ACIN
ACRT
I
t
Input Voltage = 0.5V
40mV Overdrive
Response Time
GPIOn Characteristics
l
l
l
l
V
V
Output Low Voltage
Input Threshold Voltage
Leakage Current
I
= 3mA
SINK
0.4
1.4
2
V
V
OL
ITH
0.6
–5
1
I
I
t
V
V
= 13.9V
= 2V
µA
µA
LEAK
PU
GPIO
GPIO
Internal Pull-Up Current
–15
–30
l
l
l
l
l
l
l
l
Programmable Output Delay-on-Release 000b
0.001
1.6
0.050
2.2
ms
ms
ms
ms
ms
ms
ms
ms
DRO
001b
1.1
4.5
17
35
143
286
1140
GPIO1_DELAY_ON_RELEASE,
010b
6.4
8.7
GPIO2_DELAY_ON_RELEASE and
011b
26
34
GPIO3_DELAY_ON_RELEASE
100b
101b
110b
111b
51
69
205
410
1640
275
550
2200
EEPROM Characteristics
l
l
Retention
Retention (Notes 5, 6)
Endurance (Notes 5, 6)
Fault Storage Time (Note 4)
Programming Time
Restore Time
10
Years
Cycles
ms
Endurance
10,000
t
t
t
Backup Fault Storage Operation
10
100
1
EEFS
EEPR
EERU
2
I C NACK’s During STORE_USER Operation
ms
RESTORE_USER Command
ms
Digital Inputs SCL, SDA
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis (Note 4)
Input Leakage Current
2
V
V
IH
0.8
1
IL
40
mV
µA
HYST
LEAK
l
l
l
I
SCL, SDA = GND to 5.5V
–1
Digital Output SDA
Digital Output Low Voltage
Digital Input ASEL
V
OL
I
= 3mA
SINK
0.4
V
V
V
IH
Input High Threshold Voltage
V
–
DD33
0.4
l
l
l
V
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
0.4
–20
–10
V
µA
µA
IL
I
I
ASEL = 0, V
20
10
IH,IL
FLOAT
DD33
0.5V < ASEL < V
– 0.5V
DD33
Serial Bus Timing Characteristics (Note 3)
l
l
l
l
l
f
t
t
t
t
Serial Clock Frequency
10
1.3
0.6
1.3
600
400
kHz
µs
SCL
Serial Clock LOW Period
LOW
HIGH
BUF
Serial Clock HIGH Period
µs
Bus Free Time Between STOP and START
START Condition Hold Time
µs
ns
HD:STA
2933fa
4
For more information www.linear.com/LTC2933
LTC2933
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V± = ±2V. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
600
600
0
TYP
MAX
UNITS
ns
l
l
l
l
l
t
t
t
START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
SU:STA
SU:STO
HD:DAT
ns
LTC2933 Receiving Data
ns
LTC2933 Transmitting Data
300
100
900
ns
t
t
t
Data Setup Time
ns
SU:DAT
Pulse Width of Spike Suppressed
100
32
ns
SP
Time Allowed to Complete Any Command
After Which Time SDA Will Be Released
and Command Terminated
ms
TIMEOUT_BUS
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 4: Guaranteed by design, not directly tested.
Note 5: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 6: EEPROM endurance and retention will be degraded when T > 85°C.
J
Note 3: Maximum capacitive load, C , for SCL and SDA is 400pF. Data and
B
clock rise time (t ) and fall time (t ) are:
r
f
(20 + 0.1 • C )(ns) < t < 300ns, and
B
r
(20 + 0.1 • C )(ns) < t < 300ns
B
f
C = capacitance of one bus line in pF. SCL and SDA external pull-up
B
voltage, V , is 3V < V < 5.5V.
IO
IO
2933fa
5
For more information www.linear.com/LTC2933
LTC2933
TiMing DiagraMs
Vn Supervisor Timing
Vn
Vn_THR
t
RT
t
DRO
GPIOn
2933 TD01
I2C Timing
SDA
t
f
t
r
t
t
t
BUF
t
t
r
LOW
HD:STA
SU:DAT
t
SP
t
f
SCL
t
t
t
SU:STO
HD:STA
SU:STA
t
S
Sr
P
S
HD:DAT
t
2933 TD02
HIGH
2933fa
6
For more information www.linear.com/LTC2933
LTC2933
Typical perForMance characTerisTics
V± to V4 Supply Current
vs Supply Voltage
VDD33 vs Supply Voltage
VDD33 vs Temperature
3.290
3.285
3.280
3.275
3.270
400
380
360
340
320
300
3.4
3.3
3.2
3.1
3.0
2.9
V1
V1 = 13.9V
V1 = 10V
V1 = 5V
V2-V4
V1 = 3.4V
0
3
6
9
12
15
0
3
6
9
12
15
–50
–25
0
25
50
75
100
3
100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
2933 G02
2933 G03
2933 G01
Aux Comp Response Time
vs Overdrive
V± Comp Response Time
vs Overdrive
V2 to V6 Comp Response Time
vs Overdrive
250
200
150
100
50
250
200
150
100
50
50
40
30
20
10
0
V1 = 1V
V2-V6 = 0.2V
V1 = 6V
V2-V6 = 1.2V
0
0
0
5
10
15
20
25
0
5
10
15
20
25
0
20
40
60
80
120
OVERDRIVE (LSB)
OVERDRIVE (LSB)
OVERDRIVE (mV)
2933 G04
2933 G05
2933 G06
Normalized GPIO Delay
vs Temperature
GPIO Voltage
GPIO Pins During Power-Up
vs Output Sink Current
1.20
1.15
1.10
1.05
1.00
0.95
0.90
200
150
100
50
6
5
4
3
2
1
0
10k PULL-UP FROM GPIOn TO V1
OD = 20LSB
25°C
OD = 2LSB
0.85
0.80
0
1.5
2
0
6
–50
–25
0
25
50
75 100 125
0
0.5
1
2.5
3.5
2
4
V1 (V)
TEMPERATURE (°C)
CURRENT (mA)
2933 G07
2933 G08
2933 G09
2933fa
7
For more information www.linear.com/LTC2933
LTC2933
pin FuncTions
ASEL: Ternary I C Bus Address Select. Can be connected
2
V2 to V4: Low Voltage Supervisor Input. Programmable
thresholds from 0.2V to 1.2V in 4mV increments (preci-
sion range), from 0.5V to 3V in 10mV increments (low
range) or from 1V to 5.8V in 20mV increments (medium
range). Bypass this pin to ground with a 0.1µF (or greater)
capacitor and apply 3.4V minimum through a low imped-
ance, if used to power the part. The highest voltage on
V1 to V4 is automatically selected as supply voltage. See
the Applications Information section for information on
unused channels.
to ground, V
, or left unconnected to select one of
DD33
three addresses.
Exposed Pad (DFN Package Only): Ground. The exposed
pad may be left open or connected to device ground.
GND: Ground.
GPIO±, GPIO2, GPIO3: General Purpose Input/Output.
Each GPIO is configurable as either input, open-drain
output, or weak pull-up output. Output polarity is pro-
grammable. When configured as outputs, these pins
respond to selectable UV conditions, OV conditions, MR,
auxiliary comparator output, or other input-configured
GPIOn with programmable delay-on-release. These pins
can also be configured as ALERT per SMBus standard.
When configured as inputs, each pin can be mapped to
any other output. These pins have an optional 15µA pull-
V5 to V6: Low Voltage Supervisor Input. Programmable
thresholdsfrom0.2Vto1.2Vin4mVincrements(precision
range), from 0.5V to 3V in 10mV increments (low range)
or from 1V to 5.8V in 20mV increments (medium range).
If unused, tie to ground. See the Applications Information
section for information on unused channels.
V
: 3.3V Internal Regulator Output. A 220nF capacitor
DD33
up to V
. Unused GPIO pins should be tied to V
DD33
DD33
to ground is required.
or have their pull-up enabled.
GPI±, GPI2: General Purpose Inputs. Configurable as one
PIN NAME
PIN TYPE
PIN (DFN)
PIN (SSOP)
of four possibilities (no duplication):
V4
V3
V2
V1
In
In
1
2
1
2
•
•
•
•
Manual reset (MR) input, active low, 15µA pull-up to
DD33
In
3
3
V
In
4
4
UVdisable(UVDIS),activelow,15µApull-uptoV
.
.
DD33
V
DD33
Out
Ground
In/Out
In
5
5
Outputs ignore UV faults.
GND
GPIO3
ASEL
GPIO2
GPIO1
SDA
6
6
Margin (MARG), active low, 15µA pull-up to V
Outputs ignore both UV and OV faults.
7
7
DD33
8
8
In/Out
In/Out
In/Out
In
9
9
Hi-Z Auxiliary Comparator (AUXC) Input. Program-
mable Polarity.
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
N/A
2
SCL: I C Serial Clock (400kHz maximum). Needs external
SCL
pull-up resistor.
GPI2
In
2
SDA: I C Serial Data. Needs external pull-up resistor.
GPI1
In
V6
In
V±:HighVoltageSupervisorInput.Programmablethresh-
olds,from1Vto5.8Vin20mVincrements(mediumrange)
or from 2.5V to 13.9V in 50mV increments (high range).
Bypass this pin to ground with a 0.1µF (or greater) capaci-
tor and apply 3.4V minimum through a low impedance, if
used to power the part. The highest voltage on V1 to V4
is automatically selected as supply voltage. If unused, tie
to ground. See the Applications Information section for
information on unused channels.
V5
In
Exposed Pad
2933fa
8
For more information www.linear.com/LTC2933
LTC2933
block DiagraM
V
DD33
I/O CELL 1
EEPROM
15µA
POLARITY
SELECT
TIMING
REGISTERS
SCL
SELECT
GPIO1
2
SDA
I C
INTERFACE
DELAY-ON-
RELEASE
POLARITY
ASEL
GPIO2
GPIO3
CHANNEL 1
V1_THR_HI
I/O CELL 2
I/O CELL 3
V1_POL_HI
REF
8-BIT DAC
–
COMP1_HI
V1
+
REFERENCE
REF
MUX
V1_THR_LO
8-BIT DAC
+
INPUT CELL 1
V
DD33
COMP1_LO
REF
GND
–
15µA
V1_RANGE
V1_POL_LO
V2
V3
V4
V5
V6
+
–
0.5V
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
GPI1
GPI2
AUX
COMP
+
–
INPUT CELL 2
REGULATOR
V
DD33
2933 BD
2933fa
9
For more information www.linear.com/LTC2933
LTC2933
operaTion
The LTC2933 can perform the following operations:
Threshold Accuracy
2
The LTC2933 1% threshold accuracy specification
improves the reliability of the system over supervisors
with wider threshold tolerances. A less accurate voltage
supervisor increases the required system voltage margin.
Thisinturnincreasestheprobabilityofsystemmalfunction.
•
•
Accept I C bus programming commands.
Simultaneously monitor up to six inputs with respect
to programmed fault limits.
•
•
Configure and monitor for OV/UV faults using two
independent comparators per channel.
Consider a 5V 10% supply: it may vary between 4.5V and
5.5V and the circuitry powered by it must operate reliably
within this band. An ideal, perfectly accurate supervisor
would generate a reset at exactly 4.5V. The LTC2933
threshold varies 1% around the nominal threshold volt-
age, in the medium range, if the selected value is greater
than 3V. The reset threshold band and the power supply
tolerance bands should not overlap, in order to prevent
false alarms when the power supply actually meets its
specified tolerance band (see Figure 1).
Configuretwogeneralpurposeinputsasmanualreset
(MR), undervoltage disable (UVDIS), margin (MARG)
or auxiliary comparator (AUXC) inputs.
•
Configure three general purpose inputs/outputs
(GPIOn) to output faults, inputs from GPIn or from
other GPIOn.
•
•
Independently select each general purpose output
polarity and type (open-drain or weak pull-up).
A 10% threshold is usually set to 11% below the nominal
input voltage, or 4.45V in this example. The threshold is
guaranteed to be within the 4.4V to 4.5V band over tem-
perature. To prevent malfunction, the powered system
must operate reliably down to 4.4V.
Independently select each general purpose output
response delay-on-release (with respect to the mo-
ment its condition is internally cleared).
•
Generate interrupt (ALERT) signals in response to any
voltage faults, as well as the logic state of the inputs.
•
•
•
Store register contents to EEPROM.
NOMINAL SUPPLY VOLTAGE
5V
Store voltage and timing fault history to EEPROM.
SUPPLY TOLERANCE
MINIMUM RELIABLE
SYSTEM VOLTAGE
IDEAL SUPERVISOR
THRESHOLD
RestoreEEPROMcontentsintotheoperatingmemory,
2
by I C command and at power-up.
4.5V
4.45V
4.4V
–10%
–11%
–12%
•
•
Report voltage fault status and history.
Software write-protect the operating memory.
REGION OF POTENTIAL MALFUNCTION
2933 F01
Figure ±. ±1 Threshold Accuracy Improves System Reliability
2933fa
10
For more information www.linear.com/LTC2933
LTC2933
operaTion
I C Serial Digital Interface
2
generating SCL to allow the transfer. In the event of an
OV/UV fault, the LTC2933 can be configured to assert the
ALERT output low in order to notify the host.
The LTC2933 communicates with a host (master) using
2
the I C serial bus interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources
are required on these lines.
Slave Address
The LTC2933 can respond to one of three addresses. By
connecting the address ASEL input to V
floating it, the slave address is determined as shown in
the following table. The LTC2933 always responds to the
special addresses.
, GND, or by
DD33
The LTC2933 is a transmit/receive slave-only device. The
master device must initiate data transfer on the bus by
LTC2933 Slave Address Table
ASEL
0
HI-Z
0x1D
0x3A
±
7-Bit Address
8-Bit Address
0x1C
0x38
0x1E
0x3C
LTC2933 Special Slave Addresses
7-Bit
Address
8-Bit
Address Description
0x0C
0x1B
0x19
0x36
Alert Response Address. Independent of the ASEL pin.
Global address to which all LTC2933’s will respond. Independent of the ASEL pin.
Communication Protocols
S
Sr
START CONDITION
REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
MASTER TO SLAVE
SLAVE TO MASTER
Send Byte Format
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
Write Word Format
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
Read Word Format
1
7
1
1
8
1
1
7
1
1
8
1
8
1
A
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
P
2933 F00
2933fa
11
For more information www.linear.com/LTC2933
LTC2933
operaTion
Register Command Set
COMMAND
R/W/S
DATA LENGTH COMMAND
FUNCTION
DESCRIPTION
(See Note)
(BITS)
16
BYTE
0x00
0x01
DEFAULT VALUE
1010_1010_1010_1000b
X001_0000_X000_0000b
WRITE_PROTECT Contains lock key code and write lock.
R/W
R/W
GPI_CONFIG
Configure GPI2 and GPI1 assignment, GPIOn mapping
and MR internal response.
16
GPIO1_CONFIG
Configure GPIO1 type, delay-on-release and mapping to
GPIO2, GPIO3.
R/W
R/W
16
16
0x02
0x03
X000_0000_0010_1011b
0010_1011_0010_1011b
GPIO2_3_CONFIG Configure GPIO3 type, delay-on-release and mapping
to GPIO1 and GPIO2. Configure GPIO2 type, delay-on-
release and mapping to GPIO1 and GPIO3.
V1_THR
Encode high and low voltage thresholds on channel V1.
Encode high and low voltage thresholds on channel V2.
Encode high and low voltage thresholds on channel V3.
Encode high and low voltage thresholds on channel V4.
Encode high and low voltage thresholds on channel V5
Encode high and low voltage thresholds on channel V6.
Encode comparator range, polarity and GPIOn mapping.
Encode comparator range, polarity and GPIOn mapping.
Encode comparator range, polarity and GPIOn mapping.
Encode comparator range, polarity and GPIOn mapping.
Encode comparator range, polarity and GPIOn mapping.
Encode comparator range, polarity and GPIOn mapping.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
16
16
16
16
16
16
16
16
16
16
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
1101_1110_1010_1000b
1110_1001_1011_0001b
1000_1011_0110_0101b
1110_1001_1011_0001b
1001_1011_0111_0011b
0111_1010_0101_1000b
XXXX_XX00_1000_1001b
XXXX_XX00_1000_1001b
XXXX_XX00_1000_1001b
XXXX_XX01_1000_1001b
XXXX_XX01_1000_1001b
V2_THR
V3_THR
V4_THR
V5_THR
V6_THR
V1_CONFIG
V2_CONFIG
V3_CONFIG
V4_CONFIG
V5_CONFIG
V6_CONFIG
R/W
R
S
S
S
16
16
0
0
0
0x0F
0x11
0x1B
0x1C
0x1D
XXXX_XX01_1000_1001b
HISTORY_WORD Read the fault history. Read only.
CLEAR_HISTORY Clear volatile memory history register. Write only.
STORE_USER
RESTORE_USER
NA
NA
NA
NA
Store volatile memory to EEPROM. Write only.
Restore volatile memory from EEPROM. Write only.
BACKUP_WORD
R
16
0x1E
NA
Read the EEPROM backup of the first fault history.
Read only.
STATUS_WORD
R
16
0x1F
NA
Read the fault status. Read only.
Note: R = read, W = write, S = send byte
2933fa
12
For more information www.linear.com/LTC2933
LTC2933
operaTion
DETAILED COMMAND REGISTER DESCRIPTIONS
When locked, WRITE_LOCK can only be written to 0 if
KEY matches the existing value in memory. For effective
protection against false writes, KEY should contain at
least one bit set to 1.
WRITE_PROTECT (Command Byte 0x00)
The WRITE_PROTECT command provides the ability to
prevent any write operations into the volatile memory, if
WRITE_LOCK=1.KEYmaybechangedwhenWRITE_LOCK
= 0, or in the same command that sets WRITE_LOCK = 1.
Writes to supported commands are ignored when
WRITE_LOCK = 1. All commands may be read regardless
of the WRITE_LOCK bit setting.
WRITE_PROTECT Data Contents
BIT(S)
SYMBOL
PURPOSE
b[15:2]
KEY
Must match against programmed combination in order to deactivate write lock.
Factory default 10_1010_1010_1010b (0x2AAA).
b[1]
b[0]
Reserved
Ignore
WRITE_LOCK
0: Unlocked. Writes to volatile memory are permitted.
1: Locked. Writing to volatile memory is not permitted. To unlock, set WRITE_LOCK = 0 with the
appropriate key.
Factory default 0.
2933fa
13
For more information www.linear.com/LTC2933
LTC2933
operaTion
GPI_CONFIG (Command Byte 0x0±)
The GPI_CONFIG command configures internal response
to a manual reset, sets each GPI function, and option-
ally maps GPI pins configured as Manual Reset (MR) or
Auxiliary Comparator (AUXC) to one or more GPIO pins.
GPI_CONFIG Data Contents
BIT(S)
b[15]
b[14]
SYMBOL
OPERATION
Reserved
Ignore
GPI2_MR_RESPONSE
Effective only if the input GPI2 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI2.
Factory default 0.
b[13:11]
GPI2_CONFIG
000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI2.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI2.
Factory default 010b.
b[10]
b[9]
MAP_GPI2_TO_GPIO3
MAP_GPI2_TO_GPIO2
MAP_GPI2_TO_GPIO1
0: GPI2 input is not mapped to GPIO3.
1: GPI2 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
0: GPI2 input is not mapped to GPIO2.
1: GPI2 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
b[8]
0: GPI2 input is not mapped to GPIO1.
1: GPI2 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
b[7]
b[6]
Reserved
Ignore
GPI1_MR_RESPONSE
Effective only if the input GPI1 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI1.
Factory default 0.
b[5:3]
GPI1_CONFIG
000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI1.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI1.
Factory default 000b.
b[2]
b[1]
b[0]
MAP_GPI1_TO_GPIO3
MAP_GPI1_TO_GPIO2
MAP_GPI1_TO_GPIO1
0: GPI1 input is not mapped to GPIO3.
1: GPI1 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
0: GPI1 input is not mapped to GPIO2.
1: GPI1 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
0: GPI1 input is not mapped to GPIO1.
1: GPI1 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
2933fa
14
For more information www.linear.com/LTC2933
LTC2933
operaTion
GPIO±_CONFIG (Command Byte 0x02)
LTC2933 acknowledges the alert response address (see
SMBus protocol), HISTORY_WORD is read, or a CLEAR_
HISTORYcommandisreceived. OnlyoneGPIOnpinshould
be configured as ALERT. GPIOn_DELAY_ON_RELEASE
does not apply to a GPIOn pin configured as ALERT.
The GPIO1_CONFIG command configures the GPIO1
mapping, delay-on-releasetime, outputtype, andpolarity.
If GPIO1_TYPE_AND_POLARITY is configured as ALERT
(100b or 111b), the output is latched and cleared after the
GPIO±_CONFIG Data Contents
BIT(S)
b[15:8]
b[7]
SYMBOL
OPERATION
Reserved
Ignore
MAP_GPIO1_TO_GPIO3
0: GPIO1 input is not mapped to GPIO3.
1: GPIO1 input is mapped to GPIO3.
Factory default 0.
MAP_GPIO1_TO_GPIO2
b[6]
0: GPIO1 input is not mapped to GPIO2.
1: GPIO1 input is mapped to GPIO2.
Factory default 0.
b[5:3]
GPIO1_DELAY_ON_RELEASE
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
b[2:0]
GPIO1_TYPE_AND_POLARITY
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
2933fa
15
For more information www.linear.com/LTC2933
LTC2933
operaTion
GPIO2_3_CONFIG (Command Byte 0x03)
and is cleared after the LTC2933 acknowledges the alert
responseaddress(seeSMBusprotocol),HISTORY_WORD
is read, or a CLEAR_HISTORY command is received.
Only one GPIOn pin should be configured as ALERT.
GPIOn_DELAY_ON_RELEASE does not apply to a GPIOn
pin configured as ALERT.
The GPIO2_3_CONFIG command configures GPIO2 and
GPIO3 mapping, delay-on-release time, output type, and
polarity.IfGPIO2_TYPE_AND_POLARITYisconfiguredas
ALERT(100bor111b),orGPIO3_TYPE_AND_POLARITYis
configuredasALERT(100bor111b),theoutputislatched,
GPIO2_3_CONFIG Data Contents
BIT(S)
SYMBOL
OPERATION
b[15]
MAP_GPIO3_TO_GPIO2
0: GPIO3 is not mapped into GPIO2.
1: GPIO3 is mapped into GPIO2.
Factory default 0.
b[14]
MAP_GPIO3_TO_GPIO1
0: GPIO3 is not mapped into GPIO1.
1: GPIO3 is mapped into GPIO1.
Factory default 0.
b[13:11]
GPIO3_DELAY_ON_RELEASE
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
b[10:8]
GPIO3_TYPE_AND_POLARITY
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
b[7]
b[6]
MAP_GPIO2_TO_GPIO3
MAP_GPIO2_TO_GPIO1
GPIO2_DELAY_ON_RELEASE
0: GPIO2 is not mapped into GPIO3.
1: GPIO2 is mapped into GPIO3.
Factory default 0.
0: GPIO2 is not mapped into GPIO1.
1: GPIO2 is mapped into GPIO1.
Factory default 0.
b[5:3]
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
b[2:0]
GPIO2_TYPE_AND_POLARITY
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
2933fa
16
For more information www.linear.com/LTC2933
LTC2933
operaTion
V±_THR (Command Byte 0x04), V2_THR (0x05),
V3_THR (0x06), V4_THR (0x07),V5_THR (0x08),
V6_THR (0x09)
The Vn_THR command allows the user to specify the high
and low threshold monitoring voltages on each channel.
Vn_THR Data Contents Channels V± to V6
BIT(S)
SYMBOL
OPERATION
b[15:8]
Vn_THR_HI
The COMPn_HI threshold. See the Applications Information section. Factory default settings of 0xDE, 0xE9, 0x8B, 0xE9,
0x9B, 0x7A correspond to 13.35V, 5.56V, 3.68V, 2.78V, 2.00V and 1.67V for channels V1 to V6, respectively.
b[7:0]
Vn_THR_LO
The COMPn_LO threshold. See the Applications Information section. Factory default settings of 0xA8, 0xB1, 0x65, 0xB1,
0x73, 0x58 correspond to 10.65V, 4.44V, 2.92V, 2.22V, 1.60V and 1.33V for channels V1 to V6, respectively.
V±_CONFIG (Command Byte 0x0A), V2_CONFIG (0x0B),
V3_CONFIG (0x0C), V4_CONFIG (0x0D),
V5_CONFIG (0x0E), V6_CONFIG (0x0F)
The Vn_CONFIG command programs V1 through V6
comparator range, polarity and mapping to GPIOn.
Vn_CONFIG Data Contents Channel V± to V6
BIT(S)
b[15:10]
b[9:8]
SYMBOL
Reserved
Vn_RANGE
OPERATION
Ignore
Channel V1:
00b: High Range.
01b: Medium Range.
10b and 11b: Reserved.
Factory default 00b.
Channels V2, V3, V4, V5 and V6:
00b: Medium Range.
01b: Low Range.
10b and 11b: Precision Range.
Factory defaults are 00b on V2 to V3 and 01b on V4, V5 and V6.
b[7]
b[6]
Vn_POL_HI
Vn_POL_LO
Controls polarity of COMPn_HI output reported by STATUS_WORD. See STATUS_WORD
description for details.
0: Undervoltage. Indicates a fault when the input voltage is below Vn_THR_HI.
1: Overvoltage. Indicates a fault when the input voltage is above Vn_THR_HI.
Factory default 1.
Controls polarity of COMPn_LO output reported by STATUS_WORD. See STATUS_WORD
description for details.
0: Undervoltage. Indicates a fault when the input voltage is below Vn_THR_LO.
1: Overvoltage. Indicates a fault when the input voltage is above Vn_THR_LO.
Factory default 0.
b[5]
b[4]
b[3]
MAP_COMPn_HI_TO_GPIO3
MAP_COMPn_HI_TO_GPIO2
MAP_COMPn_HI_TO_GPIO1
0: High comparator not mapped to GPIO3.
1: High comparator mapped to GPIO3.
Factory default 0.
0: High comparator not mapped to GPIO2.
1: High comparator mapped to GPIO2.
Factory default 0.
0: High comparator not mapped to GPIO1.
1: High comparator mapped to GPIO1.
Factory default 1.
2933fa
17
For more information www.linear.com/LTC2933
LTC2933
operaTion
Vn_CONFIG Data Contents Channel V± to V6
BIT(S)
SYMBOL
OPERATION
b[2]
MAP_COMPn_LO_TO_GPIO3
0: Low comparator not mapped to GPIO3.
1: Low comparator mapped to GPIO3.
Factory default 0.
b[1]
b[0]
MAP_COMPn_LO_TO_GPIO2
MAP_COMPn_LO_TO_GPIO1
0: Low comparator not mapped to GPIO2.
1: Low comparator mapped to GPIO2.
Factory default 0.
0: Low comparator not mapped to GPIO1.
1: Low comparator mapped to GPIO1.
Factory default 1.
HISTORY_WORD (Command Byte 0x±±)
CLEAR_HISTORY (Command Byte 0x±B)
The HISTORY_WORD command returns two bytes of
information with a summary of the faults since power was
applied or HISTORY_WORD was last cleared. HISTORY_
WORD is located in volatile memory and is automatically
updated each time a fault occurs. HISTORY_WORD is
cleared using the CLEAR_HISTORY command.
TheCLEAR_HISTORYcommandclearsallthefaultslogged
in the volatile HISTORY_WORD register. A manual reset
performsthesameoperationifGPIn_MR_RESPONSE=1.
Clearing HISTORY_WORD does not affect the STATUS_
WORD content. Processing of the CLEAR_HISTORY
command typically takes less than 10ms, and the part will
2
not acknowledge other I C operations during that time.
HISTORY_WORD Data Contents
BIT(S)
b[15:13]
b[12]
SYMBOL
OPERATION
Reserved
Ignore
V6_HI_LATCHED_FAULT
1: Latched V6_HI_FAULT.
0: No fault.
b[11]
b[10]
b[9]
b[8]
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
V6_LO_LATCHED_FAULT
V5_HI_LATCHED_FAULT
V5_LO_LATCHED_FAULT
V4_HI_LATCHED_FAULT
V4_LO_LATCHED_FAULT
V3_HI_LATCHED_FAULT
V3_LO_LATCHED_FAULT
V2_HI_LATCHED_FAULT
V2_LO_LATCHED_FAULT
V1_HI_LATCHED_FAULT
V1_LO_LATCHED_FAULT
Reserved
1: Latched V6_LO_FAULT.
0: No fault.
1: Latched V5_HI_FAULT.
0: No fault.
1: Latched V5_LO_FAULT.
0: No fault.
1: Latched V4_HI_FAULT.
0: No fault.
1: Latched V4_LO_FAULT.
0: No fault.
1: Latched V3_HI_FAULT.
0: No fault.
1: Latched V3_LO_FAULT.
0: No fault.
1: Latched V2_HI_FAULT.
0: No fault.
1: Latched V2_LO_FAULT.
0: No fault.
1: Latched V1_HI_FAULT.
0: No fault.
1: Latched V1_LO_FAULT.
0: No fault.
Ignore
2933fa
18
For more information www.linear.com/LTC2933
LTC2933
operaTion
STORE_USER (Command Byte 0x±C)
RESTORE_USER (Command Byte 0x±D)
BACKUP_WORD (Command Byte 0x±E)
After the first fault occurs, HISTORY_WORD is written to
EEPROM for backup. Any subsequent BACKUP_WORD
writefollowingafaultisinhibiteduntiltheCLEAR_HISTORY
command is issued. BACKUP_WORD can be retrieved
by sending a RESTORE_USER command followed by a
BACKUP_WORD read. BACKUP_WORD can be cleared
in EEPROM by sending a CLEAR_HISTORY command
followed by a STORE_USER command.
The STORE_USER and RESTORE_USER commands
access nonvolatile EEPROM memory. Once a command
is stored in EEPROM using STORE_USER, it will
be restored to volatile operating memory with the
RESTORE_USER command or when the part powers up.
BACKUP_WORD Data Contents
BIT(S)
b[15:13]
b[12]
SYMBOL
OPERATION
Reserved
Ignore
V6_HI_STORED_FAULT
1: Stored V6_HI_FAULT.
0: No fault.
b[11]
b[10]
b[9]
b[8]
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
V6_LO_STORED_FAULT
V5_HI_STORED_FAULT
V5_LO_STORED_FAULT
V4_HI_STORED_FAULT
V4_LO_STORED_FAULT
V3_HI_STORED_FAULT
V3_LO_STORED_FAULT
V2_HI_STORED_FAULT
V2_LO_STORED_FAULT
V1_HI_STORED_FAULT
V1_LO_STORED_FAULT
Reserved
1: Stored V6_LO_FAULT.
0: No fault.
1: Stored V5_HI_FAULT.
0: No fault.
1: Stored V5_LO_FAULT.
0: No fault.
1: Stored V4_HI_FAULT.
0: No fault.
1: Stored V4_LO_FAULT.
0: No fault.
1: Stored V3_HI_FAULT.
0: No fault.
1: Stored V3_LO_FAULT.
0: No fault.
1: Stored V2_HI_FAULT.
0: No fault.
1: Stored V2_LO_FAULT.
0: No fault.
1: Stored V1_HI_FAULT.
0: No fault.
1: Stored V1_LO_FAULT.
0: No fault.
Ignore
2933fa
19
For more information www.linear.com/LTC2933
LTC2933
operaTion
STATUS_WORD (Command Byte 0x±F)
STATUS_WORD faults may be disabled by setting GPI1_
CONFIG = 010b (MARG), GPI1_CONFIG = 011b (UVDIS),
GPI2_CONFIG = 010b (MARG) or GPI2_CONFIG = 011b
(UVDIS) and asserting the appropriate GPIn pin.
The STATUS_WORD command returns two bytes
of information with a summary of the current faults.
The STATUS_WORD content is read directly from the
comparators and is a snapshot of the current state.
STATUS_WORD Data Contents
BIT(S)
b[15:13]
b[12]
SYMBOL
OPERATION
Reserved
Ignore
V6_HI_FAULT
V6_POL_HI = 1 (default).
1: Fault (V6 greater than V6_THR_HI).
0: No fault (V6 less than V6_THR_HI).
V6_POL_HI = 0.
1: Fault (V6 less than V6_THR_HI).
0: No fault (V6 greater than V6_THR_HI).
b[11]
b[10]
b[9]
V6_LO_FAULT
V5_HI_FAULT
V5_LO_FAULT
V4_HI_FAULT
V4_LO_FAULT
V3_HI_FAULT
V6_POL_LO = 1.
1: Fault (V6 greater than V6_THR_LO).
0: No fault (V6 less than V6_THR_LO).
V6_POL_LO = 0 (default).
1: Fault (V6 less than V6_THR_LO).
0: No fault (V6 greater than V6_THR_LO).
V5_POL_HI = 1 (default).
1: Fault (V5 greater than V5_THR_HI).
0: No fault (V5 less than V5_THR_HI).
V5_POL_HI = 0.
1: Fault (V5 less than V5_THR_HI).
0: No fault (V5 greater than V5_THR_HI).
V5_POL_LO = 1.
1: Fault (V5 greater than V5_THR_LO).
0: No fault (V5 less than V5_THR_LO).
V5_POL_LO = 0 (default).
1: Fault (V5 less than V5_THR_LO).
0: No fault (V5 greater than V5_THR_LO).
b[8]
V4_POL_HI = 1 (default).
1: Fault (V4 greater than V4_THR_HI).
0: No fault (V4 less than V4_THR_HI).
V4_POL_HI = 0.
1: Fault (V4 less than V4_THR_HI).
0: No fault (V4 greater than V4_THR_HI).
b[7]
V4_POL_LO = 1.
1: Fault (V4 greater than V4_THR_LO).
0: No fault (V4 less than V4_THR_LO).
V4_POL_LO = 0 (default).
1: Fault (V4 less than V4_THR_LO).
0: No fault (V4 greater than V4_THR_LO).
b[6]
V3_POL_HI = 1 (default).
1: Fault (V3 greater than V3_THR_HI).
0: No fault (V3 less than V3_THR_HI).
V3_POL_HI = 0.
1: Fault (V3 less than V3_THR_HI).
0: No fault (V3 greater than V3_THR_HI).
2933fa
20
For more information www.linear.com/LTC2933
LTC2933
operaTion
STATUS_WORD Data Contents
BIT(S)
SYMBOL
OPERATION
b[5]
V3_LO_FAULT
V3_POL_LO = 1.
1: Fault (V3 greater than V3_THR_LO).
0: No fault (V3 less than V3_THR_LO).
V3_POL_LO = 0 (default).
1: Fault (V3 less than V3_THR_LO).
0: No fault (V3 greater than V3_THR_LO).
b[4]
b[3]
b[2]
b[1]
b[0]
V2_HI_FAULT
V2_LO_FAULT
V1_HI_FAULT
V1_LO_FAULT
Reserved
V2_POL_HI = 1 (default).
1: Fault (V2 greater than V2_THR_HI).
0: No fault (V2 less than V2_THR_HI).
V2_POL_HI = 0.
1: Fault (V2 less than V2_THR_HI).
0: No fault (V2 greater than V2_THR_HI).
V2_POL_LO = 1.
1: Fault (V2 greater than V2_THR_LO).
0: No fault (V2 less than V2_THR_LO).
V2_POL_LO = 0 (default).
1: Fault (V2 less than V2_THR_LO).
0: No fault (V2 greater than V2_THR_LO).
V1_POL_HI = 1 (default).
1: Fault (V1 greater than V1_THR_HI).
0: No fault (V1 less than V1_THR_HI).
V1_POL_HI = 0.
1: Fault (V1 less than V1_THR_HI).
0: No fault (V1 greater than V1_THR_HI).
V1_POL_LO = 1.
1: Fault (V1 greater than V1_THR_LO).
0: No fault (V1 less than V1_THR_LO).
V1_POL_LO = 0 (default).
1: Fault (V1 less than V1_THR_LO).
0: No fault (V1 greater than V1_THR_LO).
Ignore
2933fa
21
For more information www.linear.com/LTC2933
LTC2933
applicaTions inForMaTion
Power Supply
The command byte for the voltage threshold can be cal-
culated for the V1 to V6 medium range with the following
equation:
The LTC2933 is powered from any one of the voltage
monitoring inputs V1 to V4. A virtual diode-OR scheme
selects the highest supply voltage. V1 to V4 should be
driven by a low impedance source for proper operation of
the diode-OR circuit. The LTC2933 generates a regulated
Command Byte = ROUND [50 • (V – 0.9)]
TH
Inputs from V2 through V6 have a low range that is based
on a full scale of 0.45V to 3V. The 8-bit programming step
size is 10mV. On the low range, threshold accuracy below
0.5V is not specified, but the thresholds are reachable.
3.3V supply on the V
pin. A 100nF external capacitor
DD33
from the highest supply voltage pin (V1 to V4) to GND is
required in order to decouple any supply noise. A 220nF
externalcapacitorfromV
toGNDisrequiredtoproperly
The command byte for the voltage threshold can be
calculated for the V2 to V6 low range with the following
equation:
DD33
compensate the internal voltage regulator.
Power-Up Condition
Command Byte = ROUND [100 • (V – 0.45)]
TH
When power is applied such that at least one of the supply
inputs V1 to V4 exceeds 3.4V, the part turns on and the
EEPROM contents are loaded into the volatile operating
memory. This operation typically takes less than 200µs.
Inputs from V2 through V6 have a precision range that
is based on a full scale of 0.18V to 1.2V. The 8-bit pro-
gramming step size is 4mV. On the low range, threshold
accuracy below 0.2V is not specified, but the thresholds
are reachable.
Power-Down Condition
The command byte for the voltage threshold can be
calculated for the V2 to V6 precision range with the fol-
lowing equation:
If all of the supply inputs, V1 to V4, drop below 3.4V, the
internal regulator will start to fall out of regulation. Once
DD33
theGPIOoutputswillpulllow.SeetheTypicalPerformance
Characteristics section.
V
fallsbelowtheinternalundervoltagelockoutvoltage,
Command Byte = ROUND [250 • (V – 0.18)]
TH
Although all six channels have built-in glitch immunity,
100nF bypass capacitors on the V1 to V4 inputs are rec-
ommended because the largest V1 to V4 voltage is also
the power supply for the device.
Voltage Threshold Programming
The V1 input has a high range that is based on a full scale
of2.25Vto15V.The8-bitprogrammingstepsizeis50mV.
Some of these thresholds are outside of the 14V abs max
voltageratingoftheV1input. Onthehighrange, threshold
accuracy below 2.5V and above 13.9V is not specified, but
the thresholds are reachable.
Unused Channels
The user must connect all unused channel inputs to
ground,programtheirconfigurationwords(Vn_CONFIG)
to 0x01C0, and program their thresholds (Vn_THR) to
0x0000 in order to avoid false faults.
The command byte for the voltage threshold can be cal-
culated for the V1 high range with the following equation:
Command Byte = ROUND [20 • (V – 2.25)]
TH
Auxiliary Comparators
Inputs from V1 through V6 have a medium range that is
based on a full scale of 0.9V to 6V. The 8-bit program-
ming step size is 20mV. On the medium range, threshold
accuracy below 1V and above 5.8V is not specified, but
the thresholds are reachable.
Two additional auxiliary comparators can be connected
to the general purpose inputs with either their inverting
or their noninverting input while the other input internally
connectstoa0.5Vreferencevoltage.Theselowoffset,low
drift comparators can be used for additional monitoring
purposes.
2933fa
22
For more information www.linear.com/LTC2933
LTC2933
applicaTions inForMaTion
If the tap point on an external resistive divider from an
not respond to UV type faults. This feature is useful when
power cycling the monitored supply. An internal 15µA
external voltage, V
, to GND (see Figure 2) connects to
TRIP
current source pulls UVDIS to V
.
the auxiliary comparator input, the trip voltage is:
DD33
⎛
⎞
⎟
⎠
R1
R2
Margin
VTRIP = 0.5V • 1+
⎜
⎝
When a GPIn pin is configured as MARG, the input is
active low. When MARG is grounded, the LTC2933 does
not respond to any OV or UV faults. This feature is useful
when margining the monitored supply. An internal 15µA
In a negative voltage application (also shown in Figure 2)
the resistive divider is connected between the negative
voltage being sensed and V
, and the trip voltage is:
DD33
⎛
⎞
current source pulls MARG to V
.
R3
R4
DD33
VTRIP = 0.5V −2.8V •
⎜
⎟
⎝
⎠
Outputs
The minimum value for R4 is limited by the V
sourcing capability at:
current
DD33
TheGPIOnoutputsareopen-drain,withanoptionalinternal
15µA current source pulling to V
pull-up voltage up to 14V.
and can tolerate a
DD33
3.3V−0.5V
=2.8kΩ
1mA
All faults, GPIn, or other GPIOn inputs mapped to a GPIOn
output are combined with a logical OR function.
Manual Reset
The GPIOn pins have programmable delay-on-release
timing. The GPIOn pin asserts its active state immediately
andde-assertsafterthedelay-on-releasetimehaselapsed.
Any fault causing a GPIOn pin to assert while its delay-on-
releasetimerisactivewillresetthedelay-on-releasetimer.
When a GPIn pin is configured as MR, the input is ac-
tive low. If GPIn_MR_RESPONSE = 1, the HISTORY_
WORD register is cleared when MR is pulled low.
An internal 15µA current source pulls MR to V
.
DD33
The MR input can also be mapped to a GPIO pin and com-
bined with COMPn_HI and COMPn_LO faults to generate
a system reset signal.
When a GPIOn indicates an alert, the alert may be cleared
using the standard SMBus Alert Response Address (ARA)
protocol. Alerts may also be cleared by reading (or clear-
ing) HISTORY_WORD unless the condition causing the
alert persists.
UV Disable
When a GPIn pin is configured as UVDIS, the input is
active low. When UVDIS is grounded, the LTC2933 does
V
TRIP
LTC2933
LTC2933
V
= 3.3V
DD33
R1
R4
R3
+
–
–
+
R2
+
+
–
0.5V
0.5V
–
V
TRIP
2933 F02
Figure 2. Auxiliary Comparator Usage
2933fa
23
For more information www.linear.com/LTC2933
LTC2933
applicaTions inForMaTion
Write Protect Features
where:
2
When the WRITE_LOCK lock bit is set high, all I C write
AF = acceleration factor
wordcommandsareignored.Thisfeatureprotectsagainst
accidental writing. The lock bit may still be written when
the device is write-protected if the provided value for KEY
matches the value in memory.
E = activation energy = 1.5eV
a
–5
k = 8.617 • 10 eV/°k
T
T
= 85°C maximum specified operating temperature
USE
EEPROM
= actual temperature °C
STRESS
The user may save and restore configuration data to the
operatingmemoryregistersatanytimewithSTORE_USER
and RESTORE_USER commands. Upon power-up, user-
stored data is automatically loaded into the operating
memory.ThepartignoresI Ccommandswhileperforming
EEPROM transactions.
Example: Calculate effect on retention when operating at
a temperature of 95°C for 10 hours.
T
= 95°C, T
= 85°C, AF = 3.74
STRESS
USE
2
So, the overall retention of the EEPROM was degraded
by 37.4 hours as a result of operation at a junction tem-
perature of 95°C for 10 hours. Note that the effect of this
overstress is negligible when compared to the overall
EEPROM retention rating of 10 years (87,600 hours) at a
temperature of 85°C.
Nondestructive operation above T = 85°C is possible,
A
but may result in a slight degradation of the retention
characteristics. The degradation in EEPROM retention
for temperatures exceeding 85°C can be approximated
by calculating the acceleration factor:
Negative Supply Power Monitor
⎡
⎢
⎤
⎞
⎥
⎟
⎠
⎦
⎛
⎞
⎛
Ea
k
1
1
•
−
⎜
⎟ ⎜
Figure 3 illustrates how to configure the LTC2933 to
monitor a negative supply rail. Assume the need to moni-
tor the following supply rails: 1.5V within a 5% system
specification, 3.3V, 5V and –5V, within a 10% system
specification. In this example V1 and V2 are not used.
⎠
⎝
AF = e⎣⎝
T
USE +273
TSTRESS +273
5V
5V
3.3V
1.5V
–5V
3.3V
1.5V
–5V
DC/DC
0.1µF
R1
249k
SYSTEM
4.7k
4.7k
R2
100k
0.22µF
V
V1 V2 V3
V4
V5
V6
DD33
RST
GPIO1
GPIO2
GPIO3
SDA
OV
GPI1
ALERT
LTC2933
MR
SCL
MARG
GPI2
GND
ASEL
2933 F03
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
Figure 3. Negative Power Supply Monitor
2933fa
24
For more information www.linear.com/LTC2933
LTC2933
applicaTions inForMaTion
Channel V6 is set to medium range, channels V3 and V4
are set to high range, channel V5 is set to precision range,
and channels V1 and V2 are not used.
The normal polarities of the OV and UV comparators need
to be swapped, since a drop of the negative supply below
its specified absolute value increases V5
beyond its
MAX
encoded threshold. An increase of the negative supply
Select low range for V6 (0.5V to 3V):
above its specified absolute value decreases V5
its encoded threshold.
below
MIN
V6_THR_HI = ROUND [100 • (1.5 • 1.06 –0.45)] = 114
V6_THR_LO = ROUND [100 • (1.5 • 0.94 –0.45)] = 96
The GPIOn outputs are programmed as RST (active low
system reset), OV (active low system OV) and ALERT
(active low ALERT, see SMBus specification). The UV
comparators are mapped to GPIO1 and GPIO3. The OV
comparators are mapped to GPIO2 and GPIO3. The GPI1
input is configured as MR (manual reset) and is mapped
to GPIO1. The GPI2 input is configured as MARG (margin
testing) allowing the system to disable OV and UV faults
during margin testing.
Select medium range for V3 and V4 (1V to 6V):
V3_THR_HI = ROUND [50 • (3.3 • 1.11 – 0.9)] = 139
V3_THR_LO = ROUND [50 • (3.3 • 0.89 – 0.9)] = 101
V4_THR_HI = ROUND [50 • (5 • 1.11 – 0.9)] = 233
V4_THR_LO = ROUND [50 • (5 • 0.89 – 0.9)] = 177
Tomonitor–5V,useanexternalresistivedividerconnected
between V
and the negative rail. The voltage at V
DD33
DD33
is 3.3V. In order to minimize the error introduced by the
leakage current into the V5 input pin, the output of this
divider is targeted to lie within the precision voltage range
(0.2V to 1.2V). The OV and UV thresholds for the –5V rail
are calculated as follows:
(3.3 • R1)− 1.1•(5 • R2)
V5MIN
V5MAX
=
> 0.2V
R1+R2
(3.3 • R1)− 0.9 •(5 • R2)
R1+R2
=
< 1.2V
R1 = 249k 0.1% and R2 = 100k 0.1% satisfy the
previous relationships. The programming codes can be
calculated as shown in the following equations:
(3.3 • 0.98) • (249 • 0.999)−(1.1• 5) • (100 • 1.001)
V5MIN
V5MAX
=
= 0.728V
(249 • 0.999)+(100 • 1.001)
(3.3 • 1.02) • (249 • 1.001)−(0.9 • 5) • (100 • 0.999)
(249 • 1.001)+(100 • 0.999)
=
= 1.115V
⎡
⎤
V5_THR_HI=ROUND 250 • 0.728 • 0.99−0.18 = 135
(
)
⎦
⎣
⎡
⎤
V5_THR_LO =ROUND 250 • 1.115 •1.01−0.18 = 237
(
)
⎦
⎣
2933fa
25
For more information www.linear.com/LTC2933
LTC2933
applicaTions inForMaTion
Eleven-Channel Supply Power Monitor
faults. The GPI1 input is connected to the first supervisor
RST1 output and is mapped to the second supervisor
GPIO1 pin to generate the system RST signal. The GPI2
input is connected to the first supervisor OV1 output and
is mapped to the second supervisor GPIO2 pin to gener-
ate the system OV signal. Thus, if any of the supervised
rails faults or if there is a valid MR signal, an appropriate
global RST or OV is generated.
Figure 4 illustrates how to use multiple LTC2933 super-
visors to monitor power rails. The system consists of
two cascaded LTC2933 supervisors, both of them being
powered from a common 12V dedicated rail connected to
V1 to supervise ten supplies, plus the 12V rail.
ThefirstsupervisormonitorssixrailsandgeneratesRST1
and OV1 signals if a rail faults. The MR signal on GPI1 is
also mapped into RST1.
Both GPIO3 outputs of the LTC2933 supervisors are
wired together and configured as ALERT signals, per the
SMBus protocol.
The second supervisor monitors the remaining five chan-
nels and generates RST and OV signals in response to any
12V
5V
3.3V
2.5V
1.8V
1.5V
1.25V
1.0V
1.0V
0.9V
0.9V
DC/DC
MR
V1
GPI1
GPI2
V2
V3
V4
V
DD33
0.22µF
SYSTEM
LTC2933
V5
ASEL
GND
V6
SCL
GPIO1
GPIO2
GPIO3
SDA
RST1
OV1
V1
GPI1
GPI2
V2
V3
V
DD33
V4
0.22µF
LTC2933
V5
ASEL
GND
0.1µF
V6
SCL
SDA
GPIO1
GPIO2
GPIO3
ALERT
RST
OV
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
2933 F04
Figure 4. ±±-Channel Supply Power Monitor
2933fa
26
For more information www.linear.com/LTC2933
LTC2933
Typical applicaTions
Two-Channel Voltage Monitoring with EEPROM Fault
Storage Power Backup
Low Cost Multipoint Temperature Control System
Figure 6 in the Typical Applications section illustrates a
low cost, 4-point temperature control system, which is
suited for such commercial applications as electric ovens
and dryers.
Figure 5 in the Typical Applications section illustrates an
EEPROMfaultstoragepowerbackupcircuit.TheLTC2933
is supplied by the 12V rail, which is also monitored on V1.
The other monitored rail, 1.8V on V3, is too low to provide
adequate supply voltage, in case the 12V line collapses
to ground. In case such a fault occurs, the LTC2933 still
needs adequate power for EEPROM backup fault storage,
which takes less than 10ms. This is provided by the 22µF
capacitorconnectedbetweentheV2pinandground,which
is charged from the 12V rail through R1. Since the V2
voltage may not exceed 6V, a 4.7V voltage-limiting Zener
diode connected between V2 and ground is necessary. In
this example, V4 through V6 are not used.
Thetemperaturesensorsarefour2N3904diode-connected
BJTs, strategically placed inside the oven/dryer, which are
forward-biased at constant current through 10k resistors
connected to the regulated 3.3V pin. The diode voltages,
which exhibit a negative 2.2mV/°C temperature coef-
ficient, are monitored on the V2 to V5 inputs, set to the
precision range.
The OV faults, corresponding to under-the-limit tempera-
tures, are mapped into GPIO1, which controls the electric
heater through a power MOSFET switch and a relay.
The minimum value of the charge-storage capacitor is
calculated as:
The UV faults, corresponding to over-the-limit tempera-
tures, are mapped into GPIO2, which controls the cooling
fan through a power MOSFET switch.
I2SUP(MAX) • tEEFS
CMIN
=
A microprocessor is used to program the appropriate
V2− V2MIN
2
temperature limits into the LTC2933, via the I C interface.
1.5mA •10ms
4.7V −3.4V
All faults are also mapped into GPIO3, which alerts the
microprocessor on system status.
=
= 11.5µF
The diode connected in series with the fan 12V supply
protects the LTC2933 against inductive voltage spikes
which can propagate on its V1 supply pin through the
common 12V line.
R1hastolimittheZenerdiodereversecurrenttoavaluebe-
low its maximum rating. This determines R1’s minimum
value.
V1− V2 12V −4.7V
RMIN
=
=
= 73kΩ
Suchalowcostsystemcancontroloven/dryertemperature
within 10°C accuracy, over a 50°C to 150°C range, after
proper calibration.
IZ(MAX)
0.1mA
The maximum value of R1 is determined by the V2 pin
input current and the Zener diode reverse leakage current:
V1− V2
RMAX
=
IZ(MIN) + V2 /RIN(MIN)
12V −4.7V
0.01mA+4.7V / 400k
=
= 336kΩ
2933fa
27
For more information www.linear.com/LTC2933
LTC2933
Typical applicaTions
Seven-Power Supply Monitor
The GPI1 comparator monitors the UV limit and is pro-
grammedfornegativepolarity.TheGPI2comparatormoni-
tors the OV limit and is programmed for positive polarity.
Figure 7 in the Typical Applications section illustrates
how to use the LTC2933 auxiliary comparators to expand
powersupplymonitoringtosevenchannels.Thesystemis
poweredbya12Vsource, whichisalsomonitored. The9V
rail can be monitored, in addition to the six input channels
(12V, 5V, 3.3V, 2.5V, 1.8V and 24V), using an external
resistive divider which feeds the OV and UV tap voltages
to the auxiliary comparators on inputs GPI1 and GPI2.
A second resistive divider is used to divide the 24V rail
voltage down to 1.08V, in order to use the low leakage,
low range of the V5 channel.
Since the auxiliary comparators’ thresholds are fixed at
0.5V 10mV, to monitor a 9V 10% power supply, the
following equations apply:
R2+R3
R1+R2+R3 0.9 • 9V
0.51V
=
R3
0.49V
=
R1+R2+R3 1.1• 9V
For R3 = 8.87k, the equations yield: R2 = 2.4k and R1 =
168k.
2933fa
28
For more information www.linear.com/LTC2933
LTC2933
Typical applicaTions
12V
1.8V
12V
DC/DC
1.8V
R1
220k
100nF
22µF
SYSTEM
MMSZ4688
4.7V
220nF
V1 V2
V3 V4 V5 V6
RST
OV
V
DD33
GPIO1
GPIO2
GPIO3
SDA
LTC2933
ALERT
GPI1
SCL
MR
GPI2
GND
ASEL
2933 F05
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
Figure 5. 2-Channel Voltage Monitoring with EEPROM Fault Storage Power Backup
2933fa
29
For more information www.linear.com/LTC2933
LTC2933
Typical applicaTions
TELEDYNE
712D
12V
2N3904
× 4
10nF 10nF 10nF 10nF
110VAC
12V
HEATER
12V
1N4001
FAN
12V DC/5.4W
PMB1212PLB3-A
12V
V1
100nF
10k
× 4
Si4420DY
10k
× 2
220nF
V
V2
V3
V4
V5
V6
GPIO1
GPIO2
GPIO3
DD33
Si4420DY
GPI1
ALERT
LTC2933
MR
SDA
SCL
SYSTEM
GPI2
GND
ASEL
2933 F06
NOTE: INTERNAL GPIO3 PULL-UP ENABLED
Figure 6. Low Cost Multipoint Temperature Control System
2933fa
30
For more information www.linear.com/LTC2933
LTC2933
package DescripTion
Please refer to http://www.linear.com/product/LTC2933#packaging for the most recent package drawings.
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ707 Rev A)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.44 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.34 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.ꢀꢀ5
0.40 0.ꢀ0
5.00 0.ꢀ0
(2 SIDES)
TYP
9
ꢀ6
4.00 0.ꢀ0
(2 SIDES)
2.44 0.ꢀ0
(2 SIDES)
PIN ꢀ
TOP MARK
(SEE NOTE 6)
PIN ꢀ
NOTCH
(DHDꢀ6) DFN REV A ꢀꢀꢀ3
8
ꢀ
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.34 0.ꢀ0
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2933fa
31
For more information www.linear.com/LTC2933
LTC2933
package DescripTion
Please refer to http://www.linear.com/product/LTC2933#packaging for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2933fa
32
For more information www.linear.com/LTC2933
LTC2933
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/17 Raised storage temperature; clarified maximum junction temperature.
Added Notes 5 and 6.
2
5
Updated V2 to V4 pin function.
8
12
Changed to binary representation for the Default Value column.
Updated factory default threshold voltages in Vn_THR register.
Updated sections: Power Supply, Manual Reset, Outputs, Write Protect Features.
Added 4.7k pull-ups in Figure 3.
17
22, 23, 24
24
2933fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
33
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2933
Typical applicaTion
24V
12V
9V
24V
12V
9V
5V
5V
DC/DC
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
100k
4.7k
R1
168k
4.7k
4.7k
SYSTEM
0.1µF
R2
V1 V2 V3 V4 V5 V6
RST
OV
2.4k
GPIO1
GPIO2
GPIO3
SDA
GPI1
GPI2
V
LTC2933
ALERT
R3
8.87k
DD33
0.22µF
GND
ASEL
SCL
2933 F07
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
Figure 7. 7-Power Supply Monitor
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
Reset: V = 0.5V, 1.5% Accuracy Over Temperature, Internal V Auto
LTC2908
LTC2910
LTC2930
LTC2931
LTC2932
LTC2937
LTC2939
LTC2936
Precision 6-Input Supply Monitor
CC
CC
Select
Octal Positive/Negative Voltage Monitor
8 Adjustable Inputs (0.5V), 1.5% Accuracy, Input Glitch Rejection,
Pin-Selectable Input Polarity
Configurable 6-Supply Monitor with Adjustable Reset
Timer, Manual Reset
16 Selectable Thresholds
Configurable 6-Supply Monitor with Adjustable Reset
and Watchdog Timers
16 Selectable Thresholds, Reset Timer, Separate Voltage Monitor Outputs
Configurable 6-Supply Monitor with Adjustable Reset
Timer and Supply Tolerance
16 Selectable Thresholds, Threshold Tolerance, Separate Voltage Monitor
Outputs
Programmable Six Channel Sequencer and Voltage
Supervisor with EEPROM
Time and Event Based Sequencing, 0.75% Accurate UV/OV Supervision,
2
I C Interface
Configurable 6-Supply Monitor with Processor
Supervisory Functions
16 Selectable Thresholds, Adjustable Reset Timer, Watchdog Timeout,
Watchdog Status Output
Programmable Hex Voltage Supervisor with EEPROM and 256 Programmable Thresholds, Comparator Outputs, EEPROM,
Comparator Outputs
2
I C Interface
LTC2977
LTC2974
8-Channel PMBus Power System Manager
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision
LTC2975
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision, Input Current and Power, Input Energy Accumulator
LTC2980
LTC2970
16-Channel PMBus Power System Manager
Dual LTC2977
2
Dual I C Power Supply Monitor and Margining Controller Monitors Voltage and Current on Two Power Supplies. Margins to 0.5%
Accuracy
2933fa
LT 0117 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2933
●
●
LINEAR TECHNOLOGY CORPORATION 2013
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明