LTC2934CTS8-1-TRMPBF [Linear]

Ultra-Low Power Adjustable Supervisor with Power-Fail Output; 超低功率可调监控器与电源故障输出


型号：	LTC2934CTS8-1-TRMPBF
厂家：	Linear
描述：	Ultra-Low Power Adjustable Supervisor with Power-Fail Output 超低功率可调监控器与电源故障输出监控
文件：	总12页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2934

Ultra-Low Power

Adjustable Supervisor with

Power-Fail Output

FEATURES

DESCRIPTION

The LTC^®2934 ultra-low power voltage monitor provides

system initialization, power-fail warning and reset gen-

eration functions. Low quiescent current (500nA typical)

makes the LTC2934 an ideal choice for battery-operated

applications.

500nA Quiescent Current

±±15ꢀ ꢁ(aꢂx Accuracꢃ over ꢄemperature

Operates Down to ±16V Supplꢃ

Adjustable Reset ꢄhreshold

Adjustable Power-Fail ꢄhreshold

Early Warning Power-Fail Output

Precision power-fail and reset voltages can be conﬁgured

independently. Early warning of an impending low volt-

age condition is provided at the power-fail output (PFO)

when the PFI input falls below 0.4V. Supervisory circuits

monitor the ADJ input and pull RST low when ADJ falls

below 0.4V. When ADJ is rising from an under-threshold

condition, aninternalresettimerisstartedafterexceeding

the ADJ threshold by 5%. The reset timeout delays the

return of the RST output to a high state. A pushbutton

switch connected to the MR input is typically used to

force a manual reset. Outputs RST and PFO are available

with open-drain (LTC2934-1) or active pull-up circuits

(LTC2934-2). Operating temperature range is from –40ºC

to 85ºC.

Selectable 15ms or 200ms Reset Timeout

Manual Reset Input

Compact 8-Lead, 2mm × 2mm DFN and TSOT-23

(ThinSOT™) Packages

APPLICATIONS

Portable Equipment

Battery-Powered Equipment

Security Systems

Point-of-Sale Devices

Wireless Systems

, LT, LTC, LTM are registered trademarks of Linear Technology Corporation. ThinSOT is

a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners.

TYPICAL APPLICATION

Conﬁgurable Low Power Voltage Supervisor

Selectable Reset ꢄimeout Period

750k

11.8k

237k

PFO

RST

ADJ

0.1μF

BATTERY

POWERED

SYSTEM

LOGIC

15ms

LTC2934-2

RST, RT = GND

PFI

200ms

RST, RT = V

RT GND

2934 TA01b

2934 TA01a

POWER FAILFALLING THRESHOLD = 1.686V

RESET FALLING THRESHOLD = 1.606V

2934f

LTC2934

ABSOLUTE MAXIMUM RATINGS

ꢁNote ±x

RMS Currents

PFO, RST .......................................................... 5mA

Operating Ambient Temperature Range

Input Voltages

V ........................................................... –0.3V to 6V

ADJ, PFI................................................... –0.3V to 6V

RT, MR ......................................–0.3V to (V + 0.3V)

Output Voltages

LTC2934C ................................................ 0°C to 70°C

LTC2934I.............................................. –40°C to 85°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

PFO, RST (LTC2934-1)............................. –0.3V to 6V

PFO, RST (LTC2934-2)..............–0.3V to (V + 0.3V)

TSOT-23 Package.............................................. 300°C

PIN CONFIGURATION

TOP VIEW

ADJ

PFI

ADJ 1

PFI 2

RT 3

8 V

RST

PFO

7 MR

6 RST

5 PFO

GND

GND 4

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

= 125°C, θ = 195°C/W

DC PACKAGE

8-LEAD (2mm × 2mm) PLASTIC DFN

JMAX

= 125°C, θ = 102°C/W

EXPOSED PAD (PIN 9) PCB GND CONNECTION OPTIONAL

JMAX

ORDER INFORMATION

Lead Free Finish

ꢄAPE AND REEL ꢁ(INIx

LTC2934CTS8-1#TRMPBF

LTC2934ITS8-1#TRMPBF

LTC2934CTS8-2#TRMPBF

LTC2934ITS8-2#TRMPBF

LTC2934CDC-1#TRMPBF

LTC2934IDC-1#TRMPBF

LTC2934CDC-2#TRMPBF

LTC2934IDC-2#TRMPBF

ꢄAPE AND REEL

PARꢄ (ARKING*

LTDKR

LTDKS

LDKT

LDKV

PACKAGE DESCRIPꢄION

ꢄE(PERAꢄURE RANGE

LTC2934CTS8-1#TRPBF

LTC2934ITS8-1#TRPBF

LTC2934CTS8-2#TRPBF

LTC2934ITS8-2#TRPBF

LTC2934CDC-1#TRPBF

LTC2934IDC-1#TRPBF

LTC2934CDC-2#TRPBF

LTC2934IDC-2#TRPBF

8-Lead Plastic TSOT-23

8-Lead (2mm × 2mm) Plastic DFN

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

TRM = 500 pieces. *Temperature grades are identiﬁed by a label on the shipping container.

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2934f

LTC2934

ELECTRICAL CHARACTERISTICS ^ꢄhel denotes the speciﬁcations which applꢃ over the full operating

temperature range, otherwise speciﬁcations are at ꢄ_A= 25°C, V_CC= 316V, unless otherwise noted1 ꢁNote 2x

SY(BOL

PARA(EꢄER

CONDIꢄIONS

(IN

1.6

ꢄYP

(AX

5.5

UNIꢄS

Input Supply Voltage

Input Supply Current

225

500

1000

ꢄhreshold Adjustment Inputs: ADJ, PFI

Input Threshold (Monitored Voltage Falling)

394

400

406

THM

ADJ to PFI Threshold Matching

Reset Threshold Hysteresis

(Monitored Voltage Rising)

ADJ(HYST)

Power-Fail Threshold Hysteresis

(Monitored Voltage Rising)

PFI(HYST)

Undervoltage Detect to RST or PFO Falling

or V = V – 4mV (Note 3)

ADJ

PFI

Threshold Adjustment Input Leakage Current

ADJ

or V = 420mV

0.1

TH(LKG)

PFI

Control Inputs: MR, Rꢄ

IN(TH)

Control Input Threshold

0.3 • V

0.4

0.7 • V

1.4

Input Pulse Width

μs

Propagation Delay to RST Falling

Internal Pull-Up Resistance

Input Leakage Current (RT Input)

Manual Reset Falling

900

600

1200

kΩ

RT = V or GND

Reset and Power Fail Outputs: RST, PFO

Voltage Output Low

= 1V, 200μA Pull-Up Current

= 3V, 3mA Pull-Up Current

100

150

Voltage Output High (LTC2934-2)

Leakage Current, Output High (LTC2934-1)

Reset Timeout Period

–200μA Pull-Down Current

, V = 3.6V

0.7 • V

RST

RST PFO

RT Input High

RT Input Low

140

200

260

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 21 All currents into pins are positive, all voltages are referenced to

GND unless otherwise noted.

Note 31 Guaranteed by design. Characterized, but not production tested.

2934f

LTC2934

TYPICAL PERFORMANCE CHARACTERISTICS ^ꢄ_A^{= 25°C, unless otherwise noted1}

Supplꢃ Current vs Supplꢃ Voltage

ADJ, PFI ꢄhreshold vs ꢄemperature

1000

800

600

400

200

406

404

402

400

398

396

394

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLDS

85°C

25°C

–40°C

–50

100

–25

(V)

TEMPERATURE (°C)

2934 G01

2934 G02

Comparator Undervoltage

Glitch Immunitꢃ

Reset ꢄimeout Period

vs ꢄemperature

3.0

2.5

2.0

1.5

1.0

0.5

260

240

220

200

180

160

140

= 3.6V

= RT = 3.6V

COMPARATORS PULL DOWN

ABOVE CURVE

–50

100

0.1

100

–25

TEMPERATURE (°C)

COMPARATOR OVERDRIVE (%)

2934 G03

2934 G04

Voltage Output Low vs Pull-Up

Voltage Output High vs Pull-Down

Current ꢁRST, PFOx

100

3.6

3.5

= 3V

LTC2934-2

85°C

= 3.6V

25°C

–40°C

25°C

–40°C

3.4

3.3

3.2

85°C

–0.4

–0.6

–0.8

–1

–0.2

PULL-UP CURRENT (mA)

PULL-DOWN CURRENT (mA)

2934 G05

2934 G06

2934f

LTC2934

TYPICAL PERFORMANCE CHARACTERISTICS ^ꢄ_A^{= 25°C, unless otherwise noted1}

Supplꢃ Current vs Rꢄ

Input Voltage

Supplꢃ Current vs MR Input Voltage

250

200

150

100

= 3.6V

1.5

2.5

0.5

3.5

1.5

2.5

0.5

3.5

RT INPUT VOLTAGE (V)

MR INPUT VOLTAGE (V)

2934 G07

2934 G08

PIN FUNCTIONS

ADJ: Reset Threshold Adjustment Input. Tie to resistive

divider between monitored voltage and GND to conﬁgure

desired reset threshold. See the Applications Information

PFO: Power-Fail Output. PFO pulls low when monitored

voltage falls below the power-fail (PFI) threshold. PFO

is released when the PFI voltage rises above the power-

fail threshold by 2.5%. PFO is available with open-drain

(LTC2934-1)oractivepull-up(LTC2934-2)outputs. Leave

open if unused.

section for details. Tie to V if unused.

EꢂposedPadꢁDFNOnlꢃx:ExposedPadmaybeleftﬂoating

or connected to device ground.

RST: Reset Output. RST pulls low when monitored volt-

age falls below the reset threshold. RST is released after

monitored voltage exceeds the reset threshold plus 5%

hysteresisandafterresettimerhasexpired.RSTisavailable

withopen-drain(LTC2934-1)oractivepull-up(LTC2934-2)

outputs. Leave open if unused.

GND: Device Ground.

MR: Manual Reset Input. Attach a push-button switch

between this input and ground. A logic low on this input

pulls RST low. When the MR input returns to logic high,

RST returns high after the reset timer has expired. Tie to

if unused.

Rꢄ: Reset Timeout Selection Input. Tie to GND or V for

PFI: Power-Fail Threshold Adjustment Input. Tie to

resistive divider between monitored voltage and GND

to configure desired power-fail threshold. See the

Applications Information section for details. Tie to V or

GND if unused.

desired reset timeout. Tie low for 15ms delay or high for

200ms delay.

V : Power Supply Input. Bypass V with 0.1μF to

GND.

2934f

LTC2934

BLOCK DIAGRAM

LTC2934-2 OPTION

900k

RST

ADJ

–

RESET

DELAY

LTC2934-2 OPTION

0.4V

PFO

–

PFI

GND

2934 BD

TIMING DIAGRAM

PFI/ PFO ꢄiming

TH+HYST

PFI

PFO

2935 TD01

ADJ/ RST ꢄiming

TH+HYST

ADJ

RST

2935 TD02

2934f

LTC2934

APPLICATIONS INFORMATION

VOLꢄAGE (ONIꢄORING

ꢄhreshold Conﬁguration

Unmanaged power can cause various system problems.

Atpower-up,voltageﬂuctuationaroundcriticalthresholds

can cause improper system or processor initialization.

The LTC2934 provides power management capabilities

for the system power-up phase. The supervisory device

issues a system reset after the monitored voltage has

stabilized. Built-in hysteresis and ﬁltering ensures that

ﬂuctuations due to load transients or supply noise do

not cause chattering of the status outputs. Comparator

undervoltage glitch immunity is shown in the Typical

Performance Characteristics section. The curve dem-

onstrates the transient amplitude and width required to

switch the comparators.

TheLTC2934monitorsvoltageappliedtoitsinputsPFIand

ADJ. A resistive divider connected between a monitored

voltage and ground is used to bias the inputs. Figure 1

demonstrates how the monitor inputs can be made de-

pendent upon a single voltage (V1). Only three resistors

are required. To calculate their values, specify desired

falling power fail (V ) and reset voltages (V ) with V

> V . For example:

= 1.72V, V = 1.62V

ADJ

PFI

LTC2934

Because many batteries exhibit large series resistance,

load currents can cause signiﬁcant voltage drops. The

low DC current draw of the LTC2934 (at any input volt-

age) does not add to the loading problem. When voltage

2934 F01

is initially applied to V , RST and PFO pull low once there

is enough voltage to turn on the pull-down devices (1V

Figure ±1 Conﬁguration for Single Voltage (onitoring

maximum).

The solution for R1, R2, and R3 provides three equations

and three unknowns. Maximum resistor size is governed

by maximum input leakage current. For the LTC2934, the

maximum input leakage current over temperature is 1nA.

For a maximum error of 1% due to both input currents,

the resistor divider current should be 100 times the sum

of the leakage currents, or 0.2μA. At the reset threshold,

If the monitored supply voltage falls to the power-fail

threshold,thebuilt-inpower-failcomparatorpullsPFOlow.

PFO remains low until the PFI input rises above 0.4V plus

2.5%hysteresis.PFOistypicallyusedtosignalpreparation

forcontrolledshutdown.Forexample,thePFOoutputmay

beconnectedtoaprocessornonmaskableinterrupt. Upon

interrupt,theprocessorbeginsshutdownproceduressuch

as supply sequencing and/or storage/erasure of system

state in nonvolatile memory.

V1 = 1.62V, so R

= V1/0.2μA = 8.1M where:

SUM

= R1 + R2 + R3

SUM

If the monitored voltage drops below the reset threshold,

RST pulls low until the ADJ input rises above 0.4V plus

5% hysteresis. This may occur through battery charging

or replacement. An internal reset timer delays the return

of the RST output to a high state to provide settling and

initialization time. The RST output is typically connected

to processor reset input.

The falling monitor thresholds (V ) are 0.4 volts, so:

V_TH• R_SUM

V_PF

0.4V • 8.1M

1.72V

R1 =

= 1.88M

The closest 1% value is 1.87M. R2 can be determined

from:

V_TH• R_SUM

V_R

0.4V • 8.1M

1.62V

Few, if any external components are necessary for reliable

R2 =

– R1 =

− 1.87M

operation. However, a decoupling capacitor between V

and ground is recommended (0.01μF minimum).

R2 = 130k

2934f

LTC2934

APPLICATIONS INFORMATION

R3 is easily obtained from:

Selecting Output Logic Stꢃle

R3 = R

– R1 – R2 = 8.1M – 1.87M – 130k = 6.1M

The LTC2934 status outputs are available in two options:

open-drain (LTC2934-1) or active pull-up (LTC2934-2).

The open-drain option (LTC2934-1) allows the outputs

to be pulled up to a user deﬁned voltage with a resistor.

SUM

The closest 1% value is 6.04M. Plugging the standard

values back into the equations yields the design values

for the falling power-fail and reset voltages:

The open-drain pull-up voltage may be greater than V

= 1.720V, V = 1.608V

(5.5V maximum), which is not always possible with

inferior battery supervisors, due to internal diode clamps.

When the status outputs are low, power is dissipated in

the pull-up resistors. Recommended resistor values lie in

the range between 10k and 470k. Figure 3 demonstrates

typical LTC2934-1 RST output behavior.

Figure 2 demonstrates how the inputs can be biased

to monitor two voltages (V1, V2). In this example, four

resistors are required. Calculate each divider ratio for the

desired falling threshold (V ) using:

RnB V_FT

V_FT

0.4V

− 1=

− 1

The active pull-up option (LTC2934-2) eliminates the

need for external pull-up resistors on the status outputs.

RnA V_TH

In Figure 2, PFO is tied back to the MR input, making the

state of the RST output dependent upon both V1 and V2. If

V1 and V2 are both above the conﬁgured falling threshold

plushysteresis, RSTisallowedtopullhigh. Ifindependent

operation of the status outputs is desired, simply omit the

PFO to MR connection.

Integrated pull-up devices pull the outputs up to V .

Actively pulled up outputs may not be driven above V .

Some applications require the RST and/or PFO outputs to

be valid with V down to ground. Active pull-up handles

this requirement with the addition of an external resistor

from the output to ground. The resistor provides a path

forleakagecurrents,preventingtheoutputfromﬂoatingto

undeterminedvoltageswhenconnectedtohighimpedance

(such as CMOS logic inputs). The resistor value should

be small enough to provide effective pull-down without

excessively loading the pull-up circuitry. A 100k resistor

fromoutputtogroundissatisfactoryformostapplications.

When the status outputs are high, power is dissipated in

the pull-down resistors. Figure 4 demonstrates typical

LTC2934-2 RST output behavior.

R1B

ADJ

PFI

RST

PFO

LTC2934

R2B

R2A

R1A

Figure 21 Dual Voltage (onitoring

3.5

LTC2934-2

LTC2934-1

3.0

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLD

EXTERNALLY CONFIGURED

FOR 3V FALLING THRESHOLD

2.5

2.0

1.5

1.0

0.5

2.0

1.5

1.0

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

0.5

(V)

2934 F04

(V)

2934 F03

Figure 31 RST vs V_CCwith ±0k Pull-Up

Figure 41 RST vs V_CC

2934f

LTC2934

APPLICATIONS INFORMATION

(anual Reset Input

ance is required, series resistance between the switch and

the input is recommended. For most applications a 10k

resistor provides sufﬁcient current limiting.

When V is above its reset threshold, and the manual

reset input (MR) is pulled low, the RST output is forced

low. RST remains low for the selected reset timeout

period after the manual reset input is released and pulled

high.Themanualresetinputispulledupinternallythrough

Selecting the Reset ꢄimeout Period

Use the RT input to select between two ﬁxed reset timeout

periods.ConnectRTtogroundfora15mstimeout.Connect

900k to V . If external leakage currents have the ability

RT to V for a 200ms timeout. The reset timeout period

to pull down the manual reset input below its logic thresh-

occurs after the ADJ input is driven above threshold. After

the reset timeout period, the RST output is allowed to pull

up to a high state.

old, a lower value pull-up resistor, placed between V and

MR will ﬁx the problem.

Input MR is often pulled down through a pushbutton

switch requiring human contact. If extended ESD toler-

TYPICAL APPLICATIONS

Batterꢃ (onitor with Interface to Low Voltage Logic

3μA LDO

0.1μF

1.8V

SHDN GND

OUT

ADJ

LT3009

1.18M

1μF

590k

100k

698k

100k

324k

PFO

RST

NMI

RST

Li-Ion

ADJ

PFI

LTC2934-1

GND

μP

ESD

10k

100k

PB1

2934 TA02

POWER FAIL FALLING THRESHOLD = 3.192V

RESET FALLING THRESHOLD = 1.696V

*OPTIONAL RESISTOR FOR ADDED ESD PROTECTION

Alkaline Cell Stack Voltage (onitor

Coin Cell Voltage (onitor

845k

0.1μF

1.5V

845k

10k

LTC2934-2

GND

LTC2934-2

GND

ADJ

PFO

LOW BATTERY

SYSTEM RESET

PFO

ADJ

PFI

LOW BATTERY

SYSTEM RESET

12.7k

154k

CR2032

RST

PFI

RST

1.5V

147k

2934 TA03

2934 TA04

POWER FAIL THRESHOLD = 2.628V

RESET THRESHOLD = 2.428V

POWER FAIL THRESHOLD = 2.727V

RESET THRESHOLD = 2.553V

2934f

LTC2934

PACKAGE DESCRIPTION

DC Package

8-Lead Plastic DFN ꢁ2mm × 2mmx

(Reference LTC DWG # 05-08-1719 Rev Ø)

0.70 ±0.05

2.55 ±0.05

0.64 ±0.05

1.15 ±0.05

(2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.45 BSC

1.37 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.115

TYP

R = 0.05

TYP

0.40 ± 0.10

PIN 1 NOTCH

2.00 ±0.10 0.64 ± 0.10

(4 SIDES)

(2 SIDES)

R = 0.20 OR

0.25 × 45°

CHAMFER

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

(DC8) DFN 0106 REVØ

0.23 ± 0.05

0.45 BSC

0.75 ±0.05

0.200 REF

1.37 ±0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

2934f

LTC2934

PACKAGE DESCRIPTION

ꢄS8 Package

8-Lead Plastic ꢄSOꢄ-23

(Reference LTC DWG # 05-08-1637)

2.90 BSC

(NOTE 4)

0.52

MAX

0.65

REF

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0802

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

2934f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2934

TYPICAL APPLICATION

Portable Device Batterꢃ (onitor

3μA LDO

1.8V

SHDN GND

OUT

ADJ

LT3009

0.1μF

1.18M

590k

100k

866k

1μF

Li-Ion

ADJ

RST

PFO

100k

LTC2934-1

GND

6.34k

127k

PFI

LOW BATTERY

EARLY WARNING

2934 TA05

POWER FAIL FALLING THRESHOLD = 3.148V

RESET FALLING THRESHOLD = 2.998V

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6-Lead SOT-23 Package

LTC2904/LTC2905/ Three-State Programmable Precision Dual Supply Monitor

LTC2906/LTC2907

8-Lead SOT-23 and DFN Packages

LTC2908

LTC2909

Precision Six-Supply Monitor (Four Fixed and Two Adjustable)

8-Lead TSOT-23 and DFN Packages

Precision Triple/Dual Input UV, OV and Negative Voltage Monitor Shunt Regulated V Pin, Adjustable Threshold and Reset,

8-Lead SOT-23 and DFN Packages

LTC2910

Octal Positive/Negative Voltage Monitor

Separate V Pin, Eight Inputs, Up to Two Negative Monitors

Adjustable Reset Timer, 16-Lead SSOP and DFN Packages

LTC2912/LTC2913/ Single/Dual/Quad UV and OV Voltage Monitors

LTC2914

Separate V Pin, Adjustable Reset Timer

LTC2915/LTC2916/ Single Voltage Supervisors with 27 Pin-Selectable Thresholds

LTC2917/LTC2918

Manual Reset and Watchdog Functions, 8- and 10-Lead

TSOT-23, MSOP and DFN Packages

LTC2935

Ultralow Power Supervisor with Eight Pin-Selectable Thresholds

500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and

TSOT-23 Packages

2934f

LT 0508 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LTC2934CTS8-1-TRMPBF [Linear]

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SI9135_11

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SI9130_11

SI9137

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