LTC2978ACUPPBF [Linear]
8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement; 8通道的PMBus电源系统管理器拥有精确的输出电压测量
| 型号： | LTC2978ACUPPBF |
| 厂家： | 
Linear |
| 描述： | 8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement |
| 文件： | 总80页 (文件大小：891K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2978A
8-Channel PMBus Power
System Manager Featuring Accurate
Output Voltage Measurement
DescripTion
FeaTures
n
Sequence,Trim, Margin and Supervise Eight Power Supplies The LTC®2978A is an 8-channel Power System Manager
n
n
n
n
n
n
Manage Faults, Monitor Telemetry and Create Fault Logs
PMBus Compliant Command Set
used to sequence, trim (servo), margin, supervise, man-
age faults, provide telemetry and create fault logs. PMBus
commands support power supply sequencing, precision
point-of-load voltage adjustment and margining. DACs use
a proprietary soft-connect algorithm to minimize supply
disturbances. Supervisory functions include overvoltage
and undervoltage threshold limits for eight power supply
output channels and one power supply input channel, as
well as over and under temperature limits. Programmable
faultresponsescandisablethepowersupplieswithoptional
retry after a fault is detected. Faults that disable a power
supplycanautomaticallytriggerblackboxEEPROMstorage
of fault status and associated telemetry. An internal 16-bit
ADC monitors eight output voltages, one input voltage,
and die temperature. In addition, odd numbered chan-
nels can be configured to measure the voltage across a
current sense resistor. A programmable watchdog timer
monitorsmicroprocessoractivityforastalledconditionand
resets the microprocessor if necessary. A single wire bus
synchronizes power supplies across multiple LTC power
system management devices. Configuration EEPROM sup-
ports autonomous operation without additional software.
Supported by LTpowerPlay™ GUI
Margin or Trim Supplies to 0.25% Accuracy
Fast OV/UV Supervisors per Channel
Coordinate Sequencing and Fault Management
Across Multiple Chips
n
n
n
n
Automatic Fault Logging to Internal EEPROM
Operate Autonomously without Additional Software
Internal Temperature and Input Voltage Supervisors
Accurate Monitoring of Eight Output Voltages, Input
Voltage and Internal Die Temperature
2
n
n
n
n
n
I C/SMBus Serial Interface
Can Be Powered from 3.3V, or 4.5V to 15V
Programmable Watchdog Timer
100% Compatible with the LTC2978
Available in 64-pin 9mm × 9mm QFN Package
applicaTions
n
Computers and Network Servers
Industrial Test and Measurement
High Reliability Systems
Medical Imaging
Video
n
n
L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks and
LTpowerPlay ia a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 7382303, 7420359 and 7940091.
n
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Typical applicaTion
Typical ADC Total Unadjusted
Error vs Temperature
8-Channel PMBus Power System Manager
0.035
V
4.5V < V
IBUS
< 15V**
IN
ADC V = 1.8V
IN
0.030
0.025
V
V
V
IN_SNS
V
PWR
OUT
3.3V**
V
DIGITALLY
DD33
DACP0
MANAGED
POWER
V
R30
SENSEP0
TO INTERMEDIATE
BUS CONVERTER ENABLE
V
IN_EN
R20
R10
SUPPLY
0.020
0.015
0.010
0.005
LTC2978A*
V
SDA
LOAD
FB
SCL
V
PMBus
INTERFACE
DACM0
ALERTB
V
SENSEM0
SGND
CONTROL0
WP
V
RUN/SS
OUT_EN0
GND
WRITE-PROTECT
PWRGD
TO µP RESETB INPUT
WDI/RESETB
ASEL0
WATCHDOG
0
–50
–5
25 40 55 70 85 100
–35 –20
10
TIMER INTERRUPT
FAULTB00
TO/FROM OTHER
LTC2978s
TEMPERATURE (°C)
SHARE_CLK
ASEL1
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978a TA01b
GND
2978a TA01a
**LTC2978A MAY BE POWERED FROM EITHER AN
EXTERNAL 3.3V SUPPLY OR THE INTERMEDIATE BUS
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For more information www.linear.com/LTC2978A
LTC2978A
Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics................................. 5
PMBus Timing Diagram................................... 9
Typical Performance Characteristics ..................10
Pin Functions..............................................15
Block Diagram.............................................17
Operation...................................................18
Operation Overview ................................................ 18
EEPROM............................................................. 18
Reset ...................................................................... 19
Write-Protect Pin.................................................... 19
Other Operations .................................................... 19
Clock Sharing ..................................................... 19
PMBus Serial Digital Interface................................20
PMBus................................................................20
Device Address...................................................23
Processing Commands.......................................24
Summary Table...................................................25
PMBus Command Summary ............................25
Data Formats......................................................29
PMBus Command Description..........................30
Operation, Mode and EEPROM Commands ............30
PAGE ..................................................................30
OPERATION........................................................31
ON_OFF_CONFIG................................................32
CLEAR_FAULTS..................................................32
WRITE_PROTECT...............................................33
STORE_USER_ALL and RESTORE_USER_ALL .33
CAPABILITY........................................................33
VOUT_MODE ......................................................34
Output Voltage Related Commands........................34
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_
LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_
Input Voltage Related Commands...........................34
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_
OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT .......................................34
Temperature Related Commands............................35
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_
LIMIT and UT_FAULT_LIMIT...............................35
Timer Limits ...........................................................35
TON_DELAY, TON_RISE, TON_MAX_FAULT_
LIMIT and TOFF_DELAY......................................35
Fault Response for Voltages Measured by the High
Speed Supervisor ...................................................36
VOUT_OV_FAULT_RESPONSE and VOUT_UV_
FAULT_RESPONSE .............................................36
Fault Response for Values Measured by the ADC ...37
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE .........................................................37
Timed Fault Response ............................................37
TON_MAX_FAULT_RESPONSE..........................37
Status Commands ..................................................38
STATUS_BYTE:...................................................38
STATUS_WORD:.................................................39
STATUS_VOUT ...................................................39
STATUS_INPUT..................................................40
STATUS_TEMPERATURE....................................40
STATUS_CML ..................................................... 41
STATUS_MFR_SPECIFIC.................................... 41
ADC Monitoring Commands...................................42
READ_VIN ..........................................................42
READ_VOUT.......................................................42
READ_TEMPERATURE_1 ..................................42
PMBUS_REVISION.............................................42
Manufacturer Specific Commands..........................43
MFR_CONFIG_LTC2978.....................................43
MFR_CONFIG_ALL_LTC2978 ............................44
MFR_FAULTBz0_PROPAGATE, MFR_FAULTBz1_
PROPAGATE .......................................................45
MFR_PWRGD_EN ..............................................46
MFR_FAULTB00_RESPONSE, MFR_FAULTB01_
RESPONSE, MFR_FAULTB10_RESPONSE and
WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_
GOOD_ON and POWER_GOOD_OFF ..................34
MFR_FAULTB11_RESPONSE..............................47
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For more information www.linear.com/LTC2978A
LTC2978A
Table oF conTenTs
MFR_VINEN_OV_FAULT_RESPONSE.................48
MFR_VINEN_UV_FAULT_RESPONSE.................49
MFR_RETRY_DELAY..........................................49
MFR_RESTART_DELAY......................................50
MFR_VOUT_PEAK ..............................................50
MFR_VIN_PEAK .................................................50
MFR_TEMPERATURE_PEAK..............................50
MFR_DAC........................................................... 51
MFR_POWERGOOD_ASSERTION_DELAY ......... 51
Watchdog Operation............................................... 51
MFR_WATCHDOG_T_FIRST and MFR_
Off Sequencing...................................................65
OUT
Off Threshold Voltage................................65
V
Automatic Restart Via MFR_RESTART_DELAY
Command and CONTROLn pin ...........................65
Fault Management ..................................................65
Output Overvoltage and Undervoltage Faults .....65
Output Overvoltage and Undervoltage Warnings66
Configuring the V
Output............................66
IN_EN
Multichannel Fault Management ........................68
Interconnect Between Multiple LTC2978A’s............68
Application Circuits.................................................70
Trimming and Margining DC/DC Converters with
External Feedback Resistors...............................70
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors.....70
Trimming and Margining DC/DC Converters with a
TRIM Pin ............................................................71
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin ............................................................71
Measuring Current..............................................72
Measuring Current with a Sense Resistor...........72
Measuring Current with Inductor DCR................72
Single Phase Design Example ............................73
Measuring Multiphase Currents..........................73
Multiphase Design Example ...............................73
Anti-aliasing Filter Considerations ...................... 74
Sensing Negative Voltages ................................. 74
WATCHDOG_T .................................................... 51
MFR_PAGE_FF_MASK .......................................52
MFR_PADS.........................................................53
MFR_I2C_BASE_ADDRESS ...............................53
MFR_SPECIAL_ID..............................................53
MFR_SPECIAL_LOT...........................................54
MFR_VOUT_DISCHARGE_THRESHOLD.............54
MFR_COMMON..................................................54
MFR_SPARE_0, MFR_SPARE_1, MFR_SPARE_2,
MFR_SPARE_3 ..................................................54
MFR_VOUT_MIN ................................................55
MFR_VIN_MIN ...................................................55
MFR_TEMPERATURE_MIN ................................55
Fault Log Operation ................................................55
MFR_FAULT_LOG_STORE .................................56
MFR_FAULT_LOG_RESTORE.............................56
MFR_FAULT_LOG_CLEAR..................................56
MFR_FAULT_LOG_STATUS................................56
MFR_FAULT_LOG...............................................57
Applications Information ................................63
Overview.................................................................63
Powering the LTC2978A .........................................63
Setting Command Register Values .........................63
Sequence, Servo, Margin and Restart Operations ..63
Command Units On or Off..................................63
On Sequencing ...................................................64
On State Operation .............................................64
Servo Modes ......................................................64
DAC Modes.........................................................64
Margining ...........................................................65
2
Connecting the DC1613 USB to I C/SMBus/PMBus
Controller to the LTC2978A in System....................75
LTpowerPlay: An Interactive GUI for Power System
Managers................................................................77
PCB Assembly and Layout Suggestions .................78
Bypass Capacitor Placement ..............................78
Exposed Pad Stencil Design...............................78
PC Board Layout.................................................78
Unused ADC Sense Inputs..................................78
Package Description .....................................79
Typical Application .......................................80
Related Parts..............................................80
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LTC2978A
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltages:
V
V
V
to GND ......................................... –0.3V to 15V
to GND ....................................... –0.3V to 3.6V
to GND ..................................... –0.3V to 2.75V
PWR
DD33
DD25
Digital Input/Output Voltages:
V
V
V
V
V
V
V
V
1
2
3
4
5
6
7
8
9
48 V
47 V
46 V
45 V
44 V
43 V
42 V
41 V
40 V
39 V
38 V
37 V
36 V
SENSEM6
SENSEP3
SENSEM2
SENSEP2
DACM2
V
SENSEP7
SENSEM7
ALERTB, SDA, SCL, CONTROL0,
CONTROL1............................................ –0.3V to 5.5V
PWRGD, SHARE_CLK,
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_EN5
DACP2
SENSEM1
SENSEP1
DACM1
WDI/RESETB, WP....................–0.3V to V
FAULTB00, FAULTB01, FAULTB10,
FAULTB11 ................................–0.3V to V
ASEL0, ASEL1..........................–0.3V to V
Analog Voltages:
+ 0.3V
DD33
65
GND
DACP1
V
V
10
11
12
OUT_EN6
OUT_EN7
DACP0
+ 0.3V
+ 0.3V
DD33
DD33
DACM0
V
IN_EN
SENSEM0
DNC 13
SENSEP0
V
14
15
16
35 REFM
34 REFP
33 ASEL1
IN_SNS
REFP................................................... –0.3V to 1.35V
REFM to GND........................................ –0.3V to 0.3V
V
PWR
V
DD33
V
V
V
V
V
V
V
to GND...................................... –0.3V to 15V
IN_SNS
to GND................................. –0.3V to 6V
to GND ................................ –0.3V to 6V
OUT_EN[3:0] IN_EN
SENSEP[7:0]
SENSEM[7:0]
, V
to GND .................. –0.3V to 15V
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
to GND................................. –0.3V to 6V
OUT_EN[7:4]
DACP[7:0]
T
= 125°C, θ
= 28°C/W, θ
= 1°C/W
JMAX
JA-TOP
JC-BOTTOM
to GND .................................... –0.3V to 6V
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
to GND ................................ –0.3V to 0.3V
DACM[7:0]
Operating Junction Temperature Range:
LTC2978AC.............................................. 0°C to 70°C
LTC2978AI...........................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Maximum Junction Temperature ........................ 125°C*
*See OPERATION section for detailed EEPROM de-
rating information for junction temperatures in excess
of 85°C.
orDer inForMaTion
LEAD FREE FINISH
LTC2978ACUP#PBF
LTC2978AIUP#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
0°C to 70°C
LTC2978ACUP#TRPBF LTC2978AUP
LTC2978AIUP#TRPBF LTC2978AUP
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Characteristics
l
l
l
l
V
V
V
V
V
V
Supply Input Operating Range
Supply Current
4.5
15
13
13
2.8
V
mA
mA
V
PWR
PWR
PWR
DD33
DD33
DD33
I
I
4.5V ≤ V
≤ 15V, V
Floating
10
10
PWR
PWR
DD33
Supply Current
3.13V ≤ V
≤ 3.47V, V
= V
PWR DD33
VDD33
DD33
V
Undervoltage Lockout
Undervoltage Lockout
Hysteresis
V
Ramping Up, V
= V
2.35
2.55
120
UVLO_VDD33
DD33
PWR
DD33
mV
l
l
l
l
l
V
Supply Input Operating Range
Regulator Output Voltage
Regulator Output Short-Circuit Current
Regulator Output Voltage
Regulator Output Short-Circuit Current
Initialization Time
V
= V
3.13
3.13
75
3.47
3.47
140
2.6
V
V
DD33
PWR
DD33
4.5V ≤ V
≤ 15V
3.26
90
PWR
V
PWR
= 4.5V, V
= 0V
mA
V
DD33
V
3.13V ≤ V
≤ 3.47V
2.35
30
2.5
55
DD25
DD33
DD33
V
PWR
= V
= 3.47V, V
= 0V
80
mA
ms
DD25
t
Time from V Applied Until the
TON_DELAY Timer Starts
135
INIT
IN
Voltage Reference Characteristics
V
REF
Output Voltage
V
= V
– V
, 0 < I
REFM
< 100µA
1.232
3
V
ppm/°C
ppm
REF
REFP
REFP
Temperature Coefficient
Hysteresis
(Note 3)
100
ADC Characteristics
l
V
Voltage Sense Input Range
Differential Voltage:
= (V
0
6
V
IN_ADC
V
– V
)
IN_ADC
SENSEPn
SENSEMn
l
l
l
Single-Ended Voltage: V
Single-Ended Voltage: V
–0.1
–0.1
–170
0.1
6
V
V
SENSEMn
Current Sense Input Range (Odd
Numbered Channels Only)
, V
SENSEPn SENSEMn
Differential Voltage: V
170
mV
IN_ADC
N_ADC
Voltage Sense Resolution (Uses L16
Format)
0V ≤ V ≤ 6V
122
µV/LSB
IN_ADC
Current Sense Resolution (Odd
Numbered Channels Only)
0mV ≤ |V
| < 16mV (Note13)
15.625
31.25
62.5
µV/LSB
µV/LSB
µV/LSB
µV/LSB
µV/LSB
IN_ADC
16mV ≤ |V
32mV ≤ |V
| < 32mV
IN_ADC
IN_ADC
IN_ADC
| < 63.9mV
63.9mV ≤ |V
127.9mV ≤ |V
| < 127.9mV
125
|
250
IN_ADC
l
l
l
TUE_ADC
INL_ADC
Total Unadjusted Error
Integral Nonlinearity
V
≥ 1.8V (Note 4)
0.25
854
%
µV
µV
IN_ADC
Voltage Sense Mode (Note 5)
Current Sense Mode, Odd Numbered
Channels Only, 15.6µV/LSB (Note 5)
31.3
l
l
DNL_ADC
Differential Nonlinearity
Offset Error
Voltage Sense Mode
400
µV
µV
Current Sense Mode, Odd Numbered
Channels Only
31.3
l
l
V
Voltage Sense Mode
250
35
µV
µV
OS_ADC
Current Sense Mode, Odd Numbered
Channels Only
l
l
GAIN_ADC
Gain Error
Voltage Sense Mode, V
= 6V
0.2
0.2
%
%
IN_ADC
Current Sense Mode, Odd Numbered
Channels Only, V 0.17V
=
IN_ADC
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For more information www.linear.com/LTC2978A
LTC2978A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
6.15
24.6
24.6
160
MAX
UNITS
ms
t
Conversion Time
Voltage Sense Mode (Note 6)
Current Sense Mode (Note 6)
Temperature Input (Note 6)
CONV_ADC
ms
ms
t
Maximum Update Time
Odd Numbered Channels in Current Sense
Mode (Note 6)
ms
UPDATE_ADC
C
Input Sampling Capacitance
Input Sampling Frequency
Input Leakage Current
1
pF
kHz
µA
IN_ADC
IN_ADC
IN_ADC
f
I
62.5
l
V
= 0V, 0V ≤ V
≤ 6V,
0.5
IN_ADC
COMMONMODE
Current Sense Mode
l
l
Differential Input Current
V
V
= 0.17V, Current Sense Mode
= 6V, Voltage Sense Mode
80
10
250
15
nA
µA
IN_ADC
IN_ADC
DAC Output Characteristics
N_V
Resolution
10
Bits
DACP
l
l
V
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF Buffer Gain Setting_0
1.32
2.53
1.38
2.65
1.44
2.77
V
V
FS_VDACP
DAC Polarity = 1
Buffer Gain Setting_1
l
l
l
INL_V
Integral Nonlinearity
Differential Nonlinearity
Offset Voltage
(Note 7)
2
LSB
LSB
mV
DACP
DNL_V
(Note 7)
2.4
10
DACP
OS_VDACP
DACP
V
V
(Note 7)
Load Regulation (V
– V
)
V
DACPn
V
DACPn
= 2.65V, I Sourcing = 2mA
VDACPn
100
100
60
ppm/mA
ppm/mA
dB
DACPn
DACMn
= 0.1V, I
Sinking = 2mA
VDACPn
PSRR (V
– V
)
DC: 3.13V ≤ V
≤ 3.47V, V = V
PWR DD33
DACPn
DACMn
DD33
100mV Step in 20ns with 50pF Load
–0.1V ≤ V ≤ 0.1V
40
dB
DC CMRR (V
– V
)
60
dB
DACPn
DACMn
DACMn
l
l
l
Leakage Current
V
DACPn
V
DACPn
V
DACPn
V
DACPn
Hi-Z, 0V ≤ V
≤ 6V
100
–4
nA
DACPn
Short-Circuit Current Low
Short-Circuit Current High
Output Capacitance
Shorted to GND
–10
4
mA
Shorted to V
Hi-Z
10
mA
DD33
C
OUT
10
pF
t
DAC Output Update Rate
Fast Servo Mode
250
µs
S_VDACP
Voltage Supervisor Characteristics
l
l
V
IN_VS
Input Voltage Range (Programmable)
V
= (V
SENSEMn
Low Resolution Mode
High Resolution Mode
0
0
6
3.8
V
V
IN_VS
SENSEPn
)
– V
l
Single-Ended Voltage: V
–0.1
0.1
V
mV/LSB
mV/LSB
%
SENSEMn
N_VS
Voltage Sensing Resolution
Total Unadjusted Error
0V to 3.8V Range: High Resolution Mode
0V to 6V Range: Low Resolution Mode
4
8
l
l
TUE_VS
2V ≤ V
≤ 6V, Low Resolution Mode
1.25
1.0
IN_VS
1.5V < V
Mode
≤ 3.8V, High Resolution
%
IN_VS
l
0.8V ≤ V
Mode
≤ 1.5V, High Resolution
1.5
%
IN_VS
t
Update Rate
12.21
90
µs
S_VS
V
Input Characteristics
IN_SNS
l
l
V
V
Input Voltage Range
0
15
V
VIN_SNS
IN_SNS
IN_SNS
R
V
Input Resistance
70
110
kΩ
VIN_SNS
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For more information www.linear.com/LTC2978A
LTC2978A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
TUE
PARAMETER
CONDITIONS
3V ≤ V
MIN
TYP
MAX
2.0
UNITS
%
l
l
l
l
VIN_ON, VIN_OFF Threshold Total
Unadjusted Error
≤ 8V
≤ 8V
VIN_SNS
VIN_SNS
V
> 8V
1.0
%
VIN_SNS
READ_VIN Total Unadjusted Error
3V ≤ V
1.5
%
VIN_SNS
V
> 8V
1.0
%
VIN_SNS
DAC Soft-Connect Comparator Characteristics
Offset Voltage
Temperature Sensor Characteristics
TUE_TS Total Unadjusted Error
l
V
3
1
18
mV
°C
OS_CMP
V
OUT
Enable Output (V
[3:0]) Characteristics
OUT_EN
l
l
l
V
Output High Voltage (Note 12)
I
= –5µA, V = 3.3V
DD33
11.6
–5
3
12.5
–6
5
14.7
–8
8
V
µA
VOUT_ENn
VOUT_ENn
VOUT_ENn
I
Output Sourcing Current
Output Sinking Current
V
Pull-Up Enabled, V
= 1V
VOUT_ENn
VOUT_ENn
Strong Pull-Down Enabled,
= 0.4V
mA
V
VOUT_ENn
l
l
Weak Pull-Down Enabled, V
= 0.4V
33
50
60
1
µA
µA
VOUT_ENn
Output Leakage Current
Internal Pull-Up Disabled,
0V ≤ V
≤ 15V
VOUT_ENn
V
Enable Output (V
[7:4]) Characteristics
OUT
OUT_EN
l
l
I
Output Sinking Current
Strong Pull-Down Enabled,
OUT_ENn
3
6
9
1
mA
µA
VOUT_ENn
V
= 0.1V
Output Leakage Current
0V ≤ V
≤ 6V
VOUT_ENn
V
Enable Output (V ) Characteristics
IN_EN
IN
l
l
l
l
V
Output High Voltage
Output Sourcing Current
Output Sinking Current
Leakage Current
I
= –5µA, V = 3.3V
DD33
11.6
–5
3
12.5
–6
5
14.7
–8
8
V
µA
VIN_EN
VIN_EN
VIN_EN
I
V
V
Pull-Up Enabled, V
= 1V
IN_EN
VIN_EN
= 0.4V
mA
µA
VIN_EN
Internal Pull-Up Disabled,
0V ≤ V ≤ 15V
1
VIN_EN
EEPROM Characteristics
l
Endurance
(Notes 8, 11)
0°C < T < 85°C During EEPROM Write
10,000
10
Cycles
J
Operations
l
l
Retention
(Notes 8, 11)
T < 85°C
J
Years
ms
t
Mass Write Operation Time (Note 9)
STORE_USER_ALL, 0°C < T < 85°C During
440
20
4100
1.5
MASS_WRITE
J
EEPROM Write Operations
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
2.1
V
V
IH
l
IL
mV
µA
HYST
LEAK
l
l
I
Input Leakage Current
0V ≤ V ≤ 5.5V, SDA, SCL, CONTROLn
2
2
PIN
Pins Only
0V ≤ V ≤ V
+ 0.3V, FAULTBzn,
µA
PIN
DD33
WDI/RESETB, WP Pins Only
FAULTBzn, CONTROLn Pins Only
SDA, SCL Pins Only
t
t
Pulse Width of Spike Suppressed
10
98
µs
ns
SP
Minimum Low Pulse Width for
Externally Generated Faults
110
ms
FAULT_MIN
2978af
7
For more information www.linear.com/LTC2978A
LTC2978A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
300
0.3
TYP
MAX
UNITS
µs
l
l
l
t
t
f
Pulse Width to Assert Reset
Pulse Width to Reset Watchdog Timer
Watchdog Interrupt Input Frequency
Digital Input Capacitance
V
V
≤ 1.5V
≤ 1.5V
RESETB
WDI
WDI/RESETB
WDI/RESETB
200
1
µs
MHz
pF
WDI
C
10
IN
Digital Input SHARE_CLK
l
l
l
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Frequency Operating Range
Assertion Low Time
Rise Time
1.6
V
V
IH
0.8
110
1.1
450
1
IL
f
t
t
I
90
kHz
µs
SHARE_CLK_IN
LOW
V
V
< 0.8V
0.825
SHARE_CLK
< 0.8V to V
> 1.6V
ns
RISE
SHARE_CLK
SHARE_CLK
Input Leakage Current
Input Capacitance
0V ≤ V
≤ V + 0.3V
DD33
µA
pF
LEAK
SHARE_CLK
C
10
IN
Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11
l
l
V
Digital Output Low Voltage
I
= 3mA
0.4
V
OL
SINK
f
Output Frequency Operating Range
5.49kΩ Pull-Up to V
90
100
110
kHz
SHARE_CLK_OUT
DD33
Digital Inputs ASEL0,ASEL1
l
l
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
V
DD33
– 0.5
V
V
IH
0.5
95
24
IL
I
I
ASEL[1:0] = 0, V
µA
µA
pF
IH,IL
IH, Z
DD33
C
Input Capacitance
10
IN
Serial Bus Timing Characteristics
l
l
l
l
f
t
t
t
Serial Clock Frequency (Note 10)
Serial Clock Low Period (Note 10)
Serial Clock High Period (Note 10)
10
1.3
0.6
1.3
400
kHz
µs
SCL
LOW
HIGH
BUF
µs
Bus Free Time Between Stop and Start
(Note 10)
µs
l
l
l
l
t
t
t
t
Start Condition Hold Time (Note 10)
Start Condition Setup Time (Note 10)
Stop Condition Setup Time (Note 10)
600
600
600
0
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DAT
Data Hold Time (LTC2978A Receiving
Data) (Note 10)
l
l
Data Hold Time (LTC2978A
Transmitting Data) (Note 10)
300
100
900
ns
t
t
Data Setup Time (Note 10)
ns
ns
SU,DAT
Pulse Width of Spike Suppressed
(Note 10)
98
SP
l
l
t
Time Allowed to Complete any PMBus Longer Timeout = 0
Command after Which Time SDA Will Longer Timeout = 1
Be Released and Command Terminated
25
200
35
280
ms
ms
TIMEOUT_BUS
Additional Digital Timing Characteristics
Minimum Off-Time for Any Channel
t
100
ms
OFF_MIN
2978af
8
For more information www.linear.com/LTC2978A
LTC2978A
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating for extended periods may affect device reliability and lifetime.
Note 7: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 8: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
pin only, connect
DD33
V
and V
pins together.
PWR
DD33
Note 9: The LTC2978A will not acknowledge any PMBus commands while
a
mass write operation is being executed. This includes the STORE_USER_ALL
and MFR_FAULT_LOG_STORE commands or a fault log store initiated by
a channel faulting off.
Note 3: Hysteresis in the output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 10: Maximum capacitive load, C , for SCL and SDA is 400pF. Data
B
Note 4: TUE(%) is defined as:
and clock rise time (t ) and fall time (t ) are: (20 + 0.1 • C ) (ns) < t < 300ns
r f B r
and (20 + 0.1 • C ) (ns) < t < 300ns. C = capacitance of one bus line in pF.
B
f
B
Gain Error (%) + 100 • (INL + V )/V .
OS IN
SCL and SDA external pull-up voltage, V , is 3.13V < V < 5.5V.
IO
IO
Note 5: Integral nonlinearity (INL) is defined as the deviation of a code
from a straight line passing through the actual endpoints of the transfer
curve (0V and 6V). The deviation is measured from the center of the
quantization band.
Note 11: EEPROM endurance and retention will be degraded when T > 85°C.
J
Note 12: Output enable pins are charge-pumped from V
.
DD33
Note 13: The current sense resolution is determined by the L11 format
Note 6: The time between successive ADC conversions (latency of the
ADC) for any given channel is given as: 36.9ms + (6.15ms • number of
ADC channels configured in Low Resolution mode) + (24.6ms • number of
ADC channels configured in High Resolution mode).
and the mV units of the returned value. For example a full scale value
of 170mV returns an L11 value of 0xF2A8 = 680 • 2 = 170. This is the
–2
lowest range that can represent this value without overflowing the L11
–2
mantissa and the resolution for 1LSB in this range is 2 mV = 250µV.
Each successively lower range improves resolution by cutting the LSB size
in half.
pMbus TiMing DiagraM
SDA
t
r
t
SU(DAT)
t
t
SP
t
r
HD(SDA)
t
t
t
t
f
BUF
f
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
2978a TD
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
2978af
9
For more information www.linear.com/LTC2978A
LTC2978A
Typical perForMance characTerisTics
ADC Total Unadjusted Error
vs Temperature
Temperature Sensor Error
Reference Voltage vs Temperature
vs Temperature
1.2355
1.2350
1.2345
1.2340
1.2335
1.2330
1.2325
1.2320
1.2315
1.2310
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.035
0.030
ADC V = 1.8V
IN
0.025
0.020
0.015
0.010
0.005
THREE TYPICAL PARTS
0
–50 –35 –20 –5 10 25
100
–50 –35 –20 –5 10 25 40 55 70 85 100
–50
–5
55
100
70 85
40 55 70 85
–35 –20
10 25 40
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2978a G01
2978a G02
2978a G03
ADC Zero Code Center Offset
Voltage vs Temperature
ADC-INL
ADC-DNL
0.8
0.6
0
–20
3.0
2.5
2.0
1.5
1.0
0.5
0
VOLTAGE SENSE MODE
122µV/LSB
0.4
–40
0.2
–60
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
–160
–180
–0.5
–1.0
–1.5
–0.2 0.8
1.8
2.8
3.8
4.8
–50 –35 –20 –5 10 25
100
–0.2 0.8
1.8
2.8
3.8
4.8
5.8
40 55 70 85
5.8
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
2978a G06
2978a G04
2978a G05
ADC Rejection
vs Frequency at VIN
ADC Rejection
vs Frequency at VIN (Zoom)
ADC Rejection vs Frequency
at VIN (Current Sense Mode)
0
0
0
–20
–20
–20
–40
–60
–40
–60
–40
–60
–80
–100
–120
–80
–100
–120
–80
–100
–120
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
0
3125
6250
FREQUENCY (Hz)
9375
12500
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
2978a G07
2978a G08
2978a G09
2978af
10
For more information www.linear.com/LTC2978A
LTC2978A
Typical perForMance characTerisTics
ADC Rejection vs Frequency
Voltage Supervisor Total
Unadjusted Error vs Temperature
ADC Noise Histogram
at VIN (Current Sense Mode, Zoom)
1200
1000
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
V
IN
= 0V
V
= 0.8V
IN
HIGH RESOLUTION MODE
HIGH RESOLUTION MODE
–20
800
600
–40
–60
400
200
0
–80
–100
–120
–20
–10
0
10
20
0
3125
6250
9375
12500
–50 –35 –20 –5 10 25 40 55 70 85 100
READ_V
(µV)
FREQUENCY (Hz)
OUT
TEMPERATURE (°C)
2978a G11
2978a G10
2978a G12
DAC Full-Scale Output Voltage vs
Temperature
Input Sampling Current
vs Differential Input Voltage
ADC High Resolution Mode
Differential Input Current
2.698
9
8
7
6
5
4
3
2
1
90
80
70
60
50
40
30
20
10
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
0
0
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
0
1
2
3
6
4
5
0
20 40 60 80 100
180
120 140 160
INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (mV)
2978a G15
2978a G13
2978a G14
DAC Offset Voltage vs
Temperature
DAC-INL
DAC-DNL
1.0
0.8
1.0
0.8
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
200
400
600
800
1000
0
200
400
600
800
1000
–50 –35 –20 –5 10 25 40 55 70 85 100
DAC CODE
DAC CODE
TEMPERATURE (°C)
2978a G17
2978a G18
2978a G16
2978af
11
For more information www.linear.com/LTC2978A
LTC2978A
Typical perForMance characTerisTics
DAC Short-Circuit Current vs
Temperature
DAC Load Regulation (Sourcing)
DAC Load Regulation (Sinking)
2.698
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
9.00
8.95
0.1038
0.1036
0.1034
0.1032
0.1030
0.1028
0.1026
85°C
85°C
25°C
25°C
8.90
8.85
8.80
8.75
8.70
–40°C
–40°C
0
–1
–1.50 1.75
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
–0.25 –0.5 –0.75
–1.25
–2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
CURRENT (mA)
CURRENT (mA)
2978a G19
2978a G21
2978a G20
DAC Soft-Connect Transient
Response when Transitioning from
Hi-Z State to ON State
DAC Soft-Connect Transient
Response when Transitioning from
ON State to Hi-Z State
DAC Transient Response to 1LSB
DAC Code Change
CODE ‘h200
HI-Z
HI-Z
500µV/DIV
10mV/DIV
10mV/DIV
CONNECTED
CONNECTED
CODE ‘h1FF
2978a G22
2978a G24
2978a G23
2µs/DIV
500µs/DIV
500µs/DIV
100k SERIES RESISTANCE ON
CODE: ‘h1FF
100k SERIES RESISTANCE ON
CODE: ‘h1FF
2978af
12
For more information www.linear.com/LTC2978A
LTC2978A
Typical perForMance characTerisTics
VDD33 Regulator Output Voltage
vs Temperature
V
DD33 Regulator Short-Circuit
VDD33 Regulator Line Regulation
Current vs Temperature
3.275
3.270
3.265
3.260
3.255
3.250
3.245
3.240
3.235
400
300
–86
–88
85°C
25°C
200
–90
100
–92
–40°C
0
–94
–100
–200
–300
–400
–96
–98
–100
–102
–500
–50 –35 –20 –5 10 25 40 55 70 85 100
4.5
6
7.5
9
15
–50 –35 –20 –5 10 25 40 55 70 85 100
10.5 12 13.5
(V)
V
TEMPERATURE (°C)
TEMPERATURE (°C)
PWR
2978a G25
2978a G26
2978a G27
VOUT_EN[3:0] and VIN_EN Output
High Voltage vs Load Current
Supply Current vs Supply Voltage
Supply Current vs Temperature
14.0
10.5
10.4
10.3
10.2
10.1
10.0
9.9
10.16
10.14
V
= V
DD33
V
= 12V
PWR
PWR
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
85°C
25°C
–40°C
10.12
10.10
10.08
10.06
10.04
9.8
9.5
10.02
3.1
3.2
3.4
3
3.5
3.6
3.3
0
1
2
3
7
4
5
6
10
25 40 55 70 85 100
–50
–5
–35 –20
CURRENT SOURCING (µA)
V
(V)
TEMPERATURE (°C)
DD33
2978a G28
2978a G30
2978a G29
2978af
13
For more information www.linear.com/LTC2978A
LTC2978A
Typical perForMance characTerisTics
VOUT_EN[3:0] and VIN_EN VOL
vs Current
DAC Output Impedance vs
Frequency
V
OUT_EN[7:4] VOL vs Current
1000
100
10
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
85°C
25°C
1
–40°C
–40°C
0.1
0.01
0.01
0.1
1
10
100
1000
0
8
12
(mA)
16
20
24
8
12
4
0
2
4
6
10
I
FREQUENCY (kHz)
I
(mA)
SINK
SINK
2978a G31
2978a G33
2978a G32
PWRGD and FAULTBzn VOL
vs Current
ALERTB VOL vs Current
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
85°C
25°C
–40°C
8
12
0
2
4
6
10
0
4
6
8
10
12
2
I
(mA)
I
(mA)
SINK
SINK
2978a G35
2978a G34
2978af
14
For more information www.linear.com/LTC2978A
LTC2978A
pin FuncTions
PIN NAME
PIN NUMBER
PIN TYPE
In
DESCRIPTION
V
V
V
V
V
V
V
V
V
V
V
V
1*
2*
3*
4
5
6
7
8
9
10
11
12
13
14
DC/DC Converter Differential (–) Output Voltage-6 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Differential (–) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Open-Drain Pull-Down Output-4
DC/DC Converter Open-Drain Pull-Down Output-5
DC/DC Converter Open-Drain Pull-Down Output-6
DC/DC Converter Open-Drain Pull-Down Output-7
DC/DC Converter V ENABLE Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
SENSEM6
SENSEP7
SENSEM7
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_EN5
OUT_EN6
OUT_EN7
IN_EN
In
In
Out
Out
Out
Out
Out
Out
Out
Out
0ut
IN
DNC
Do Not Connect Do Not Connect to This Pin
V
In
V SENSE Input. This Voltage is Compared Against the V On and Off Voltage Thresholds in Order to
IN IN
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
IN_SNS
V
15
16
In
V
Serves as the Unregulated Power Supply Input to the Chip (4.5V to 15V). If a 4.5V to 15V Supply
PWR
PWR
Voltage is Unavailable, Short V
GND with 0.1µF Capacitor.
to V
and Power the Chip Directly from a 3.3V Supply. Bypass to
PWR
DD33
V
In/Out
If Shorted to V
, it Serves as 3.13V to 3.47V Supply Input Pin. Otherwise it is a 3.3V Internally
PWR
DD33
Regulated Voltage Output (Use 0.1µF Decoupling Capacitor to GND)
Input for Internal 2.5V Sub-Regulator. Short This Pin to Pin 16
2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1µF Capacitor
Digital Input. Write-Protect Input Pin, Active High
Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as System
Power-On Reset. The Latency of This Signal May Be as Long as the ADC Latency. See Note 6.
V
V
WP
17
18
19
20
In
In/Out
In
DD33
DD25
PWRGD
Out
SHARE_CLK
WDI/RESETB
21
22
In/Out
In
Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to V
DD33
Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to V
. Rising Edge
DD33
Resets Watchdog Counter. Holding This Pin Low for More Than t
Resets the Chip
RESETB
FAULTB00
FAULTB01
FAULTB10
FAULTB11
23
24
25
26
In/Out
In/Out
In/Out
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-00. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-01. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-10. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 10k Pull-Up
Resistor to V
DD33
SDA
SCL
27
28
29
30
31
32
33
34
35
36*
37*
38*
39
In/Out
In
Out
In
In
In
PMBus Bidirectional Serial Data Pin
PMBus Serial Clock Input Pin (400kHz Maximum)
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
Control Pin 0 Input
Control Pin 1 Input
Ternary Address Select Pin 0 Input. Connect to V
Ternary Address Select Pin 1 Input. Connect to V
Reference Voltage Output. Needs 0.1µF Decoupling Capacitor to REFM
Reference Return Pin. Needs 0.1µF Decoupling Capacitor to REFP.
DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin
DAC0 Return. Connect to Channel 0 DC/DC Converter’s GND Sense or Return to GND
DAC0 Output
ALERTB
CONTROL0
CONTROL1
ASEL0
ASEL1
REFP
, GND or Float to Encode 1 of 3 Logic States
, GND or Float to Encode 1 of 3 Logic States
DD33
In
DD33
Out
Out
In
REFM
V
V
V
V
V
SENSEP0
SENSEM0
DACM0
DACP0
In
Out
Out
Out
40
DAC1 Output
DACP1
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
pin FuncTions
PIN NAME
PIN NUMBER
41*
42*
43*
44
PIN TYPE
Out
In
DESCRIPTION
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DAC1 Return. Connect to Channel 1 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-1 Sensing Pins
DAC2 Output
DAC2 Return. Connect to Channel 2 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-3 Sensing Pins
DAC3 Output
DAC3 Return. Connect to Channel 3 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-4 Sensing Pin
DAC4 Return. Connect to Channel 4 DC/DC Converter’s GND Sense or Return to GND
DAC4 Output
DACM1
SENSEP1
SENSEM1
DACP2
In
Out
Out
In
In
In
45*
46*
47*
48*
49*
50
51*
52*
53*
54*
55
DACM2
SENSEP2
SENSEM2
SENSEP3
SENSEM3
DACP3
In
Out
Out
In
DACM3
SENSEP4
SENSEM4
DACM4
In
Out
Out
Out
Out
Out
Out
Out
Out
In
DACP4
56
DAC5 Output
DACP5
57*
58*
59
DAC5 Return. Connect to Channel 5 DC/DC Converter’s GND Sense or Return to GND
DAC6 Return. Connect to Channel 6 DC/DC Converter’s GND Sense or Return to GND
DAC6 Output
DACM5
DACM6
DACP6
60
DAC7 Output
DACP7
61*
62*
63*
64*
65
DAC7 Return. Connect to Channel 7 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin
Exposed Pad, Must be Soldered to PCB
DACM7
SENSEP5
SENSEM5
SENSEP6
In
In
Ground
GND
*Any unused V
or V
or V pins must be tied to GND.
DACMn
SENSEPn
SENSEMn
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
block DiagraM
3.3V REGULATOR
IN
V
15
16
V
V
OUT
PWR
V
V
DD
DD33
2.5V REGULATOR
IN
OUT
V
V
17
18
V
V
DD33
DD25
3R
V
V
SENSEM0
SENSEP0
V
14
IN_SNS
R
V
V
SENSEM1
36
37
42
43
46
47
48
49
52
53
62
63
64
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SENSEP0
SENSEM0
SENSEP1
SENSEM1
SENSEP2
SENSEM2
SENSEP3
SENSEM3
SENSEP4
SENSEM4
SENSEP5
SENSEM5
SENSEP6
SENSEM6
SENSEP7
SENSEM7
SENSEP1
GND 65
V
V
SENSEM2
SENSEP2
V
V
SENSEM3
SENSEP3
–
+
–
+
V
V
SENSEM4
SENSEP4
INTERNAL
TEMP
SENSOR
CMP0
MUX
+
–
10-BIT
DAC
V
V
SENSEM5
SENSEP5
V
V
SENSEM6
SENSEP6
V
V
SENSEM7
SENSEP7
+
–
16-BIT
∆∑ ADC
2
3
ADC
CLOCKS
39
40
44
50
55
56
59
60
V
V
V
V
V
V
V
V
+
–
VBUF
DACP0
DACP1
DACP2
DACP3
DACP4
DACP5
DACP6
DACP7
10-BIT
DAC
V
DD
REFERENCE
1.232V
(TYP)
REFP 34
REFM 35
38
41
45
51
54
57
58
61
V
V
V
V
V
V
V
V
DACM0
DACM1
DACM2
DACM3
DACM4
DACM5
DACM6
DACM7
NONVOLATILE MEMORY
EEPROM
SCL 28
SDA 27
PAGE 0
PMBus
INTERFACE
ALERTB 29
ASEL0 32
ASEL1 33
2
(400kHz I C
RAM
COMPATIBLE)
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
PAGE 7
WP 19
4
5
6
7
V
V
V
V
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUTPUT
CONTROL0 30
CONTROL1 31
WDI/RESETB 22
FAULTB00 23
FAULTB01 24
FAULTB10 25
FAULTB11 26
CONFIG
CLOCK
GENERATION
OSCILLATOR
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
12
V
IN_EN
V
DD
8
9
V
V
V
V
OUT_EN4
OUT_EN5
OUT_EN6
OUT_EN7
SEQUENCER
UVLO
OPEN-DRAIN
OUTPUT
10
11
PWRGD
20
SHARE_CLK 21
2978a BD
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
OPERATION OVERVIEW
n
n
n
Restore EEPROM contents through PMBus program-
ming or when V is applied on power-up.
DD33
The LTC2978A is a PMBus programmable power system
controller,monitor,sequencerandvoltagesupervisorthat
can perform the following operations:
Report the DC/DC converter output voltage status
throughthePMBusinterfaceandthepowergoodoutput.
n
Accept PMBus compatible programming commands.
Generate interrupt requests by asserting the ALERTB
pin in response to supported PMBus faults and
warnings.
n
Provide DC/DC converter input voltage and output volt-
age/current read back through the PMBus interface.
n
Coordinate system wide fault responses for all DC/DC
converters connected to the FAULTBz0 and FAULTBz1
pins.
n
Control the output of DC/DC converters that set the
output voltage with a trim pin or DC/DC converters
that set the output voltage using an external resistor
feedback network.
n
n
n
Synchronizesequencingdelaysorshutdownformultiple
devices using the SHARE_CLK pin.
n
Sequence the start-up of DC/DC converters via PMBus
programming and their control input pins.
Software and hardware write protect the command
registers.
n
Trim the DC/DC converter output voltage (typically in
0.02% steps), in closed-loop servo operating mode,
through PMBus programming.
Disable the input voltage to the supervised DC/DC
converters in response to output voltage OV and UV
faults.
n
Margin the DC/DC converter output voltage to PMBus
programmed limits.
n
n
Log telemetry and status data to EEPROM in response
to a faulted-off condition
n
Allow the user to trim or margin the DC/DC converter
outputvoltageinamanualoperatingmodebyproviding
direct access to the margin DAC.
Supervise an external microcontroller’s activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
n
Supervise the DC/DC converter output voltage, input
n
Prevent a DC/DC converter from re-entering the ON
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
voltage, and the LTC2978A die temperature for over-
value/undervalue conditions with respect to PMBus
programmedlimitsandgenerateappropriatefaultsand
warnings.
n
Respond to a fault condition by either continuing op-
n
Record minimum and maximum observed values of
input voltage, output voltages and temperature.
eration indefinitely, latching off after a programmable
deglitchperiodorlatchingoffimmediately.Aretrymode
maybeusedtoautomaticallyrecoverfromalatched-off
condition.
EEPROM
The LTC2978A contains internal EEPROM (nonvolatile
memory) to store configuration settings and fault log
information. EEPROM endurance, retention, and mass
write operation time are specified over the operating junc-
tion temperature range. See Electrical Characteristics and
Absolute Maximum Ratings sections.
n
Optionally stop trimming the DC/DC converter output
voltage after it reached the initial margin or nominal
target. Optionally allow servo to resume if target drifts
outside of V
warning limits.
OUT
n
StorecommandregistercontentswithCRCtoEEPROM
through PMBus programming.
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
Nondestructive operation above T = 85°C is possible
RESET
Holding the WDI/RESETB pin low for more than t
J
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
RESETB
will cause the LTC2978A to enter the power-on reset
state. While in the power-on reset state, the device will not
Operating the EEPROM above 85°C may result in a deg-
radation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these reg-
isters occur above 85°C, a slight degradation in the data
retention characteristics of the fault log may occur.
2
communicate on the I C bus. Following the subsequent
rising-edge of the WDI/RESETB pin, the LTC2978A will
execute its power-on sequence per the user configuration
stored in EEPROM. Connect WDI/RESETB to VDD33 with
a 10k resistor. WDI/RESETB includes an internal 256µs
deglitch filter so additional filter capacitance on this pin
is not recommended.
It is recommended that the EEPROM not be written using
STORE_USER_ALLorbulkprogrammingwhenT >85°C.
J
WRITE-PROTECT PIN
The degradation in EEPROM retention for temperatures
>85°C can be approximated by calculating the dimension-
less acceleration factor using the following equation.
TheWPpinallowstheusertowrite-protecttheLTC2978A’s
configuration registers. The WP pin is active high, and
when asserted it provides Level 2 protection: all writes are
disabled except to the WRITE_PROTECT, PAGE, STORE_
USER_ALL, OPERATION, MFR_PAGE_FF_MASK and
CLEAR_FAULTS commands. The most restrictive setting
between the WP pin and WRITE_PROTECT command will
override. For example if WP = 1 and WRITE_PROTECT =
0x80, then the WRITE_PROTECT command overrides,
since it is the most restrictive.
Ea
k
1
1
•
−
TUSE +273 TSTRESS +273
AF = e
Where:
AF = acceleration factor
Ea = activation energy = 1.4 eV
−5
k = 8.625×10 eV/°K
OTHER OPERATIONS
Clock Sharing
T
T
= 85°C specified junction temperature
USE
= actual junction temperature °C
STRESS
Multiple LTC PMBus devices can synchronize their clocks
in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired
OR. In this case the fastest clock will take over and syn-
chronize all LTC2978As.
Example: Calculate the effect on retention when operating
at a junction temperature of 95°C for 10 hours.
T
T
= 95°C
STRESS
= 85°C
USE
SHARE_CLKcanoptionallybeusedtosynchronizeON/OFF
AF = 3.4
dependency on V across multiple chips by setting the
IN
Equivalent operating time at 85°C = 34 hours.
Mfr_config_all_vin_share_enablebitoftheMFR_CONFIG_
ALL_LTC2978register.Whenconfiguredthiswaythechip
willholdSHARE_CLKlowwhentheunitisoffforinsufficient
inputvoltage, andupondetectingthatSHARE_CLKisheld
low the chip will disable all channels after a brief deglitch
period. When the SHARE_CLK pin is allowed to rise, the
So the overall retention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 95°C for 10 hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 85°C.
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
chip will respond by beginning a soft-start sequence. In
this case the slowest VIN_ON detection will take over and
synchronize other chips to its soft-start sequence.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
PMBus SERIAL DIGITAL INTERFACE
The LTC2978A communicates with a host (master) using
thestandardPMBusserialbusinterface.ThePMBusTiming
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The PMBus two wire interface is an incremental extension
2
of the SMBus. SMBus is built upon I C with some minor
differences in timing, DC parameters and protocol. The
2
SMBus protocols are more robust than simple I C byte
commands because they provide timeouts to prevent
bus hangs and optional packet error checking (PEC) to
ensure data integrity. In general, a master device that
The LTC2978A is a slave device. The master can com-
municate with the LTC2978A using the following formats:
2
can be configured for I C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: paragraph 5: Transport. This can be
found at:
The following SMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
www.pmbus.org.
n
Alert Response Address
For a description of the differences between SMBus and
2
Figures 1-12 illustrate the aforementioned SMBus
protocols.AlltransactionssupportPEC(parityerrorcheck)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBustimeoutmaybeextendedusingtheMfr_config_all_
longer_pmbus_timeout setting.
I C, refer to system management bus (SMBus) specifica-
tionversion2.0:AppendixB–DifferencesBetweenSMBus
2
and I C. This can be found at:
www.smbus.org.
2
When using an I C controller to communicate with a
PMBus part it is important that the controller be able to
write a byte of data without generating a stop. This will
allow the controller to properly form the repeated start
of the PMBus read command by concatenating a start
TheLTC2978AwillnotacknowledgeanyPMBuscommand
if it is still busy with a STORE_USER_ALL, RESTORE_
USER_ALL, MFR_CONFIG_LTC2978 or if fault log data
is being written to the EEPROM. Status_word_busy will
also be set, but ALERTB will not be asserted low.
2
command byte write with an I C read.
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
x
COMMAND CODE
A
x
P
S
Sr
START CONDITION
REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x
SHOWN UNDER A FIELD INDICATES THAT THE
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
...
2978a F01a
Figure 1a. PMBus Packet Protocol Diagram Element Key
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
2978a F01b
Figure 1b. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
2978a F02
Figure 2. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
2978a F03
Figure 3. Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
2978a F04
Figure 4. Write Word Protocol with PEC
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
2978a F05
Figure 5. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
2978a F06
Figure 6. Send Byte Protocol with PEC
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
1
7
1
1
8
1
1
7
1
1
8
1
8
1
A
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
P
2978a F07
Figure 7. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
A
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
P
2978a F08
Figure 8. Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
A
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
P
2978a F09
Figure 9. Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
1
A
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
P
2978a F10
Figure 10. Read Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
...
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr
A
BYTE COUNT = N
A
SLAVE ADDRESS Rd
2978a F11
...
...
8
1
8
1
8
1
A
1
1
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
P
Figure 11. Block Read
1
7
1
1
8
1
1
7
1
1
8
1
...
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr
A
BYTE COUNT = N A
SLAVE ADDRESS Rd
2978a F12
...
...
8
1
8
1
8
1
8
1
A
1
1
DATA BYTE 1
A
DATA BYTE 2
A
A
P
DATA BYTE N
PEC
Figure 12. Block Read with PEC
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
Device Address
be changed unless the desired range of addresses overlap
existingaddresses. Watchthattheaddressrangedoesnot
2
The I C/SMBus address of the LTC2978A equals the base
2
overlap with other I C/SMBus device or global addresses,
address + N where N is a number from 0 to 8. N can be
2
including I C/SMBus multiplexers and bus buffers. This
configuredbysettingtheASEL0andASEL1pinstoV
,
DD33
will bring you great happiness.
GND or FLOAT. See Table 1. Using one base address and
the nine values of N, nine LTC2978As can be connected
togethertocontrol72outputs. Thebaseaddressisstored
in the MFR_I2C_BASE_ADDRESS register. The base ad-
dress can be written to any value, but generally should not
The LTC2978A always responds to its global address and
theSMBusAlertResponseaddressregardlessofthestateof
itsASELpinsandtheMFR_I2C_BASE_ADDRESSregister.
Table 1. LTC2978A Device Address Look-Up Table
ADDRESS
DESCRIPTION
HEX DEVICE
ADDRESS
BINARY DEVICE ADDRESS BITS
ADDRESS PINS
7-Bit
0C
8-Bit
19
6
0
1
1
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
1
1
1
1
1
4
0
1
1
1
1
1
0
0
0
0
0
3
1
1
1
1
1
1
0
0
0
0
0
2
1
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
R/W
1
ASEL1
ASEL0
Alert Response
Global
N = 0
X
X
X
X
5B
5C*
5D
5E
5F
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
0
0
L
L
N = 1
0
L
NC
H
N = 2
0
L
N = 3
0
NC
NC
NC
H
L
N = 4
60
61
62
63
64
0
NC
H
N = 5
0
N = 6
0
L
N = 7
0
H
NC
H
N = 8
0
H
H = Tie to V
, NC = No Connect = Open or Float, L = Tie to GND, X = Don’t Care
DD33
*MFR_I2C_BASE_ADDRESS = 7bit 5C (Factory Default)
2978af
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For more information www.linear.com/LTC2978A
LTC2978A
operaTion
Processing Commands
The LTC2978A uses a dedicated processing block to ensure quick response to all of its commands. There are a few
exceptions where the part will NACK a subsequent command because it is still processing the previous command.
These are summarized in the following tables.
EEPROM Related Commands
COMMAND
TYPICAL DELAY*
COMMENT
STORE_USER_ALL
t
See Electrical Characteristics table. The LTC2978A will not accept any commands while it is
transferring register contents to the EEPROM. The command byte will be NACKed.
MASS_WRITE
RESTORE_USER_ALL
MFR_FAULT_LOG_CLEAR
MFR_FAULT_LOG_STORE
Internal Fault log
30ms
The LTC2978A will not accept any commands while it is transferring EEPROM data to command
registers. The command byte will be NACKed.
175ms
20ms
10ms
The LTC2978A will not accept any commands while it is initializing the fault log EEPROM space. The
command byte will be NACKed.
The LTC2978A will not accept any commands while it is transferring the fault log RAM buffer to
EEPROM space. The command byte will be NACKed.
An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM
in response to a fault. Internal fault logging may be disabled. Commands received during this
EEPROM write are NACKed.
MFR_FAULT_LOG_RESTORE
2ms
The LTC2978A will not accept any commands while it is transferring EEPROM data to the fault log
RAM buffer. The command byte will be NACKed.
*The typical delay is measured from the command’s stop to the next command’s start.
COMMAND
TYPICAL DELAY*
COMMENT
MFR_CONFIG_LTC2978
<50µs
The LTC2978A will not accept any commands while it is completing this command. The command
byte will be NACKed.
*The typical delay is measured from the command’s stop to the next command’s start.
Other PMBus Timing Notes
COMMAND
COMMENT
CLEAR_FAULTS
The LTC2978A will accept commands while it is completing this command but the affected status flags will not be cleared
for up to 500µs.
2978af
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LTC2978A
pMbꢀꢁ coMManD suMMary
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
PAGE
0x00 Channel or page currently selected for any R/W Byte
command that supports paging.
N
Y
Y
Reg
Reg
Reg
0x00
0x00
0x12
30
31
32
OPERATION
0x01 Operating mode control. On/Off, Margin
High and Margin Low.
R/W Byte
R/W Byte
Send Byte
Y
Y
ON_OFF_CONFIG
0x02 CONTROL pin & PMBus bus on/off
command setting.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Y
N
NA
32
33
WRITE_PROTECT
0x10 Level of protection provided by the device R/W Byte
against accidental changes.
Reg
Y
0x00
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x15 Store entire operating memory to
EEPROM.
Send Byte
Send Byte
R Byte
N
N
N
NA
NA
33
33
33
0x16 Restore entire operating memory from
EEPROM.
0x19 Summary of PMBus optional
communication protocols supported by
this device.
Reg
0xE0
VOUT_MODE
VOUT_COMMAND
VOUT_MAX
0x20 Output voltage data format and mantissa
R Byte
Y
Y
Y
Reg
L16
L16
0x13
34
34
34
–13
exponent. (2
)
0x21 Servo Target. Nominal DC/DC converter
output voltage setpoint.
R/W Word
V
V
Y
Y
1.0
0x2000
0x24 Upper limit on the output voltage the unit R/W Word
can command regardless of any other
commands.
4.0
0x8000
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VIN_ON
0x25 Margin high DC/DC converter output
voltage setting.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
N
N
L16
L16
L11
L11
V
V
V
V
Y
Y
Y
Y
1.05
34
34
34
34
0x219A
0x26 Margin low DC/DC converter output
voltage setting.
0.95
0x1E66
0x35 Input voltage (V
) above which
10.0
0xD280
IN_SNS
power conversion can be enabled.
VIN_OFF
0x36 Input voltage (V
) below which
9.0
0xD240
IN_SNS
power conversion is disabled. All V
pins go off immediately.
OUT_EN
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
Y
L16
Reg
L16
L16
L16
V
Y
Y
Y
Y
Y
1.1
34
36
34
34
34
0x2333
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
0x80
0x42 Output overvoltage warning limit.
V
V
V
1.075
0x2266
0x43 Output undervoltage warning limit.
0.925
0x1D9A
0x44 Output undervoltage fault limit. Limit
used to determine if TON_MAX_FAULT
has been met and the unit is on.
0.9
0x1CCD
VOUT_UV_FAULT_RESPONSE
OT_FAULT_LIMIT
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
N
Reg
L11
Y
Y
0x7F
36
35
0x4F Overtemperature fault limit.
R/W Word
°C
85.0
0xEAA8
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LTC2978A
pMbꢀꢁ coMManD suMMary
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
OT_FAULT_RESPONSE
0x50 Action to be taken by the device when an
overtemperature fault is detected.
R/W Byte
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Reg
L11
L11
L11
Reg
L11
Reg
L11
L11
L11
Reg
L16
L16
L11
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0xB8
37
35
35
35
37
34
37
34
34
34
37
34
34
35
OT_WARN_LIMIT
0x51 Overtemperature warning limit.
0x52 Undertemperature warning limit.
0x53 Undertemperature fault limit.
R/W Word
R/W Word
R/W Word
R/W Byte
°C
°C
°C
75.0
0xEA58
UT_WARN_LIMIT
0
0x8000
UT_FAULT_LIMIT
–5.0
0xCD80
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
POWER_GOOD_ON
POWER_GOOD_OFF
TON_DELAY
0x54 Action to be taken by the device when an
undertemperature fault is detected.
0xB8
0x55 Input overvoltage fault limit measured at R/W Word
pin
V
15.0
0xD3C0
V
IN_SNS
0x56 Action to be taken by the device when an
input overvoltage fault is detected.
R/W Byte
0x80
0x57 Input overvoltage warning limit measured R/W Word
at V pin
V
V
V
14.0
0xD380
IN_SNS
0x58 Input undervoltage warning limit
measured at V pin.
R/W Word
0
0x8000
IN_SNS
0x59 Input undervoltage fault limit measured at R/W Word
pin
0
V
0x8000
IN_SNS
0x5A Action to be taken by the device when an
input undervoltage fault is detected.
R/W Byte
0x00
0x5E Output voltage at or above which a power R/W Word
good should be asserted.
V
V
0.96
0x1EB8
0x5F Output voltage at or below which a power R/W Word
good should be deasserted.
0.94
0x1E14
0x60 Time from CONTROL pin and/or
OPERATION command = ON to V
pin = ON.
R/W Word
ms
1.0
0xBA00
OUT_EN
TON_RISE
0x61 Time from when the V
pin goes
R/W Word
Y
Y
L11
L11
ms
ms
Y
Y
10.0
35
35
OUT_ENn
high until the LTC2978A optionally soft-
connects its DAC and begins to servo the
output voltage to the desired value.
0xD280
TON_MAX_FAULT_LIMIT
0x62 Maximum time from V
= ON
R/W Word
15.0
0xD3C0
OUT_EN
assertion that an UV condition will be
tolerated before a TON_MAX_FAULT
condition results.
TON_MAX_FAULT_RESPONSE 0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
Y
Y
Reg
L11
Y
Y
0xB8
37
35
TOFF_DELAY
0x64 Time from CONTROL pin and/or
OPERATION command = OFF to V
pin = OFF.
R/W Word
ms
1.0
0xBA00
OUT_EN
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
0x78 One byte summary of the unit’s fault
condition.
R Byte
R Word
R Byte
Y
Y
Y
Reg
Reg
Reg
NA
NA
NA
38
39
0x79 Two byte summary of the unit’s fault
condition.
0x7A Output voltage fault and warning status.
39
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Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
STATUS_INPUT
0x7C Input voltage fault and warning status
measured at VIN_SNS pin.
R Byte
N
N
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
40
40
41
41
STATUS_TEMPERATURE
STATUS_CML
0x7D Temperature fault and warning status for
READ_TEMPERATURE_1.
R Byte
R Byte
R Byte
0x7E Communication and memory fault and
warning status.
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
READ_VIN
0x88 Input voltage measured at VIN_SNS pin.
0x8B DC/DC converter output voltage.
0x8D Internal junction temperature.
R Word
R Word
R Word
R Byte
N
Y
N
N
L11
L16
L11
Reg
V
V
NA
NA
42
42
42
42
READ_VOUT
READ_TEMPERATURE_1
PMBUS_REVISION
°C
NA
0x98 PMBus revision supported by this device.
Current revision is 1.1.
0x11
MFR_CONFIG_LTC2978
0xD0 Configuration bits that are channel
specific.
R/W Word
Y
N
Y
Reg
Reg
Reg
Y
Y
Y
0x0080
0x7B
43
44
45
MFR_CONFIG_ALL_LTC2978
MFR_FAULTBz0_PROPAGATE
0xD1 Configuration bits that are common to all R/W Byte
pages.
0xD2 Configuration that determines if a
channel’s faulted off state is propagated
to the FAULTB00 and FAULTB10 pins.
R/W Byte
0x00
MFR_FAULTBz1_PROPAGATE
0xD3 Manufacturer configuration that
Configuration that determines if a
R/W Byte
Y
Reg
Y
0x00
45
channel’s faulted off state is propagated
to the FAULTB01 and FAULTB11 pins.
MFR_PWRGD_EN
0xD4 Configuration for mapping PWRGD and
WDI/RESETB status to the PWRGD pin.
R/W Word
N
N
N
N
N
N
N
N
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
Reg
L11
L11
L16
Y
Y
Y
Y
Y
Y
Y
Y
Y
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
46
47
47
47
47
48
49
49
50
50
MFR_FAULTB00_RESPONSE
MFR_FAULTB01_RESPONSE
MFR_FAULTB10_RESPONSE
MFR_FAULTB11_RESPONSE
0xD5 Action to be taken by the device when the R/W Byte
FAULTB00 pin is asserted low.
0xD6 Action to be taken by the device when the R/W Byte
FAULTB01 pin is asserted low.
0xD7 Action to be taken by the device when the R/W Byte
FAULTB10 pin is asserted low.
0xD8 Action to be taken by the device when the R/W Byte
FAULTB11 pin is asserted low.
MFR_VINEN_OV_FAULT_
RESPONSE
0xD9 Action to be taken by the V
pin in
R/W Byte
R/W Byte
R/W Word
R/W Word
R Word
IN_EN
response to a VOUT_OV_FAULT.
MFR_VINEN_UV_FAULT_
RESPONSE
0xDA Action to be taken by the V
pin in
IN_EN
response to a VOUT_UV_FAULT.
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
0xDB Retry interval during FAULT retry mode.
ms
ms
V
200.0
0xF320
0xDC Delay from actual CONTROL active edge
to virtual CONTROL active edge.
400.0
0xFB20
0xDD Maximum measured value of READ_
VOUT.
NA
MFR_VIN_PEAK
0xDE Maximum measured value of READ_VIN.
R Word
R Word
N
N
L11
L11
V
NA
NA
50
50
MFR_TEMPERATURE_PEAK
0xDF Maximum measured value of READ_
TEMPERATURE_1.
°C
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LTC2978A
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Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
MFR_DAC
0xE0 Manufacturer register that contains the
code of the 10-bit DAC.
R/W Word
Y
N
N
N
N
Reg
L11
L11
L11
Reg
0x0000
51
51
51
51
52
MFR_POWERGOOD_
ASSERTION_DELAY
0xE1 Power good output assertion delay.
0xE2 First watchdog timer interval.
0xE3 Watchdog timer interval.
R/W Word
R/W Word
R/W Word
R/W Byte
ms
ms
ms
Y
Y
Y
Y
100.0
0xEB20
MFR_WATCHDOG_T_FIRST
0
0x8000
MFR_WATCHDOG_T
0
0x8000
MFR_PAGE_FF_MASK
0xE4 Configuration defining which channels
respond to global page commands
(PAGE=0xFF).
0xFF
MFR_PADS
0xE5 Current state of selected digital I/O pads.
R Word
N
N
Reg
Reg
N/A
53
53
2
MFR_I2C_BASE_ADDRESS
0xE6 Base value of the I C/SMBus address
R/W Byte
Y
Y
Y
0x5C
byte.
MFR_SPECIAL_ID
MFR_SPECIAL_LOT
0xE7 Manufacturer code for identifying the
LTC2978A
R Word
R Byte
N
Y
Reg
Reg
0x0124
53
54
0xE8 Customer dependent codes that
identify the factory programmed user
configuration stored in EEPROM. Contact
factory for default value.
MFR_VOUT_DISCHARGE_
THRESHOLD
0xE9 Coefficient used to multiply VOUT_
R/W Word
Y
N
N
N
L11
Y
2.0
54
56
56
56
COMMAND in order to determine V
threshold voltage.
off
0xC200
OUT
MFR_FAULT_LOG_STORE
MFR_FAULT_LOG_RESTORE
MFR_FAULT_LOG_CLEAR
0xEA Command a transfer of the fault log from Send Byte
RAM to EEPROM. This causes the part to
NA
NA
NA
behave as if a channel has faulted off.
0xEB Command a transfer of the fault log
previously stored in EEPROM back to
RAM.
Send Byte
Send Byte
0xEC Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
MFR_FAULT_LOG_STATUS
MFR_FAULT_LOG
0xED Fault logging status.
R Byte
N
N
Reg
Reg
Y
Y
NA
NA
56
57
0xEE Fault log data bytes. This sequentially
retrieved data is used to assemble a
complete fault log. 256 Bytes: 0xFF
R Block
followed by 255 bytes of fault log data.
MFR_COMMON
0xEF Manufacturer status bits that are common
across multiple LTC chips.
R Byte
N
Reg
NA
54
MFR_SPARE_0
MFR_SPARE_1
MFR_SPARE_2
MFR_SPARE_3
MFR_VOUT_MIN
0xF7 Scratchpad register.
R/W Word
R/W Word
R/W Word
R/W Word
R Word
N
N
Y
Y
Y
Reg
Reg
Reg
Reg
L16
Y
Y
Y
Y
0x0000
NA
54
54
54
54
55
0xF8 Manufacturer reserved.
0xF9 Paged scratchpad register.
0xFA Manufacturer reserved.
0x0000
NA
0xFB Minimum measured value of READ_
VOUT.
V
NA
MFR_VIN_MIN
0xFC Minimum measured value of READ_VIN.
R Word
R Word
N
N
L11
L11
V
NA
NA
55
55
MFR_TEMPERATURE_MIN
0xFD Minimum measured value of READ_
TEMPERATURE_1.
°C
2978af
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Data Formats
L11
Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer
Example:
READ_VIN = 10V
For b[15:0] = 0xD280 = 1101_0010_1000_0000b
–6
Value = 640 • 2 = 10
See PMBus Spec Part II: Paragraph 7.1
L16
Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2 where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s complement
exponent that is hardwired to –13 decimal.
Example:
VOUT_COMMAND = 4.75V
For b[15:0] = 0x9800 = 1001_1000_0000_0000b
–13
Value = 38912 • 2 = 4.75
See PMBus Spec Part II: Paragraph 8.3.1
Reg
CF
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Register Description.
Custom Format
PMBus data field b[15:0]
Value is defined in detailed PMBus Command Register Description. This is often an unsigned or two’s complement
integer scaled by an MFR specific constant.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
OPERATION, MODE AND EEPROM COMMANDS
PAGE
TheLTC2978AhaseightpagesthatcorrespondtotheeightDC/DCconverterchannelsthatcanbemanaged. EachDC/DC
converter channel can be uniquely programmed by first setting the appropriate page.
The PAGE command provides the ability to configure, control and monitor multiple outputs on one unit.
SettingPAGE=0xFFallowsasimultaneouswritetoallpagesforPMBuscommandsthatsupportglobalpageprogramming.
The only commands that support PAGE = 0xFF are OPERATION and ON_OFF_CONFIG. See MFR_PAGE_FF_MASK for
additional options. Reading any paged PMBus register with PAGE = 0xFF returns unpredictable data and will trigger
a CML fault.
PAGE Data Contents
BIT(S) SYMBOL PURPOSE
b[7:0] Page Page operation.
0x00: All PMBus commands address channel/page 0.
0x01: All PMBus commands address channel/page 1.
•
•
•
0x07: All PMBus commands address channel/page 7.
0xXX: All nonspecified values reserved.
0xFF: A single PMBus write/send to commands that support this mode will simultaneously address all channels/pages with
MFR_PAGE_FF_MASK enabled.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the CONTROLn pin and ON_OFF_
CONFIG. This command register responds to the global page command (PAGE=0xFF). The contents and functions of
the data byte are shown in the following tables. A minimum t
commands used to turn the unit off and then back on.
wait time must be observed between OPERATION
OFF_MIN
OPERATION Data Contents (On_off_config_use_pmbus=1)
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
00
b[5:4]
XX
b[3:2]
XX
b[1:0]
00
Turn off immediately
Turn on
10
00
XX
00
Margin Low (Ignore Faults and
Warnings)
10
01
01
00
Margin Low
10
10
01
10
10
01
00
00
Margin High (Ignore Faults and
Warnings
Margin High
10
01
10
00
10
00
00
FUNCTION
Sequence off and margin to
nominal
XX
Sequence off and Margin Low
(Ignore Faults and Warnings)
01
01
01
00
Sequence off and Margin Low
01
01
01
10
10
01
00
00
Sequence off and Margin High
(Ignore Faults and Warnings)
Sequence off and Margin High
Reserved
01
10
10
00
All remaining combinations
OPERATION Data Contents (On_off_config_use_pmbus=0)
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
b[5:4]
00
b[3:2]
XX
b[1:0]
00
Output at Nominal
00, 01 or 10
00, 01 or 10
Margin Low (Ignore faults and
Warnings)
01
01
00
Margin Low
00, 01 or 10
00, 01 or 10
01
10
10
01
00
00
FUNCTION
Margin High (Ignore Faults and
Warnings
Margin High
Reserved
00, 01 or 10
10
10
00
All remaining combinations
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LTC2978A
pMbꢀꢁ coMManD DescripTion
ON_OFF_CONFIG
TheON_OFF_CONFIGcommandconfiguresthecombinationofCONTROLnpininputandPMBusbuscommandsneeded
to turn the LTC2978A on/off, including the power-on behavior, as shown in the following table. This command register
responds to the global page command (PAGE=0xFF). After the part has initialized, an additional comparator monitors
VIN_SNS. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After V is initially
IN
applied, the part will typically require t
time to initialize and begin the TON_DELAY timer. The readback of voltages
INIT
and currents may require an additional wait for t
. A minimum t
wait time must be observed for any
UPDATE_ADC
OFF_MIN
CONTROL pin toggle used to turn the unit off and then back on.
ON_OFF_CONFIG Data Contents
BITS(S) SYMBOL
OPERATION
b[7:5]
b[4]
Reserved
Don’t care. Always returns 0.
On_off_config_controlled_on
Controls default autonomous power-up operation.
0: Unit powers up regardless of the CONTROLn pin or OPERATION value. Unit always powers up with
sequencing. To turn unit on without sequencing, set TON_DELAY = 0.
1: Unit does not power up unless commanded by the CONTROLn pin and/or the OPERATION command
on the serial bus. If On_off_config[3:2] = 00, the unit never powers up.
b[3]
b[2]
On_off_config_use_pmbus
On_off_config_use_control
Reserved
Controls how the unit responds to commands received via the serial bus.
0: Unit ignores the Operation_control[1:0] bits.
1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also
require the CONTROLn pin to be asserted for the unit to start.
Controls how unit responds to the CONTROLn pin.
0: Unit ignores the CONTROLn pin.
1: Unit requires the CONTROLn pin to be asserted to start the unit. Depending on On_off_config_use_
pmbus the OPERATION command may also be required to instruct the device to start.
b[1]
b[0]
Not supported. Always returns 1.
On_off_config_control_fast_off CONTROLn pin turn off action when commanding the unit to turn off
0: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible, i.e. pull V
low
OUT_ENn
immediately. The device does not sink current in order to decrease the output voltage fall time.
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any status bits that have been set. This command clears all fault and
warning bits in all unpaged status registers, and the paged status registers selected by the current PAGE setting. At
the same time, the device negates (clears, releases) its contribution to ALERTB.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing
Latched Faults for more information.
If the fault condition is present after the fault status is cleared, the fault status bit shall be set again and the host noti-
fied by the usual means.
Note: This command register does not respond to the global page command (PAGE=0xFF).
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LTC2978A
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WRITE_PROTECT
The WRITE_PROTECT command provides protection against accidental programming of the LTC2978A command
registers. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting.
There are two levels of write protection:
• Level 1: Nothing can be changed except the level of write protection itself. Values can be read from all pages. This
setting can be stored to EEPROM.
• Level 2: Nothing can be changed except for the level of protection, channel on/off state and clearing of faults. Values
can be read from all pages. This setting can be stored to EEPROM.
WRITE_PROTECT Data Contents
BITS(S) SYMBOL
OPERATION
b[7:0] Write_protect[7:0] Level 1: 1000_0000b: Disable all writes except to the WRITE_PROTECT, PAGE, and STORE_USER_ALL commands.
Level 2: 0100_0000b: Disable all writes except to the WRITE_PROTECT, PAGE, STORE_USER_ALL, OPERATION, MFR_
PAGE_FF_MASK, and CLEAR_FAULTS.
0000_0000b: Enable writes to all commands.
xxxx_xxxxb: All other values reserved.
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is
stored in User EEPROM, it will be restored with an explicit restore command or when the part emerges from power-
2
on reset after power is applied. While either of these commands is being processed, the device will NACK I C writes.
STORE_USER_ALL.IssuingthiscommandwillstorealloperatingmemorycommandswithacorrespondingEEPROM
memory location. It is recommended that this command not be executed while a unit is enabled since all monitoring
is suspended while the operating memory is transferred to EEPROM.
RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended
that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is
transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially
stored in operating memory.
CAPABILITY
The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2978A.
This one byte command is read only.
CAPABILITY Data Contents
BITS(S) SYMBOL
OPERATION
b[7]
Capability_pec
Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate
whether PEC is currently required.
b[6]
b[5]
Capability_scl_max
Hard coded to 1 indicating the maximum supported bus speed is 400kHz.
Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response
Protocol.
b[4:0] Reserved
Always returns 0.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
VOUT_MODE
This command is read only and specifies the mode and exponent for all commands with a L16 data format. See Data
Formats table on page 29.
VOUT_MODE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:5] Vout_mode_type
Reports linear mode. Hard wired to 000b.
b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit two’s complement integer. Hardwired to 0x13 (–13 decimal).
OUTPUT VOLTAGE RELATED COMMANDS
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT, VOUT_
OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and POWER_GOOD_OFF
These commands use the same format and provide various servo, margining, and supervising limits for a channel’s
output voltage. When odd channels are configured to measure current, the OV_WARN_LIMIT, UV_WARN_LIMIT,
OV_FAULT_LIMIT and UV_FAULT_LIMIT commands are not supported.
Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Vout_command[15:0],
Vout_max[15:0],
These commands relate to output voltage. The data uses the L16 format.
Units: V
Vout_margin_high[15:0],
Vout_margin_low[15:0],
Vout_ov_fault_limit[15:0],
Vout_ov_warn_limit[15:0],
Vout_uv_warn_limit[15:0],
Vout_uv_fault_limit[15:0],
Power_good_on[15:0],
Power_good_off[15:0]
INPUT VOLTAGE RELATED COMMANDS
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_
FAULT_LIMIT
These commands use the same format and provide voltage supervising limits for the input voltage V
.
IN_SNS
Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Vin_on[15:0],
Vin_off[15:0],
These commands relate to input voltage. The data uses the L11 format.
Units: V.
Vin_ov_fault_limit[15:0],
Vin_ov_warn_limit[15:0],
Vin_uv_warn_limit[15:0],
Vin_uv_fault_limit[15:0]
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LTC2978A
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TEMPERATURE RELATED COMMANDS
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT
These commands provide supervising limits for temperature.
Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Ot_fault_limit[15:0], The data uses the L11 format.
Ot_warn_limit[15:0], Units: °C.
Ut_warn_limit[15:0],
Ut_fault_limit[15:0]
TIMER LIMITS
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY
These commands share the same format and provide sequencing and timer fault and warning delays in ms.
TON_DELAY sets the amount of time in milliseconds that a channel waits following the start of an ON sequence before
its V
pin enables a DC/DC converter. This delay is counted using SHARE_CLK only.
OUT_EN
TON_RISE sets the amount of time in ms that elapses after the power supply has been enabled until the LTC2978A’s
DAC soft-connects and servos the output voltage to the desired level if Mfr_dac_mode = 00b. This delay is counted
using SHARE_CLK only.
TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2978A
can attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If the output reaches VOUT_UV_
FAULT_LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2978A unmasks the VOUT_UV_FAULT_LIMIT threshold. If
it does not, then a TON_MAX_FAULT is declared. (Note that a value of zero means there is no limit to how long the
power supply can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only.
TOFF_DELAY is the amount of time that elapses after the CONTROLn pin and/or OPERATION command is deasserted
until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used.
Data Contents
BIT(S) SYMBOL
b[15:0] Ton_delay[15:0],
Ton_rise[15:0],
OPERATION
The data uses the L11 format.
The internal timers operate on a 10µs internal clock. The SHARE_CLK pin may be used to synchronize the
10µs timer.
Ton_max_fault_limit[15:0],
Delays are rounded to the nearest 10µs
Units: ms. Max value: 655ms
Toff_delay[15:0],
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LTC2978A
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FAULT RESPONSE FOR VOLTAGES MEASURED BY THE HIGH SPEED SUPERVISOR
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2978A will also:
• Set the appropriate bit(s) in the STATUS_BYTE
• Set the appropriate bit(s) in the STATUS_WORD
•
Set the appropriate bit in the corresponding STATUS_VOUT register, and
• Notify the host by pulling the ALERTB pin low.
Note: Odd numbered channels configured for high resolution ADC measurements (current measurements) will not
respond to OV/UV faults or warnings.
Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Vout_ov_fault_response_action, Response action:
Vout_uv_fault_response_action 00b: The unit continues operation without interruption.
01b: The unit continues operating for the delay time specified by bits[2:0] in increments of ts_vs. (See
Electrical Characteristics Table, Voltage Supervisor Characteristics section).
If the fault is still present at the end of the delay time, the unit shuts down and responds as programmed in
the retry setting (bits [5:3]).
1Xb: The device shuts down and responds according to the retry setting in bits [5:3].
Response retry behavior:
b[5:3] Vout_ov_fault_response_retry,
Vout_uv_fault_response_retry
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart continuously, without limitation, at intervals of Mfr_retry_
delay, until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Vout_ov_fault_response_delay, This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
Vout_uv_fault_response_delay
000b: The unit turns off immediately.
001b-111b: The unit turns off after b[2:0] samples at the sampling period of ts_vs (12.2µs typical).
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LTC2978A
pMbꢀꢁ coMManD DescripTion
FAULT RESPONSE FOR VALUES MEASURED BY THE ADC
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE
The fault response documented here is for values that are measured by the ADC. These values are measured over a
longer period of time and are not deglitched. Note that in addition to the response described by these commands, the
LTC2978A will also:
• Set the appropriate bit(s) in the STATUS_BYTE
• Set the appropriate bit(s) in the STATUS_WORD
• Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and
• Notify the host by pulling the ALERTB pin low.
Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ot_fault_response_action,
Ut_fault_response_action,
Response action:
00b: The unit continues operation without interruption.
Vin_ov_fault_response_action, 01b to 11b: The device shuts down and responds according to the retry setting in bits [5:3].
Vin_uv_fault_response_action
b[5:3] Ot_fault_response_retry,
Response retry behavior:
Ut_fault_response_retry,
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
001b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
Hard coded to 000b. There is no additional deglitch delay applied to fault detection.
b[2:0] Ot_fault_response_delay,
Ut_fault_response_delay,
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
TIMED FAULT RESPONSE
TON_MAX_FAULT_RESPONSE
This command defines the LTC2978A response to a TON_MAX_FAULT. It may be used to protect against a short-
circuitedoutputatstart-up. Afterstart-upuseVOUT_UV_FAULT_RESPONSEtoprotectagainstashort-circuitedoutput.
The device also:
• Sets the HIGH_BYTE bit in the STATUS_BYTE,
• Sets the VOUT bit in the STATUS_WORD,
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and
• Notifies the host by asserting ALERTB.
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LTC2978A
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TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
b[7:6] Ton_max_fault_response_action Response action:
00b: The unit continues operation without interruption.
OPERATION
01b: The unit continues operating for the delay time specified which for this type of fault corresponds to an
immediate shutdown. After shutting off, the device responds according to the retry settings in bits [5:3].
1Xb: The device shuts down and responds according to the retry setting in bits [5:3].
Response retry behavior:
b[5:3] Ton_max_fault_response_retry
000b: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Ton_max_fault_response_delay Hard coded to 000b. There is no additional deglitch delay applied to fault detection.
Clearing Latched Faults
When a channel shuts down due to a fault, the off state is latched. This is referred to as a latched fault condition. Latched
faults are reset by toggling the CONTROL pin, using the OPERATION or ON_OFF_CONFIG command, or removing and
reapplying the bias voltage to the V
pin. All fault and warning conditions result in the ALERTB pin being asserted
IN_SNS
low and the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents
of the status registers and de-asserts the ALERTB output, but it does not clear a faulted off state nor allow a channel
to turn back on.
After resetting the faults, ALERTB will be de-asserted. If using a CONTROL pin toggle that does not affect all channels,
a non-global OPERATION or ON_OFF_CONFIG command, or a CLEAR_FAULTS command, check the Status_word of
all other channels to make sure no additional faults are reported.
STATUS COMMANDS
STATUS_BYTE:
The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as
shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information.
STATUS_BYTE Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Status_byte_busy
Same as Status_word_busy
Same as Status_word_off
Same as Status_word_vout_ov
Same as Status_word_iout_oc
Same as Status_word_vin_uv
Same as Status_word_temp
Same as Status_word_cml
Same as Status_word_high_byte
Status_byte_off
Status_byte_vout_ov
Status_byte_iout_oc
Status_byte_vin_uv
Status_byte_temp
Status_byte_cml
Status_byte_high_byte
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LTC2978A
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STATUS_WORD:
The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on
the information in these bytes, the host can get more information by reading the appropriate detailed status register.
The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
STATUS_WORD Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Status_word_vout
b[14] Status_word_iout
b[13] Status_word_input
b[12] Status_word_mfr
An output voltage fault or warning has occurred. See STATUS_VOUT.
Notsupported.Alwaysreturns0.
An input voltage fault or warning has occurred. See STATUS_INPUT.
A manufacturer specific fault has occurred. See STATUS_MFR_SPECIFIC.
b[11] Status_word_power_not_good The PWRGD pin, if enabled, is negated. Power is not good.
b[10] Status_word_fans
Notsupported.Alwaysreturns0.
b[9]
b[8]
b[7]
b[6]
Status_word_other
Status_word_unknown
Status_word_busy
Status_word_off
Notsupported.Alwaysreturns0.
Notsupported.Alwaysreturns0.
Device busy when PMBus command received. See OPERATION: Processing Commands.
This bit is asserted if the unit is not providing power to the output, regardless of the reason, including
simply not being enabled. The off bit is clear if unit is allowed to provide power to the output.
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Status_word_vout_ov
Status_word_iout_oc
Status_word_vin_uv
Status_word_temp
Status_word_cml
An output overvoltage fault has occurred.
Notsupported.Alwaysreturns0.
A V undervoltage fault has occurred.
IN
A temperature fault or warning has occurred. See STATUS_TEMPERATURE.
A communication, memory or logic fault has occurred. See STATUS_CML.
A fault/warning not listed in b[7:1] has occurred.
Status_word_high_byte
STATUS_VOUT
The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as
shown in the following table:
STATUS_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_vout_ov_fault
b[6] Status_vout_ov_warn
b[5] Status_vout_uv_warn
b[4] Status_vout_uv_fault
b[3] Status_vout_max_fault
Overvoltage fault.
Overvoltage warning.
Undervoltage warning
Undervoltage fault.
VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the
VOUT_MAX command. After being cleared, Status_vout_max_fault will not report additional faults until a
channel state transition (off-then-on) has been performed or a valid output voltage, lower than allowed by
VOUT_MAX, has been set.
b[2] Status_vout_ton_max_fault
b[1] Status_vout_toff_max_warn
b[0] Status_vout_tracking_error
TON_MAX_FAULT sequencing fault.
Not supported. Always returns 0.
Not supported. Always returns 0.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
STATUS_INPUT
The STATUS_INPUT command returns the summary of the V faults or warnings which have occurred, as shown in
IN
the following table:
STATUS_INPUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Status_input_ov_fault
V
V
V
V
Overvoltage fault
IN
IN
IN
IN
Status_input_ov_warn
Status_input_uv_warn
Status_input_uv_fault
Status_input_off
Overvoltage warning
Undervoltage warning
Undervoltage fault
Unit is off for insufficient input voltage.
Not supported. Always returns 0.
Not supported. Always returns 0.
Not supported. Always returns 0.
I
IN
I
IN
overcurrent fault
overcurrent warn
PIN overpower warn
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have oc-
curred, as shown in the following table:
STATUS_TEMPERATURE Data Contents
Bit(s) Symbol
Operation
b[7] Status_temperature_ot_fault
Overtemperature fault.
b[6] Status_temperature_ot_warn Overtemperature warning.
b[5] Status_temperature_ut_warn Undertemperature warning.
b[4] Status_temperature_ut_fault
b[3] Reserved
Undertemperature fault.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
b[2] Reserved
b[1] Reserved
b[0] Reserved
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STATUS_CML
The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which
have occurred, as shown in the following table:
STATUS_CML Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_cml_cmd_fault
b[6] Status_cml_data_fault
b[5] Status_cml_pec_fault
Illegal or unsupported command fault has occurred.
Illegal or unsupported data received.
A PEC fault has occurred. Note: PEC checking is always active in the LTC2978A. Any extra byte received before a
STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte.
b[4] Status_cml_memory_fault
A fault has occurred in the EEPROM. The CLEAR_FAULTS command will clear this bit, but correct operation
should not be assumed until a successful retry of the failing EEPROM access has occurred.
b[3] Status_cml_processor_fault Not supported, always returns 0.
b[2] Reserved
Reserved, always returns 0.
b[1] Status_cml_pmbus_fault
A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally
2
formed I C/SMBus commands (Example: An address byte with read =1 received immediately after a START).
b[0] Status_cml_unknown_fault Not supported, always returns 0.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked CHANNEL = All are
not paged. Bits marked STICKY = Yes stay set until a CLEAR_FAULTS is issued or the channel is commanded on by the
user. Bits marked ALERT = Yes pull ALERTB low when the bit is set. Bits marked OFF = Yes indicate that the event can
be configured elsewhere to turn the channel off.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL
OPERATION
CHANNEL
STICKY ALERT
OFF
b[7] Status_mfr_discharge
A V
discharge fault occurred while attempting to enter
Current Page
Yes
Yes
Yes
OUT
the ON state
b[6] Status_mfr_fault1_in
b[5] Status_mfr_fault0_in
This channel attempted to turn on while the FAULTBz1 pin
was asserted low, or this channel has shut down at least
once in response to a FAULTBz1 pin asserting low since the
last CONTROLn pin toggle, OPERATION command ON/OFF
cycle or CLEAR_FAULTS command.
Current Page
Yes
Yes
Yes
This channel attempted to turn on while the FAULTBz0 pin
was asserted low, or this channel has shut down at least
once in response to a FAULTBz0 pin asserting low since the
last CONTROLn pin toggle, OPERATION command ON/OFF
cycle or CLEAR_FAULTS command.
Current Page
Yes
Yes
Yes
b[4] Status_mfr_servo_target_reached Servo target has been reached.
Current Page
Current Page
Current Page
No
No
No
No
No
No
No
No
b[3] Status_mfr_dac_connected
b[2] Status_mfr_dac_saturated
DAC is connected and driving V
pin.
DACP
A previous servo operation terminated with maximum or
minimum DAC value.
Yes
b[1] Status_mfr_vinen_faulted_off
b[0] Status_mfr_watchdog_fault
V
has been deasserted due to a V
fault.
All
All
No
No
No
No
IN_EN
OUT
A watchdog fault has occurred.
Yes
Yes
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LTC2978A
pMbꢀꢁ coMManD DescripTion
ADC MONITORING COMMANDS
READ_VIN
This command returns the most recent ADC measured value of the voltage measured at the V
pin.
IN_SNS
READ_VIN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Read_vin[15:0] The data uses the L11 format.
Units: V
READ_VOUT
This command returns the most recent ADC measured value of the channel’s output voltage. When odd channels are
configured to measure current, the data contents use the L11 format with units in mV.
READ_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Read_vout[15:0] The data uses the L16 format.
Units: V
READ_VOUT Data Contents—for Odd Channels Configured to Measure Current (Mfr_config_adc_hires = 1)
Bit(s) Symbol
Operation
The data uses the L11 format.
Units: mV
b[15:0] Read_vout[15:0]
READ_TEMPERATURE_1
This command returns the most recent ADC measured value of junction temperature in °C as determined by the
LTC2978A’s internal temperature sensor.
READ_TEMPERATURE_1 Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Read_temperature_1 [15:0] The data uses the L11 format.
Units: °C.
PMBUS_REVISION
The PMBUS_REVISION command register is read only and reports the LTC2978A compliance to the PMBus standard
revision 1.1.
PMBUS_REVISION Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] PMBus_rev Reports the PMBus standard revision compliance. This is hard-coded to 0x11 for revision 1.1.
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LTC2978A
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MANUFACTURER SPECIFIC COMMANDS
MFR_CONFIG_LTC2978
This command is used to configure various manufacturer specific operating parameters for each channel.
MFR_CONFIG_LTC2978 Data Contents
BIT(S) SYMBOL
OPERATION
b[15:12] Reserved
Don’t care. Always returns 0.
b[11] Mfr_config_fast_servo_off
Disables fast servo when margining or trimming output voltages:
0: fast-servo enabled.
1: fast-servo disabled.
b[10] Mfr_config_supervisor_resolution Selects supervisor resolution:
0: high resolution – 4mV/LSB, range for V
– V
is 0V to 3.8V.
is 0V to 6.0V.
VSENSEPn
VSENSEMn
1: low resolution – 8mV/LSB, range for V
– V
VSENSEPn
VSENSEMn
b[9] Mfr_config_adc_hires
Selects ADC resolution for odd channels. This is typically used to measure current. Ignored for even
channels (they always use low resolution).
0: low resolution – 122µV/LSB.
1: high resolution – 15.6µV/LSB.
b[8] Mfr_config_controln_sel
Selects the active control pin input (CONTROL0 or CONTROL1) for this channel.
0: Select CONTROL0 pin.
1: Select CONTROL1 pin.
b[7] Mfr_config_servo_continuous
Select whether the UNIT should continuously servo V
after it has reached a new margin or nominal
OUT
target. Only applies when Mfr_config_dac_mode = 00b.
0: Do not continuously servo V after reaching initial target.
OUT
1: Continuously servo V
to target.
OUT
b[6] Mfr_config_servo_on_warn
b[5:4] Mfr_config_dac_mode
Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 00b and
Mfr_config_servo_continuous = 0.
0: Do not allow the unit to re-servo when a V
warning threshold is met or exceeded.
OUT
1: Allow the unit to re-servo V
to nominal target if
OUT
V
V
≥ V(Vout_ov_warn_limit) or
≤ V(Vout_uv_warn_limit).
OUT
OUT
Determines how DAC is used when channel is in the ON state and TON_RISE has elapsed.
00: Soft-connect (if needed) and servo to target.
01: DAC not connected.
10: DAC connected immediately using value from MFR_DAC command. If this is the configuration after a
reset or RESTORE_USER_ALL, MFR_DAC will be undefined and must be written to desired value.
11: DAC is soft-connected. After soft-connect is complete MFR_DAC may be written.
b[3] Mfr_config_vo_en_wpu_en
b[2] Mfr_config_vo_en_wpd_en
V
pin charge-pumped, current-limited pull-up enable.
OUT_EN
0: Disable weak pull-up. V
1: Use weak current-limited pull-up on V
For channels 4-7 this bit is treated as a 0 regardless of its value.
pin driver is three-stated when channel is on.
OUT_EN
pin when the channel is on.
OUT_EN
V
pin current-limited pull-down enable.
OUT_EN
0: Use a fast N-channel device to pull down V
pin when the channel is off for any reason.
OUT_EN
1: Use weak current-limited pull-down to discharge V
pin when channel is off due to soft stop by the
OUT_EN
CONTROLn pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down on
V
pin.
OUT_EN
For channels 4-7 this bit is treated as a 0 regardless of its value.
b[1] Mfr_config_dac_gain
DAC buffer gain.
0: Select DAC buffer gain dac_gain_0 (1.38V full-scale)
1: Select DAC buffer gain dac_gain_1 (2.65V full-scale)
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_CONFIG_LTC2978 Data Contents
BIT(S) SYMBOL
OPERATION
b[0] Mfr_config_dac_pol
DAC output polarity.
0: Encodes negative (inverting) DC/DC converter trim input.
1: Encodes positive (noninverting) DC/DC converter trim input.
MFR_CONFIG_ALL_LTC2978
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2978 Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_config_all_fault_log_enable
Enable fault logging to EEPROM in response to Fault.
0: Fault logging to EEPROM is disabled
1: Fault logging to EEPROM is enabled
b[6] Mfr_config_all_vin_on_clr_faults_en Allow V rising above VIN_ON to clear all latched faults
IN
0: VIN_ON clear faults feature is disabled
1: VIN_ON clear faults feature is enabled
b[5] Mfr_config_all_control1_pol
b[4] Mfr_config_all_control0_pol
b[3] Mfr_config_all_vin_share_enable
Selects active polarity of CONTROL1 pin.
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
Selects active polarity of CONTROL0 pin.
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
Allow this unit to hold SHARE_CLK pin low when V has not risen above VIN_ON or has fallen below
VIN_OFF. When enabled, this unit will also turn all channels off in response to share-clock being held
low.
IN
0: SHARE_CLK inhibit is disabled
1: SHARE_CLK inhibit is enabled
b[2] Mfr_config_all_pec_en
PMBus packet error checking enable.
0: PEC is accepted but not required
1: PEC is required
b[1] Mfr_config_all_longer_pmbus_
timeout
Increase PMBus timeout internal by a factor of 8. Recommended for fault logging.
0: PMBus timeout is not multiplied by a factor of 8
1: PMBus timeout is multiplied by a factor of 8
b[0] Mfr_config_all_vinen_wpu_dis
V
IN_EN
charge-pumped, current-limited pull-up disable.
0: Use weak current-limited pull-up on V
off.
after power-up, as long as no faults have forced V
IN_EN
IN_EN
1: Disable weak pull-up. V
IN_EN
driver is three-stated after power-up as long as no faults have forced
IN_EN
V
off.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_FAULTBz0_PROPAGATE, MFR_FAULTBz1_PROPAGATE
These manufacturer specific commands enable channels that have faulted off to propagate that state to the appropri-
ate fault pin. Faulted off states for pages 0 through 3 can only be propagated to pins FAULTB00 and FAULTB01; this is
referred to as zone 0. Faulted off states for pages 4 through 7 can only be propagated to pins FAULTB10 and FAULTB11;
this is referred to as zone 1. The z designator in the command name is used to indicate that this command affects
different zones depending on the page. See Figure 19.
Note that pulling a fault pin low will have no effect for channels that have MFR_FAULTBzn_RESPONSE set to 0. The
channel continues operation without interruption. This fault response is called Ignore (0x0) in LTpowerPlay.
MFR_FAULTBz0_PROPAGATE Data Content
BIT(S) SYMBOL
OPERATION
b[7:1]
b[0]
Reserved
Don’t care. Always returns 0.
Enable fault propagation.
Mfr_faultbz0_propagate
For pages 0 through 3, zone 0
0: Channel’s faulted off state does not assert FAULTB00 low.
1: Channel’s faulted off state asserts FAULTB00 low.
For pages 4 through 7, zone 1
0: Channel’s faulted off state does not assert FAULTB10 low.
1: Channel’s faulted off state asserts FAULTB10 low.
MFR_FAULTBz1_PROPAGATE Data Content
BIT(S) SYMBOL OPERATION
b[7:1]
b[0]
Reserved
Don’t care. Always returns 0.
Mfr_faultbz1_propagate
Enable fault propagation.
For pages 0 through 3, zone 0
0: Channel’s faulted off state does not assert FAULTB01 low.
1: Channel’s faulted off state asserts FAULTB01 low.
For pages 4 through 7, zone 1
0: Channel’s faulted off state does not assert FAULTB11 low.
1: Channel’s faulted off state asserts FAULTB11 low.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin. Note
that odd numbered channels whose ADC is in high res mode do not contribute to power good.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:9] Reserved
Read only, always returns 0s.
Watchdog
b[8] Mfr_pwrgd_en_wdog
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to
determine when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
Channel 7
b[7] Mfr_pwrgd_en_chan7
b[6] Mfr_pwrgd_en_chan6
b[5] Mfr_pwrgd_en_chan5
b[4] Mfr_pwrgd_en_chan4
b[3] Mfr_pwrgd_en_chan3
b[2] Mfr_pwrgd_en_chan2
b[1] Mfr_pwrgd_en_chan1
b[0] Mfr_pwrgd_en_chan0
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 6
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 5
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 4
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 3
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 2
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 1
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
Channel 0
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_FAULTB00_RESPONSE, MFR_FAULTB01_RESPONSE, MFR_FAULTB10_RESPONSE and MFR_
FAULTB11_RESPONSE
These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB
pins. For fault zone 0, MFR_FAULTB00_RESPONSE determines whether channels 0 to 3 shut off when the FAULTB00
pin is asserted, and MFR_FAULTB01_RESPONSE determines whether channels 0 to 3 shut off when the FAULTB01
pin is asserted. For fault zone 1, MFR_FAULTB10_RESPONSE determines whether channels 4 to 7 shut off when the
FAULTB10 pin is asserted, and MFR_FAULTB11_RESPONSE determines whether channels 4 to 7 shut off when the
FAULTB11 pin is asserted. When a channel shuts off in response to a FAULTB pin, the ALERTB pin is asserted low and
the appropriate bit is set in the STATUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the
left hand side of Figure 19, Channel Fault Management Block Diagram.
Data Contents—Fault Zone 0 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0s.
b[3] Mfr_faultb00_response_chan3, Channel 3 response.
Mfr_faultb01_response_chan3 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb00_response_chan2, Channel 2 response.
Mfr_faultb01_response_chan2 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb00_response_chan1, Channel 1 response.
Mfr_faultb01_response_chan1 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0] Mfr_faultb00_response_chan0, Channel 0 response.
Mfr_faultb01_response_chan0 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
Data Contents—Fault Zone 1 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0s.
b[3] Mfr_faultb10_response_chan7, Channel 7 response.
Mfr_faultb11_response_chan7 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb10_response_chan6, Channel 6 response.
Mfr_faultb11_response_chan6 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb10_response_chan5, Channel 5 response.
Mfr_faultb11_response_chan5 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0] Mfr_faultb10_response_chan4, Channel 4 response.
Mfr_faultb11_response_chan4 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_VINEN_OV_FAULT_RESPONSE
This command register determines whether V
pulled low.
overvoltage faults from a given channel cause the V
pin to be
IN_EN
OUT
MFR_VINEN_OV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
Response to channel 7 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
b[7] Mfr_vinen_ov_fault_response_chan7
IN_EN
0 = Do not disable V
.
IN_EN
b[6] Mfr_vinen_ov_fault_response_chan6
b[5] Mfr_vinen_ov_fault_response_chan5
b[4] Mfr_vinen_ov_fault_response_chan4
b[3] Mfr_vinen_ov_fault_response_chan3
b[2] Mfr_vinen_ov_fault_response_chan2
b[1] Mfr_vinen_ov_fault_response_chan1
b[0] Mfr_vinen_ov_fault_response_chan0
Response to channel 6 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 5 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 4 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 3 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 2 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 1 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 0 VOUT_OV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_VINEN_UV_FAULT_RESPONSE
This command register determines whether V
pulled low.
undervoltage faults from a given channel cause the V
pin to be
IN_EN
OUT
MFR_VINEN_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
Response to channel 7 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
b[7] Mfr_vinen_uv_fault_response_chan7
IN_EN
0 = Do not disable V
.
IN_EN
b[6] Mfr_vinen_uv_fault_response_chan6
b[5] Mfr_vinen_uv_fault_response_chan5
b[4] Mfr_vinen_uv_fault_response_chan4
b[3] Mfr_vinen_uv_fault_response_chan3
b[2] Mfr_vinen_uv_fault_response_chan2
b[1] Mfr_vinen_uv_fault_response_chan1
b[0] Mfr_vinen_uv_fault_response_chan0
Response to channel 6 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 5 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 4 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 3 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 2 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 1 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
Response to channel 0 VOUT_UV_FAULT.
1 = Disable (pull low) V via fast pull-down.
IN_EN
0 = Do not disable V
.
IN_EN
MFR_RETRY_DELAY
ThiscommanddeterminestheretryintervalwhentheLTC2978Aisinretrymodeinresponsetoafaultcondition.Theread
valueofthiscommandalwaysreturnswhatwaslastwrittenanddoesnotreflectinternallimiting.
MFR_RETRY_DELAY Data Contents
BIT(S) SYMBOL
b[15:0] Mfr_retry_delay The data uses the L11 format.
This delay is counted using SHARE_CLK only.
OPERATION
Delays are rounded to the nearest 200µs.
Units: ms. Max delay is 13.1 sec.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_RESTART_DELAY
ThiscommandsetstheminimumofftimeofaCONTROLinitiatedrestart.IftheCONTROLpinistoggledoffforatleast10µs
thenon,alldependentchannelsaredisabled,heldoffforatime=Mfr_restart_delay,thensequencedbackon.CONTROLn
pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value of all zeros disables
thisfeature.Thereadvalueofthiscommandalwaysreturnswhatwaslastwrittenanddoesnotreflectinternallimiting.
MFR_RESTART_DELAY Data Contents
BIT(S) SYMBOL
b[15:0] Mfr_restart_delay The data uses the L11 format.
This delay is counted using SHARE_CLK only.
OPERATION
Delays are rounded to the nearest 200µs.
Units: ms. Max delay is 13.1 sec.
MFR_VOUT_PEAK
This command returns the maximum ADC measured value of the channel’s output voltage. This command is not
supported for odd channels that are configured to measure current. This register is reset to 0xF800 (0.0) when the
LTC2978A emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_vout_peak[15:0] The data uses the L16 format.
Units: V.
MFR_VIN_PEAK
25
This command returns the maximum ADC measured value of the input voltage. This register is reset to 0x7C00 (–2 )
when the LTC2978A emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VIN_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_vin_peak[15:0] The data uses the L11 format.
Units: V
MFR_TEMPERATURE_PEAK
ThiscommandreturnsthemaximumADCmeasuredvalueofjunctiontemperaturein°CasdeterminedbytheLTC2978A’s
25
internal temperature sensor. This register is reset to 0x7C00 (–2 ) when the LTC2978A emerges from power-on reset
or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_temperature_peak[15:0] The data uses the L11 format.
Units: °C.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_DAC
This command register allows the user to directly program the 10-bit DAC. Manual DAC writes require the channel
to be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2978 b[5:4] = 10b or 11b. Writing MFR_
CONFIG_LTC2978 b[5:4] = 10b commands the DAC to hard-connect with the value in Mfr_dac_direct_val. Writing
b[5:4] = 11b commands the DAC to soft-connect. Once the DAC has soft-connected, Mfr_dac_direct_val returns the
value that allowed the DAC to be connected without perturbing the power supply. MFR_DAC writes are ignored when
MFR_CONFIG_LTC2978 b[5:4] = 00b or 01b.
MFR_DAC Data Contents
BIT(S) SYMBOL
OPERATION
b[15:10] Reserved
Read only, always returns 0.
b[9:0] Mfr_dac_direct_val DAC code value.
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power good signal becomes valid
until the power good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value
of this command always returns what was last written and does not reflect internal limiting.
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
BIT(S) SYMBOL
b[15:0] Mfr_powergood_assertion_delay The data uses the L11 format.
This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used.
OPERATION
Delays are rounded to the nearest 200µs.
Units: ms. Max delay is 13.1 sec.
WATCHDOG OPERATION
A non zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the
WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output
is optionally deasserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the
MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the PWRGD pin, assuming the PWRGD pin reflects the status of the watchdog timer. If assertion
of PWRGD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first
timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables
the watchdog timer.
The MFR_WATCHDOG_T register allows the user to program watchdog time intervals subsequent to the MFR_
WATCHDOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the
watchdog timer. A non-zero write to MFR_WATCHDOG_T will reset the watchdog timer.
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_watchdog_t_first The data uses the L11 format.
Mfr_watchdog_t
These timers operate on an internal clock. The Mfr_watchdog_t timer will align to SHARE_CLK if it is running.
Delays are rounded to the nearest 10µs for _t and 1ms for _t_first.
Writing a zero value for Y to the Mfr_watchdog_t or Mfr_watchdog_t_first registers will disable the watchdog timer.
Units: ms. Max timeout is 0.6 sec for _t and 65 sec for _t_first
MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command
(PAGE=0xFF) is in use.
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_page_ff_mask_chan7
Channel 7 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 6 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
b[6] Mfr_page_ff_mask_chan6
b[5] Mfr_page_ff_mask_chan5
b[4] Mfr_page_ff_mask_chan4
b[3] Mfr_page_ff_mask_chan3
b[2] Mfr_page_ff_mask_chan2
b[1] Mfr_page_ff_mask_chan1
b[0] Mfr_page_ff_mask_chan0
1 = fully respond to global page command accesses
Channel 5 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 4 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 3 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 2 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 1 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 0 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
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LTC2978A
pMbꢀꢁ coMManD DescripTion
MFR_PADS
The MFR_PADS command provides read only access to slow frequency digital pads (pins). The input values presented
in bits[9:0] are before any deglitching logic.
MFR_PADS Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Mfr_pads_pwrgd_drive
0 = PWRGD pad is being driven low by this chip
1 = PWRGD pad is not being driven low by this chip
0 = ALERTB pad is being driven low by this chip
1 = ALERTB pad is not being driven low by this chip
b[14] Mfr_pads_alertb_drive
b[13:10] Mfr_pads_faultb_drive[3.0] Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for
FAULTB11 pad as follows:
0 = FAULTBzn pad is being driven low by this chip
1 = FAULTBzn pad is not being driven low by this chip
b[9:8] Mfr_pads_asel1[1:0]
b[7:6] Mfr_pads_asel0[1:0]
11: Logic high detected on ASEL1 input pad
10: ASEL1 input pad is floating
01: Reserved
00: Logic low detected on ASEL1 input pad
11: Logic high detected on ASEL0 input pad
10: ASEL0 input pad is floating
01: Reserved
00: Logic low detected on ASEL0 input pad
1: Logic high detected on CONTROL1 pad
0: Logic low detected on CONTROL1 pad
1: Logic high detected on CONTROL0 pad
0: Logic low detected on CONTROL0 pad
b[5] Mfr_pads_control1
b[4] Mfr_pads_control0
b[3:0] Mfr_pads_faultb[3:0]
Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for
FAULTB11 pad as follows:
1: Logic high detected on FAULTBzn pad
0: Logic low detected on FAULTBzn pad
MFR_I2C_BASE_ADDRESS
2
The MFR_I2C_BASE_ADDRESS command determines the base value for the I C/SMBus address byte. Offsets of 0
2
to 9 are added to this base address to make the device I C/SMBus address. The part responds to the device address.
MFR_I2C_BASE_ADDRESS Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Reserved
Read only, always returns 0.
2
b[6:0] i2c_base_address This 7-bit value determines the base value of the 7-bit I C/SMBus address. See Operation Section: Device Address.
MFR_SPECIAL_ID
This register contains the manufacturer ID for the LTC2978A.
MFR_SPECIAL_ID Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_special_id
Read only, always returns 0x0124.
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MFR_SPECIAL_LOT
These paged registers contain information that identifies the user configuration that was programmed at the factory.
MFR_SPECIAL_LOT Data Contents
BIT(S)
SYMBOL
OPERATION
b[7:0]
Mfr_special_lot
Contains the LTC default special lot number. Contact the factory to request a custom factory programmed user configu-
ration and special lot number.
MFR_VOUT_DISCHARGE_THRESHOLD
This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold
voltage for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_
THRESHOLD • VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, the Status_
mfr_discharge bit in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In
addition, the channel will not enter the ON state until the output has decayed below its OFF threshold voltage. Setting
this to a value greater than 1.0 effectively disables DISCHARGE_THRESHOLD checking, allowing the channel to turn
back on even if it has not decayed at all.
Other channels can be held off if a particular output has failed to discharge by using the bidirectional FAULTBzn pins
(refer to the MFR_FAULTBzn_RESPONSE and MFR_FAULTBzn_PROPAGATE registers).
MFR_VOUT_DISCHARGE_THRESHOLD Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_vout_discharge_ The data uses the L11 format.
threshold
Units: Dimensionless, this register contains a coefficient.
MFR_COMMON
This command returns status information for the share-clock pin (SHARE_CLK) and the write-protect pin (WP).
MFR_COMMON Data Contents
BIT(S)
b[7:2]
b[1]
SYMBOL
OPERATION
Reserved
Read only, always returns 0s
Returns status of share-clock pin
1: Share-clock pin is being held low
0: Share-clock pin is active
Returns status of write-protect pin
1: Write-protect pin is high
0: Write-protect pin is low
Mfr_common_
share_clk
b[0]
Mfr_common_
write_protect
MFR_SPARE_0, MFR_SPARE_1, MFR_SPARE_2, MFR_SPARE_3
These registers are provided as user scratchpad and additional manufacturer reserved locations.
MFR_SPARE_1 and MFR_SPARE_3 are all reserved for manufacturer use. Such uses include manufacturer traceability
information and LTpowerPlay features like the CRC calculation and storage for user EEPROM configurations.
MFR_SPARE_0 and MFR_SPARE_2 are available for user scratchpad use. These 18 bytes (1 unpaged word plus 8
paged words) might be used for traceability or revision information such as serial number, board model number, as-
sembly location, or assembly date.
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All MFR_SPARE registers may be stored and recalled from EEPROM using the STORE_USER_ALL and RESTORE_
USER_ALL commands.
MFR_VOUT_MIN
This command returns the minimum ADC measured value of the channel’s output voltage. This register is
reset to 0xFFFF (7.999) when the LTC2978A emerges from power-on reset or when a CLEAR_FAULTS com-
mand is executed. When odd channels are configured to measure current, this command is not supported.
Updates are disabled when undervoltage detection is disabled, such as when Margin Low (Ignore Faults and
Warnings) is enabled.
MFR_VOUT_MIN Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_vout_min
The data uses the L16 format.
Units: V.
MFR_VIN_MIN
This command returns the minimum ADC measured value of the input voltage. This register is reset to 0x7BFF
25
(approximately 2 ) when the LTC2978A emerges from power-on reset or when a CLEAR_FAULTS command is ex-
ecuted. Updates are disabled when unit is off for insufficient input voltage.
MFR_VIN_MIN Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_vin_min
The data uses the L11 format.
Units: V.
MFR_TEMPERATURE_MIN
ThiscommandreturnstheminimumADCmeasuredvalueofjunctiontemperaturein°CasdeterminedbytheLTC2978A’s
25
internal temperature sensor. This register is reset to 0x7BFF (approximately 2 ) when the LTC2978A emerges from
power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_MIN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_temperature_min The data uses the L11 format.
Units: °C.
FAULT LOG OPERATION
A conceptual diagram of the fault log is shown in Figure 13. The fault log provides black box capability to the LTC2978A.
During normal operation, the contents of the status registers, the output voltage/current readings, temperature readings
as well as peak and min values of these quantities are stored in a continuously updated buffer in RAM. You can think
of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM
for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log being
available for reading at a later time.
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RAM 255 BYTES
EEPROM 255 BYTES
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
.
.
.
.
.
.
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
2978a F13
Figure 13. Fault Log Conceptual Diagram
MFR_FAULT_LOG_STORE
This command allows the user to transfer data from the RAM buffer to EEPROM.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a
restore the RAM buffer is locked until a successful MFR_FAULT_LOG read or MFR_FAULT_LOG_CLEAR.
MFR_FAULT_LOG_CLEAR
This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will
be erased by this operation and logging of the fault log RAM to EEPROM will be enabled. Make sure that Mfr_fault_
log_status_ram = 0 before issuing the MFR_FAULT_LOG_CLEAR command.
MFR_FAULT_LOG_STATUS
Read only. This register is used to manage fault log events.
Mfr_fault_log_status_eepromissetafteraMFR_FAULT_LOG_STOREcommandorafaulted-offeventtriggersatransfer
of the fault log from RAM to EEPROM. This bit is cleared by a MFR_FAULT_LOG_CLEAR command.
Mfr_fault_log_status_ram is set after a MFR_FAULT_LOG_RESTORE to indicate that the data in the RAM has been
restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful
execution of an MFR_FAULT_LOG command, or by a successful execution of an MFR_FAULT_LOG_CLEAR command.
MFR_FAULT_LOG_STATUS Data Contents
BIT(S) SYMBOL
OPERATION
b[1] Mfr_fault_log_status_ram
Fault log RAM status:
0: The fault log RAM allows updates.
1: The fault log RAM is locked until the next Mfr_fault_log read.
b[0] Mfr_fault_log_status_eeprom Fault log EEPROM status:
0: The transfer of the fault log RAM to the EEPROM is enabled.
1: The transfer of the fault log RAM to the EEPROM is inhibited.
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MFR_FAULT_LOG
Table 2. Data Block Contents
DATA
Position_last[7:0]
BYTE* DESCRIPTION
Read only. This 2040-bit (255 byte) data block contains
a copy of the RAM buffer fault log. The RAM buffer is
continuously updated after each ADC conversion as long
as Mfr_fault_log_status_ram is clear.
0
Position of fault log pointer
when fault occurred.
SharedTime[7:0]
SharedTime[15:8]
1
2
3
4
5
41-bit share-clock counter
value when fault occurred.
Counter LSB is in 200µs
increments. This counter is
cleared at power-up or after
the LTC2978A is reset
SharedTime[23:16]
SharedTime[31:24]
SharedTime[39:32]
SharedTime[40]
Mfr_vout_peak0[7:0]
Mfr_vout_peak0[15:8]
Mfr_vout_min0[7:0]
Mfr_vout_min0[15:8]
Mfr_vout_peak1[7:0]
Mfr_vout_peak1[15:8]
Mfr_vout_min1[7:0]
Mfr_vout_min1[15:8]
Mfr_vin_peak[7:0]
With Mfr_config_all_fault_log_enable = 1 and Mfr_fault_
log_status_eeprom = 0, the RAM buffer is transferred to
EEPROM whenever an LTC2978A fault causes a channel
to latch off or a MFR_FAULT_LOG_STORE command is
received.
6
7
8
9
Mfr_fault_log_status_eeprom is set high after the RAM
buffer is transferred to EEPROM and not cleared until
a MFR_FAULT_LOG_CLEAR is received, even if the
LTC2978A is reset or powered down. Fault log EEPROM
transfers are not initiated as a result of Status_mfr_dis-
charge events.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Mfr_vin_peak[15:8]
Mfr_vin_min[7:0]
DuringaMFR_FAULT_LOGread,dataisreturnedasdefined
by the following table. The fault log data is partitioned
into two sections. The first section is referred to as the
preamble and contains the Position-last pointer, time
information and peak and minimum values. The second
section contains a chronological record of telemetry and
requires Position-last for proper interpretation. The fault
log stores approximately 0.5 seconds of telemetry. To
prevent timeouts during block reads, it is recommended
that Mfr_config_all_longer_pmbus_timeout be set to 1.
Mfr_vin_min[15:8]
Mfr_vout_peak2[7:0]
Mfr_vout_peak2[15:8]
Mfr_vout_min2[7:0]
Mfr_vout_min2[15:8]
Mfr_vout_peak3[7:0]
Mfr_vout_peak3[15:8]
Mfr_vout_min3[7:0]
Mfr_vout_min3[15:8]
Mfr_temp_peak[7:0]
Mfr_temp_peak[15:8]
Mfr_ temp_min[7:0]
Mfr_ temp_min[15:8]
Mfr_vout_peak4[7:0]
Mfr_vout_peak4[15:8]
Mfr_vout_min4[7:0]
Mfr_vout_min4[15:8]
Mfr_vout_peak5[7:0]
Mfr_vout_peak5[15:8]
Mfr_vout_min5[7:0]
Mfr_vout_min5[15:8]
Mfr_vout_peak6[7:0]
Mfr_vout_peak6[15:8]
Mfr_vout_min6[7:0]
Mfr_vout_min6[15:8]
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Table 2. Data Block Contents
Table 3. Interpreting Cyclical Loop
DATA
BYTE* DESCRIPTION
POSITION
17
DATA
Read_vout3[15:8]
Status_vout3
Mfr_vout_peak7[7:0]
Mfr_vout_peak7[15:8]
Mfr_vout_min7[7:0]
Mfr_vout_min7[15:8]
43
44
45
46
18
19
20
21
22
23
Status_mfr3
Read_temperature_1[7:0]
Read_temperature_1[15:8]
Status_temp
47 bytes for preamble
Fault_log [Position_last]
Fault_log
47
48
Reserved
.
.
.
24
25
26
Read_vout4[7:0]
Read_vout4[15:8]
Status_vout4
27
28
29
30
Status_mfr4
Fault_log
Reserved
237
238-254
Last Valid Byte
Read_vout5[7:0]
Read_vout5[15:8]
Status_vout5
Number of loops
(238-47)/40 = 4.8
*Note: PMBus data byte numbers start at 1 rather than 0. Position_last is the
first byte returned after BYTE COUNT = OxFF. See block read protocol.
31
32
33
34
35
36
37
38
Status_mfr5
Read_vout6[7:0]
Read_vout6[15:8]
Status_vout6
Thedatareturnedbetweenbytes47and237oftheprevious
table is interpreted using Position_last and the following
table. The key to identifying byte 47 is to locate the DATA
corresponding to POSITION = Position_last in the next
table. Subsequent bytes are identified by decrementing
the value of POSITION. For example: If Position_last = 9
then the first data returned in byte position 47 of a block
readisRead_vin[15:8]followedbyRead_vin[7:0]followed
by Status_mfr of page 1. See Table 3.
Status_mfr6
Read_vout7[7:0]
Read_vout7[15:8]
Status_vout7
Status_mfr7
Total Bytes =40
39
The following table fully decodes a sample fault log read
to help clarify the cyclical nature of the operation.
MFR_FAULT_LOG DATA BLOCK CONTENTS
PREAMBLE INFORMATION
Table 3. Interpreting Cyclical Loop
POSITION
DATA
0
1
2
3
4
5
6
7
8
Read_vout0[7:0]
Read_vout0[15:8]
Status_vout0
Status_mfr0
Read_vout1[7:0]
Read_vout1[15:8]
Status_vout1
Status_mfr1
BYTE
BYTE
NUMBER NUMBER
DECIMAL
HEX
DATA
DESCRIPTION
0
00
Position_last[7:0] = 9 Position of
Fault-Log
Pointer When
Fault Occured.
1
01
SharedTime[7:0]
41-Bit Share-
Clock Counter
Value When
Fault Occurred.
Counter LSB
Is in 200µs
Read_vin[7:0]
Read_vin[15:8]
Status_vin
9
10
11
12
13
14
15
16
Reserved
Increments.
Read_vout2[7:0]
Read_vout2[15:8]
Status_vout2
Status_mfr2
2
3
4
02
03
04
SharedTime[15:8]
SharedTime[23:16]
SharedTime[31:24]
Read_vout3[7:0]
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BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER
NUMBER NUMBER
DECIMAL
5
HEX
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
DATA
DESCRIPTION
DECIMAL
HEX
DATA
DESCRIPTION
SharedTime[39:32]
SharedTime[40]
44
45
46
2C
Mfr_vout_peak7[15:8]
6
2D
2E
Mfr_vout_min7[7:0]
7
Mfr_vout_peak0[7:0]
Mfr_vout_peak0[15:8]
Mfr_vout_min0[7:0]
Mfr_vout_min0[15:8]
Mfr_vout_peak1[7:0]
Mfr_vout_peak1[15:8]
Mfr_vout_min1[7:0]
Mfr_vout_min1[15:8]
Mfr_vin_peak[7:0]
Mfr_vout_min7[15:8] End of Preamble
8
CYCLICAL DATA LOOPS
LOOP
BYTE
9
BYTE
BYTE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
NUMBER NUMBER NUMBER
40 BYTES PER
DECIMAL
HEX
DECIMAL
DATA LOOP 0
Read_vin[15:8]
Read_vin[7:0]
Status_mfr1
LOOP
47
2F
9
8
7
6
5
4
3
2
1
0
Position_last
48
30
31
32
33
34
35
36
37
38
49
50
Status_vout1
Mfr_vin_peak[15:8]
Mfr_vin_min[7:0]
51
Read_vout1[15:8]
Read_vout1[7:0]
Status_mfr0
52
Mfr_vin_min[15:8]
Mfr_vout_peak2[7:0]
Mfr_vout_peak2[15:8]
Mfr_vout_min2[7:0]
Mfr_vout_min2[15:8]
Mfr_vout_peak3[7:0]
Mfr_vout_peak3[15:8]
Mfr_vout_min3[7:0]
Mfr_vout_min3[15:8]
Mfr_temp_peak[7:0]
Mfr_temp_peak[15:8]
Mfr_ temp_min[7:0]
Mfr_ temp_min[15:8]
Mfr_vout_peak4[7:0]
Mfr_vout_peak4[15:8]
Mfr_vout_min4[7:0]
Mfr_vout_min4[15:8]
Mfr_vout_peak5[7:0]
Mfr_vout_peak5[15:8]
Mfr_vout_min5[7:0]
Mfr_vout_min5[15:8]
Mfr_vout_peak6[7:0]
Mfr_vout_peak6[15:8]
Mfr_vout_min6[7:0]
Mfr_vout_min6[15:8]
Mfr_vout_peak7[7:0]
53
54
Status_vout0
55
Read_vout0[15:8]
Read_vout0[7:0]
56
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
39
3A
3B
3C
3D
3E
3F
DECIMAL
DATA LOOP 1
Status_mfr7
57
39
58
38
Status_vout7
59
37
Read_vout7[15:8]
Read_vout7[7:0]
Status_mfr6
60
36
61
35
62
34
Status_vout6
63
33
Read_vout6[15:8]
Read_vout6[7:0]
Status_mfr5
64
40
41
42
43
44
45
46
47
48
49
4A
32
65
31
66
30
Status_vout5
67
29
Read_vout5[15:8]
Read_vout5[7:0]
Status_mfr4
68
28
69
27
70
26
Status_vout4
71
25
Read_vout4[15:8]
Read_vout4[7:0]
Reserved
72
24
73
23
74
22
Status_temp
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LOOP
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
DECIMAL
DATA LOOP 1
DECIMAL
HEX
6D
6E
6F
DECIMAL
DATA LOOP 2
Status_mfr4
75
4B
21
Read_
temperature_1[15:8]
109
27
26
25
24
23
22
21
110
Status_vout4
Read_vout4[15:8]
Read_vout4[7:0]
Reserved
76
4C
20
Read_
temperature_1[7:0]
111
112
70
71
72
73
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
19
18
17
16
15
14
13
12
11
10
9
Status_mfr3
113
Status_vout3
114
Status_temp
Read_vout3[15:8]
Read_vout3[7:0]
Status_mfr2
115
Read_
temperature_1[15:8]
116
74
20
Read_
temperature_1[7:0]
Status_vout2
Read_vout2[15:8]
Read_vout2[7:0]
Reserved
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
19
18
17
16
15
14
13
12
11
10
9
Status_mfr3
Status_vout3
Read_vout3[15:8]
Read_vout3[7:0]
Status_mfr2
Status_vin
Read_vin[15:8]
Read_vin[7:0]
Status_mfr1
8
Status_vout2
7
Read_vout2[15:8]
Read_vout2[7:0]
Reserved
6
Status_vout1
5
Read_vout1[15:8]
Read_vout1[7:0]
Status_mfr0
4
Status_vin
3
Read_vin[15:8]
Read_vin[7:0]
Status_mfr1
2
Status_vout0
8
1
Read_vout0[15:8]
Read_vout0[7:0]
7
0
6
Status_vout1
5
Read_vout1[15:8]
Read_vout1[7:0]
Status_mfr0
LOOP
BYTE
4
BYTE
BYTE
3
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
2
Status_vout0
DECIMAL
HEX
61
62
63
64
65
66
67
68
69
6A
6B
6C
DECIMAL
DATA LOOP 2
Status_mfr7
1
Read_vout0[15:8]
Read_vout0[7:0]
97
39
0
98
38
Status_vout7
99
37
Read_vout7[15:8]
Read_vout7[7:0]
Status_mfr6
LOOP
BYTE
100
101
102
103
104
105
106
107
108
36
BYTE
BYTE
35
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
34
Status_vout6
DECIMAL
HEX
DECIMAL
DATA LOOP 3
Status_mfr7
33
Read_vout6[15:8]
Read_vout6[7:0]
Status_mfr5
137
89
39
38
37
36
35
32
138
8A
8B
8C
8D
Status_vout7
31
139
Read_vout7[15:8]
Read_vout7[7:0]
Status_mfr6
30
Status_vout5
140
29
Read_vout5[15:8]
Read_vout5[7:0]
141
28
2978af
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LTC2978A
pMbꢀꢁ coMManD DescripTion
LOOP
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
NUMBER NUMBER NUMBER
40 BYTES PER
DECIMAL
142
143
144
145
146
147
148
149
150
151
152
153
154
155
HEX
8E
8F
DECIMAL
DATA LOOP 3
Status_vout6
DECIMAL
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
HEX
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
DECIMAL
DATA LOOP 4
LOOP
34
39
Status_mfr7
33
Read_vout6[15:8]
Read_vout6[7:0]
Status_mfr5
38
Status_vout7
90
91
92
93
94
95
96
97
98
99
9A
9B
32
37
Read_vout7[15:8]
Read_vout7[7:0]
Status_mfr6
31
36
30
Status_vout5
35
29
Read_vout5[15:8]
Read_vout5[7:0]
Status_mfr4
34
Status_vout6
28
33
Read_vout6[15:8]
Read_vout6[7:0]
Status_mfr5
27
32
26
Status_vout4
31
25
Read_vout4[15:8]
Read_vout4[7:0]
Reserved
30
Status_vout5
24
29
Read_vout5[15:8]
Read_vout5[7:0]
Status_mfr4
23
28
22
Status_temp
27
21
Read_
temperature_1[15:8]
26
Status_vout4
25
Read_vout4[15:8]
Read_vout4[7:0]
Reserved
156
9C
20
Read_
temperature_1[7:0]
24
23
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
9D
9E
9F
19
18
17
16
15
14
13
12
11
10
9
Status_mfr3
22
Status_temp
Status_vout3
21
Read_
temperature_1[15:8]
Read_vout3[15:8]
Read_vout3[7:0]
Status_mfr2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
196
C4
20
Read_
temperature_1[7:0]
Status_vout2
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
19
18
17
16
15
14
13
12
11
10
9
Status_mfr3
Read_vout2[15:8]
Read_vout2[7:0]
Reserved
Status_vout3
Read_vout3[15:8]
Read_vout3[7:0]
Status_mfr2
Status_vin
Read_vin[15:8]
Read_vin[7:0]
Status_mfr1
Status_vout2
Read_vout2[15:8]
Read_vout2[7:0]
Reserved
8
7
6
Status_vout1
5
Read_vout1[15:8]
Read_vout1[7:0]
Status_mfr0
Status_vin
4
Read_vin[15:8]
Read_vin[7:0]
Status_mfr1
3
8
2
Status_vout0
7
1
Read_vout0[15:8]
Read_vout0[7:0]
6
Status_vout1
Read_vout1[15:8]
0
5
2978af
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LTC2978A
pMbꢀꢁ coMManD DescripTion
LOOP
RESERVED BYTES
BYTE
BYTE
BYTE
238
EE
0x00
Bytes EE - FE
Return 0x00 But
Must Be Read
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
D4
D5
D6
D7
D8
DECIMAL
DATA LOOP 4
Read_vout1[7:0]
Status_mfr0
212
4
3
2
1
0
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
213
214
Status_vout0
215
Read_vout0[15:8]
Read_vout0[7:0]
216
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
HEX
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
DECIMAL
DATA LOOP 5
Status_mfr7
39
38
Status_vout7
37
Read_vout7[15:8]
Read_vout7[7:0]
Status_mfr6
36
35
34
Status_vout6
33
Read_vout6[15:8]
Read_vout6[7:0]
Status_mfr5
32
Use One Block
Read Command
to Read 255
Bytes Total,
from 0x00 to
0xFE
31
30
Status_vout5
29
Read_vout5[15:8]
Read_vout5[7:0]
Status_mfr4
28
27
26
Status_vout4
25
Read_vout4[15:8]
Read_vout4[7:0]
Reserved
24
23
22
Status_temp
21
Read_
temperature_1[15:8]
236
237
EC
ED
20
19
Read_
temperature_1[7:0]
Status_mfr3
Last Valid Fault
Log Byte
2978af
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LTC2978A
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OVERVIEW
Alternatively, power from an external 3.3V supply may
be applied directly to the V
pins 16 and 17 using a
DD33
The LTC2978A is a power management IC that is capable
of sequencing, margining, trimming, supervising output
voltageforOV/UVconditions,providingfaultmanagement,
and voltage read back for eight DC/DC converters. Input
voltageandLTC2978Ajunctiontemperaturereadbackare
also available. Odd numbered channels can be configured
to read back sense resistor voltages to provide current
measurements for those channels. Linear Technology
PowerSystemManagerscancoordinateoperationamong
multipledevicesusingcommonSHARE_CLK,FAULTBand
CONTROLpins.TheLTC2978AutilizesaPMBuscompliant
interface and command set.
voltagebetween3.13Vand3.47V. TieV
toV
pins.
PWR
DD33
See Figure 15. All functionality is available when using
this alternate power method. The higher voltages needed
for the V
pins and bias for the V
pins are
OUT_EN[0:3]
charge-pumped from V
SENSE
.
DD33
SETTING COMMAND REGISTER VALUES
The command register settings described herein are in-
tendedasareferenceandforthepurposeofunderstanding
the registers in a software development environment. In
actual practice, the LTC2978A can be completely config-
2
ured for standalone operation with the LTC USB to I C/
POWERING THE LTC2978A
SMBus/PMBus controller (DC1613) and software GUI
using intuitive menu driven objects.
TheLTC2978Acanbepoweredtwoways.Thefirstmethod
requires that a voltage between 4.5V and 15V be applied
SEꢀUENCE, SERVO, MARGIN AND RESTART
OPERATIONS
to the V
pin. See Figure 14. An internal linear regula-
PWR
internal circuitry of the LTC2978A.
PWR
tor converts V
down to 3.3V which drives all of the
Command Units On or Off
4.5V < V
< 15V
Three control parameters determine how a particular
channel is turned on and off. The CONTROL pins, the
OPERATION command and the value of the input voltage
PWR
V
V
IN_SNS
PWR
0.1µF
0.1µF
0.1µF
V
V
V
DD33
DD33
DD25
measured at the V
pin (V ). In all cases, V must
IN_SNS
IN IN
LTC2978A
GND
exceed VIN_ON in order to enable the device to respond
to the CONTROL pin or OPERATION command. When V
IN
drops below VIN_OFF an immediate OFF of all channels
will result. Refer to the OPERATION section in the data
sheet for a detailed description of the ON_OFF_CONFIG
command.
*SOME DETAILS
OMITTED FOR CLARITY
2978a F14
Figure 14. Powering LTC2978A Directly from an Intermediate Bus
Some examples of typical ON/OFF configurations are:
1. ADC/DCconvertermaybeconfiguredtoturnonanytime
EXTERNAL 3.3V
0.1µF
V
PWR
V exceeds VIN_ON.
IN
V
V
V
2. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command.
DD33
DD33
DD25
LTC2978A
GND
3. A DC/DC converter may be configured to turn on only
via the CONTROL pin.
0.1µF
*SOME DETAILS
OMITTED FOR CLARITY
2978a F15
4. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command and the
CONTROL pin is asserted.
Figure 15. Powering LTC2978A from External 3.3V Supply
2978af
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LTC2978A
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On Sequencing
Servo Modes
The ADC, DAC and internal processor comprise a digital
servo loop that can be configured to operate in several
usefulmodes.Theservotargetreferstothedesiredoutput
voltage.
The TON_DELAY command sets the amount of time that
a channel will wait following the start of an ON sequence
beforeitsV
pinwillenableaDC/DCconverter. Once
OUT_EN
theDC/DCconverterhasbeenenabled,theTON_RISEvalue
determines the time at which the device soft-connects
the DAC and servos the DC/DC converter output to the
VOUT_COMMAND value. The TON_MAX_FAULT_LIMIT
value determines the time at which the device checks for
an undervoltage condition. If a TON_MAX_FAULT occurs,
the channel can be configured to disable the DC/DC
converter and propagate the fault to other channels using
thebidirectionalFAULTBpins.Notethatovervoltagefaults
are checked against the VOUT_OV_FAULT_LIMIT at all
times the device is powered up and not in a reset state nor
margining while ignoring OVs. Figure 16 shows a typical
on-sequence using the CONTROL pin.
Continuous/noncontinuous trim mode. MFR_CONFIG_
LTC2978A b[7]. In continuous trim mode, the servo will
update the DAC in a closed loop fashion each time it
takes a V
reading. The update rate is determined by
OUT
the time it takes to step through the ADC MUX, which is
no more than t . See Electrical Characteristics
UPDATE_ADC
Table Note 6. In noncontinuous trim mode, the servo will
drive the DAC until the ADC measures the output voltage
desired and then stop updating the DAC.
Aspartofcontinuous/noncontinuoustrimmode,fastservo
mode can be used to speed up large output transitions,
such as margin commands, or ON events. To use, set
Mfr_config_fast_servo_off=0. When enabled, fast servo
is started by a change to the target voltage or a new soft-
On State Operation
Once a channel has reached the ON state, the OPERATION
command can be used to command the DC/DC converter’s
output to margin high, margin low, or return to a nominal
output voltage indicated by VOUT_COMMAND. The
user also has the option of configuring a channel to
continuously trim the output of the DC/DC converter to the
connect. TheDACisrampedonelsbeveryt
period
S_VDACP
until it is near the new target voltage, at which point slow
servo mode is entered to avoid overshoot.
Noncontinuous servo on warn mode. MFR_CONFIG_
LTC2978A b[7] = 0, b[6] = 1. When in noncontinuous
mode, the LTC2978A will retrim (reservo) the output if
the output drifts beyond the OV or UV warn limits.
VOUT_COMMANDvoltage, orthechannel’sV
output
DACPn
can be placed in a high impedance state thus allowing the
DC/DC converter output voltage to go to its nominal value,
DAC Modes
V
.RefertotheMFR_CONFIG_LTC2978command
DCn(NOM)
for details on how to configure the output voltage servo.
The DACs that drive the V
pins can operate in several
DACn
useful modes. See MFR_CONFIG_LTC2978.
V
CONTROL
• Soft-connect. Using the LTC patented soft-connect
feature, the DAC output is driven to within 1 LSB of the
voltageattheDC/DC’sfeedbacknodebeforeconnecting
toavoidintroducingtransientsontheoutput.Thismode
is used when servoing the output voltage. During start-
up, the LTC2978A waits until TON_RISE has expired
before connecting the DAC. This is the most common
operating mode.
V
OUT_EN
VOUT_0V_FAULT_LIMIT
V
OUT_COMMAND
DAC SOFT-CONNECTS
AND BEGINS
ADJUSTING OUTPUT
V
DC(NOM)
VOUT_UV_FAULT_LIMIT
V
OUT
• Disconnected. DAC output is high Z.
2978a F16
TON_RISE
TON_DELAY
• DAC manual with soft-connect. Non servo mode. The
TON_MAX_FAULT_LIMIT
DAC soft-connects to the feedback node . Soft-connect
Figure 16. Typical On Sequence Using Control Pin
drivestheDACcodetomatchthevoltageatthefeedback
2978af
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LTC2978A
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node. After connection, the DAC is moved by writing
DAC codes to the MFR_DAC register.
STATUS_MFR_SPECIFIC register, and the ALERTB pin
will be asserted low. When the output voltage has decayed
belowitsOFFthreshold,thechannelcanentertheONstate.
• DAC manual with hard-connect. Non servo mode. The
DAC hard-connects to the feedback node using the
currentvalueinMFR_DAC. Afterconnection, theDACis
moved by writing DAC codes to the MFR_DAC register.
Automatic Restart Via MFR_RESTART_DELAY
Command and CONTROLn pin
An automatic restart sequence can be initiated by driving
the CONTROL pin to the off state for >10μs then releasing
Margining
it. The automatic restart disables all V
pins that are
OUT_EN
The LTC2978A margins and trims the output of a DC/DC
converter by forcing a voltage across an external resistor
connectedbetweentheDACoutputandthefeedbacknode
or the trim pin. Preset limits for margining are stored in
the VOUT_MARGIN_HIGH/LOW registers. Margining is
actuated by writing the appropriate bits to the OPERA-
TION register.
mapped to a particular CONTROL pin for a time period
= MFR_RESTART_DELAY and then starts all DC-DC
Converters according to their respective TON_DELAYs.
CONTROL
PIN BOUNCE
V
CONTROL
Margining requires the DAC to be connected. Margin
requests from a non-global OPERATION command that
occur when the DAC is disconnected will force the DAC
to soft-connect. If a global (PAGE=0xFF) OPERATION
command is used to margin, the DACs must already be
connected using MFR_CONFIG_LTC2978 commands.
When in the margin high/low state, the DAC cannot be
disconnected. The DAC can only be disconnected from
the ON state.
V
OUT_END
2978a F17
TOFF_DELAY0
MFR_RESTART_DELAY TON_DELAY0
Figure 17. Off Sequence with Automatic Restart
(See Figure 17). V
pins are mapped to one of the
OUT_ENn
CONTROLpinsbytheMFR_CONFIG_LTC2978command.
This feature allows a host that is about to reset to restart
the power in a controlled manner after it has recovered.
Off Sequencing
An off sequence is initiated using the CONTROL pin or the
OPERATIONcommand.TheTOFF_DELAYvaluedetermines
the amount of time that elapses from the beginning of the
FAULT MANAGEMENT
Output Overvoltage and Undervoltage Faults
off sequence until each channel’s V
pin is pulled
OUT_EN
low, thus disabling its DC/DC converter.
The high speed voltage supervisor OV and UV fault
thresholds are configured using the VOUT_OV_FAULT_
LIMIT and VOUT_UV_FAULT_LIMIT commands,
respectively. The VOUT_OV_FAULT_RESPONSE and
VOUT_UV_FAULT_RESPONSE commands determine the
responsestoOV/UVfaults.Faultresponsescanrangefrom
disabling the DC/DC converter immediately, waiting to
see if the fault condition persists for some interval before
disabling the DC/DC converter, or allowing the DC/DC
convertertocontinueoperatinginspiteofthefault.IfaDC/
DCconverterisdisabled, theLTC2978Acanbeconfigured
V
OUT
Off Threshold Voltage
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the channel
can enter/re-enter the ON state. The OFF threshold voltage
is specified by multiplying MFR_VOUT_DISCHARGE_
THRESHOLD and VOUT_COMMAND. In the event that an
output voltage has not decayed below its OFF threshold
before attempting to enter the ON state, the channel will
continue to be held off, the appropriate bit is set in the
2978af
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Configuring the V
Output
to retry or latch-off. The retry interval is specified using
the MFR_RETRY_DELAY command. Latched faults are
resetbytogglingtheCONTROLpin,usingtheOPERATION
command, or removing and reapplying the bias voltage to
IN_EN
The V
output may be used to disable the intermediate
IN_EN
bus voltage in the event of an output OV or UV fault.
Use the MFR_VINEN_OV_FAULT_RESPONSE and
MFR_VINEN_UV_FAULT_RESPONSE registers to
the V
pin. All fault and warning conditions result in
IN_SNS
theALERTBpinbeingassertedlowandthecorresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
deasserts the ALERTB output.
configure the V
pin to assert low in response to
IN_EN
VOUT_OV/UVfaultconditions. TheV
outputwillstop
IN_EN
pullinglowwhentheLTC2978Aiscommandedtore-enter
the ON state following a faulted-off condition.
Acharge-pumped5µApull-upto12Visalsoavailableonthe
IN_EN
register description in the PMBus COMMAND DESCRIP-
TION section for more information.
Output Overvoltage and Undervoltage Warnings
V
output. Refer to the MFR_CONFIG_ALL_LTC2978
OV and UV warning threshold voltages are processed by
the LTC2978A’s ADC. These thresholds are set by the
VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT
commands respectively. If a warning occurs, the
corresponding bits are set in the status registers and
the ALERTB output is asserted low. Note that a warning
Figure 18 shows an application circuit where the V
IN_EN
outputisusedtotriggeraSCRcrowbarontheintermediate
bus in order to protect the DC/DC converter’s load from a
catastrophic fault such as a stuck top gate.
will never cause a V
converter.
output pin to disable a DC/DC
OUT_EN
R
Q1
SENSE
0.007Ω
Si4894BDY
V
IN
V
V
IN
<15V
C
BYPASS
V
IN_SNS
OUT
V
V
PWR
DACP0
DC/DC
CONVERTER
100Ω
V
V
SENSE
GATE
LTC4210-3
SENSEP0
CC
0.1µF
LTC2978A*
24.3k
V
LOAD
FB
68Ω
0.01µF
ON
V
DACM0
TIMER GND
V
10k
SGND
SENSEM0
V
RUN/SS
0.22µF
OUT_EN0
GND
10k
0.01µF
2978a F18
2N2907
220Ω
MCR12DC
4.99k
0.1µF
BAT54
REFP
V
REFM
IN_EN
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
V
V
V
GND
DD33 DD33 DD25
0.1µF
0.1µF
Figure 18. LTC2978A Application Circuit with Crowbar Protection on Intermediate Bus
2978af
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Mfr_faultb00_response, page = 0
Mfr_faultbz0_propagate_ch0
FAULTED_OFF
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
FAULTB00
FAULTB01
Mfr_faultb01_response, page = 0
Mfr_faultbz1_propagate_ch0
Mfr_faultb00_response, page = 1
Mfr_faultb01_response, page = 1
Mfr_faultbz0_propagate_ch1
FAULTED_OFF
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
Mfr_faultbz1_propagate_ch1
Mfr_faultb00_response, page = 2
Mfr_faultb01_response, page = 2
Mfr_faultbz0_propagate_ch2
FAULTED_OFF
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
Mfr_faultbz1_propagate_ch2
Mfr_faultb00_response, page = 3
Mfr_faultb01_response, page = 3
Mfr_faultbz0_propagate_ch3
FAULTED_OFF
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
Mfr_faultbz1_propagate_ch3
ZONE 0
ZONE 1
ZONE 0
ZONE 1
Mfr_faultb10_response, page = 4
Mfr_faultb11_response, page = 4
Mfr_faultbz0_propagate_ch4
FAULTED_OFF
CHANNEL 4
EVENT PROCESSOR
PAGE = 4
FAULTB10
Mfr_faultbz1_propagate_ch4
Mfr_faultb10_response, page = 5
Mfr_faultb11_response, page = 5
Mfr_faultbz0_propagate_ch5
FAULTED_OFF
CHANNEL 5
EVENT PROCESSOR
PAGE = 5
Mfr_faultbz1_propagate_ch5
Mfr_faultb10_response, page = 6
Mfr_faultb11_response, page = 6
Mfr_faultbz0_propagate_ch6
FAULTB11
FAULTED_OFF
CHANNEL 6
EVENT PROCESSOR
PAGE = 6
Mfr_faultbz1_propagate_ch6
Mfr_faultb10_response, page = 7
Mfr_faultb11_response, page = 7
Mfr_faultbz0_propagate_ch7
FAULTED_OFF
Mfr_faultbz1_propagate_ch7
CHANNEL 7
EVENT PROCESSOR
PAGE = 7
2978a F19
Figure 19. Channel Fault Management Block Diagram
2978af
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LTC2978A
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Multichannel Fault Management
• A FAULTBzn pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 10µs deglitch delay.
Multichannel fault management is handled using the
bidirectional FAULTBzn pins. The “z” designates the fault
zone which is either 0 or 1. There are two fault zones in
the LTC2978A. Each zone contains 4-channels. Figure 19
illustrates the connections between channels and the
FAULTBzn pins.
INTERCONNECT BETWEEN MULTIPLE LTC2978A’S
Figure 20 shows how to interconnect the pins in a typical
multi-LTC2978A array.
• TheMFR_FAULTBz0_PROPAGATEcommandactslikea
programmableswitchthatallowsfaulted-offconditions
from a particular channel (PAGE) to propagate to
either FAULTBzn output in that channel’s zone. The
MFR_FAULTBzn_RESPONSEcommandcontrolssimilar
switches on the inputs to each channel that allow any
channel to shut down in response to any combination
of the FAULTBzn pins within a zone. Channels respond-
ing to a FAULTBzn pin pulling low will attempt a new
start sequence when the FAULTBzn pin in question is
released by the faulted channel.
• All V
lines should be tied together in a star type
IN_SNS
connection at the point where V is to be sensed.
IN
This will minimize timing errors for the case where the
ON_OFF_CONFIG is configured to start the LTC2978A
based on V and ignore the CONTROL line and the
IN
OPERATION command. In multi-part applications that
are sensitive to timing differences, it is recommended
that the Vin_share_enable bit of the MFR_CONFIG_
ALL_LTC2978 register be set high in order to allow
SHARE_CLK to synchronize on/off sequencing in
response to the VIN_ON and VIN_OFF thresholds.
• To establish dependencies across fault zones, tie the
fault pins together, e.g., FAULTB01 to FAULTB10. Any
channelcandependonanyother.Todisableallchannels
in response to any channel faulting off, short all the
FAULTBzn pins together, and set MFR_FAULTBzn_
PROPAGATE = 0x01 and MFR_FAULTBzn_RESPONSE
= 0x0F for all channels.
• Connecting all V
lines together will allow selected
IN_EN
faults on any DC/DC converter’s output in the array to
shut off a common input switch.
TO V OF
IN
DC/DCs
TO INPUT
SWITCH
TO HOST CONTROLLER
LTC2978A N-1
LTC2978A N
VIN_SNS
VIN_EN
VIN_SNS
VIN_EN
SDA
SCL
SDA
SCL
ALERTB
ALERTB
CONTROL0
CONTROL1
WDI/RESETB
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
CONTROL0
CONTROL1
WDI/RESETB
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
GND
GND
2978a F20
TO OTHER LTC2978As–10k EQUIV PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
Figure 20. Typical Connections Between Multiple LTC2978As
2978af
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• ALERTB is typically one line in an array of PMBus
converters. The LTC2978A allows a rich combination
of faults and warnings to be propagated to the ALERTB
pin.
• PWRGDreflectsthestatusoftheoutputsthataremapped
to it by the MFR_PWRGD_EN command. Figure 20
shows all the PWRGD pins connected together, but any
combination may be used. Note that the latency of the
PWRGD pin response may be in the range of 30ms to
185ms depending on ADC MUX settings. See Electrical
Characteristics Table Note 6.
• WDI/RESETB can be used to put the LTC2978A in the
power-on reset state. Pull WDI/RESETB low for at least
t
to enter this state.
RESETB
A fast deassertion of PWRGD may be implemented by
• TheFAULTBznlinescanbeconnectedtogethertocreate
fault dependencies. Figure 20 shows a configuration
where a fault on any FAULTBzn will pull all others low.
This is useful for arrays where it is desired to abort a
start-up sequence in the event any channel does not
come up (see Figure 21).
wire ANDing the V
pin with the PWRGD pin. If, for
IN_EN
example, a UV or OV fault threshold is crossed, V
IN_EN
willpulllowiftheassociatedbitintheMFR_VINEN_UV_
FAULT_RESPONSE or MFR_VINEN_OV_FAULT_RE-
SPONSE register is set. See Figure 22.
V
CONTROLn
V
OUT0
TON_DELAY0
TON_DELAY1
V
V
OUT1
OUT2
TON_DELAY2
•
•
•
•
•
•
V
OUTn
TON_DELAYn
BUSSED
VFAULTBzn
PINS
2978a F21
TON_MAX_FAULT1
Figure 21. Aborted On Sequence Due to Channel 1 Short
V
DD33
4.7k
V
IN_EN
VOUTn
UV FAULT LIMIT
LTC2978A
PWRGD
FAST PWRGD
DEASSERT
VIN_EN/PWRGD
t
S_VS
2978a F22
Figure 22. PWRGD Deassert
2978af
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APPLICATION CIRCUITS
V
is the output voltage of the DC/DC converter
DC(NOM)
whentheLTC2978A’sV
pinisinahighimpedance
DACP0
Trimming and Margining DC/DC Converters with
External Feedback Resistors
state. R10 is a function of R20, V
, the voltage at
DC(NOM)
the feedback node (V ) when the loop is in regulation,
FB
and the feedback node’s input current (I ).
FB
Figure 23 shows a typical application circuit for trimming/
margining a power supply with an external feedback
R20 • VFB
R10 =
(1)
network. The V
and V
differential inputs
SENSEP0
SENSEM0
VDC(NOM) –IFB • R20 – V
FB
sense the load voltage directly, and a correction voltage
is developed between the V and V pins
DACP0
DACM0
2. Solve for the value of R30 that yields the maximum
required DC/DC converter output voltage V
by the closed-loop servo algorithm. V
is Kelvin
DACM0
.
DC(MAX)
connected to the point-of-load GND in order to minimize
the effects of load induced grounding errors. The V
output is connected to the DC/DC converter’s feedback
node through resistor R30. For this configuration, set
Mfr_config_dac_pol to 0.
WhenV
is at its maximum voltage.
isat0V,theoutputoftheDC/DCconverter
DACP0
DACP0
R20 • VFB
R30 ≤
(2)
VDC(MAX) – VDC(NOM)
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
3. Solve for the minimum value of V
that is needed
DACP0
to yield the minimum required DC/DC converter output
voltage V
.
The following four-step procedure should be used to
calculate the resistor values required for the application
circuit shown in Figure 23.
DC(MIN)
The DAC has two full-scale settings, 1.38V and 2.65V.
In order to select the appropriate full-scale setting,
calculate the minimum required V
voltage:
output
1. AssumevaluesforfeedbackresistorR20andthenominal
DACP0(F/S)
DC/DC converter output voltage V
for R10.
, and solve
DC(NOM)
R30
R20
VDACP0(F /S) > VDC(NOM) – VDC(MIN)
•
+ VFB
(
)
(3)
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
PWR
IN_SNS
OUT
0.1µF
V
DACP0
0.1µF
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R20
R10
LTC2978A*
V
LOAD
FB
V
DACM0
0.1µF
V
SGND
SENSEM0
V
RUN/SS
OUT_EN0
GND
2978a F23
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 23. Application Circuit for DC/DC Converters with External Feedback Resistors
2978af
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4. Recalculate the minimum, nominal, and maximum DC/
DC converter output voltages and the resulting margin-
ing resolution.
relationships between these resistors and the ∆% change
in the output voltage of the DC/DC converter are typically
expressed as:
R20
R10
RTRIM • 50
VDC(NOM) = VFB • 1+
+IFB •R20
(4)
RTRIM_DOWN
=
–RTRIM
(8)
ΔDOWN
%
R20
R30
R20
R30
VDC(MIN) = VDC(NOM)
–
• V
– V
(5)
(6)
RTRIM_UP
=
(
)
FB
DACP0(F /S)
VDC • 100+ Δ %
(
)
50
VDC(MAX) = VDC(NOM)
+
• V
UP
FB
RTRIM
•
–
– 1
(9)
2 • VREF • ΔUP%
Δ %
UP
R20
• VDACP0(F /S)
R30
where R
is the resistance looking into the TRIM pin,
VRES
=
V/DAC LSB
(7)
TRIM
1024
V
istheTRIMpin’sopen-circuitoutputvoltageandV
REF
DC
istheDC/DCconverter’snominaloutputvoltage.∆ %and
UP
Trimming and Margining DC/DC Converters with a
TRIM Pin
∆
% denote the percentage change in the converter’s
DOWN
output voltage when margining up or down, respectively.
Figure 24 illustrates a typical application circuit for
trimming/margining the output voltage of a DC/DC
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin
converter with a TRIM Pin. The LTC2978A’s V
pin
DACP0
connects to the TRIM pin through resistor R30, and the
pin is connected to the converter’s point-of-load
V
The following two-step procedure should be used to cal-
culatetheresistorvalueforR30andtherequiredfull-scale
DAC voltage (refer to Figure 24).
DACM0
ground. For this configuration, set the DAC polarity bit
Mfr_config_ dac_pol in MFR_CONFIG_LTC2978 to 1.
DC/DC converters with a TRIM pin may be margined
high or low by connecting an external resistor between
1. Solve for R30:
50 – ΔDOWN
%
the TRIM pin and either the V
or V
pin. The
SENSEP
SENSEM
R30 ≤RTRIM
•
(10)
ΔDOWN
%
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
+
OUT
V
V
IN_SNS
PWR
R30
0.1µF
TRIM
V
V
DACP0
0.1µF
+
V
V
V
V
SENSEP0
SENSE
DD33
DD33
DD25
DC/DC
LTC2978A*
CONVERTER
LOAD
V
DACM0
0.1µF
–
V
V
SENSEM0
SENSE
ON/OFFB
GND
V
OUT_EN0
GND
2978a F24
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 24. Application Circuit for DC/DC Converters with Trim Pin
2978af
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Measuring Current with Inductor DCR
2. Calculate the maximum required output voltage for
V
DACP0
:
Figure 26 shows the circuit for applications that require
DCR current sense. A second order RC filter is required
in these applications in order to minimize the ripple volt-
age seen at the current sense inputs. A value of 1kΩ
ΔUP%
VDAC ≥ 1+
• V
(11)
P0
REF
ΔDOWN
%
is suggested for R
and R
in order to minimize
CM1
CM2
Note: Not all DC/DC’s converters follow these trim equa-
tionsespeciallynewerbricks.ConsultLTC FieldApplication
Engineering.
gain errors due the current sense inputs’ internal resis-
tance. C should be selected to provide cancellation
CM1
of the zero created by the DCR and inductance, i.e.
= L/(DCR • R ). C should be selected to
C
CM1
CM1
CM2
Measuring Current
provide a second stage corner frequency at < 1/10 of the
Odd numbered ADC channels may be used to measure
supply current. Set the ADC to high resolution mode to
configure for current measuring and improve sensitivity.
Note that no OV or UV faults or warnings are reported in
thismode,buttelemetryisavailablefromtheREAD_VOUT
command using the 11-bit signed mantissa plus 5-bit
signed exponent L11 data format. Set the MFR_CONFIG_
LTC2978 bit b[9] = 1 in order to enable high res mode.
DC/DC converter’s switching frequency. In addition, C
needs to be much smaller than C
significant loading of the filter’s first stage.
CM2
in order to prevent
CM1
R
CM
V
V
SENSEP1
C
C
CM
LTC2978A
The V
pin will assert low in this mode and cannot
R
CM
OUT_EN
CM
SENSEM1
be used to control a DC/DC converter. The V
pin is also unavailable.
output
L
R
DACP
SNS
2978a F25
LOAD CURRENT
Measuring Current with a Sense Resistor
Figure 25. Sense Resistor Current Sensing Circuits
A circuit for measuring current with a sense resistor is
shown in Figure 25. The balanced filter rejects both com-
mon mode and differential mode noise from the output of
theDC/DCconverter.Thefilterisplaceddirectlyacrossthe
sense resistor in series with the DC/DC converter’s induc-
tor. Note that the current sense inputs must be limited to
less than 6V with respect to ground. Select R and C
R
R
CM2
CM2
V
V
SENSEP1
C
C
CM2
LTC2978A
C
C
CM1
CM1
CM2
SENSEM1
CM
CM
2978a F26
such that the filter’s corner frequency is < 1/10 the DC/DC
converter’sswitchingfrequency.Thiswillresultinacurrent
sense waveform that offers a good compromise between
the voltage ripple and the delay through the filter. A value
R
R
CM1
CM1
L
DCR
SWX0
Figure 26. Inductor DCR Current Sensing Circuits
1kΩ for R is suggested in order to minimize gain er-
CM
rors due to the current sense inputs’ internal resistance.
2978af
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Single Phase Design Example
Measuring Multiphase Currents
As a design example for a DCR current sense application,
For current sense applications with more than one phase,
RC averaging may be employed. Figure 27 shows an
example of this approach for a 3-phase system with DCR
currentsensing.Thecurrentsensewaveformsareaveraged
together prior to being applied to the second stage of the
assume L = 2.2μH, DCR = 10mΩ, and F = 500kHz.
SW
Let R
= 1kΩ and solve for C
:
CM1
CM1
2.2µH
10mΩ • 1kΩ
C
≥
= 220nF
CM1
filter consisting of R
and C . Because the R
CM2 CM2 CM1
resistors for the three phases are in parallel, the value of
must be multiplied by the number of phases. Also
R
Let R
SW
= 1kΩ. In order to get a second pole at
CM1
CM2
/10 = 50kHz:
note that since the DCRs are effectively in parallel, the
value for IOUT_CAL_GAIN will be equal to the inductor’s
DCR divided by the number of phases. Care should to be
taken in the layout of the multiphase inductors to keep the
PCB trace resistance from the DC side of each inductor to
the summing node balanced in order to provide the most
accurate results.
F
1
C
≅
= 3.18nF
CM2
2π• 50kHz • 1kΩ
Let C
CM1
= 3.3nF. Note that since C
is much less than
CM2
CM2
C
the loading effects of the second stage filter on the
matched first stage are not significant. Consequently, the
delay time constant through the filter for the current sense
waveform will be approximately 3μs.
Multiphase Design Example
Using the same values for inductance and DCR from
the previous design example, the value for R
will be
CM1
3kΩ for a three phase DC/DC converter if C
is left at
CM1
220nF. Similarly, the value for IOUT_CAL_GAIN will be
DCR/3 = 3.33mΩ.
SWX1
R
R
CM1
CM1
R
CM2
R
C
CM1
C
CM2
CM1
L
V
V
SENSEP1
LTC2978A
DCR
SENSEM1
2978a F27
R
/3
CM1
R
CM2
DCR
DCR
C
CM1
C
CM2
L
L
TO LOAD
SWX2
SWX3
Figure 27. Multiphase DCR Current Sensing Circuits
2978af
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Anti-aliasing Filter Considerations
while the VSENSEP1 input is tied to the REFP pin which
has a typical output voltage of 1.23V. The voltage divider
should be configured in order to present about 0.5V to the
voltage sense inputs when the negative supply reaches its
POWER_GOOD_ON threshold so that the current flowing
out of the VSENSEMn pin is minimized to ~1µA. The
relationship between the POWER_GOOD_ON register
value and the corresponding negative supply value can
be expressed as:
Noisy environments require an anti-aliasing filter on the
input to the LTC2978A’s ADC. The R-C circuit shown in
Figure 28 is adequate for most situations. Keep R40 = R50
≤ 200Ω to minimize ADC gain errors, and select a value
for capacitors C10 and C20 that does not add too much
additional response time to the OV/UV supervisor, e.g. τ
≅ 10µs (R = 100Ω, C = 0.10µF).
Sensing Negative Voltages
R2
R1
+1 – 1µA•R2
VEE = VREFP –(READ_VOUT) •
Figure 29 shows the LTC2978A sensing a negative power
supply (V ). The R1/R2 resistor divider translates the
EE
negativesupplyvoltagetotheLTC2978AsVSENSEM1input
Where READ_VOUT returns VSENSEP – VSENSEM
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
OUT
0.1µF
0.1µF
0.1µF
V
DACP0
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R40
R50
C10
C20
R20
R10
LTC2978A*
V
LOAD
FB
V
SENSEM0
V
SGND
DACM0
V
RUN/SS
OUT_EN0
GND
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978a F28
Figure 28. Antialiasing Filter on VSENSE Lines
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
LTC2978A
1.23V TYP
0.1µF
REFP
REFM
SDA
V
SENSEP1
SCL
PMBus
INTERFACE
1µA AT 0.5V
0.1µF
R1 = 4.99k
R2 = 120k
ALERTB
CONTROL
V
SENSEM1
WDI/RESETB
FAULTB
V
= –12V
EE
SHARE_CLK
ASEL0
POWER_GOOD_ON = 0.5V FOR V POWER_GOOD = –11.414V
EE
PWRGD
WHERE V POWER_GOOD =
EE
ASEL1
ONLY ONE OF EIGHT CHANNELS SHOWN,
SOME DETAILS OMITTED FOR CLARITY
WDI/RESETB
WP GND
2978a F29
Figure 29. Sensing Negative Voltages
2978af
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2
Connecting the DC1613 USB to I C/SMBus/PMBus
Figures 30 and 31 illustrate application schematics for
powering, programming and communicating with one
Controller to the LTC2978A in System
2
or more LTC2978A’s via the DC1613 I C/SMBus/PMBus
2
The DC1613 USB to I C/SMBus/PMBus Controller can be
controller regardless of whether or not system power is
present.
interfacedtoLTC2978Asontheuser’sboardforprogram-
ming, telemetry and system debug. The controller, when
used in conjunction with LTpowerPlay software, provides
a powerful way to debug an entire power system. Failures
arequicklydiagnosedusingtelemetry,faultstatusregisters
and the fault log. The final configuration can be quickly
developed and stored to the LTC2978A’s EEPROM.
Figure30showstherecommendedschematictousewhen
the LTC2978A is powered by the system intermediate bus
through its V
pin.
PWR
REPEAT OUTLINED CIRCUIT FOR EVERY LTC2978A
4.5V TO 15V
150k
49.9k
V
PWR
0.1µF
LTC2978A
ISOLATED 3.3V
V
V
DD33
DD33
SCL
Si1303
GND
0.1µF
0.1µF
SDA
V
DD25
TO DC1613
I C/SMBUS/PMBUS
CONTROLLER
PIN CONNECTIONS
OMITTED FOR
CLARITY
2
10k
10k
5.49k
SCL
SDA
SHARE_CLK
WP GND
TO/FROM OTHER
LTC2978As
2978a F30
Figure 30. DC1613 Controller Connections When VPWR is Used
2978af
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Figure31showstherecommendedschematictousewhen
the LTC2978A is powered by the system 3.3V through its
node because this will interfere with bus communication
in the absence of system power.
V
and V
pins. The LTC4412 ideal ORing circuit al-
PWR
2
DD33
The DC1613 controller’s I C/SMBus connections are
lowseitherthecontrollerorsystemtopowertheLTC2978A.
opto-isolated from the PC’s USB port. The 3.3V supply
from the controller and the LTC2978A’s V
pin can be
Becauseofthecontroller’slimitedcurrentsourcingcapabil-
ity, only the LTC2978As, their associated pull up resistors
DD33
paralleled because the LTC LDOs that generate these volt-
ages can be backdriven and draw <10μA. The controller’s
3.3V current limit is 100mA.
2
and the I C/SMBus pull-up resistors should be powered
fromtheORed3.3Vsupply.Inaddition,anydevicesharing
2
I C/SMBusbusconnectionswiththeLTC2978Ashouldnot
have body diodes between the SDA/SCL pins and its V
DD
IDEAL
DIODE
0R’d 3.3V
TP0101K-SSOT23
SYSTEM
LTC2978A_3.3V
V
V
V
V
PWR
DD33
DD33
DD25
3.3V
LTC4412
10k
10k 5.49k
V
SENSE
GATE
STAT
IN
GND
CTL
0.1µF
0.1µF
LTC2978A
PIN CONNECTIONS
OMITTED FOR
CLARITY
ISOLATED 3.3V
SCL
SCL
GND
SDA
SHARE_CLK
SDA
WP GND
2978a F31
TO DC1613
I C/SMBUS/PMBUS
CONTROLLER
TO/FROM OTHER
LTC2978As
2
2
NOTE: DC1613 CONTROLLER I C CONNECTIONS ARE OPTO-ISOLATED
ISOLATED 3.3V FROM CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW < 10µA
ISOLATED 3.3V CURRENT LIMIT = 100mA
Figure 31. DC1613 Controller Connections When LTC2978A Powered Directly from 3.3V
2978af
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LTpowerPlay: AN INTERACTIVE GUI FOR POWER
SYSTEM MANAGERS
to program or tweak the power management scheme in
a system or to diagnose power issues when bringing up
rails. LTpowerPlay utilizes Linear Technology’s DC1613
LTpowerPlay is a powerful Windows based develop-
ment environment that supports Linear Technology
Power System Manager ICs with EEPROM, including the
LTC2978A 8-channel PMBus Power System Manager.
The software supports a variety of different tasks. You
can use LTpowerPlay to evaluate Linear Technology ICs
by connecting to a demo board system. LTpowerPlay can
also be used in an offline mode (with no hardware pres-
ent) in order to build a multi-chip configuration file that
can be saved and reloaded at a later time. LTpowerPlay
provides unprecedented diagnostic and debug features. It
becomes a valuable diagnostic tool during board bring-up
2
USB-to-I C/SMBus/PMBus Controller to communicate
with one of many potential targets, including the DC1540
demoboardset,theDC1508socketedprogrammingboard,
or a customer target system. The software also provides
an automatic update feature to keep the software current
with the latest set of device drivers and documentation.
A great deal of context sensitive help is available within
LTpowerPlay along with several tutorial demos. Complete
information is available at:
www.linear.com/ltpowerplay
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PCB ASSEMBLY AND LAYOUT SUGGESTIONS
The proposed stencil design enables out-gassing of the
solderpasteduringreflowaswellasregulatingthefinished
solder thickness. See IPC7525A.
Bypass Capacitor Placement
The LTC2978A requires 0.1µF bypass capacitors between
PC Board Layout
the V
pins and GND, the V
pin and GND, and the
DD33
DD25
REFP pin and REFM pin. If the chip is being powered from
the V input, then that pin should also be bypassed
to GND by a 0.1µF capacitor. In order to be effective,
these capacitors should be made of high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible.
Mechanical stress on a PC board and soldering-induced
stress can cause the LTC2978A’s reference voltage and
voltage drift to shift. A simple way to reduce these stress-
related shifts is to mount the IC near the short edge of the
PC board, or in a corner. The board edge acts as a stress
boundary, or a region where the flexure of the board is
minimal.
PWR
Exposed Pad Stencil Design
Unused ADC Sense Inputs
The LTC2978A’s package is thermally and electrically
efficient. This is enabled by the exposed die attach pad
on the under side of the package which must be soldered
down to the PCB or mother board substrate. It is a good
practice to minimize the presence of voids within the
exposed pad inter-connection. Total elimination of voids
is difficult, but the design of the exposed pad stencil is
key. Figure 32 shows a suggested screen print pattern.
Connect all unused ADC sense inputs (V
SENSEMn
or
SENSEPn
V
) to GND. In a system where the inputs are
connected to removable cards and may be left floating
in certain situations, connect the inputs to GND using
100k resistors. Place the 100k resistors before any filter
components, as shown in Figure 33, to prevent loading
of the filter.
V
SENSEP
100k
LTC2978A
SENSEM
V
100k
2978a F33
Figure 33. Connecting Unused Inputs to GND
2978a F32
Figure 32. Suggested Screen Pattern for Die Attach Pad
2978af
78
For more information www.linear.com/LTC2978A
LTC2978A
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UP Package
64-Lead Plastic qFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
R = 0.10
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ± 0.10
7.50 REF
(4-SIDES)
7.15 ± 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
2978af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
79
LTC2978A
Typical applicaTion
0.1µF
3.3V
0.1µF
0.1µF
13 35 34 65 19 18 17 16 15 33 32 14
V
V
V
V
IN
IN
OUT
39
36
60
2
OUT
V
V
V
DACP7
DACP0
R30
R20
R37
R27
DC/DC
CONVERTER
V
DC/DC
CONVERTER
SENSEP0
SENSEP7
V
V
LOAD
LOAD
LOAD
LOAD
LOAD
FB
FB
37
38
3
R10
V
V
V
R17
SENSEM0
DACM0
SENSEM7
61
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM7
4
11
V
V
OUT_EN7
OUT_EN0
V
V
IN
40
42
59
64
OUT
V
V
V
DACP6
DACP1
R36
R26
V
DC/DC
CONVERTER
SENSEP1
SENSEP6
V
FB
43
41
1
V
V
V
R16
SENSEM1
DACM1
SENSEM6
58
V
SGND RUN/SS
GND
DACM6
5
10
V
V
OUT_EN6
OUT_EN1
LTC2978A
V
V
V
V
IN
IN
OUT
44
46
56
62
OUT
V
V
V
DACP5
DACP2
R32
R22
R35
R25
DC/DC
V
DC/DC
CONVERTER
SENSEP2
SENSEP5
CONVERTER
V
FB
V
LOAD
FB
47
45
63
57
R12
V
V
V
R15
SENSEM2
DACM2
SENSEM5
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM5
6
9
V
V
OUT_EN5
OUT_EN2
V
V
IN
50
48
55
52
OUT
V
V
V
DACP4
DACP3
R34
R24
V
DC/DC
CONVERTER
SENSEP3
SENSEP4
V
FB
49
51
53
54
V
V
V
R14
SENSEM3
DACM3
SENSEM4
V
SGND RUN/SS
GND
DACM4
IN
OUT
7
8
INTERMEDIATE
V
V
OUT_EN4
OUT_EN3
2978a F34
BUS
CONVERTER
12 23 24 25 26 21 27 28 29 30 31 20
10k
22
EN
10k
10k
10k
10k
10k
10k
3.3V
3.3V
10k
10k
10k
5.49k
10k
TO/FROM OTHER LTC2974s, LTC2978As AND MICROCONTROLLER
Figure 34. LTC2978A Application Circuit with 3.3V Chip Power
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
2
LTC2970
LTC2974
LTC2977
LTC3880
LTC3883
Dual I C Power Supply Monitor and Margining Controller 5V to 15V, 0.5% TUE 14-Bit ADC, 8-Bit DAC, Temperature Sensor
4-Channel PMBus Power System Manager
8-Channel PMBus Power System Manager
Dual Output PolyPhase Step-Down DC/DC Controller
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
Single Output PolyPhase Step-Down DC/DC Controller 0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
2978af
LT 0413 • PRINTED IN USA
80 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2978A
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