LTC2978CUPPBF [Linear]
Octal PMBus Power Supply Monitor and Controller with EEPROM; 八路的PMBus电源监视器和控制器与EEPROM
| 型号： | LTC2978CUPPBF |
| 厂家： | 
Linear |
| 描述： | Octal PMBus Power Supply Monitor and Controller with EEPROM |
| 文件： | 总64页 (文件大小：2157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2978
Octal PMBus Power Supply
Monitor and Controller
with EEPROM
FeaTures
DescripTion
The LTC®2978 is an octal, PMBus compliant power sup-
ply monitor, supervisor, sequencer and margin control-
ler. PMBus functions include warning and fault OV/UV
threshold pairs for eight output channels and one input
channel. Programmable fault response allows the power
supplies to be disabled with optional retry after a fault has
been detected. PMBus reads allow eight output voltages
and one input voltage to be monitored. In addition, odd
numbered channels can substitute sense resistor voltage
measurements for output voltage measurements. PMBus
commandssupportpowersupplysequencingandprecision
point-of-load voltage servo to one of three programmed
values: margin high, margin low and nominal. A program-
mable watchdog timer monitors microprocessor activity
for a stalled condition and resets the micro if necessary.
The 1-wire synchronization bus supports power supply
sequencing across multiple LTC2978 devices. User pro-
grammableparameterscanbestoredinEEPROM.Voltage
supervisor, voltage monitor and temperature faults can
also be logged to EEPROM.
n
PMBus Compliant Interface and Command Set
n
Configuration EEPROM
n
Fault Logging to Internal EEPROM
n
Differential Input, 15-Bit ∆Σ ADC with Less Than
±0.25% of Total Unadjusted Error
n
Monitors Eight Output Channels and One Input
Voltage
8-Channel Sequencer
Programmable Watchdog Timer
Eight UV/OV Voltage Supervisors
n
n
n
n
Eight 10-Bit Voltage-Buffered IDACs with Soft
Connect
n
Linear, Voltage Servo Adjusts Supply Voltages by
Ramping Voltage-Buffered IDAC Outputs Up/Down
n
Supports Multichannel Fault Management
n
On-Chip Digital Temperature Sensor
n
Available in 64-Pin 9mm × 9mm QFN Package
applicaTions
n
Computers
Network Servers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7382203 and 7420359.
n
Typical applicaTion
Octal Power Supply Controller with PMBus Interface
V
V
4.5V < V
IBUS
< 15V
IN
V
V
V
IN_SNS
PWR
OUT
TO INTERMEDIATE
BUS CONVERTER
ENABLE
V
DIGITALLY
MANAGED
POWER
IN_EN
DACP0
R30
41.2k
V
SENSEP0
R20
7.5k
SUPPLY
LTC2978*
V
SDA
LOAD
FB
R10
20k
SCL
V
PMBus
DACM0
INTERFACE
ALERTB
V
SENSEM0
SGND
CONTROL0
WP
V
RUN/SS
OUT_EN0
GND
WRITE-PROTECT
PWRGD
TO µP RESETB INPUT
WDI/RESETB
ASEL0
WATCHDOG
TIMER INTERRUPT
FAULTB00
TO/FROM OTHER
LTC2978s
SHARE_CLK
ASEL1
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978 TA01
2978fa
ꢀ
LTC2978
Table oF conTenTs
Features.............................................................................................................................1
Applications ........................................................................................................................1
Typical Application ................................................................................................................1
Description..........................................................................................................................1
Absolute Maximum Ratings......................................................................................................3
Order Information..................................................................................................................3
Pin Configuration ..................................................................................................................3
Electrical Characteristics.........................................................................................................4
Timing Diagram....................................................................................................................8
Typical Performance Characteristics ...........................................................................................8
Pin Functions..................................................................................................................... 12
Block Diagram.................................................................................................................... 14
Operation.......................................................................................................................... 15
Operation Overview ...............................................................................................................................................15
PMBus Serial Digital Interface ...............................................................................................................................16
Register Command Set..........................................................................................................................................18
Detailed PMBus Command Register Descriptions .................................................................................................22
Manufacturer Specific Commands.........................................................................................................................35
Watchdog ..............................................................................................................................................................49
Reset .....................................................................................................................................................................49
Write-Protect Pin...................................................................................................................................................49
Other Operations....................................................................................................................................................49
Applications Information ....................................................................................................... 50
PCB Assembly and Layout Suggestions ................................................................................................................61
Typical Application .............................................................................................................. 62
Package Description ............................................................................................................ 63
Typical Application .............................................................................................................. 64
Related Parts..................................................................................................................... 64
2978fa
ꢁ
LTC2978
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltages:
V
V
V
V
to GND......................................... –0.3V to 15V
PWR
IN_SNS
DD33
DD25
to GND ..................................... –0.3V to 15V
to GND ....................................... –0.3V to 3.6V
to GND ..................................... –0.3V to 2.75V
V
V
V
V
V
V
V
V
1
2
3
4
5
6
7
8
9
48 V
SENSEM6
SENSEP3
V
47 V
46 V
45 V
44 V
43 V
42 V
41 V
40 V
39 V
38 V
37 V
36 V
SENSEP7
SENSEM7
SENSEM2
SENSEP2
DACM2
Digital Input/Output Voltages:
ALERTB, SDA, SCL, CONTROL0,
CONTROL1............................................ –0.3V to 5.5V
PWRGD, SHARE_CLK,
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_EN5
DACP2
SENSEM1
SENSEP1
DACM1
65
WDI, WP..................................–0.3V to V
FAULTB00, FAULTB01, FAULTB10,
FAULTB11 ................................–0.3V to V
ASEL0, ASEL1..........................–0.3V to V
Analog Voltages:
+ 0.3V
DD33
DACP1
V
V
10
11
12
OUT_EN6
OUT_EN7
DACP0
DACM0
+ 0.3V
+ 0.3V
V
DD33
DD33
IN_EN
SENSEM0
SENSEP0
DNC 13
V
14
15
16
35 REFM
34 REFP
33 ASEL1
IN_SNS
V
PWR
V
DD33
REFP................................................... –0.3V to 1.35V
REFM to GND........................................ –0.3V to 0.3V
V
V
V
V
V
V
to GND................................. –0.3V to 6V
to GND ................................ –0.3V to 6V
OUT_EN[3:0] IN_EN
SENSEP[7:0]
SENSEM[7:0]
, V
to GND .................. –0.3V to 15V
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
to GND................................. –0.3V to 6V
OUT_EN[7:4]
DACP[7:0]
DACM[7:0]
T
= 125°C, θ = 28°C/W
JA
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
JMAX
to GND .................................... –0.3V to 6V
to GND ............................... –0.3V to 0.3V
Operating Temperature Range:
LTC2978C................................................ 0°C to 70°C
LTC2978I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
orDer inForMaTion
LEAD FREE FINISH
LTC2978CUP#PBF
LTC2978IUP#PBF
TAPE AND REEL
PART MARKING*
LTC2978
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2978CUP#TRPBF
LTC2978IUP#TRPBF
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
LTC2978
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2978fa
ꢂ
LTC2978
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Characteristics
l
l
l
l
V
V
V
V
V
V
Supply Input Operating Range
Supply Current
4.5
15
13
13
2.8
V
mA
mA
V
PWR
PWR
PWR
DD33
DD33
DD33
I
I
4.5V ≤ V
≤ 15V, V
Floating
DD33
10
10
PWR
PWR
Supply Current
3.13V ≤ V
≤ 3.47V, V
= V
PWR
VDD33
DD33
DD33
DD33
V
Undervoltage Lockout
Undervoltage Lockout
Hysteresis
V
Ramping Up, V = V
PWR
2.35
2.55
120
UVLO_VDD33
DD33
mV
l
l
l
l
l
V
Supply Input Operating Range
Regulator Output Voltage
V
= V
3.13
3.13
75
3.47
3.47
140
2.6
V
V
DD33
PWR
DD33
4.5V ≤ V
≤ 15V
3.26
90
PWR
Regulator Output Short-Circuit Current
Regulator Output Voltage
V
= 4.5V, V
= 0V
DD33
mA
V
PWR
V
3.13V ≤ V
≤ 3.47V
2.35
30
2.5
55
DD25
DD33
DD33
Regulator Output Short-Circuit Current
V
= V
= 3.47V, V
= 0V
80
mA
PWR
DD25
Voltage Reference Characteristics
V
Output Voltage
1.232
3
V
ppm/°C
ppm
REF
Temperature Coefficient
Hysteresis
(Note 3)
100
ADC Characteristics
l
V
Voltage Sense Input Range
Differential Voltage:
= (V
0
6
V
IN_ADC
V
– V
)
IN_ADC
SENSEPn
SENSEMn
l
l
l
Single-Ended Voltage: V
Single-Ended Voltage: V
–0.1
–0.1
–170
0.1
6
V
V
SENSEMn
Current Sense Input Range (Odd
Numbered Channels Only When So
Configured)
, V
SENSEPn SENSEMn
Differential Voltage: V
170
mV
IN_ADC
N_ADC
Voltage Sense Resolution
0V ≤ V ≤ 6V
122
µV/LSB
IN_ADC
Current Sense Resolution (Odd
Numbered Channels Only When So
Configured)
0mV ≤ |V
| < 16mV
15.625
31.25
62.5
µV/LSB
µV/LSB
µV/LSB
µV/LSB
µV/LSB
IN_ADC
16mV ≤ |V
32mV ≤ |V
| < 32mV
IN_ADC
IN_ADC
IN_ADC
| < 63.9mV
63.9mV ≤ |V
127.9mV ≤ |V
| < 127.9mV
125
|
250
IN_ADC
l
l
l
TUE_ADC
INL_ADC
Total Unadjusted Error
Integral Nonlinearity
V
≥ 1.8V (Note 4 )
0.25
854
%
µV
µV
IN_ADC
Voltage Sense Mode (Note 5)
Current Sense Mode, Odd Numbered
Channels Only, 15.6µV/LSB (Note 5)
31.3
l
l
DNL_ADC
Differential Nonlinearity
Offset Error
Voltage Sense Mode
400
µV
µV
Current Sense Mode, Odd Numbered
Channels Only
31.3
l
l
V
Voltage Sense Mode
250
35
µV
µV
OS_ADC
Current Sense Mode, Odd Numbered
Channels Only
l
l
GAIN_ADC
Gain Error
Voltage Sense Mode, V
= 6V
0.2
0.2
%
%
IN_ADC
Current Sense Mode, Odd Numbered
Channels Only, V 0.17V
=
IN_ADC
t
Conversion Time
Voltage Sense Mode (Note 6)
Current Sense Mode (Note 6)
Temperature Input (Note 6)
6.15
24.6
24.6
1
ms
ms
CONV_ADC
ms
C
Input Sampling Capacitance
Input Sampling Frequency
pF
IN_ADC
f
62.5
kHz
2978fa
IN_ADC
ꢃ
LTC2978
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
= 0V, 0V ≤ V ≤ 6V,
COMMONMODE
MIN
TYP
MAX
UNITS
l
I
Input Leakage Current
V
0.5
µA
IN_ADC
IN_ADC
Current Sense Mode
l
l
Differential Input Current
V
V
= 0.17V, Current Sense Mode
= 6V, Voltage Sense Mode
80
10
250
15
nA
µA
IN_ADC
IN_ADC
Voltage Buffered IDAC Output Characteristics
N_V
Resolution
10
Bits
DACP
l
l
V
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF Buffer Gain Setting_0
DAC Polarity = 1
(Note 7)
1.32
2.53
1.38
2.65
1.44
2.77
V
V
FS_VDACP
Buffer Gain Setting_1
l
l
l
INL_V
Integral Nonlinearity
Differential Nonlinearity
Offset Voltage
2
LSB
LSB
mV
DACP
DNL_V
(Note 7)
2.4
10
DACP
OS_VDACP
DACP
V
V
(Note 7)
Load Regulation (V
– V
)
V
V
= 2.65V, I Sourcing = 2mA
VDACPn
100
100
60
ppm/mA
ppm/mA
dB
DACPn
DACMn
DACPn
DACPn
= 0.1V, I
Sinking = 2mA
VDACPn
PSRR (V
– V
)
DC: 3.13V ≤ V
≤ 3.47V, V
= V
PWR DD33
DACPn
DACMn
DD33
100mV Step in 20ns with 50pF Load
–0.1V ≤ V ≤ 0.1V
40
dB
DC CMRR (V
– V
)
60
dB
DACPn
DACMn
DACMn
l
l
l
Leakage Current
V
V
V
V
Hi-Z, 0V ≤ V
≤ 6V
100
–4
nA
DACPn
DACPn
DACPn
DACPn
DACPn
Short-Circuit Current Low
Short-Circuit Current High
Output Capacitance
Shorted to GND
–10
4
mA
Shorted to V
Hi-Z
10
mA
DD33
C
10
pF
OUT
t
DAC Output Update Rate
Fast Servo Mode
250
µs
S_VDACP
Voltage Supervisor Characteristics
l
l
V
Input Voltage Range (Programmable)
V
= (V
SENSEMn
Low Resolution Mode
High Resolution Mode
0
0
6
3.8
V
V
IN_VS
IN_VS
SENSEPn
)
– V
l
Single-Ended Voltage: V
–0.1
0.1
V
mV/LSB
mV/LSB
%
SENSEMn
N_VS
Voltage Sensing Resolution
Total Unadjusted Error
0V to 3.8V Range: High Resolution Mode
0V to 6V Range: Low Resolution Mode
4
8
l
l
l
TUE_VS
2V ≤ V
≤ 6V, Low Resolution Mode
1.25
1.0
IN_VS
1.5V < V
0.8V ≤ V
≤ 3.8V, High Resolution Mode
≤ 1.5V, High Resolution Mode
%
IN_VS
IN_VS
1.5
%
t
Update Rate
12.21
90
µs
S_VS
V
Input Characteristics
IN_SNS
l
l
l
l
l
l
V
V
Input Voltage Range
0
15
110
2.0
1.0
1.5
1.0
V
kΩ
%
VIN_SNS
IN_SNS
IN_SNS
R
V
V
Input Resistance
Threshold Total
70
VIN_SNS
TUE
, V
3V ≤ V
≤ 8V
≤ 8V
VIN_SNS
IN_ON IN_OFF
VIN_SNS
Unadjusted Error
V
> 8V
%
VIN_SNS
READ_V Total Unadjusted Error
3V ≤ V
%
IN
VIN_SNS
V
> 8V
%
VIN_SNS
Voltage Buffered IDAC Soft-Connect Comparator Characteristics
Offset Voltage
Temperature Sensor Characteristics
TUE_TS Total Unadjusted Error
Enable Output (V
l
V
3
1
18
mV
°C
OS_CMP
V
[3:0]) Characteristics
OUT
OUT_EN
l
V
Output High Voltage
I
= –5µA, V = 3.3V
DD33
11.6
12.5
14.7
V
VOUT_ENn
VOUT_ENn
2978fa
ꢄ
LTC2978
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
Pull-Up Enabled, V
MIN
–5
3
TYP
–6
5
MAX
–8
UNITS
µA
l
l
I
Output Sourcing Current
Output Sinking Current
V
= 1V
VOUT_ENn
VOUT_ENn
VOUT_ENn
Strong Pull-Down Enabled,
= 0.4V
8
mA
V
VOUT_ENn
l
l
Weak Pull-Down Enabled, V
Internal Pull-Up Disabled,
= 0.4V
33
50
60
1
µA
µA
VOUT_ENn
Output Leakage Current
0V ≤ V
≤ 15V
VOUT_ENn
V
Enable Output (V
[7:4]) Characteristics
OUT
OUT_EN
l
l
I
Output Sinking Current
Strong Pull-Down Enabled,
OUT_ENn
3
6
9
1
mA
µA
VOUT_ENn
V
= 0.1V
Output Leakage Current
0V ≤ V
≤ 6V
VOUT_ENn
V
Enable Output (V ) Characteristics
IN_EN
IN
l
l
l
l
l
V
Output High Voltage
I
= –5µA, V = 3.3V
DD33
11.6
–5
3
12.5
–6
5
14.7
–8
8
V
µA
VIN_EN
VIN_EN
VIN_EN
I
Output Sourcing Current
Output Sinking Current
V
Pull-Up Enabled, V
= 1V
IN_EN
VIN_EN
Strong Pull-Down Enabled, V
= 0.4V
mA
µA
VIN_EN
Weak Pull-Down Enabled, V
Internal Pull-Up Disabled,
0V ≤ V
= 0.4V
33
50
60
1
VIN_EN
Leakage Current
µA
≤ 15V
VIN_EN
EEPROM Characteristics
l
Endurance
(Note 8)
0°C < T < 85°C During EEPROM Write
10,000
10
Cycles
J
Operations
l
l
Retention
(Note 8)
T < 85°C
A
Years
ms
Mass_Write Mass Write Operation Time (Note 9)
STORE_USER_ALL, 0°C < T < 85°C During
440
20
4100
1.5
J
EEPROM Write Operations
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
2.1
V
V
IH
l
IL
mV
µA
HYST
LEAK
l
l
I
Input Leakage Current
0V ≤ V ≤ 5.5V, SDA, SCL, CONTROLx
2
2
PIN
Pins Only
0V ≤ V ≤ V
+ 0.3V, FAULTBxx,
µA
PIN
DD33
WDI/RESETB, WP Pins Only
FAULTBxx, CONTROLx Pins Only
SDA, SCL Pins Only
t
Pulse Width of Spike Suppressed
10
98
µs
ns
SP
l
l
l
t
t
Pulse Width to Assert Reset
V
≤ 1.5V
≤ 1.5V
300
0.3
µs
RESETB
WDI
WDI/RESETB
Pulse Width to Reset Watchdog Timer
Watchdog Interrupt Input Frequency
Digital Input Capacitance
V
200
1
µs
WDI/RESETB
f
MHz
pF
WDI
C
10
IN
Digital Input SHARE_CLK
l
l
l
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Frequency Operating Range
Assertion Low Time
Rise Time
1.6
V
V
IH
0.8
110
1.1
450
1
IL
f
t
t
I
90
kHz
µs
SHARE_CLK_IN
LOW
V
V
< 0.8V
0.825
SHARE_CLK
SHARE_CLK
< 0.8V to V
> 1.6V
ns
RISE
SHARE_CLK
Input Leakage Current
Input Capacitance
0V ≤ V
≤ V + 0.3V
DD33
µA
pF
LEAK
SHARE_CLK
C
10
IN
2978fa
ꢅ
LTC2978
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11
l
l
V
Digital Output Low Voltage
I
= 3mA
0.4
V
OL
SINK
f
Output Frequency Operating Range
5.49kΩ Pull-Up to V
90
100
110
kHz
SHARE_CLK_OUT
DD33
Digital Inputs ASEL0,ASEL1
l
l
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
V
DD33
– 0.5
V
V
IH
0.5
95
24
IL
I
I
ASEL[1:0] = 0, V
µA
µA
pF
IH,IL
IH, Z
DD33
C
Input Capacitance
10
IN
Serial Bus Timing Characteristics
l
l
l
l
f
t
t
t
Serial Clock Frequency (Note 10)
Serial Clock Low Period (Note 10)
Serial Clock High Period (Note 10)
10
1.3
0.6
1.3
400
kHz
µs
SCL
LOW
HIGH
BUF
µs
Bus Free Time Between Stop and Start
(Note 10)
µs
l
l
l
l
t
t
t
t
Start Condition Hold Time (Note 10)
Start Condition Setup Time (Note 10)
Stop Condition Setup Time (Note 10)
600
600
600
0
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DAT
Data Hold Time (LTC2978 Receiving
Data) (Note 10)
l
l
Data Hold Time (LTC2978 Transmitting
Data) (Note 10)
300
100
900
ns
t
t
Data Setup Time (Note 10)
ns
ns
SU,DAT
SP
Pulse Width of Spike Suppressed
(Note 10)
98
l
l
t
Time Allowed to Complete any PMBus Longer Timeout = 0
Command After Which Time SDA Will Longer Timeout = 1
Be Released and Command Terminated
25
200
35
280
ms
ms
TIMEOUT_BUS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating for extended periods may affect device reliability and
lifetime.
Note 6: The time between successive ADC conversions (latency of the
ADC) for any given channel is given as: 36.9ms + (6.15ms • number of
ADC channels configured in Low Resolution mode) + (24.6ms • number of
ADC channels configured in High Resolution mode).
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
Note 7: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
specified. If power is supplied to the chip via the V
pin only, connect
DD33
Note 8: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 9: The LTC2978 will not acknowledge any PMBus write commands
when a STORE_USER_ALL command is being executed.
V
and V
pins together.
PWR
DD33
Note 3: Hysteresis in the output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 10: Maximum capacitive load, C , for SCL and SDA is 400pF. Data
B
Note 4: TUE(%) is defined as:
and clock rise time (t ) and fall time (t ) are: (20 + 0.1• C ) (ns) < t <
r
f
B
r
Gain Error (%) + 100 • (INL + V )/V .
300ns and (20 + 0.1 • C ) (ns) < t < 300ns. C = capacitance of one bus
OS IN
B f B
line in pF. SCL and SDA external pull-up voltage, V , is 3.13V < V < 5.5V.
IO
IO
Note 5: Integral nonlinearity (INL) is defined as the deviation of a code
from a straight line passing through the actual endpoints of the transfer
curve (0V and 6V). The deviation is measured from the center of the
quantization band.
2978fa
ꢆ
LTC2978
TiMing DiagraM
SDA
t
r
t
SU(DAT)
t
t
SP
t
HD(SDA)
r
t
t
t
f
t
f
BUF
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
2978 TD
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
Typical perForMance characTerisTics
ADC Total Unadjusted Error
vs Temperature
Temperature Sensor Error
Reference Voltage vs Temperature
vs Temperature
1.2355
1.2350
1.2345
1.2340
1.2335
1.2330
1.2325
1.2320
1.2315
1.2310
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.035
0.030
ADC V = 1.8V
IN
0.025
0.020
0.015
0.010
0.005
THREE TYPICAL PARTS
0
–50 –35 –20 –5 10 25
100
–50 –35 –20 –5 10 25 40 55 70 85 100
–50
–5
55
100
70 85
40 55 70 85
–35 –20
10 25 40
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2978 G01
2978 G02
2978 G03
ADC Zero Code Center Offset
Voltage vs Temperature
ADC-INL
ADC-DNL
0.8
0.6
0
–20
3.0
2.5
2.0
1.5
1.0
0.5
0
VOLTAGE SENSE MODE
122µV/LSB
122µV/LSB
0.4
–40
0.2
–60
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
–160
–180
–0.5
–1.0
–1.5
–0.2 0.8
1.8
2.8
3.8
4.8
–50 –35 –20 –5 10 25
100
–0.2 0.8
1.8
2.8
3.8
4.8
5.8
40 55 70 85
5.8
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
2978 G06
2978 G04
2978 G05
2978fa
ꢇ
LTC2978
Typical perForMance characTerisTics
ADC Rejection
vs Frequency at VIN
ADC Rejection
vs Frequency at VIN (Zoom)
ADC Rejection vs Frequency
at VIN (Current Sense Mode)
0
0
0
–20
–20
–20
–40
–60
–40
–60
–40
–60
–80
–100
–120
–80
–100
–120
–80
–100
–120
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
0
3125
6250
FREQUENCY (Hz)
9375
12500
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
2978 G07
2978 G08
2978 G09
ADC Rejection vs Frequency
Voltage Supervisor Total
ADC Noise Histogram
at VIN (Current Sense Mode, Zoom)
Unadjusted Error vs Temperature
1200
1000
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
V
= 0V
V
= 0.8V
IN
IN
HIGH RESOLUTION MODE
HIGH RESOLUTION MODE
–20
800
600
–40
–60
400
200
0
–80
–100
–120
–20
–10
0
10
20
0
3125
6250
9375
12500
–50 –35 –20 –5 10 25 40 55 70 85 100
READ_V
(µV)
FREQUENCY (Hz)
OUT
TEMPERATURE (°C)
2978 G11
2978 G10
2978 G12
Voltage Buffered IDAC Full-Scale
Output Voltage vs Temperature
Input Sampling Current
vs Differential Input Voltage
ADC High Resolution Mode
Differential Input Current
2.698
9
8
7
6
5
4
3
2
1
90
80
70
60
50
40
30
20
10
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
0
0
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
0
1
2
3
6
4
5
0
20 40 60 80 100
180
120 140 160
INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (mV)
2978 G15
2978 G13
2978 G14
2978fa
ꢈ
LTC2978
Typical perForMance characTerisTics
Voltage Buffered IDAC Offset
Voltage vs Temperature
Voltage Buffered IDAC DNL
Voltage Buffered IDAC-INL
1.0
0.8
1.0
0.8
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
200
400
600
800
1000
0
200
400
600
800
1000
–50 –35 –20 –5 10 25 40 55 70 85 100
DAC CODE
DAC CODE
TEMPERATURE (°C)
2978 G17
2978 G18
2978 G16
IDAC Voltage Buffer Load
Regulation (Sinking)
IDAC Voltage Buffer Short-Circuit
Current vs Temperature
Voltage Buffered IDAC Load
Regulation (Sourcing)
2.698
9.00
8.95
0.1038
0.1036
0.1034
0.1032
0.1030
0.1028
0.1026
85°C
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
85°C
25°C
25°C
8.90
8.85
8.80
8.75
8.70
–40°C
–40°C
0
–1
–1.50 1.75
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
–0.25 –0.5 –0.75
–1.25
–2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
CURRENT (mA)
CURRENT (mA)
2978 G19
2978 G21
2978 G20
IDAC Voltage Buffer Soft Connect
Transient Response when
Transitioning from Hi-Z State to
ON State
IDAC Voltage Buffer Soft Connect
Transient Response when
Transitioning from ON State to
Hi-Z State
IDAC Voltage Buffer Transient
Response to 1LSB DAC Code
Change
CODE ‘h200
HI-Z
HI-Z
500µV/DIV
10mV/DIV
10mV/DIV
CONNECTED
CONNECTED
CODE ‘h1FF
2978 G22
2978 G24
2978 G23
2µs/DIV
500µs/DIV
500µs/DIV
100k SERIES RESISTANCE ON
CODE: ‘h1FF
100k SERIES RESISTANCE ON
CODE: ‘h1FF
2978fa
ꢀ0
LTC2978
Typical perForMance characTerisTics
VDD33 Regulator Output Voltage
vs Temperature
VDD33 Regulator Short-Circuit
Current vs Temperature
VDD33 Regulator Line Regulation
3.275
3.270
3.265
3.260
3.255
3.250
3.245
3.240
3.235
–86
–88
400
300
85°C
25°C
200
–90
100
–92
–40°C
0
–94
–100
–200
–300
–400
–96
–98
–100
–102
–500
–50 –35 –20 –5 10 25 40 55 70 85 100
–50 –35 –20 –5 10 25 40 55 70 85 100
4.5
6
7.5
9
15
10.5 12 13.5
(V)
TEMPERATURE (°C)
V
TEMPERATURE (°C)
PWR
2978 G25
2978 G27
2978 G26
VOUT_EN[3:0] and VIN_EN Output
High Voltage vs Load Current
Supply Current vs Supply Voltage
Supply Current vs Temperature
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
10.5
10.4
10.3
10.2
10.1
10.0
9.9
10.16
10.14
V
= V
DD33
V
= 12V
PWR
PWR
85°C
25°C
10.12
–40°C
10.10
10.08
10.06
10.04
9.8
9.5
10.02
3.1
3.2
3.4
3
3.5
3.6
3.3
0
1
2
3
7
4
5
6
10
25 40 55 70 85 100
–50
–5
–35 –20
CURRENT SOURCING (µA)
V
(V)
TEMPERATURE (°C)
DD33
2978 G28
2978 G30
2978 G29
VOUT_EN[3:0] and VIN_EN VOL
vs Current
Voltage Buffered IDAC Output
Impedance vs Frequency
VOUT_EN[7:4] VOL vs Current
1000
100
10
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
85°C
25°C
1
–40°C
–40°C
0.1
0.01
0.01
0.1
1
10
100
1000
0
8
12
(mA)
16
20
24
8
12
4
0
2
4
6
10
I
FREQUENCY (kHz)
I
(mA)
SINK
SINK
2978 G31
2978 G33
2978 G32
2978fa
ꢀꢀ
LTC2978
Typical perForMance characTerisTics
PWRGD and FAULTBzn VOL
vs Current
ALERTB VOL vs Current
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
85°C
25°C
–40°C
8
12
0
2
4
6
10
0
4
6
8
10
12
2
I
(mA)
I
(mA)
SINK
SINK
2978 G35
2978 G34
pin FuncTions
PIN NAME
PIN NUMBER
PIN TYPE
In
DESCRIPTION
V
V
V
V
V
V
V
V
V
V
V
V
1*
2*
3*
4
5
6
7
8
9
10
11
12
13
14
DC/DC Converter Differential (–) Output Voltage-6 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Differential (–) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
DC/DC Converter Open-Drain Pull-Down Output-4
DC/DC Converter Open-Drain Pull-Down Output-5
DC/DC Converter Open-Drain Pull-Down Output-6
DC/DC Converter Open-Drain Pull-Down Output-7
DC/DC Converter V ENABLE Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA
SENSEM6
SENSEP7
SENSEM7
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_EN5
OUT_EN6
OUT_EN7
IN_EN
In
In
Out
Out
Out
Out
Out
Out
Out
Out
0ut
IN
DNC
Do Not Connect Do Not Connect to This Pin
V
V
V
In
V SENSE Input. This Voltage is Compared Against the V On and Off Voltage Thresholds in Order to
IN IN
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
V Serves as the Unregulated Power Supply Input to the Chip (4.5V to 15V). If a 4.5V to 15V Supply
PWR
Voltage is Unavailable, Short V
If Shorted to V
IN_SNS
15
16
In
PWR
to V
and Power the Chip Directly from a 3.3V Supply
PWR
DD33
In/Out
, it Serves as 3.13V to 3.47V Supply Input Pin. Otherwise it is a 3.3V Internally
DD33
PWR
Regulated Voltage Output (Use 100nF Decoupling Capacitor to GND)
Input for Internal 2.5V Sub-Regulator. Short This Pin to Pin 16
2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1µF Capacitor
Digital Input. Write-Protect Input Pin, Active High
Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as System
Power-On Reset
V
V
WP
17
18
19
20
In
In/Out
In
DD33
DD25
PWRGD
Out
SHARE_CLK
WDI/RESET
21
22
In/Out
In
Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to V
DD33
Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to V
. Rising Edge
DD33
Resets Watchdog Counter. Holding This Pin Low for More Than t
Resets the Chip
RESETB
2978fa
ꢀꢁ
LTC2978
pin FuncTions
FAULTB00
FAULTB01
FAULTB10
FAULTB11
23
24
25
26
In/Out
In/Out
In/Out
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-00. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-01. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-10. Connect a 10k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 10k Pull-Up
Resistor to V
DD33
SDA
SCL
27
28
29
30
31
32
33
34
35
36*
37*
38
39
40
In/Out
In
Out
In
In
In
PMBus Bidirectional Serial Data Pin
PMBus Serial Clock Input Pin (400kHz Maximum)
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
Control Pin 0 Input
Control Pin 1 Input
Ternary Address Select Pin 0 Input. Connect to V
Ternary Address Select Pin 1 Input. Connect to V
Reference Voltage Output. Needs 0.1µF Decoupling Capacitor to REFM
Reference Return Pin. Needs 0.1µF Decoupling Capacitor to REFP.
DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin
Voltage Buffered IDAC0 Return. Connect to Channel 0 DC/DC Converter’s GND Sense or Return to GND
Voltage Buffered IDAC0 Output
ALERTB
CONTROL0
CONTROL1
ASEL0
ASEL1
REFP
, GND or Float to Encode 1 of 3 Logic States
, GND or Float to Encode 1 of 3 Logic States
DD33
In
DD33
Out
Out
In
REFM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SENSEP0
SENSEM0
DACM0
In
Out
Out
Out
Out
In
DACP0
Voltage Buffered IDAC1 Output
DACP1
41
Voltage Buffered IDAC1 Return. Connect to Channel 1 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-1 Sensing Pins
Voltage Buffered IDAC2 Output
Voltage Buffered IDAC2 Return. Connect to Channel 2 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-3 Sensing Pins
Voltage Buffered IDAC3 Output
Voltage Buffered IDAC3 Return. Connect to Channel 3 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-4 Sensing Pin
Voltage Buffered IDAC4 Return. Connect to Channel 4 DC/DC Converter’s GND Sense or Return to GND
Voltage Buffered IDAC4 Output
DACM1
42*
43*
44
SENSEP1
SENSEM1
DACP2
In
Out
Out
In
In
In
45
DACM2
46*
47*
48*
49*
50
SENSEP2
SENSEM2
SENSEP3
SENSEM3
DACP3
In
Out
Out
In
51
DACM3
52*
53*
54
55
56
57
58
59
60
SENSEP4
SENSEM4
DACM4
In
Out
Out
Out
Out
Out
Out
Out
Out
In
DACP4
Voltage Buffered IDAC5 Output
DACP5
Voltage Buffered IDAC5 Return. Connect to Channel 5 DC/DC Converter’s GND Sense or Return to GND
Voltage Buffered IDAC6 Return. Connect to Channel 6 DC/DC Converter’s GND Sense or Return to GND
Voltage Buffered IDAC6 Output
DACM5
DACM6
DACP6
Voltage Buffered IDAC7 Output
DACP7
61
Voltage Buffered IDAC7 Return. Connect to Channel 7 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin
Exposed Pad, Must be Soldered to PCB
DACM7
62*
63*
64*
65
SENSEP5
SENSEM5
SENSEP6
In
In
Ground
GND
*Any unused V
or V
pins must be tied to GND.
SENSEPn
SENSEMn
2978fa
ꢀꢂ
LTC2978
block DiagraM
3.3V REGULATOR
IN
V
15
16
V
V
OUT
PWR
V
V
DD
DD33
2.5V REGULATOR
IN
OUT
V
V
17
18
V
V
DD33
DD25
3R
V
V
SENSEM0
SENSEP0
V
14
IN_SNS
R
V
V
SENSEM1
SENSEP1
36
37
42
43
46
47
48
49
52
53
62
63
64
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SENSEP0
SENSEM0
SENSEP1
SENSEM1
SENSEP2
SENSEM2
SENSEP3
SENSEM3
SENSEP4
SENSEM4
SENSEP5
SENSEM5
SENSEP6
SENSEM6
SENSEP7
SENSEM7
GND 65
V
V
SENSEM2
SENSEP2
V
V
SENSEM3
SENSEP3
–
+
–
+
V
V
SENSEM4
SENSEP4
INTERNAL
TEMP
SENSOR
CMP0
MUX
+
–
10-BIT
VDAC
V
V
SENSEM5
SENSEP5
V
V
SENSEM6
SENSEP6
V
V
SENSEM7
SENSEP7
+
–
15-BIT
+
$∑ ADC
2
SC
CMP0
3
–
IDAC0
10 BITS
+
ADC
CLOCKS
39
40
44
50
55
56
59
60
V
V
V
V
V
V
V
V
VBUF0
DACP0
DACP1
DACP2
DACP3
DACP4
DACP5
DACP6
DACP7
–
V
DD
REFERENCE
1.232V
REFP 34
REFM 35
(TYP)
38
41
45
51
54
57
58
61
V
V
V
V
V
V
V
V
DACM0
DACM1
DACM2
DACM3
DACM4
DACM5
DACM6
DACM7
NONVOLATILE MEMORY
EEPROM
SCL 28
SDA 27
PMBus
INTERFACE
ALERTB 29
ASEL0 32
ASEL1 33
2
(400kHz I C
RAM
COMPATIBLE)
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
WP 19
4
5
6
7
V
V
V
V
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUTPUT
CONFIG
CONTROL0 30
CONTROL1 31
WDI/RESET 22
FAULTB00 23
FAULTB01 24
FAULTB10 25
FAULTB11 26
CLOCK
GENERATION
OSCILLATOR
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
12
V
IN_EN
V
DD
8
9
V
V
V
V
OUT_EN4
OUT_EN5
OUT_EN6
OUT_EN7
SEQUENCER
UVLO
OPEN-DRAIN
OUTPUT
10
11
PWRGD
20
SHARE_CLK 21
2978 BD
2978fa
ꢀꢃ
LTC2978
operaTion
OPERATION OVERVIEW
n
n
n
Store command register contents to EEPROM through
PMBus programming.
The LTC2978 is a PMBus programmable power supply
controller, monitor, sequencer and voltage supervisor that
can perform the following operations:
Restore EEPROM contents through PMBus program-
ming or on POR.
n
Accept PMBus compatible programming commands.
Report the DC/DC converter output voltage status
through the PMBus interface and the power good
output.
n
Provide DC/DC converter input voltage and output volt-
age/current read back through the PMBus interface.
n
n
n
n
n
Generate interrupt requests by asserting the ALERTB
pin in response to supported PMBus faults.
n
Control the output of modules that set voltage with a
trim pin or modules that set the output voltage using
an external resistor feedback network.
Shut down multiple DC/DC converters in response to
a fault through the FAULTBz0 and FAULTBz1 pins.
n
Sequence the start-up of DC/DC converters via PMBus
programming and the CONTROL input pins.
Synchronizesequencingdelaysorshutdownformultiple
devices using the SHARE_CLK pin.
n
Trim the DC/DC converter output voltage (typically in
0.1% steps), in closed-loop servo operating mode,
through PMBus programming.
Software and hardware write protect the command
registers.
n
Margin the DC/DC converter output voltage to PMBus
programmed limits (typically 10%).
Disable the input voltage to the supervised DC/DC
converters in response to output voltage OV and UV
faults.
n
Allow the user to trim or margin the DC/DC converter
n
n
outputvoltageinamanualoperatingmodebyproviding
direct access to the margin DAC.
Log telemetry and status data to EEPROM in response
to a faulted-off condition
n
Supervise the DC/DC converter output voltage, input
Supervise an external microcontroller’s activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
voltage, and the LTC2978 die temperature for over-
value/undervalue conditions with respect to PMBus
programmedlimitsandgenerateappropriatefaultsand
warnings.
n
Prevent a DC/DC converter from re-entering the ON
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
n
Respond to a fault condition by either continuing op-
eration indefinitely, latching off after a programmable
de-glitch period or latching off immediately. A retry
mode may be used to automatically recover from a
latched-off condition.
n
Record minimum and maximum observed values of
input voltage, output voltages and temperature.
n
StoptrimmingtheDC/DCconverteroutputvoltageafter
itreachedtheinitialmarginornominaltarget.Optionally
allows servo to resume if target drifts outside of V
warning limits.
OUT
2978fa
ꢀꢄ
LTC2978
operaTion
PMBus SERIAL DIGITAL INTERFACE
Figures 1-10 illustrate the aforementioned SMBus pro-
tocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 256 bytes of returned data. For this reason, the
PMBustimeoutmaybeextendedusingtheMfr_config_all_
longer_pmbus_timeout setting.
The LTC2978 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
TheLTC2978willnotacknowledgeanyPMBuscommandif
itisstillbusywithaSTORE_USER_ALL,RESTORE_USER_
ALL, MFR_CONFIG or if fault log data is being written to
the EEPROM. Status_word_busy will also be set.
TheLTC2978isaslavedevice.Themastercancommunicate
with the LTC2978 using the following formats:
n
Master transmitter, slave receiver
Slave Address
n
Master receiver, slave transmitter
The LTC2978 can be configured to respond to one of nine
addresses for a given MFR_I2C_BASE_ADDRESS value
(the factory default value for this register is 7’h5C). In
addition, the LTC2978 will always respond to its global
address and the PMBus Alert Response address regard-
less of the state of the address select pins.
The following SMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
n
Alert Response Address
By connecting each of the address inputs to V
, GND,
DD33
or by floating them, the user determines the slave address
as shown in Table 1.
Table 1. LTC2978 Address Look-Up Table
HEX DEVICE
DESCRIPTION
ADDRESS
BINARY DEVICE ADDRESS
ADDRESS PINS
7’h
8’h
19
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
6
0
1
1
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
1
1
1
1
1
4
0
1
1
1
1
1
0
0
0
0
0
3
1
1
1
1
1
1
0
0
0
0
0
2
1
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
R/W
1
ASEL1
ASEL0
Alert Response
0C
5B
5C
5D
5E
5F
60
61
62
63
64
X
X
X
X
Global
0
0*
1
0
L
L
0
L
NC
H
2
0
L
3
0
NC
NC
NC
H
L
4
0
NC
H
5
0
6
0
L
7
0
H
NC
H
8
0
H
H = Tie to V
, NC = No Connect, Open or Float, L = Tie to GND, X = Don’t Care
DD33
*MFR_I2C_BASE_ADDRESS = 7’h5C (Factory Default)
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ꢀꢅ
LTC2978
operaTion
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
2978 F01
Figure 1. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
2978 F02
Figure 2. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
2978 F03
Figure 3. Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
2978 F04
Figure 4. Write Word Protocol with PEC
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
DATA BYTE
A
P
2978 F05
Figure 5. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
DATA BYTE
A
PEC
A
P
2978 F06
Figure 6. Send Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
1 2978 F07
Figure 7. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
1 2978 F08
Figure 8. Read Word Protocol with PEC
1
7
1
1
8
1
1
8
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE
A
P
1 2978 F09
Figure 9. Read Byte Protocol
1
7
1
1
8
1
1
8
1
1
8
1
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
1 2978 F10
Figure 10. Read Byte Protocol with PEC
2978fa
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LTC2978
operaTion
REGISTER COMMAND SET
Summary
DATA
NV
LENGTH COMMAND MEMORY DEFAULT PAGED
COMMAND FUNCTION
PAGE
DESCRIPTION
R/W
R/W
R/W
R/W
(BITS) BYTE VALUE
TYPE
VALUE
?
N
Y
Y
8
8
8
‘h00
‘h01
‘h02
‘h00
OPERATION
Operating mode control.
EEPROM
EEPROM
‘h00
ON_OFF_CONFIG
CONTROL pin and PMBus bus on/off
command setting.
‘h12
CLEAR_FAULTS
CLEAR_FAULTS is used to clear any fault
bits that have been set.
W
R/W
W
0
8
0
0
8
‘h03
‘h10
‘h15
‘h16
‘h19
NA
‘h00
NA
Y
N
N
N
N
WRITE_PROTECT
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
Provides protection against accidental
changes.
EEPROM
ROM
Store entire operating memory to
EEPROM.
Restore entire operating memory from
EEPROM.
W
NA
The CAPABILITY command provides a
way for a host system to determine the
capabilities of the PMBus device.
R
‘hE0
VOUT_MODE
Output voltage format control.
R
8
‘h20
‘h21
ROM
‘h13
Y
Y
VOUT_COMMAND
Servo DC/DC converter output voltage
value setting.
R/W
16
EEPROM
‘h2000
VOUT_MAX
The VOUT_MAX command sets an upper
limit on the output voltage, in volts, the
unit can command regardless of any other
commands or combinations.
R/W
16
‘h24
EEPROM
‘h8000
Y
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VIN_ON
Margin high DC/DC converter output
voltage limit setting.
R/W
R/W
R/W
16
16
16
‘h25
‘h26
‘h35
EEPROM
EEPROM
EEPROM
‘h219A
‘h1E66
‘hD280
Y
Y
N
Margin low DC/DC converter output
voltage limit setting.
The VIN_ON command sets the input
voltage, in volts, at which the unit should
start power conversion.
VIN_OFF
The VIN_OFF command sets the input
voltage, in volts, at which the unit should
stop power conversion.
R/W
16
‘h36
EEPROM
‘hD240
N
VOUT_OV_FAULT_LIMIT
Overvoltage DC/DC converter fault limit
setting.
R/W
R/W
16
8
‘h40
‘h41
EEPROM
EEPROM
‘h2333
‘h80
Y
Y
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE
command instructs the device on what
action to take in response to an output
overvoltage fault.
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
Overvoltage DC/DC converter warning limit R/W
setting.
16
16
‘h42
‘h43
EEPROM
EEPROM
‘h2266
‘h1D9A
Y
Y
Undervoltage DC/DC converter warning
limit setting.
R/W
2978fa
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LTC2978
operaTion
Summary
DATA
NV
LENGTH COMMAND MEMORY DEFAULT PAGED
COMMAND FUNCTION
DESCRIPTION
R/W
(BITS) BYTE VALUE
TYPE
VALUE
?
VOUT_UV_FAULT_LIMIT
Undervoltage DC/DC converter fault limit
setting. This limit is also used to determine
if Ton_max_fault has been met and the
unit is on.
R/W
16
‘h44
EEPROM ‘h1CCD
Y
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE
command instructs the device on
what action to take in response to an
undervoltage fault.
R/W
8
‘h45
EEPROM
‘h7F
Y
OT_FAULT_LIMIT
Overtemperature fault limit setting.
R/W
R/W
16
8
‘h4F
‘h50
EEPROM
EEPROM
‘hEAA8
‘hB8
N
N
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command
instructs the device on what action to take
in response to an overtemperature fault.
OT_WARN_LIMIT
UT_WARN_LIMIT
UT_FAULT_LIMIT
UT_FAULT_RESPONSE
Overtemperature warning limit setting.
Undertemperature warn limit setting.
Undertemperature fault limit setting.
R/W
R/W
R/W
R/W
16
16
16
8
‘h51
‘h52
‘h53
‘h54
EEPROM
EEPROM
EEPROM
EEPROM
‘hEA58
‘h8000
‘hCD80
‘hB8
N
N
N
N
The UT_FAULT_RESPONSE command
instructs the device on what action to take
in response to an undertemperature fault.
VIN_OV_FAULT_LIMIT
Input supply overvoltage fault limit setting. R/W
16
8
‘h55
‘h56
EEPROM
EEPROM
‘hD3C0
‘h80
N
N
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command R/W
instructs the device on what action to take
in response to an input overvoltage fault.
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
Overvoltage input supply warning limit
setting.
R/W
R/W
R/W
16
16
16
8
‘h57
‘h58
‘h59
‘h5A
EEPROM
EEPROM
EEPROM
EEPROM
‘hD380
‘h8000
‘h8000
‘h00
N
N
N
N
Undervoltage input supply warning limit
setting.
Undervoltage input supply fault limit
setting.
The VIN_UV_FAULT_RESPONSE command R/W
instructs the device on what action to take
in response to an input undervoltage fault.
POWER_GOOD_ON
POWER_GOOD_OFF
TON_DELAY
Output voltage at or above which a power
good should be asserted.
R/W
R/W
R/W
R/W
16
16
16
16
‘h5E
‘h5F
‘h60
‘h61
EEPROM
EEPROM
EEPROM
EEPROM
‘h1EB8
‘h1E14
‘hBA00
‘hD280
Y
Y
Y
Y
Output voltage at or below which a power
good should be deasserted.
Time, in ms, from CONTROL and/or
Operation on to V
on.
OUT_EN
TON_RISE
Time, in ms, from when the output starts
to rise until the LTC2978 optionally soft-
connects its voltage-buffered current DAC
and begins to servo the output voltage to
the desired value.
TON_MAX_FAULT_LIMIT
Maximum time, in ms, from V
R/W
R/W
16
8
‘h62
‘h63
EEPROM
EEPROM
‘hD3C0
‘hB8
Y
OUT_EN
on assertion that an UV condition will
be tolerated before a TON_MAX_FAULT
condition results.
TON_MAX_FAULT_RESPONSE
Specifies response to a TON_MAX_FAULT
event.
Y
2978fa
ꢀꢈ
LTC2978
operaTion
Summary
DATA
NV
LENGTH COMMAND MEMORY DEFAULT PAGED
COMMAND FUNCTION
DESCRIPTION
R/W
(BITS) BYTE VALUE
TYPE
VALUE
?
TOFF_DELAY
Time, in ms, from CONTROL and/or
Operation off to VOUT_EN off.
R/W
16
‘h64
EEPROM
‘hBA00
Y
STATUS_BYTE
Fault status reporting.
R
R
8
‘h78
‘h79
NA
NA
Y
Y
STATUS_WORD
The STATUS_WORD command returns
two bytes of information with a summary
of the unit’s fault condition.
16
STATUS_VOUT
STATUS_INPUT
Voltage fault status reporting.
R
R
8
8
‘h7A
‘h7C
NA
NA
Y
N
The STATUS_INPUT command returns one
byte with status on V
.
IN_SNS
STATUS_TEMPERATURE
STATUS_CML
The STATUS_TEMPERATURE command
returns one byte with status information
on temperature.
R
R
R
8
8
8
‘h7D
‘h7E
‘h80
NA
NA
NA
N
N
Y
The STATUS_CML command returns
one byte with status information on
communication and memory.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command
returns one byte with the manufacturer
specific status information.
READ_VIN
Input supply voltage read back.
R
R
16
16
16
8
‘h88
‘h8B
‘h8D
‘h98
‘hD0
NA
NA
N
Y
N
N
Y
READ_VOUT
DC/DC converter output voltage read back.
Internal junction temperature read back.
Read the supported PMBus revision (1.1).
READ_TEMPERATURE_1
PMBUS_REVISION
MFR_CONFIG
R
NA
R
ROM
‘h11
‘h0080
Manufacturer configuration bits that are
channel specific.
R/W
16
EEPROM
MFR_CONFIG_ALL
Manufacturer configuration bits that are
common to all pages.
R/W
R/W
8
8
‘hD1
‘hD2
EEPROM
EEPROM
‘h7B
‘h00
N
Y
MFR_FAULTBz0_PROPAGATE
Manufacturer configuration that
determines which channel faults are
propagated to FAULTBz0 where z = 0 for
channels 0-3, and z=1 for channels 4-7.
MFR_FAULTBz1_PROPAGATE
Manufacturer configuration that
determines which channel faults are
propagated to FAULTBz1.
R/W
8
‘hD3
EEPROM
‘h00
Y
MFR_PWRGD_EN
Maps PWRGD status to the PWRGD pin.
R/W
R/W
16
8
‘hD4
‘hD5
EEPROM
EEPROM
‘h0000
‘h00
N
N
MFR_FAULTB00_RESPONSE
Determines response to FAULTB00 pin
being asserted low.
MFR_FAULTB01_RESPONSE
MFR_FAULTB10_RESPONSE
MFR_FAULTB11_RESPONSE
MFR_VINEN_OV_FAULT_RESPONSE
Determines response to FAULTB01 pin
being asserted low.
R/W
R/W
R/W
R/W
8
8
8
8
‘hD6
‘hD7
‘hD8
‘hD9
EEPROM
EEPROM
EEPROM
EEPROM
‘h00
‘h00
‘h00
‘h00
N
N
N
N
Determines response to FAULTB10 pin
being asserted low.
Determines response to FAULTB11 pin
being asserted low.
Determines the response of the VIN_EN
pin to a VOUT_OV_FAULT
2978fa
ꢁ0
LTC2978
operaTion
Summary
DATA
NV
LENGTH COMMAND MEMORY DEFAULT PAGED
COMMAND FUNCTION
DESCRIPTION
R/W
(BITS) BYTE VALUE
TYPE
VALUE
?
MFR_VINEN_UV_FAULT_RESPONSE
Determines the response of the VIN_EN
pin to a VOUT_UV_FAULT
R/W
8
‘hDA
EEPROM
‘h00
N
MFR_RETRY_DELAY
Sets retry interval during retry mode.
R/W
R/W
16
16
‘hDB
‘hDC
EEPROM
EEPROM
‘hF320
‘hFB20
N
N
MFR_RESTART_DELAY
Sets delay from actual CONTROL active
edge to virtual CONTROL active edge.
MFR_VOUT_PEAK
MFR_VIN_PEAK
Returns the maximum measured value of
OUT
R
R
16
16
16
16
‘hDD
‘hDE
‘hDF
‘hE0
NA
NA
Y
N
N
Y
V
.
Returns the maximum measured value of
V
.
IN_SNS
MFR_TEMPERATURE_PEAK
MFR_DAC
Returns the maximum measured value of
temperature.
R
NA
Manufacturer register that contains the
code of the 10-bit voltage-buffered current
DAC.
R/W
EEPROM
EEPROM
‘h0000
MFR_POWERGOOD_ASSERTION_DELAY Determines power good output assertion
delay.
R/W
16
‘hE1
‘hEB20
N
MFR_WATCHDOG_T_FIRST
MFR_WATCHDOG_T
First watchdog timer interval.
Watchdog timer interval.
R/W
R/W
R/W
16
16
8
‘hE2
‘hE3
‘hE4
EEPROM
EEPROM
EEPROM
‘h8000
‘h8000
‘hFF
N
N
N
MFR_PAGE_FF_MASK
Selects which channels respond to global
page commands.
MFR_PADS
Returns values detected and driven onto
digital I/O pads.
R
16
8
‘hE5
‘hE6
‘hE7
‘hE8
N/A
‘h5C
N
N
N
Y
MFR_I2C_BASE_ADDRESS
MFR_SPECIAL_ID
MFR_SPECIAL_LOT
This register determines the base value of
R/W
R
EEPROM
EEPROM
2
the I C address byte.
This register contains the manufacturer
code for identifying the LTC2978.
16
8
‘h0121
These registers contain customer
dependent codes that identify the factory
programmed user configuration stored in
EEPROM.
R/W
EEPROM Contact
the
Factory
MFR_VOUT_DISCHARGE_THRESHOLD
MFR_FAULT_LOG_STORE
Coefficient used to multiply VOUT_
COMMAND in order to determine VOUT
OFF threshold voltage.
R/W
W
16
0
‘hE9
‘hEA
‘hEB
‘hEC
EEPROM
‘hC200
NA
Y
N
N
N
Command a transfer of the fault log from
RAM to EEPROM. This causes the part to
behave as if a channel has faulted off.
MFR_FAULT_LOG_RESTORE
MFR_FAULT_LOG_CLEAR
Command a transfer of the fault log
previously stored in EEPROM back to
RAM.
W
0
NA
Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
W
0
NA
MFR_FAULT_LOG_STATUS
MFR_FAULT_LOG
This command returns one byte with
status information on fault logging.
R
R
8
‘hED
‘hEE
EEPROM
EEPROM
NA
NA
N
N
Fault log. Accessed using a block read.
Returns data in the form last in first out.
2048
2978fa
ꢁꢀ
LTC2978
operaTion
Summary
DATA
NV
LENGTH COMMAND MEMORY DEFAULT PAGED
COMMAND FUNCTION
DESCRIPTION
R/W
(BITS) BYTE VALUE
TYPE
VALUE
?
MFR_COMMON
Contains manufacturer status bits that are
common across multiple LTC chips.
R
8
‘hEF
NA
N
MFR_SPARE_0
MFR_SPARE_2
MFR_VOUT_MIN
Scratchpad register.
R/W
R/W
R
16
16
16
‘hF7
‘hF9
‘hFB
EEPROM
EEPROM
‘h0000
‘h0000
NA
N
Y
Y
Paged scratchpad register.
Returns the minimum measured value of
VOUT.
MFR_VIN_MIN
Returns the minimum measured value of
IN_SNS
R
R
16
16
‘hFC
‘hFD
NA
NA
N
N
V
.
MFR_TEMPERATURE_MIN
Returns the minimum measured junction
temperature value.
PAGE Data Contents
BIT(S) SYMBOL PURPOSE
b[7:0] Page Page operation.
DETAILED PMBus COMMAND REGISTER
DESCRIPTIONS
‘h00: All PMBus commands address channel/page 0.
‘h01: All PMBus commands address channel/page 1.
PAGE
The PAGE command provides the ability to configure,
control and monitor multiple outputs on one unit. Set-
ting PAGE = ‘hFF allows PMBus commands that support
global page programming to be written simultane-
ously. The only commands that support PAGE = ‘hFF are
OPERATION and ON_OFF_CONFIG. See MFR_PAGE_FF_
MASK for additional options. Reading any PMBus register
withPAGE=‘hFFreturnsunpredictabledataandwilltrigger
a CML fault.
•
•
•
‘h07: All PMBus commands address channel/page 7.
‘hXX: All nonspecified values reserved.
‘hFF: PMBus commands that support this global PAGE
write mode will be written simultaneously.
2978fa
ꢁꢁ
LTC2978
operaTion
OPERATION
The OPERATION command is used to turn the unit on and
off in conjunction with the CONTROLn pin and ON_OFF_
CONFIG. This command register responds to the global
page command. The contents and functions of the data
byte are shown in the following tables.
OPERATION Data Contents When On_Off_Config_Use_PMBus Enables Operation_Control
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
00
b[5:4]
XX
b[3:2]
XX
b[1:0]
00
Turn off immediately
Turn on
10
00
XX
00
Margin Low (Ignore Faults and
Warnings)
10
01
01
00
Margin Low
10
10
01
10
10
01
00
00
Margin High (Ignore Faults and
Warnings
Margin High
10
01
10
00
10
00
00
FUNCTION
Sequence off and margin to
nominal
XX
Sequence off and Margin Low
(Ignore Faults and Warnings)
01
01
01
00
Sequence off and Margin Low
01
01
01
10
10
01
00
00
Sequence off and Margin High
(Ignore Faults and Warnings)
Sequence off and Margin High
Reserved
01
10
10
00
All remaining combinations
OPERATION Data Contents When On_Off_Config is Configured Such That OPERATION Command is Not Used to Command Channel On
or Off
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
b[5:4]
00
b[3:2]
XX
b[1:0]
00
Output at Nominal
00, 01 or 10
00, 01 or 10
Margin Low (Ignore faults and
Warnings)
01
01
00
Margin Low
00, 01 or 10
00, 01 or 10
01
10
10
01
00
00
FUNCTION
Margin High (Ignore Faults and
Warnings
Margin High
Reserved
00, 01 or 10
10
10
00
All remaining combinations
2978fa
ꢁꢂ
LTC2978
operaTion
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combina-
tion of CONTROLn pin input and PMBus bus commands
neededtoturntheLTC2978on/off, includingthepower-on
behavior, as shown in the following table. This command
register responds to the global page command.
ON_OFF_CONFIG Data Contents
BITS(S) SYMBOL
OPERATION
b[7:5] Reserved
Don’t care. Always returns 0.
b[4] On_off_config_controlled_on
Control default autonomous power-up operation.
0: Unit powers up regardless of the CONTROLn pin. Unit always powers up with sequencing. To turn unit on
without sequencing, set TON_DELAY = 0.
1: Unit does not power up unless commanded by the CONTROLn pin and/or the OPERATION command on
the serial bus. If On_off_config[3:2] = 00, the unit never powers up.
b[3] On_off_config_use_pmbus
b[2] On_off_config_use_control
b[1] Reserved
Controls how the unit responds to commands received via the serial bus.
0: Unit ignores the Operation_control[1:0].
1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also
require the CONTROLn pin to be asserted for the unit to start.
Controls how unit responds to the CONTROLn pin.
0: Unit ignores the CONTROLn pin.
1: Unit requires the CONTROLn pin to be asserted to start the unit. Depending on On_off_config_use_
PMBus the OPERATION command may also be required to instruct the device to start.
Not supported. Always returns 1.
b[0] On_off_config_control_fast_off CONTROLn pin turn off action when commanding the unit to turn off
0: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible. The device does not sink current
in order to decrease the output voltage fall time.
2978fa
ꢁꢃ
LTC2978
operaTion
STORE_USER_ALL. No Data Contents. Accessing this
command will store all operating memory commands
with a corresponding EEPROM memory location. It is
recommended that this command not be executed while
a unit is enabled since all monitoring is suspended while
the operating memory is transferred to EEPROM.
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any status
faults that have been set. This command clears all bits in
allunpagedstatusregisters,andthepagedstatusregisters
selected by the current PAGE setting. At the same time,
the device negates (clears, releases) its contribution to
ALERTB.
RESTORE_USER_ALL. No Data Contents. Accessing
this command will restore all commands from EEPROM
Memory. It is recommend that this command not be
executed while a unit is enabled since all monitoring is
suspended while the EEPROM is transferred to operating
memory, and intermediate values from EEPROM may not
be compatible with the values initially stored in operating
memory.
The CLEAR_FAULTS command does not cause a unit that
has latched off for a fault condition to restart.
If the fault condition is present after the fault status is
cleared, the fault status bit shall be set again and the host
notified by the usual means.
Note: this command register does not respond to the
global page command.
CAPABILITY
WRITE_PROTECT
The CAPABILITY command provides a way for a host
systemtodeterminesomekeycapabilitiesoftheLTC2978.
This one byte command is read only.
The WRITE_PROTECT command provides protection
againstaccidentalprogrammingoftheLTC2978command
registers.Allsupportedcommandsmayhavetheirparam-
eters read, regardless of the WRITE_PROTECT setting.
CAPABILITY Data Contents
BITS(S) SYMBOL
OPERATION
b[7]
Capability_pec
Hard coded to 1 indicating Packet
Error Checking is supported. Reading
the Mfr_config_all_pec_en bit will
indicate whether PEC is currently
required.
WRITE_PROTECT Data Contents
BITS(S) SYMBOL
OPERATION
b[7:0] Write_protect[7:0] 8’b1000_0000: Disable all writes except
to the WRITE_PROTECT, PAGE, and
STORE_USER_ALL commands.
b[6]
b[5]
Capability_scl_max
Hard coded to 1 indicating the
maximum supported bus speed is
400kHz.
8’b0100_0000: Disable all writes except
to the WRITE_PROTECT, PAGE, STORE_
USER_ALL, OPERATION, MFR_PAGE_
FF_MASK, and CLEAR_FAULTS.
Capability_smb_alert Hard coded to 1 indicating this device
does have an ALERTB pin and does
support the SMBus Alert Response
Protocol.
8’b0000_0000: Enable writes to all
commands.
8’bxxxx_xxxx: All other values reserved.
b[4:0] Reserved
X: Always returns 0.
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands
provide access to user nonvolatile EEPROM memory.
Once a command is stored in EEPROM, it will be restored
with explicit restore command or when the part emerges
from power-on reset after power is applied. While either
of these commands is being processed, the device will
2
NACK I C writes.
2978fa
ꢁꢄ
LTC2978
operaTion
VOUT_MODE
Output Voltage Related Commands
The data byte for the VOUT_MODE command is 8 bits
that consists of a three bit format and a five bit exponent.
The three bit format specifies PMBus linear mode for all
output voltage related commands. The five bit exponent
provides the exponent for the mantissa specified in the
data word. The LTC2978 device sets the format at the time
of manufacture. The five bit exponent is read only and is
set to a value of –13 decimal.
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF
Thesecommandsusethesameformatandprovidevarious
servo, margining, and supervising limits for a channel’s
output voltage. When odd channels are configured to
measurecurrent,theOV_WARN_LIMIT,UV_WARN_LIMIT,
OV_FAULT_LIMIT and UV_FAULT_LIMIT commands are
not supported.
Output voltage related commands are calculated as fol-
lows except for odd numbered channels configured to
measure current:
N
Voltage = V[15:0] • 2
Data Contents
where Voltage is the parameter of interest in volts.
BIT(S) SYMBOL
OPERATION
b[15:0] Vout_command[15:0],
Vout_max[15:0],
These commands relate to
output voltage. The data uses
the linear mode format as
defined by VOUT_MODE:
V is a 16-bit unsigned binary integer for all voltages,
(e.g. Margin_high[15:0]);
Vout_margin_high[15:0],
Vout_margin_low[15:0],
Vout_ov_fault_limit[15:0],
Vout_ov_warn_limit[15:0],
Vout_uv_warn_limit[15:0],
Vout_uv_fault_limit[15:0],
Power_good_on[15:0],
Power_good_off[15:0]
N=Vout_mode_exponent, isa5-bittwo’scomplementary
binary integer with a value hardwired to –13 decimal.
N
V(Symbol) = Y • 2 where
Y = b[15:0] is an unsigned
integer and N = Vout_mode_
parameter is a 5-bit two’s
complement exponent that’s
hardwired to –13 decimal.
Vout_mode_parameter is read only.
Vout_mode_type is read only.
VOUT_MODE Data Contents
Units: V
BIT(S) SYMBOL
OPERATION
b[7:5] Vout_mode_type
Reports linear mode. Hard wired to
3’b000.
b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit two’s
complement integer. Hardwired to
‘h13 (–13 decimal).
2978fa
ꢁꢅ
LTC2978
operaTion
Input Voltage Related Commands
TON_DELAY is the amount time in ms that elapses after
the channel has been allowed on (usually due to CON-
TROLn pin or OPERATION command) until the channel
enables the power supply. This delay is counted using
SHARE_CLK only.
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_
WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_
FAULT_LIMIT
Thesecommandsusethesameformatandprovidevoltage
supervising limits for VIN.
TON_RISE is the amount of time in ms that elapses after
the power supply has been enabled until the LTC2978’s
voltage buffered current DAC soft connects and servo’s
the output voltage to the desired level if Mfr_dac_mode =
2’b00. This delay is counted using SHARE_CLK only.
Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Vin_on[15:0],
Vin_off[15:0],
These commands relate to input
voltage. The data uses the linear
format:
TON_MAX_FAULT_LIMITisthemaximumamountoftime
that can elapse after the power supply has been enabled
until the LTC2978 unmasks the VOUT_UV_FAULT_LIMIT
threshold. (Notethatavalueofzeromeansthereisnolimit
to how long the power supply can attempt to bring up its
output voltage.) This delay is counted using SHARE_CLK
only.
Vin_ov_fault_limit[15:0],
N
V(Symbol) = Y • 2
Vin_ov_warn_limit[15:0],
Vin_uv_warn_limit[15:0],
Vin_uv_fault_limit[15:0]
where N = b[15:11] is a 5-bit
two’s complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
Units: V.
TOFF_DELAY is the amount of time that elapses after the
CONTROLn pin and/or OPERATION command is deas-
serted until the channel is disabled (soft-off). This delay
is counted using SHARE_CLK if available, otherwise the
internal oscillator is used.
Temperature Related Commands
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT
and UT_FAULT_LIMIT
These commands provide supervising limits for tem-
perature.
Data Contents
BIT(S) SYMBOL
b[15:0] Ton_delay[15:0],
Ton_rise[15:0],
OPERATION
Data Contents
The data uses the linear format:
BIT(S) SYMBOL
OPERATION
N
T(Symbol) = Y • 2
b[15:0] Ot_fault_limit[15:0], The data uses the linear format:
Ton_max_fault_limit[15:0], Where N = b[15:11] is a 5-bit
N
Ot_warn_limit[15:0], T(Symbol) = Y • 2
two’s complement integer and
Toff_delay[15:0],
Ut_warn_limit[15:0], where N = b[15:11] is a 5-bit two’s
Y = b[10:0] is an 11-bit two’s
complement integer
complement integer and
Ut_fault_limit[15:0]
Y = b[10:0] is an 11-bit two’s
complement integer
The internal timers operate
on a 10µs internal clock. The
SHARE_CLK pin may be used to
synchronize the 10µs timer.
Units: °C.
Delays are rounded to the nearest
10µs
Timer Limits
Units: ms. Max value: 655ms
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and
TOFF_DELAY
These commands share the same format and provide
sequencing and timer fault and warning delays in ms.
2978fa
ꢁꢆ
LTC2978
operaTion
Fault Response for Voltages Measured by the High
Speed Supervisor
• Set the appropriate bit(s) in the STATUS_BYTE
• Set the appropriate bit(s) in the STATUS_WORD
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_
RESPONSE
•
Set the appropriate bit in the corresponding STATUS_
VOUT register, and
The fault response documented here is for voltages that
aremeasuredbythehighspeedsupervisor.Thesevoltages
are measured over a short period of time and may require
a de-glitch period. Note that in addition to the response
described by these commands, the LTC2978 will also:
• Notify the host by pulling the ALERTB pin low.
Note: Odd numbered channels configured for high resolu-
tion ADC measurements will not respond to OV/UV faults
or warnings.
Data Contents
BIT(S) SYMBOL
b[7:6] Vout_ov_fault_response_action, Response action.
Vout_uv_fault_response_action 2’b00: The unit continues operation without interruption.
OPERATION
2’b01: The unit continues operating for the delay time specified by bits[2:0] in increments of Ts_vs.
If the fault is still present at the end of the delay time, the unit responds as programmed in the retry
setting (bits [5:3]).
2’b1X: The device shuts down and responds according to the retry setting in bits [5:3].
Response action:
b[5:3] Vout_ov_fault_response_retry,
Vout_uv_fault_response_retry
3’b000: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
3’b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
b[2:0] Vout_ov_fault_response_delay, This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to de-glitch fast faults.
Vout_uv_fault_response_delay
3’b000: The unit turns off immediately.
3’b001 – 3’b111: The unit turns off after b[2:0] samples at the sampling period of Ts_vs (12.2µs typical).
2978fa
ꢁꢇ
LTC2978
operaTion
Fault Response for Values Measured by the ADC
• Set the appropriate bit(s) in the STATUS_BYTE
• Set the appropriate bit(s) in the STATUS_WORD
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE
• SettheappropriatebitinthecorrespondingSTATUS_VIN
or STATUS_TEMPERATURE register, and
The fault response documented here is for values that are
measured by the ADC. These values are measured over a
longer period of time and are not de-glitched. Note that in
addition to the response described by these commands,
the LTC2978 will also:
• Notify the host by pulling the ALERTB pin low.
Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ot_fault_response_action,
Ut_fault_response_action,
Response action:
2’b00: The unit continues operation without interruption.
Vin_ov_fault_response_action, 2’b01: The device shuts down and responds according to the retry setting in bits [5:3].
Vin_uv_fault_response_action 2’b10: The device shuts down and responds according to the retry setting in bits [5:3].
2’b11: The device shuts down and responds according to the retry setting in bits [5:3].
b[5:3] Ot_fault_response_retry,
Response action:
Ut_fault_response_retry,
3’b000: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
3’b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
b[2:0] Ot_fault_response_delay,
Ut_fault_response_delay,
Hard coded to 3’b000. The unit turns off immediately.
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
2978fa
ꢁꢈ
LTC2978
operaTion
Timed Fault Response
The device also:
• Sets the HIGH_BYTE bit in the STATUS_BYTE,
• Sets the VOUT bit in the STATUS_WORD,
TON_MAX_FAULT_RESPONSE
This command defines the LTC2978 response to a
TON_MAX_FAULT. At start-up, the TON_MAX_FAULT_
RESPONSE is disarmed once the output voltage reaches
the VOUT_UNDER_VOLTAGE_LIMIT. The only way to
protect against a short-circuited output at start-up is
to take action in response to a TON_MAX_FAULT since
VOUT_UV_FAULT_RESPONSEisnotarmeduntiltheoutput
reaches the VOUT_UNDER_VOLTAGE_LIMIT.
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT
register, and
• Notifies the host by asserting ALERTB.
TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
b[7:6] Ton_max_fault_response_action Response action.
2’b00: The unit continues operation without interruption.
OPERATION
2’b01: The unit continues operating for the delay time specified which for this type of fault corresponds to an
immediate shutdown. After shutting off, the device responds according to the retry settings in bits [5:3].
2’b1X: The device shuts down and responds according to the retry setting in bits [5:3].
Response action:
b[5:3] Ton_max_fault_response_retry
3’b000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
3’b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
b[2:0] Ton_max_fault_response_delay Hard coded to 3’b000. The unit turns off immediately.
2978fa
ꢂ0
LTC2978
operaTion
STATUS_WORD Data Contents
BIT(S) SYMBOL
STATUS_BYTE:
OPERATION
The STATUS_BYTE command returns the summary of the
most critical faults or warnings which have occurred, as
shown in the following table:
b[15] Status_word_vout
An output voltage fault or
warning has occurred.
b[14] Status_word_iout
b[13] Status_word_input
Notsupported.Alwaysreturns0.
An input voltage fault or
warning has occurred.
STATUS_BYTE Data Contents
BIT(S) SYMBOL
OPERATION
b[12] Status_word_mfr
A manufacturer specific fault
has occurred.
b[7] Status_byte_busy
Device busy when PMBus command
received.
b[11] Status_word_power_not_good The POWER_GOOD signal, if
b[6] Status_byte_off
This bit is asserted if the unit is
not providing power to the output,
regardless of the reason, including
simply not being enabled.
present is negated. Power is
not good.
b[10] Status_word_cooling
b[9] Status_word_other
b[8] Status_word_unknown
b[7] Status_word_busy
Notsupported.Alwaysreturns0.
Notsupported.Alwaysreturns0.
Notsupported.Alwaysreturns0.
b[5] Status_byte_vout_ov
An output overvoltage fault has
occurred.
b[4] Status_byte_iout_oc
b[3] Status_byte_vin_uv
b[2] Status_byte_temp
Not supported. Always returns 0.
Device busy when PMBus
command received.
A V undervoltage fault has occurred.
IN
b[6] Status_word_off
Status_byte_off
A temperature fault or warning has
occurred.
b[5] Status_word_vout_ov
b[4] Status_word_iout_oc
b[3] Status_word_vin_uv
b[2] Status_word_temp
b[1] Status_word_cml
Status_byte_vout_ov
Notsupported.Alwaysreturns0.
Status_byte_vin_uv
Status_byte_temp
b[1] Status_byte_cml
A communication, memory or logic
fault has occurred.
b[0] Status_byte_high_byte Fault/warning not listed in b[7:1].
Status_byte_cml
STATUS_WORD:
b[0] Status_word_high_byte
A bit in the high byte of the
STATUS_WORD (b[15:8]) is
set.
The STATUS_WORD command returns two bytes of infor-
mation with a summary of the unit’s fault condition. Based
on the information in these bytes, the host can get more
information by reading the appropriate status byte.
The low byte of the STATUS_WORD is the same register
as the STATUS_BYTE command.
2978fa
ꢂꢀ
LTC2978
operaTion
STATUS_VOUT
STATUS_TEMPERATURE
The STATUS_VOUT command returns the summary of
the voltage faults or warnings which have occurred, as
shown in the following table:
The STATUS_TEMPERATURE command returns the sum-
mary of the temperature faults or warnings which have
occurred, as shown in the following table:
STATUS_VOUT Data Contents
STATUS_TEMPERATURE Data Contents
BIT(S) SYMBOL
OPERATION
Bit(s) Symbol
Operation
b[7] Status_vout_ov_fault
b[6] Status_vout_ov_warn
b[5] Status_vout_uv_warn
b[4] Status_vout_uv_fault
b[3] Status_vout_max_fault
Overvoltage fault.
Overvoltage warning.
Undervoltage warning
Undervoltage fault.
b[7] Status_temperature_ot_fault
b[6] Status_temperature_ot_warn
b[5] Status_temperature_ut_warn
b[4] Status_temperature_ut_fault
b[3] Reserved
Overtemperature fault.
Overtemperature warning.
Undertemperature warning.
Undertemperature fault.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
VOUT_MAX fault. An attempt
has been made to set the output
voltage to a value higher than
allowed by the VOUT_MAX
command.
b[2] Reserved
b[1] Reserved
b[0] Reserved
b[2] Status_vout_ton_max_fault TON_MAX_FAULT sequencing
fault.
STATUS_CML
b[1] Status_vout_toff_max_warn Not supported. Always returns 0.
b[0] Status_vout_tracking_error Not supported. Always returns 0.
The STATUS_CML command returns the summary of the
communication, memory and logic faults or warnings
which have occurred, as shown in the following table:
STATUS_INPUT
The STATUS_INPUT command returns the summary of
STATUS_CML Data Contents
BIT(S) SYMBOL
the V faults or warnings which have occurred, as shown
IN
OPERATION
in the following table:
b[7] Status_cml_cmd_fault
1 = An illegal or unsupported
command fault has occurred.
STATUS_INPUT Data Contents
BIT(S) SYMBOL
0 = No fault has occurred.
OPERATION
b[6] Status_cml_data_fault
1 = Illegal or unsupported data
received.
b[7] Status_input_ov_fault
b[6] Status_input_ov_warn
b[5] Status_input_uv_warn
b[4] Status_input_uv_fault
b[3] Status_input_off
V
V
V
V
Overvoltage fault
IN
IN
IN
IN
Overvoltage warning
Undervoltage warning
Undervoltage fault
0 = No fault has occurred.
1 = A PEC fault has occurred.
0 = No fault has occurred.
b[5] Status_cml_pec_fault
b[4] Status_cml_memory_fault
1 = A fault has occurred in the
NVM.
Unit is off for insufficient input voltage.
Not supported. Always returns 0.
Not supported. Always returns 0.
Not supported. Always returns 0.
b[2]
b[1]
I
I
overcurrent fault
overcurrent warn
IN
IN
0 = No fault has occurred.
b[3] Status_cml_processor_fault Not supported, always returns 0.
b[0] PIN overpower warn
b[2] Reserved
Not supported, always returns 0.
b[1] Status_cml_PMBus_fault
1 = A communication fault other
than ones listed in this table has
occurred.
0 = No fault has occurred.
b[0] Status_cml_unknown_fault Not supported, always returns 0.
2978fa
ꢂꢁ
LTC2978
operaTion
STATUS_MFR_SPECIFIC
TheSTATUS_MFR_SPECIFICcommandreturnsmanufac-
turer specific status flags. Bits marked FAULT = No are
intended to support polled handshaking; these are not
latched nor do they assert ALERTB. Bits marked Channel
= All can be read from any page. Bits marked FAULT = Yes
assert ALERTB low and are cleared by CLEAR_FAULTS.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL
OPERATION
1 = A V discharge fault occurred while attempting to enter the ON state
CHANNEL
Current Page
FAULT
b[7] Status_mfr_discharge
Yes
OUT
0 = No V
discharge fault has occurred
OUT
b[6] Status_mfr_fault1_in
b[5] Status_mfr_fault0_in
This channel attempted to turn on while the FAULTBz1 pin was asserted low, Current Page
or this channel has shut down at least once in response to a FAULTBz1 pin
asserting low since the last CONTROLn pin toggle, OPERATION command
ON/OFF cycle or CLEAR_FAULTS command.
Yes
Yes
This channel attempted to turn on while the FAULTBz0 pin was asserted low, Current Page
or this channel has shut down at least once in response to a FAULTBz0 pin
asserting low since the last CONTROLn pin toggle, OPERATION command
ON/OFF cycle or CLEAR_FAULTS command.
b[4] Status_mfr_servo_target_reached Servo target has been reached.
Current Page
Current Page
Current Page
No
No
b[3] Status_mfr_dac_connected
b[2] Status_mfr_dac_saturated
DAC is connected and driving V
pin.
DACP
A previous servo operation terminated with maximum or minimum DAC
value.
Yes
b[1] Status_mfr_vinen_faulted_off
b[0] Status_mfr_watchdog_fault
V
has been deasserted due to a VOUT fault.
All
All
No
IN_EN
1 = A watchdog fault has occurred.
0 = No watchdog fault has occurred.
Yes
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ADC Monitoring Commands
READ_TEMPERATURE_1
This command returns the most recent ADC measured
value of junction temperature in °C as determined by the
LTC2978’s internal temperature sensor.
READ_VIN
This command returns the most recent ADC measured
value of the voltage measured at the V
pin.
IN_SNS
READ_TEMPERATURE_1 Data Contents
READ_VIN Data Contents
BIT(S) SYMBOL
OPERATION
BIT(S) SYMBOL
OPERATION
b[15:0] Read_temperature_1 [15:0] The data uses the linear format:
N
b[15:0] Read_vin[15:0] The data uses the linear format:
Temp(Symbol) = Y • 2
N
V(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit
two’s complement integer and
where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
Y = b[10:0] is an 11-bit two’s complement
integer
Units: °C.
Units: V
PMBUS_REVISION
READ_VOUT
ThePMBUS_REVISIONcommandregisterisreadonlyand
reports the LTC2978 compliance to the PMBus standard
revision 1.1.
This command returns the most recent ADC measured
value of the channel’s output voltage. When odd channels
are configured to measure current, the data contents have
a slightly modified meaning, as described in the second
table below.
PMBUS_REVISION Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] PMBus_rev Reports the PMBus standard revision
compliance. This is hard-coded to ‘h11 for
revision 1.1.
READ_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Read_vout[15:0] The data uses the linear mode format as
defined by VOUT_MODE:
N
V(Read_vout) = Y • 2 where Y = b[15:0] is
an unsigned integer and N = Vout_mode_
parameter is a 5-bit two’s complement
exponent that’s hardwired to –13 decimal.
Units: V.
READ_VOUT Data Contents—for Odd Channels Configured to
Measure Current
Bit(s) Symbol
Operation
b[15:0] Read_vout[15:0] The data uses the linear format:
N
V(Symbol) = Y • 2
where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s complement
integer
Units: mV
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MANUFACTURER SPECIFIC COMMANDS
MFR_CONFIG:
This command is used to configure various manufacturer
specific operating parameters for each channel.
MFR_CONFIG Data Contents
BIT(S) SYMBOL
OPERATION
b[15:12] Reserved
Don’t care. Always returns 0.
b[11] Mfr_config_fast_servo_off
Disables fast servo when margining or trimming output voltages:
0: fast-servo enabled.
1: fast-servo disabled.
b[10] Mfr_config_supervisor_resolution Selects supervisor resolution:
0: high resolution – 4mV/LSB, range for V
1: low resolution – 8mV/LSB, range for V
is 0V to 3.8V.
SENSEP
is 0V to 6.0V.
SENSEP
b[9] Mfr_config_adc_hires
Selects ADC resolution for odd channels. Ignored for even channels (they always use low res).
0: low resolution – 122µV/LSB.
1: high resolution – 15.6µV/LSB.
b[8] Mfr_config_controln_sel
b[7] Mfr_config_servo_continuous
Selects the active control pin input (CONTROL0 or CONTROL1) for this channel.
0: Select CONTROL0 pin.
1: Select CONTROL1 pin.
Select whether the UNIT should continuously servo V
after it has reached a new margin or nominal
OUT
target. Only applies when Mfr_dac_mode = 2’b00.
0: Do not continuously servo V
after reaching initial target.
OUT
1: Continuously servo V
to target.
OUT
b[6] Mfr_config_servo_on_warn
b[5:4] Mfr_config_dac_mode
Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 2’b00 and
Mfr_config_servo_continuous = 0.
0: Do not allow the unit to re-servo when a V
warning threshold is met or exceeded.
OUT
1: Allow the unit to re-servo V
to nominal target if
OUT
V
V
≥ V(Vout_ov_warn_limit) or
≤ V(Vout_uv_warn_limit).
OUT
OUT
Determines how DAC is used when channel enters ON state or is already in ON state.
00: Soft connect (if needed) and servo to target. Wait for TON_RISE if just entering ON state.
01: DAC not connected.
10: DAC connected using value from MFR_DAC command. Does not wait for TON_RISE if just entering ON state.
11: DAC is soft connected. After soft connect is complete MFR_DAC may be written.
b[3] Mfr_config_vo_en_wpu_en
b[2] Mfr_config_vo_en_wpd_en
V
charge pumped, current-limited pull-up enable.
O_EN
0: Disable weak pull-up. V
1: Use weak current-limited pull-up on V
For channels 4-7 this bit is treated as a 0 regardless of its value.
V
driver is three-stated when channel is on.
O_EN
when the channel is on.
O_EN
current-limited pull-down enable.
O_EN
0: Use a fast N-channel device to pull down V
when the channel is off for any reason.
O_EN
1: Use weak current-limited pull-down to discharge V
when channel is off due to soft stop by the CONTROLn
O_EN
pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down on V
For channels 4-7 this bit is treated as a 0 regardless of its value.
DAC buffer gain.
.
O_EN
b[1] Mfr_config_dac_gain
b[0] Mfr_config_dac_pol
0: Select DAC buffer gain dac_gain_0 (1.38V full-scale)
1: Select DAC buffer gain dac_gain_1 (2.65V full-scale)
DAC output polarity.
0: Encodes negative (inverting) DC/DC converter trim input.
1: Encodes positive (noninverting) DC/DC converter trim input.
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MFR_CONFIG_ALL:
This command is used to configure parameters that are
common to all channels on the IC. They may be set or
reviewed from any PAGE setting.
MFR_CONFIG_ALL Data Contents
MFR_CONFIG_ALL Data Contents
b[3] Mfr_config_vin_share_enable Allow this unit to hold share-
clock pin low when VIN_ON
BIT(S) SYMBOL
OPERATION
b[7] Mfr_config_fault_log_enable Enable fault logging to NVM in
response to Fault.
has fallen below VIN_OFF. When
enabled, this unit will also turn
0: Fault logging to NVM is
disabled
all channels off in response to
share-clock being held low.
1: Fault logging to NVM is
enabled
VIN_ON rising edge to clear all
latched faults
0: VIN_ON clear faults feature is
disabled
1: VIN_ON clear faults feature is
enabled
Selects active polarity of
control1 pin.
0: Active low (pull pin low to
start unit)
1: Active high (pull pin high to
start unit)
Selects active polarity of
control0 pin.
0: Share-clock inhibit is disabled
1: Share-clock inhibit is enabled
PMBus packet error checking
enable.
0: PEC is accepted but not
required
1: PEC is required
Increase PMBus timeout internal
by a factor of 8.
0: PMBus timeout is not
multiplied by a factor of 8
1: PMBus timeout is multiplied
by a factor of 8
b[6] Mfr_vin_on_clr_faults_en
b[5] Mfr_config_control1_pol
b[4] Mfr_config_control0_pol
b[2] Mfr_config_all_pec_en
b[1] Mfr_config_all_longer_
pmbus_timeout
b[0] Mfr_config_all_vinen_wpu_
dis
V
charge pumped, current-
IN_EN
limited pull-up disable.
0: Use weak current-limited pull-
0: Active low (pull pin low to
start unit)
1: Active high (pull pin high to
start unit)
up on V
after power-up, as
IN_EN
long as no faults have forced
off.
V
IN_EN
1: Disable weak pull-up. V
driver is three-stated after
IN_EN
power-up as long as no faults
have forced V
off.
IN_EN
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MFR_FAULTB00_PROPAGATE, MFR_FAULTB01_
PROPAGATE, MFR_FAULTB10_PROPAGATE and
MFR_FAULTB11_PROPAGATE
MFR_FAULTB10_PROPAGATE Data Contents—Fault Zone 1
(Pages 4-7)
BIT(S) SYMBOL
b[7:1] Reserved
OPERATION
Don’t care. Always returns 0.
These manufacturer specific commands enable channels
that have faulted off to propagate that state to the ap-
propriate fault pin. There are two zones in the LTC2978.
In zone 0, faulted off states for channels 0 through 3 can
be propagated to FAULT00 or FAULT01. In zone 1, faulted
off states for channels 4 through 7 can be propagated to
FAULT10 or FAULT11. See Figure 13.
b[0]
Mfr_faultb10_propagate
Enable fault propagation.
0: FAULTB10 will not be affected if
a fault is declared.
1: FAULTB10 will be asserted low
if a fault is declared.
MFR_FAULTB11_PROPAGATE Data Contents—Fault Zone 1
(Pages 4-7)
MFR_FAULTB00_PROPAGATE Data Contents—Fault Zone 0
(Pages 0-3)
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
BIT(S) SYMBOL
OPERATION
b[0]
Mfr_faultb11_propagate
Enable fault propagation.
0: FAULTB11 will not be affected if
a fault is declared.
b[7:1] Reserved
Don’t care. Always returns 0.
b[0]
Mfr_faultb00_propagate
Enable fault propagation.
1: FAULTB11 will be asserted low
if a fault is declared.
0: FAULTB00 will not be affected if
a fault is declared.
1: FAULTB00 will be asserted low
if a fault is declared.
MFR_FAULTB01_PROPAGATE Data Contents—Fault Zone 0
(Pages 0-3)
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
b[0]
Mfr_faultb01_propagate
Enable fault propagation.
0: FAULTB01 will not be affected if
a fault is declared.
1: FAULTB01 will be asserted low
if a fault is declared.
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MFR_PWRGD_EN
This command register controls the mapping of power
good status to the power good pin. Note that odd num-
bered channels whose ADC is in high res mode do not
contribute to power good.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:9] Reserved
Read only, always returns 0s.
Watchdog
b[8] Mfr_pwrgd_en_wdog
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to
determine when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
Channel 7
b[7] Mfr_pwrgd_en_chan7
b[6] Mfr_pwrgd_en_chan6
b[5] Mfr_pwrgd_en_chan5
b[4] Mfr_pwrgd_en_chan4
b[3] Mfr_pwrgd_en_chan3
b[2] Mfr_pwrgd_en_chan2
b[1] Mfr_pwrgd_en_chan1
b[0] Mfr_pwrgd_en_chan0
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 6
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 5
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 4
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 3
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 2
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 1
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
Channel 0
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = PRWGD status for this channel does not affect the PWRGD pin.
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LTC2978
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MFR_FAULTB00_RESPONSE, MFR_FAULTB01_
RESPONSE, MFR_FAULTB10_RESPONSE and MFR_
FAULTB11_RESPONSE
when the FAULTB01 pin is asserted. For fault zone 1,
MFR_FAULTB10_RESPONSE determines how channels
4-7 respond when the FAULTB10 pin is asserted, and
MFR_FAULTB11_RESPONSE determines how channels
4-7 respond when the FAULTB11 pin is asserted. If one
or more bits in the MFR_FAULTBzn_RESPONSE registers
are set, a FAULTBzn assertion will cause the ALERTB pin to
assertlowandsettheappropriatebitintheSTATUS_MFR_
SPECIFIC register.
These manufacturer specific commands share the same
format and specify the response to assertions of the bidi-
rectional fault pins. For fault zone 0, MFR_FAULTB00_RE-
SPONSE determines how channels 0-3 respond when
the FAULTB00 pin is asserted, and MFR_FAULTB01_
RESPONSE determines how channels 0-3 respond
Data Contents—Fault Zone 0 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0s.
b[3] Mfr_faultb00_response_chan3, Channel 3 response.
Mfr_faultb01_response_chan3 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb00_response_chan2, Channel 2 response.
Mfr_faultb01_response_chan2 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb00_response_chan1, Channel 1 response.
Mfr_faultb01_response_chan1 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0] Mfr_faultb00_response_chan0, Channel 0 response.
Mfr_faultb01_response_chan0 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
Data Contents—Fault Zone 1 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0s.
b[3] Mfr_faultb10_response_chan7, Channel 7 response.
Mfr_faultb11_response_chan7 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb10_response_chan6, Channel 6 response.
Mfr_faultb11_response_chan6 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb10_response_chan5, Channel 5 response.
Mfr_faultb11_response_chan5 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0] Mfr_faultb10_response_chan4, Channel 4 response.
Mfr_faultb11_response_chan4 0: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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MFR_VINEN_OV_FAULT_RESPONSE
This command register determines whether V
voltage faults from a given channel cause the V
to be forced off.
over
IN_EN
OUT
pin
MFR_VINEN_OV_FAULT_RESPONSE Data Contents
BIT(S)
SYMBOL
OPERATION
Response to channel 7 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
b[7]
Mfr_vinen_ov_fault_response_chan7
IN_EN
0 = Leave V
as-is.
IN_EN
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Mfr_vinen_ov_fault_response_chan6
Mfr_vinen_ov_fault_response_chan5
Mfr_vinen_ov_fault_response_chan4
Mfr_vinen_ov_fault_response_chan3
Mfr_vinen_ov_fault_response_chan2
Mfr_vinen_ov_fault_response_chan1
Mfr_vinen_ov_fault_response_chan0
Response to channel 6 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 5 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 4 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 3 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 2 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 1 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 0 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
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LTC2978
operaTion
MFR_VINEN_UV_FAULT_RESPONSE
This command register determines whether V
under
IN_EN
OUT
voltage faults from a given channel cause the V
pin
to be forced off.
MFR_VINEN_UV_FAULT_RESPONSE Data Contents
BIT(S)
SYMBOL
OPERATION
Response to channel 7 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
b[7]
Mfr_vinen_uv_fault_response_chan7
IN_EN
0 = Leave V
as-is.
IN_EN
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Mfr_vinen_uv_fault_response_chan6
Mfr_vinen_uv_fault_response_chan5
Mfr_vinen_uv_fault_response_chan4
Mfr_vinen_uv_fault_response_chan3
Mfr_vinen_uv_fault_response_chan2
Mfr_vinen_uv_fault_response_chan1
Mfr_vinen_uv_fault_response_chan0
Response to channel 6 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 5 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 4 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 3 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 2 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 1 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
Response to channel 0 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
0 = Leave V
as-is.
IN_EN
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MFR_RETRY_DELAY
MFR_VOUT_PEAK
This command determines the retry interval when the
LTC2978isinhiccupmodeinresponsetoafaultcondition.
ThiscommandreturnsthemaximumADCmeasuredvalue
of the channel’s output voltage. This command is not sup-
ported for odd channels that are configured to measure
current. This register is reset to zero when the LTC2978
emerges from power-on reset or when a CLEAR_FAULTS
command is executed.
MFR_RETRY_DELAY Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_retry_delay The data uses the linear format:
N
T(Symbol) = Y • 2
MFR_VOUT_PEAK Data Contents
Where N = b[15:11] is a 5-bit two’s
complement integer and
BIT(S) SYMBOL
OPERATION
Y = b[10:0] is an 11-bit two’s complement
integer
b[15:0] Mfr_vout_peak[15:0] The data uses the linear mode format as
defined by VOUT_MODE:
This delay is counted using SHARE_CLK
only.
N
V(mfr_vout_peak) = Y • 2 where Y =
b[15:0] is an unsigned integer and N =
Vout_mode_parameter is a 5-bit two’s
complement exponent that’s hardwired
to –13 decimal.
Delays are rounded to the nearest 200µs.
Units: ms. Max delay is 13.1 sec.
Units: V.
MFR_RESTART_DELAY
This command determines how the CONTROLn pins are
adjusted before use. The time the adjusted version of the
CONTROLnpinisintheoffpolarityisstretchedbythiscom-
mand to be at least Mfr_restart_delay ms. CONTROLn pin
transitionswhoseOFFtimeexceedsMfr_restart_delayare
not affected by this command. A value of all zeros disables
thisfeature.
MFR_VIN_PEAK
ThiscommandreturnsthemaximumADCmeasuredvalue
of the input voltage. The contents of this register are reset
to‘h7C00whentheLTC2978emergesfrompower-onreset
or when a CLEAR_FAULTS command is executed.
MFR_VIN_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
MFR_RESTART_DELAY Data Contents
b[15:0] Mfr_vin_peak[15:0] The data uses the linear format:
BIT(S) SYMBOL
OPERATION
N
V(Symbol) = Y • 2
b[15:0] Mfr_restart_delay The data uses the linear format:
where N = b[15:11] is a 5-bit two’s
complement integer and
N
T(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
Y = b[10:0] is an 11-bit two’s complement
integer
Units: V
This delay is counted using SHARE_CLK
only.
MFR_TEMPERATURE_PEAK
Delays are rounded to the nearest 200µs.
Units: ms. Max delay is 13.1 sec.
This command returns the maximum ADC measured
value of junction temperature in °C as determined by
the LTC2978’s internal temperature sensor. The contents
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LTC2978
operaTion
of this register are reset to ‘h7C00 when the LTC2978
emerges from power-on reset or when a CLEAR_FAULTS
command is executed.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
TheMFR_WATCHDOG_T_FIRSTregisterallowstheuserto
program the duration of the first watchdog timer interval
followingassertionofthePOWERGOODsignal, assuming
thePOWERGOODsignalreflectsthestatusofthewatchdog
timer.IfassertionofPOWERGOODisnotconditionedbythe
watchdogtimer’sstatus,thenMFR_WATCHDOG_T_FIRST
appliestothefirsttimingintervalafterthetimerisenabled.
Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST
register disables the watchdog timer.
MFR_TEMPERATURE_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_temperature_peak[15:0] The data uses the linear format:
N
V(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit
two’s complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
The MFR_WATCHDOG_T register allows the user to
program watchdog time intervals subsequent to the
MFR_WATCHDOG_T_FIRST timing interval. Writing a
valueof0mstotheMFR_WATCHDOG_Tregisterdisables
the watchdog timer. A non-zero write to MFR_WATCH-
DOG_T will reset the watchdog timer.
Units: °C.
MFR_DAC
This command register returns the 10-bit value for the
voltage-buffered current DAC. This register may be writ-
ten when Mfr_config_dac_mode is configured for either
of the two manual DAC modes.
MFR_WATCHDOG_T_POR and MFR_WATCHDOG_T Data
Contents
MFR_DAC Data Contents
BIT(S) SYMBOL
BIT(S) SYMBOL
OPERATION
OPERATION
b[15:0] Mfr_watchdog_t_first The data uses the linear format:
b[15:10] Reserved
Read only, always returns ‘h3F.
N
Mfr_watchdog_t
T(Symbol) = Y • 2
b[9:0] Mfr_dac_direct_val Voltage-buffered current DAC code value.
Where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the
delay from when the internal power good signal becomes
valid until the power good output is asserted.
These timers operate on an internal
clock independent of SHARE_CLK.
Delays are rounded to the nearest 10µs
for _t and 1ms for _t_first.
Writing a zero value for Y to the
Mfr_watchdog_t or Mfr_watchdog_t_
first registers will disable the watchdog
timer.
Units: ms. Max timeout is 0.6 sec for _t
and 65 sec for _t_first
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_powergood_assertion_delay The data uses the linear format:
N
T(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit
two’s complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer.
This delay is counted using
internal clock independent of
SHARE_CLK.
Delays are rounded to the
nearest 200µs
Units: ms. Max delay is 13.1
sec.
2978fa
ꢃꢂ
LTC2978
operaTion
MFR_PAGE_FF_MASK
b[5] Mfr_pads_control1
b[4] Mfr_pads_control0
b[3:0] Mfr_pads_faultb[3:0]
1: Logic high detected on
CONTROL1 pad
The MFR_PAGE_FF_MASK command is used to select
which channels respond when the global page (FF) is in
use. Note that the only commands that support PAGE =
‘hFF are OPERATION and ON_OFF_CONFIG.
0: Logic low detected on
CONTROL1 pad
1: Logic high detected on
CONTROL0 pad
0: Logic low detected on
CONTROL0 pad
Bit[3] used for FAULTB00 pad,
bit[2] used for FAULTB01 pad,
bit[1] used for FAULTB10 pad,
bit[0] used for FAULTB11 pad
as follows:
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] Mfr_page_ff_mask Global page response enable, per channel
Each bit enables/disables the
corresponding channel:
0 = ignore global page accesses
1 = fully respond to global page accesses
1: Logic high detected on
FAULTBzn pad
0: Logic low detected on
FAULTBzn pad
MFR_PADS
The MFR_PADS command provides read only access to
slow frequency digital pads. The input values presented
in bits[9:0] are before any deglitching logic.
MFR_I2C_BASE_ADDRESS
TheMFR_I2C_BASE_ADDRESScommanddeterminesthe
2
base value for the I C address byte.
MFR_PADS_PWRGD_DRIVE Data Contents
BIT(S) SYMBOL
OPERATION
MFR_I2C_BASE_ADDRESS Data Contents
b[15] Mfr_pads_pwrgd_drive
0 = PWRGD pad is being driven
low by this chip
BIT(S) SYMBOL
OPERATION
b[7] Reserved
Read only, always returns 0.
1 = PWRGD pad is not being
driven low by this chip
0 = ALERTB pad is being driven
low by this chip
b[6:0] i2c_base_address This 7-bit value determines the base value
2
of the 7-bit I C address.
b[14] Mfr_pads_alertb_drive
MFR_SPECIAL_ID
1 = ALERTB pad is not being
driven low by this chip
This register contains the manufacturer ID for the
LTC2978.
b[13:10] Mfr_pads_faultb_drive[3.0] Bit[3] used for FAULTB00 pad,
bit[2] used for FAULTB01 pad,
bit[1] used for FAULTB10 pad,
bit[0] used for FAULTB11 pad
as follows:
MFR_SPECIAL_ID Data Contents
BIT(S)
SYMBOL
OPERATION
0 = FAULTB pad is being driven
low by this chip
b[15:0]
Mfr_special_id
Read only, always returns ‘h0121
1 = FAULTB pad is not being
driven low by this chip
MFR_SPECIAL_LOT
b[9:8] Mfr_pads_asel1[1:0]
b[7:6] Mfr_pads_asel0[1:0]
11: Logic high detected on ASEL1
input pad
Thesepagedregisterscontaininformationthatidentifiesthe
user configuration that was programmed at the factory.
10: ASEL1 input pad is floating
01: Reserved
MFR_SPECIAL_LOT Data Contents
00: Logic low detected on ASEL1
input pad
11: Logic high detected on ASEL0
input pad
BIT(S)
SYMBOL
OPERATION
b[7:0]
Mfr_special_lot
Contains the LTC default special lot
number. Contact the factory to request
a custom factory programmed user
configuration and special lot number.
10: ASEL0 input pad is floating
01: Reserved
00: Logic low detected on ASEL0
input pad
2978fa
ꢃꢃ
LTC2978
operaTion
MFR_VOUT_DISCHARGE_THRESHOLD
MFR_FAULT_LOG_CLEAR
This register contains the coefficient that multiplies
VOUT_COMMAND in order to determine the OFF thresh-
old voltage for the associated output. If the output volt-
age has not decayed below MFR_VOUT_DISCHARGE_
THRESHOLD • VOUT_COMMAND prior to the channel
being commanded to enter/re-enter the ON state, bit [7]
in the STATUS_MFR_SPECIFIC register will be set and the
ALERTB pin will be asserted low. In addition, the channel
will not enter the ON state until the output has decayed
below its OFF threshold voltage.
This command initializes the EEPROM block reserved for
fault logging. Any previous fault log stored in EEPROM
will be erased by this operation.
MFR_FAULT_LOG_STATUS
Read only. This register is used to manage fault log
events.
Mfr_fault_log_status_eeprom is set after a MFR_FAULT_
LOG_STORE command or a faulted-off event triggers a
transfer of the fault log from RAM to EEPROM. This bit is
cleared by a MFR_FAULT_LOG_CLEAR command.
Other channels can be held off if a particular output has
failed to discharge by using the bidirectional FAULTzn pins
(refertotheMFR_FAULTBzn_RESPONSEandMFR_FAULT-
Bzn_PROPAGATE registers).
Mfr_fault_log_status_ram is set after a MFR_FAULT_
LOG_RESTORE to indicate that the data in the RAM has
been restored from EEPROM and not yet read using a
MFR_FAULT_LOG command. This bit is cleared by a
MFR_FAULT_LOG command.
MFR_VOUT_DISCHARGE_THRESHOLD Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_vout_discharge_ The data uses the linear format:
N
MFR_FAULT_LOG_STATUS Data Contents
threshold
k = Y • 2
BIT(S) SYMBOL
OPERATION
Where N=b[15:11] is a 5-bit two’s
complement integer and Y= b[10:0]
is an 11-bit two’s complement
integer.
b[1] Mfr_fault_log_status_ram
Fault log RAM status:
0: The fault log RAM allows
updates.
Units: Dimensionless, this register
contains a coefficient.
1: The fault log RAM is locked
until the next Mfr_fault_log
read.
MFR_FAULT_LOG_STORE
b[0] Mfr_fault_log_status_eeprom Fault log EEPROM status:
This command allows the user to transfer data from the
RAM buffer to EEPROM.
0: The transfer of the fault log
RAM to the EEPROM is enabled.
1: The transfer of the fault
log RAM to the EEPROM is
inhibited.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the
fault-log data from the EEPROM to the RAM buffer. After
a restore the RAM buffer is locked until a successful
Mfr_fault_log read.
2978fa
ꢃꢄ
LTC2978
operaTion
MFR_FAULT_LOG
MFR_FAULT_LOG Data Block Contents
DATA
BYTE BLOCK READ COMMAND
Read only. This 2048-bit data block contains a copy of
the RAM buffer fault log. The RAM buffer is continuously
updated after each ADC conversion as long as Mfr_fault_
log_status_ramisclear.WithMfr_config_fault_log_en=1
and Mfr_fault_log_status_eeprom = 0, the RAM buffer is
transferredtoEEPROMwheneveranLTC2978faultcauses
a channel to latch off or a MFR_FAULT_LOG_STORE com-
mand is received. Mfr_fault_log_status_eeprom is set
high after the RAM buffer is transferred to EEPROM and
not cleared until a Mfr_fault_log_clear is received; even if
the LTC2978 is reset or powered down. Fault log EEPROM
transfers are not initiated as a result of Status_mfr_dis-
charge, Status_mfr_fault1_in or Status_mfr_fault0_in
events. During a Mfr_fault_log read, data is returned one
byte at a time as defined by the following table. The fault
log stores approximately 1 to 2 seconds of telemetry.
Mfr_vin_min[15:8]
Mfr_vout_peak2[7:0]
Mfr_vout_peak2[15:8]
Mfr_vout_min2[7:0]
Mfr_vout_min2[15:8]
Mfr_vout_peak3[7:0]
Mfr_vout_peak3[15:8]
Mfr_vout_min3[7:0]
Mfr_vout_min3[15:8]
Mfr_temp_peak[7:0]
Mfr_temp_peak[15:8]
Mfr_ temp_min[7:0]
Mfr_ temp_min[15:8]
Mfr_vout_peak4[7:0]
Mfr_vout_peak4[15:8]
Mfr_vout_min4[7:0]
Mfr_vout_min4[15:8]
Mfr_vout_peak5[7:0]
Mfr_vout_peak5[15:8]
Mfr_vout_min5[7:0]
Mfr_vout_min5[15:8]
Mfr_vout_peak6[7:0]
Mfr_vout_peak6[15:8]
Mfr_vout_min6[7:0]
Mfr_vout_min6[15:8]
Mfr_vout_peak7[7:0]
Mfr_vout_peak7[15:8]
Mfr_vout_min7[7:0]
Mfr_vout_min7[15:8]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
MFR_FAULT_LOG Data Block Contents
DATA
BYTE BLOCK READ COMMAND
Position_last[7:0]
0
Position of fault log pointer
when fault occurred.
SharedTime[7:0]
1
2
3
4
5
41-bit share-clock counter
value when fault occurred.
Counter LSB is in 200µs
increments. This counter is
cleared at power-up or after
the LTC2978 is reset
SharedTime[15:8]
SharedTime[23:16]
SharedTime[31:24]
SharedTime[39:32]
SharedTime[40]
6
Mfr_vout_peak0[7:0]
Mfr_vout_peak0[15:8]
Mfr_vout_min0[7:0]
Mfr_vout_min0[15:8]
Mfr_vout_peak1[7:0]
Mfr_vout_peak1[15:8]
Mfr_vout_min1[7:0]
Mfr_vout_min1[15:8]
Mfr_vin_peak[7:0]
Mfr_vin_peak[15:8]
Mfr_vin_min[7:0]
7
8
9
47 bytes for preamble
Fault_log [Position_last]
Fault_log [Position_last-1]
.
.
47
48
10
11
12
13
14
15
16
17
.
Fault_log [Position_last-201]
Reserved
247
248-255
Number of loops
(248-47)/40 = 5
2978fa
ꢃꢅ
LTC2978
operaTion
Data is logged into memory in the order shown in the
POSITION
DATA
32
33
34
35
36
37
38
39
Read_vout6[7:0]
Read_vout6[15:8]
Status_vout6
following table.
When data is returned during a block read it is returned in
reverseorderbasedonthevalueofPosition_last[7:0].Data
byteRead_vout0[7:0]isfollowedbyStatus_mfrofpage7.
Example: If Position_last = 9 then the first data returned in
byteposition47ofablockreadisRead_vin[15:8]followed
by Read_vin[7:0] followed by Status_mfr of page 1.
Status_mfr6
Read_vout7[7:0]
Read_vout7[15:8]
Status_vout7
Status_mfr7
Total Bytes =40
POSITION
0
DATA
Read_vout0[7:0]
Read_vout0[15:8]
Status_vout0
MFR_COMMON
1
2
This command returns status information for the share-
clock pin (SCLK) and the write-protect pin (WP).
3
Status_mfr0
4
5
6
Read_vout1[7:0]
Read_vout1[15:8]
Status_vout1
MFR_COMMON Data Contents
BIT(S)
b[7:2]
b[1]
SYMBOL
OPERATION
7
Status_mfr1
Reserved
Read only, always returns 0s
Returns status of share-clock pin
1: Share-clock pin is being held low
0: Share-clock pin is active
Returns status of write-protect pin
1: Write-protect pin is high
0: Write-protect pin is low
8
9
Read_vin[7:0]
Read_vin[15:8]
Status_vin
Mfr_common_
share_clk
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
b[0]
Mfr_common_
write_protect
Read_vout2[7:0]
Read_vout2[15:8]
Status_vout2
Status_mfr2
MFR_SPARE0
Read_vout3[7:0]
Read_vout3[15:8]
Status_vout3
This 16-bit wide registers can be used to store miscel-
laneous information. The contents of these registers
may be stored and recalled from EEPROM using the
STORE_USER_ALL and RESTORE_USER_ALL com-
mands, respectively.
Status_mfr3
Read_temperature_1[7:0]
Read_temperature_1[15:8]
Status_temp
Reserved
Read_vout4[7:0]
Read_vout4[15:8]
Status_vout4
MFR_SPARE2
These 16-bit wide, paged registers can be used to store
miscellaneous information. The contents of these reg-
isters may be stored and recalled from EEPROM using
the STORE_USER_ALL and RESTORE_USER_ALL com-
mands, respectively.
Status_mfr4
Read_vout5[7:0]
Read_vout5[15:8]
Status_vout5
Status_mfr5
2978fa
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LTC2978
operaTion
MFR_VOUT_MIN
MFR_TEMPERATURE_MIN
ThiscommandreturnstheminimumADCmeasuredvalue
of the channel’s output voltage. The contents of this reg-
ister is reset to ‘hFFFF when the LTC2978 emerges from
power-on reset or when a CLEAR_FAULTS command is
executed. When odd channels are configured to measure
current, this command is not supported.
This command returns the minimum ADC measured
value of junction temperature in °C as determined by the
LTC2978’s internal temperature sensor. The contents of
this register is reset to ‘h7BFF when the LTC2978 emerges
frompower-onresetorwhenaCLEAR_FAULTScommand
is executed.
MFR_TEMPERATURE_MIN Data Contents
MFR_VOUT_MIN Data Contents
BIT(S) SYMBOL
OPERATION
BIT(S)
SYMBOL
OPERATION
b[15:0] Mfr_temperature_min The data uses the linear format:
b[15:0]
Mfr_vout_min
The data uses the linear mode format
as defined by VOUT_MODE:
N
V(mfr_vin_min) = Y • 2
N
V(mfr_vout_min) = Y • 2
Where N = b[15:11] is a 5-bit two’s
complement integer and
Where Y = b[15:0] is an unsigned
integer and N = Vout_mode_parameter
is a 5-bit two’s complement exponent
that’s hardwired to a value of –13
decimal.
Y = b[10:0] is an 11-bit two’s
complement integer
Units: °C.
Units: V.
MFR_VIN_MIN
ThiscommandreturnstheminimumADCmeasuredvalue
of the input voltage. The contents of this register is reset
to ‘h7BFF when the LTC2978 emerges from power-on
reset or when a CLEAR_FAULTS command is executed.
Updates are disabled when unit is off for insufficient input
voltage.
MFR_VIN_MIN Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0]
Mfr_vin_min
The data uses the linear format:
N
V(mfr_vin_min) = Y • 2
Where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
Units: V.
2978fa
ꢃꢇ
LTC2978
operaTion
WATCHDOG
OTHER OPERATIONS
Clock Sharing
A non-zero write to the MFR_WATCHDOG_T register will
reset the watchdog timer. Low-to-high transitions on the
WDIpinalsoresetthewatchdogtimer. Ifthetimerexpires,
ALERTB is asserted and the PWRGD output is optionally
deasserted and then reasserted after MFR_PWRGD_AS-
SERTION_DELAYms.Writing0toeithertheMFR_WATCH-
DOG_T or MFR_WATCHDOG_T_FIRST registers will
disable the timer.
MultipleLTC2978scansynchronizetheirclocksinanappli-
cationbyconnectingtogethertheopen-drainSHARE_CLK
input/outputs to a pull-up resistor as a wired AND. In this
case the fastest clock will take over and synchronize all
LTC2978s.
The LTC2978 can be configured to respond to the
SHARE_CLK pin being held low by disabling all channels
after a brief de-glitch period. When the SHARE_CLK pin
is allowed to rise, the LTC2978 will respond by beginning
a soft-start sequence.
RESET
Holding the WDI pin low for more than t
will cause
RESETB
the LTC2978 to enter the power-on reset state. Following
the subsequent rising-edge of the WDI pin, the LTC2978
willexecuteitspower-onsequencepertheuserconfigura-
tion stored in EEPROM.
The LTC2978 can be configured to hold SHARE_CLK
low when the unit is off for insufficient input voltage by
writing b[3] = 1 “mfr_config_vin_share_enable” of the
MFR_CONFIG_ALL register.
WRITE-PROTECT PIN
The WP pin allows the user to write-protect the LTC2978’s
configuration registers. The WP pin is active high, and
when asserted it overrides the WRITE_PROTECT com-
mand register. All registers are write-protected by the
WP pin except for PAGE, OPERATION, CLEAR_FAULTS,
MFR_PAGE_FF_MASK and STORE_USER_ALL.
2978fa
ꢃꢈ
LTC2978
applicaTions inForMaTion
LTC2978 Overview
Some examples of typical ON/OFF configurations are:
1. A DC/DC may be configured to turn on anytime V
The LTC2978 is a power management IC that is capable
of sequencing, margining, trimming, OV/UV supervision,
providing fault management, and voltage read back for
eight DC/DC converters. Input voltage and temperature
readbackisalsoavailable.Oddnumberedchannelscanbe
configured to read back sense resistor voltages. Multiple
LTC2978s can be synchronized to operate in unison using
theSHARE_CLK,FAULTBandCONTROLpins.TheLTC2978
utilizes a PMBus compliant interface and command set.
IN
exceeds V
.
IN_ON
2. A DC/DC may be configured to turn on only when it
receives an OPERATION command.
3. A DC/DC may be configured to turn on only via the
CONTROL pin.
4. A DC/DC may be configured to turn on only when it
receives an OPERATION command and the CONTROL
pin is asserted.
Setting Command Register Values
On Sequencing
The command register settings described herein are for
the purpose of understanding and software development
in a host processor. In actual practice, the LTC2978 can
be completely configured for standalone operation with
the LTC DC590B dongle and software GUI using intuitive
menu driven objects.
The TON_DELAY command sets the amount of time that
a channel will wait following the start of an ON sequence
beforeitsV
pinwillenableaDC/DCconverter.Once
OUT_ENn
the DC/DC converter has been enabled, the TON_RISE
command determines the amount of time the LTC2978
waits before the V
output is soft-connected and the
DACPnꢀ
Command Units On or Off
DC/DC converter output is servoed to VOUT_COMMAND
volts.TheTON_MAX_FAULT_LIMITcommanddetermines
the amount of time after the DC/DC converter has been
enabled that an undervoltage condition will be tolerated
before a fault occurs. If a TON_MAX_FAULT occurs, the
channel can be configured to disable the DC/DC converter
and propagate the fault to other channels using the bidi-
rectional FAULTBzn pins. Figure 11 shows a typical on-
sequence using the CONTROL pin.
Three control parameters determine how a particular
channel is turned on and off. The CONTROLn pins, the
OPERATION command and the value of the input voltage
measured at the V
pin (V ). In all cases, V must
IN_SNS
IN IN
exceed V
below V
in order to enable a start. When V drops
IN_ON
IN
, an immediate shutdown of all channels
IN_OFF
will result. Refer to the OPERATION section in the data
sheet for a detailed description of the ON_OFF_CONFIG
command.
V
CONTROL
V
OUT_EN
VOUT_0V_FAULT_LIMIT
V
OUT_COMMAND
DAC SOFT-CONNECTS
AND BEGINS
ADJUSTING OUTPUT
V
DC_NOM
VOUT_UV_FAULT_LIMIT
V
OUT
2978 F11
TON_RISE
TON_DELAY
TON_MAX_FAULT_LIMIT
Figure 11. Typical On Sequence Using Control Pin
2978fa
ꢄ0
LTC2978
applicaTions inForMaTion
ON State Operation
ALERTB pin will be asserted low. When the output volt-
age has decayed below its OFF threshold, the channel can
enter the ON state.
Once a channel has reached the ON state, the OPERATION
command can be used to command the DC/DC converter’s
output to margin high, margin low, or return to a nominal
outputvoltageindicatedbyVOUT_COMMAND.Theuseralso
hastheoptionofconfiguringachanneltocontinuouslytrim
theoutputoftheDC/DCconvertertotheVOUT_COMMAND
Automatic Restart via MFR_RESTART_DELAY
Command
If the CONTROLn pin is toggled quickly (>10µs deglitch),
an automatic restart sequence can be triggered using the
MFR_RESTART_DELAYcommandforthechannelsenabled
by the CONTROLn pin (see Figure 12).
voltage, or the channel’s V output can be placed in a
DACPnꢀ
high impedance state thus allowing the DC/DC converter
outputvoltagetogotoitsnominalvalue,V .Referto
DCnꢀ(NOM)
theMFR_CONFIGcommandfordetailsonhowtoconfigure
the output voltage servo.
V
OV/UV Faults
OUT
ThehighspeedvoltagesupervisorOVandUVfaultthresh-
olds are configured using the VOUT_OV_FAULT_LIMIT
and VOUT_UV_FAULT_LIMIT commands, respectively.
TheVOUT_UV_FAULT_RESPONSEandVOUT_UV_FAULT_
RESPONSE commands determine the response to an
OV/UV fault. Fault responses can range from disabling
the DC/DC converter immediately, waiting to see if the
fault condition persists for some interval before disabling
the DC/DC converter, or allowing the DC/DC converter
to continue operating in spite of the fault. If a DC/DC
converter is disabled, the LTC2978 can be configured to
retry or latch-off. The retry interval is specified using the
MFR_RETRY_DELAY command. Latched faults are reset
by toggling the CONTROLn pin, using the OPERATION
command, or removing and reapplying the bias voltage
Off Sequencing
An off sequence is initiated using the CONTROLn pin or
the OPERATION command. The TOFF_DELAY command
determines the amount of time that elapses from the be-
ginning of the off sequence until each channel’s V
pin is pulled low thus disabling its DC/DC converter.
OUT_EN
V
Off Threshold Voltage
OUT
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the chan-
nel can enter/re-enter the ON state. The OFF threshold
voltage is specified by multiplying MFR_VOUT_DIS-
CHARGE_THRESHOLD and VOUT_COMMAND. In the
event that an output voltage has not decayed below its
OFF threshold before attempting to enter the ON state,
the channel will continue to be held off, the appropriate
bit is set in the STATUS_MFR_SPECIFIC register, and the
(V
pin). All fault and warning conditions result in
IN_SNS
the ALERTB pin being asserted lowand the corresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
deasserts the ALERTB output.
CONTROL
PIN BOUNCE
V
CONTROL
V
OUT_END
2978 F012
TOFF_DELAY0
MFR_RESTART_DELAY
TON_DELAY0
Figure 12. Off Sequence with Automatic Restart
2978fa
ꢄꢀ
LTC2978
applicaTions inForMaTion
OUT
V
OV/UV Warnings
Multichannel Fault Management
OV and UV warning threshold voltages are processed
by the LTC2978’s ADC. These thresholds are set by the
VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT
commands. If a warning occurs, the corresponding bits
are set in the status registers and the ALERTB output
is asserted low. Note that a warning will never cause a
VOUT_ENn output to disable a DC/DC converter.
Multichannel fault management is handled using the
bidirectional FAULTBzn pins. The “z” designates the fault
zone which is either 0 or 1. There are two fault zones in
the LTC2978. Each zone contains 4-channels. Figure 13
illustrates the connections between channels and the
FAULTBzn pins.
• The MFR_FAULTBz0_PROPAGATE command acts like
a programmable switch that allows faulted-off condi-
tions from a particular channel (PAGE) to propagate
to either FAULTBzn output in that channel’s zone. The
MFR_FAULTBzn_RESPONSEcommandcontrolssimilar
switches on the inputs to each channel that allow any
channeltoshutdowninresponsetoanycombinationof
the FAULTBzn pins within a zone. Channels responding
to a FAULTBzn pin pulling low will attempt a new start
sequencewhentheFAULTBznpininquestionisreleased
by the faulted channel.
Configuring the V
Output
IN_EN
The V
output may be used to disable the interme-
IN_EN
diate bus voltage in the event of an output OV or UV
fault. Use the MFR_VINEN_OV_FAULT_RESPONSE and
MFR_VINEN_UV_FAULT_RESPONSE registers to config-
uretheV
pintoassertlowinresponsetoVOUT_OV/UV
IN_EN
fault conditions. The V
output will stop pulling low
IN_EN
when the LTC2978 is commanded to re-enter the ON state
following a faulted-off condition.
A charge-pumped 5µA pull-up to 12V is also available
• To establish dependencies across fault zones, tie the
fault pins together, e.g., FAULTB01 to FAULTB10. Any
channel can depend on any other. To disable all chan-
nels in response to any channel faulting off, short all
the FAULTBzn pins together, and set MFR_FAULTBzn_
PROPAGATE = ‘h01 and MFR_FAULTBzn_RESPONSE
= ‘h0F for all channels.
on the V
output. Refer to the MFR_CONFIG_ALL
IN_EN
register description in the OPERATION section for more
information.
Figure 23 shows an application circuit where the V
IN_EN
outputisusedtotriggeraSCRcrowbarontheintermediate
bus in order to protect the DC/DC converter’s load from a
catastrophic fault such as a stuck top gate.
• A FAULTBzn pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 10µs deglitch delay.
2978fa
ꢄꢁ
LTC2978
applicaTions inForMaTion
MFR_FAULTB00_RESPONSE, PAGE = 0
MFR_FAULTB00_PROPAGATE, PAGE = 0
MFR_FAULTB01_PROPAGATE, PAGE = 0
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
FAULTB00
FAULTB01
MFR_FAULTB01_RESPONSE, PAGE = 0
MFR_FAULTB00_RESPONSE, PAGE = 1
MFR_FAULTB01_RESPONSE, PAGE = 1
MFR_FAULTB00_PROPAGATE, PAGE = 1
MFR_FAULTB01_PROPAGATE, PAGE = 1
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
MFR_FAULTB00_RESPONSE, PAGE = 2
MFR_FAULTB01_RESPONSE, PAGE = 2
MFR_FAULTB00_PROPAGATE, PAGE = 2
MFR_FAULTB01_PROPAGATE, PAGE = 2
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
MFR_FAULTB00_RESPONSE, PAGE = 3
MFR_FAULTB01_RESPONSE, PAGE = 3
MFR_FAULTB00_PROPAGATE, PAGE = 3
MFR_FAULTB01_PROPAGATE, PAGE = 3
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
ZONE 0
ZONE 1
ZONE 0
ZONE 1
MFR_FAULTB10_RESPONSE, PAGE = 4
MFR_FAULTB11_RESPONSE, PAGE = 4
MFR_FAULTB10_PROPAGATE, PAGE = 4
MFR_FAULTB11_PROPAGATE, PAGE = 4
CHANNEL 4
EVENT PROCESSOR
PAGE = 4
FAULTB10
FAULTB11
MFR_FAULTB10_RESPONSE, PAGE = 5
MFR_FAULTB11_RESPONSE, PAGE = 5
MFR_FAULTB10_PROPAGATE, PAGE = 5
MFR_FAULTB11_PROPAGATE, PAGE = 5
CHANNEL 5
EVENT PROCESSOR
PAGE = 5
MFR_FAULTB10_RESPONSE, PAGE = 6
MFR_FAULTB11_RESPONSE, PAGE = 6
MFR_FAULTB10_PROPAGATE, PAGE = 6
MFR_FAULTB11_PROPAGATE, PAGE = 6
CHANNEL 6
EVENT PROCESSOR
PAGE = 6
MFR_FAULTB10_RESPONSE, PAGE = 7
MFR_FAULTB11_RESPONSE, PAGE = 7
MFR_FAULTB10_PROPAGATE, PAGE = 7
MFR_FAULTB11_PROPAGATE, PAGE = 7
CHANNEL 7
EVENT PROCESSOR
PAGE = 7
2978 F13
Figure 13. Channel Fault Management Block Diagram
2978fa
ꢄꢂ
LTC2978
applicaTions inForMaTion
Interconnect Between Multiple LTC2978s
• ALERTB is typically one line in an array of PMBus
converters. The LTC2978 allows a rich combination of
faults and warnings to be propagated to the ALERTB
pin.
Figure 14 shows how to interconnect the pins in a typical
multi-LTC2978 array.
• All V
lines should be tied together in a star type
IN_SNS
• WDI/RESET can be used to put the LTC2978 in the
power-on reset state. Pull WDI/RESET low for at least
connection at the point where V is to be sensed.
IN
This will minimize timing errors for the case where the
t
to enter this state.
RESETB
ON_OFF_CONFIG is configured to start the LTC2978
• TheFAULTBznlinescanbeconnectedtogethertocreate
fault dependencies. Figure 14 shows a configuration
where a fault on any FAULTBzn will pull all others low.
This is useful for arrays where it is desired to abort a
startup sequence in the event any channel does not
come up (see Figure 15).
based on V and ignore the CONTROLn line and the
IN
OPERATION command. In multi-part applications that
are sensitive to timing errors, it is recommended that
the Vin_share_enable bit of the MFR_CONFIG_ALL
register be set high in order to allow SHARE_CLK to
synchronizeon/offsequencinginresponsetotheV
IN_ON
and V
thresholds.
IN_OFF
• PWRGD reflects the status of the outputs that are
mapped to it by the MFR_PWRGD_EN command. Fig-
ure 14 shows all the PWRGD pins connected together,
but any combination may be used.
• Connecting all V
lines together will allow an
IN_EN
overvoltage (OV) fault on any DC/DC converter’s output
in the array to shut off a common input switch.
TO V OF
IN
DC/DCs
TO INPUT
SWITCH
TO HOST CONTROLLER
LTC2978 1
VIN_SNS
LTC2978 #n
VIN_SNS
VIN_EN
VIN_EN
SDA
SCL
SDA
SCL
ALERTB
ALERTB
CONTROL0
CONTROL1
WDI/RESET
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
CONTROL0
CONTROL1
WDI/RESET
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
GND
GND
2978 F14
TO OTHER LTC2978s–10k EQUIV PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
Figure 14. Typical Connections Between Multiple LTC2978s
2978fa
ꢄꢃ
LTC2978
applicaTions inForMaTion
Trimming and Margining DC/DC Converters with
External Feedback Resistors
is developed between the V
and V
DACM0
pins by the
DACM0
DACP0
closed-loop servo algorithm. V
is Kelvin connected
to the point-of-load GND in order to minimize the effects
of load induced grounding errors. The V output is
Figure 16 shows a typical application circuit for trim-
ming/margining a power supply with an external feedback
DACP0
connectedtotheDC/DCconverter’sfeedbacknodethrough
network. The V
and V
differential inputs
SENSEP0
SENSEM0
resistor R30.
sense the load voltage directly, and a correction voltage
V
CONTROLn
V
OUT0
TON_DELAY0
TON_DELAY1
V
V
OUT1
OUT2
TON_DELAY2
•
•
•
•
•
•
V
OUTn
TON_DELAYn
BUSSED
VFAULTBzn
PINS
2978 F15
TON_MAX_FAULT1
Figure 15. Aborted On Sequence Due to Channel 1 Short
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
OUT
0.1µF
V
DACP0
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R20
R10
LTC2978*
V
LOAD
FB
V
DACM0
0.1µF
V
SGND
SENSEM0
V
RUN/SS
OUT_EN0
GND
2978 F16
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 16. Application Circuit for DC/DC Converters with External Feedback Resistors
2978fa
ꢄꢄ
LTC2978
applicaTions inForMaTion
4-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
3. Solve for the minimum value of V
that’s needed
DACP0
to yield the minimum required DC/DC converter output
voltage V
.
DC0(MIN)
The following 4-step procedure should be used to calcu-
late the resistor values required for the application circuit
shown in Figure 16.
The voltage-buffered current DAC has two full-scale
settings, 1.33V 3.7% and 2.7V 3.7%. In order to
select the appropriate full-scale setting, calculate the
1. AssumevaluesforfeedbackresistorR20andthenominal
maximum required V
output voltage:
DAC0P
DC/DC converter output voltage V
for R10.
, and solve
DC0(NOM)
R30
VDACP0 > VDC(NOM) – VDC(MIN)
•
+ VFB (3)
R20
V
is the output voltage of the DC/DC converter
DC0(NOM)
when the LTC2978’s V
pin is in a high impedance
DACP0
4. Recalculate the minimum, nominal, and maximum
DC/DC converter output voltages and the resulting
margining resolution.
state.R10isafunctionofR20,V
,thevoltageat
DC0(NOM)
the feedback node (V ) when the loop is in regulation,
FB
and the feedback node’s input current (I ).
FB
R20
R10
R20 • VFB0
VDC(NOM) –IFB0 • R20 – V
VDC(NOM) = VFB • 1+
+IFB •R20
(4)
R10 =
(1)
FB
R20
VDC0(MIN) = VDC0(NOM)
–
• VDACP0(F/S)– V (5)
(
)
FB
2. Solve for the value of R30 that yields the maximum
required DC/DC converter output voltage V
R30
R20
R30
.
DC0(MAX)
VDC0(MAX) = VDC(NOM)
+
• V
(6)
(7)
FB
WhenV
isat0V, theoutputoftheDC/DCconverter
is at its maximum voltage.
DACP0
R20
• VDACP0(F/S)
1024
R30
R20 • VFB
R30 ≤
VRES
=
V/DAC LSB
(2)
VDC(MAX) – VDC(NOM)
2978fa
ꢄꢅ
LTC2978
applicaTions inForMaTion
Trimming and Margining DC/DC Converters
with a TRIM Pin
∆ % and ∆
% denote the percentage change in the
DOWN
UP
converter’s output voltage when margining up or down,
respectively.
Figure 17 illustrates a typical application circuit for trim-
ming/margining the output voltage of a DC/DC converter
2-Step Resistor and DAC Full-Scale Voltage Selection
Procedure for DC/DC Converters with a TRIM Pin
with a TRIM Pin. The LTC2978’s V
pin connects to
DACPn
the TRIM pin through resistor R30, and the V
pin is
DACM0
Thefollowing2-stepprocedureshouldbeusedtocalculate
the resistor value for R30 and the required full-scale DAC
voltage (refer to Figure 17).
connected to the converter’s point-of-load ground.
DC/DC converters with a TRIM pin are typically margined
high or low by connecting an external resistor between
1. Solve for R30:
the TRIM pin and either the V
or V
pin. The
SENSEP
SENSEM
relationships between these resistors and the ∆% change
in the output voltage of the DC/DC converter are typically
expressed as:
50 – ∆DOWN
%
R30 ≤ RTRIM
•
(10)
∆
%
DOWN
RTRIM • 50
2. Calculate the maximum required output voltage for
RTRIM_DOWN
=
–RTRIM
(8)
V
:
∆
%
DACP0
DOWN
∆UP%
RTRIM_UP
=
VDACP0 ≥ 1+
• VREF
(11)
∆
%
DOWN
V • 100 + ∆ %
(
)
50
DC
UP
RTRIM
•
–
– 1
(9)
2 • VREF • ∆UP%
∆ %
UP
where R
is the resistance looking into the TRIM pin,
TRIM
V
V
is the TRIM pin’s open-circuit output voltage and
is the DC/DC converter’s nominal output voltage.
REF
DC
V
IN
V
IN
4.5V < V
< 15V
IBUS
+
V
OUT
V
V
IN_SNS
PWR
R30
0.1µF
TRIM
V
V
DACP0
+
V
V
V
V
SENSEP0
SENSE
DD33
DD33
DD25
DC/DC
CONVERTER
LTC2978*
LOAD
V
DACM0
0.1µF
–
V
V
SENSEM0
SENSE
ON/OFFB
GND
V
OUT_EN0
GND
2978 F17
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 17. Application Circuit for DC/DC Converters with Trim Pin
2978fa
ꢄꢆ
LTC2978
applicaTions inForMaTion
Measuring Current
differential mode noise from the inductor of the switching
DC/DC converter. The filter to the ADC is placed directly
across the inductor or a sense resistor in series with the
inductor. Note that the + input to the ADC must be limited
Odd numbered ADC channels may be used to measure
supply current. Set the ADC to high resolution mode to
configure for current measuring and improve sensitivity.
Note that no OV or UV faults or warnings are reported in
thismode,buttelemetryisavailablefromtheREAD_VOUT
command using the 11-bit signed mantissa plus 5-bit
signed exponent linear data format. Set the MFR_CONFIG
bit b[9] = 1 in order to enable high res mode. Note: Any
channel configured for ADC high res mode should be per-
manentlycommandedoff,i.e.,OPERATIONregister=‘h00
to <6V above ground. Select R and C such that the
CM
CM
corner frequency is ≤1/10 the DC/DC converter switching
frequency and ≤1/10 of the internal 62.5kHz clock of the
LTC2978’s ∆Σ ADC. This will assure that the DC value
at the (+) input to the ADC will be equal to the output
voltage with small ripple. Good values are R = 100Ω,
CM
C
≥ 1µF. Keep R ≤ 100Ω to minimize gain errors due
CM
CM
to ADC input resistance.
(this is the factory default EEPROM value). The V
OUT_ENn
will assert low in this mode and cannot be used to control
a DC/DC. The V output is also unavailable.
Many switching regulator control ICs derive AC inductor
current information from an RC network such as the one
formed by R1, C1, R2 and C2. The proper placement of
the balanced common mode filter for the ADC input is
also shown in Figure 18.
DACPn
A circuit for measuring current is shown in Figure 18.
The balanced filter, R , C , rejects common mode and
CM CM
R
CM
LTC2978
C
C
+
–
CM
ADC
R
CM
CM
L
DCR
+
–
LOAD CURRENT
C1
R1
+
–
TO
CONTROLLER
IC
R2
C2
2978 F18
Figure 18. DCR Current Sensing Circuits
2978fa
ꢄꢇ
LTC2978
applicaTions inForMaTion
Antialiasing Filter Considerations
R40=R50≤200ΩtominimizeADCgainerrors, andselect
a value for capacitors C10 and C20 that doesn’t add too
much additional response time to the OV/UV supervisor,
e.g. τ ≅ 10µs (R = 100Ω, C = 0.10µF).
Extremelynoisyenvironmentsmayrequireanantialiasing
filter on the input to the LTC2978’s ADC. The R-C circuit
shown in Figure 19 is adequate for most situations. Keep
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
OUT
0.1µF
V
DACP0
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R40
R50
C10
C20
R20
R10
LTC2978*
GND
V
LOAD
FB
V
SENSEM0
0.1µF
V
SGND
DACM0
V
RUN/SS
OUT_EN0
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978 F09
Figure 19. Antialiasing Filter on VSENSE Lines
2978fa
ꢄꢈ
LTC2978
applicaTions inForMaTion
2
Dongle Connections
theLTC2978’sandtheI Cpull-upresistorsshouldbepow-
ered from the ORed 3.3V supply. In addition, any device
Figure20illustratestheapplicationschematicforpowering
and programming one or more LTC2978’s from the LTC
PMBuscontrollerintheabsenceofsystempower.Because
of the controller’s limited current sourcing capability, only
2
sharing I C bus connections with the LTC2978 should not
have body diodes between the SDA/SCL pins and its V
DD
node because this will interfere with bus communication
in the absence of system power.
IDEAL
DIODE
OR’d 3.3V
TP0101K-SSOT23
SYSTEM
V
V
V
V
PWR
DD33
DD33
DD25
3.3V
0.1µF
0.1µF
LTC4412
V
SENSE
IN
GND GATE
CTL STAT
LTC2978
PIN CONNECTIONS
OMITTED FOR
CLARITY
ISOLATED 3.3V
SDA
SCL
LTC
CONTROLLER
HEADER
SDA
SCL
SHARE_CLK
WP GND
TO/FROM OTHER
LTC2978s
2978 F10
2
NOTE: LTC CONTROLLER I C CONNECTONS ARE OPTO-ISOLATED
ISOLATED 3.3V FROM CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW < 10µA
ISOLATED 3.3V CURRENT LIMIT = 100mA
Figure 20. LTC Controller Connections for Powering and Communicating with the LTC2978
2978fa
ꢅ0
LTC2978
applicaTions inForMaTion
PCB ASSEMBLY AND LAYOUT SUGGESTIONS
practice to minimize the presence of voids within the
exposed pad inter-connection. Total elimination of voids
is difficult, but the design of the exposed pad stencil is
key. Figure 21 shows a suggested screen print pattern.
The proposed stencil design enables out-gassing of the
solderpasteduringreflowaswellasregulatingthefinished
solder thickness.
Bypass Capacitor Placement
The LTC2978 requires 0.1µF bypass capacitors between
the V
pins and GND, the V
pin and GND, and the
DD33
DD25
REFP pin and REFM pin. If the chip is being powered from
the V input, then that pin should also be bypassed
PWR
to GND by a 0.1µF capacitor. In order to be effective,
these capacitors should be made of high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible.
PC Board Layout
Mechanical stress on a PC board and soldering-induced
stress can cause the LTC2978’s reference voltage and
voltage drift to shift. A simple way to reduce these stress-
related shifts is to mount the IC near the short edge of the
PC board, or in a corner. The board edge acts as a stress
boundary, or a region where the flexure of the board is
minimal.
Exposed Pad Stencil Design
The LTC2978’s package is thermally and electrically
efficient. This is enabled by the exposed die attach pad
on the under side of the package which must be soldered
down to the PCB or mother board substrate. It is a good
2978 F11
Figure 21. Suggested Screen Pattern for Die Attach Pad
2978fa
ꢅꢀ
LTC2978
Typical applicaTion
0.1µF
3.3V
0.1µF
0.1µF
14 36? 35 65 20 19 18 17 16 34 33 15
V
V
V
V
IN
IN
OUT
40
37
61
3
OUT
V
V
V
DACP7
DACP0
R30
R20
R37
R27
DC/DC
CONVERTER
V
DC/DC
CONVERTER
SENSEP0
SENSEP7
V
V
LOAD
LOAD
LOAD
LOAD
LOAD
FB
FB
38
39
4
R10
V
V
V
R17
SENSEM0
DACM0
SENSEM7
62
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM7
5
12
V
V
OUT_EN7
OUT_EN0
V
V
IN
41
43
60
1
OUT
V
V
V
DACP6
DACP1
R36
R26
V
DC/DC
CONVERTER
SENSEP1
SENSEP6
V
FB
44
42
2
V
V
V
R16
SENSEM1
DACM1
SENSEM6
59
V
SGND RUN/SS
GND
DACM6
6
11
V
V
OUT_EN6
OUT_EN1
LTC2978
V
V
V
V
IN
IN
OUT
45
47
57
63
OUT
V
V
V
DACP5
DACP2
R32
R22
R35
R25
DC/DC
V
DC/DC
CONVERTER
SENSEP2
SENSEP5
CONVERTER
V
V
LOAD
FB
FB
48
46
64
58
R12
V
V
V
R15
SENSEM2
DACM2
SENSEM5
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM5
7
10
V
V
OUT_EN5
OUT_EN2
V
V
IN
51
49
56
53
OUT
V
V
V
DACP4
DACP3
R34
R24
V
DC/DC
CONVERTER
SENSEP3
SENSEP4
V
FB
50
52
54
55
V
V
V
R14
SENSEM3
DACM3
SENSEM4
V
SGND RUN/SS
GND
DACM4
IN
OUT
8
9
INTERMEDIATE
V
V
OUT_EN4
OUT_EN3
2978 F12
BUS
CONVERTER
13 24 25 26 27 22 28 29 30 31 32 21
10k
23
EN
10k
10k
3.3V
3.3V
5.49k
TO/FROM OTHER LTC2978s AND MICROCONTROLLER
Figure 22. LTC2978 Application Circuit with 3.3V Chip Power
2978fa
ꢅꢁ
LTC2978
package DescripTion
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 p0.05
7.15 p0.05
7.50 REF
8.10 p0.05 9.50 p0.05
(4 SIDES)
7.15 p0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
R = 0.10
TYP
R = 0.115
TYP
9 .00 p 0.10
(4 SIDES)
63 64
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 p 0.10
7.50 REF
(4-SIDES)
7.15 p 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
2978fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢅꢂ
LTC2978
Typical applicaTion
R
Q1
SENSE
0.007Ω
Si4894BDY
V
IN
V
V
IN
<15V
C
BYPASS
V
IN_SNS
OUT
V
V
PWR
DACP0
DC/DC
CONVERTER
100Ω
68Ω
V
V
SENSE
GATE
LTC4210-3
SENSEP0
CC
0.1µF
LTC2978*
24.3k
V
LOAD
FB
ON
V
DACM0
0.01µF
TIMER GND
V
10k
SGND
SENSEM0
V
RUN/SS
0.22µF
OUT_EN0
GND
10k
0.01µF
2978 F23
2907
MCR12DC
4.99k
220Ω
0.1µF
BAT54
REFP
V
REFM
IN_EN
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
V
V
V
GND
DD33 DD33 DD25
0.1µF
0.1µF
Figure 23. LTC2978 Application Circuit with Crowbar Protection on Intermediate Bus
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
2
LTC2970
Dual I C Power Supply Monitor and Margining Controller
14-Bit ∆Σ ADC with < 0.5% TUE, Dual 8-Bit IDACs with 1x Voltage
Buffers
2
LTC4151
High Voltage I C Current and Voltage Monitor
7V to 80V, 12-Bit Resolution
LTC4210-3
Hot Swap™ Controller in 6-Lead SOT-23 Package
Low Loss PowerPath™ Controller in ThinSOT™
Adjustable Analog Current Limit with Circuit Breaker, Fast Response
Limits Peak Fault Current
LTC4412
Replaces Power Supply ORing Diodes, Minimal External Components,
Automatic Switching Between DC Sources, Simplifies Load Sharing with
Multiple Batteries, Low Quiescent Current: 11µA
LTM®4601
LTM4608
8A, Low V DC/DC µModule® with PLL, Output Tracking
Complete Switch Mode Power Supply, 4.5V to 20V Input Voltage, 0.6V
to 5V Output Voltage, PLL Frequency Synchronization, 1.5% Regulation
IN
and Margining
8A, Low V DC/DC µModule with Tracking, Margining,
Complete Switch Mode Power Supply, 2.7V to 5.5V Input Voltage, 0.6V
to 5V Output Voltage, Onboard Frequency Synchronization, 1.5%
Regulation
IN
Multiphase and Frequency Synchronization
µModule is a registered trademark of Linear Technology Corporation. PowerPath, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
2978fa
LT 0909 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢅꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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