LTC2992HMS-1#PBF_技术文档

LTC2992

Dual Wide Range

Power Monitor

FeaTures

DescripTion

The LTC^®2992 is a rail-to-rail system monitor that mea-

sures current, voltage, and power of two supplies. It

features an operating range of 2.7V to 100V and includes

a shunt regulator for supplies above 100V. The voltage

measurement range of 0V to 100V is independent of the

input supply. Two ADCs simultaneously measure each

supply’s current. A third ADC monitors the input voltages

and four auxiliary external voltages. Each supply’s current

and power is added for total system consumption. Mini-

mum and maximum values are stored and an overrange

alert with programmable thresholds minimizes the need

n

Rail-to-Rail Input Range: 0V to 100V

n

Wide Input Supply Range: 2.7V to 100V

n

Measures Current, Voltage, and Power

Shunt Regulator for Supplies >100V

n

8-/12-Bit ADCs with Less Than 0.ꢀ3 Total Unad-

justed Error

n

Four General Purpose Inputs/Outputs Configurable

as ADC Inputs

Continuous Scan and Snapshot Modes

n

Stores Minimum and Maximum Measurements

n

Alerts When Alarm Thresholds Exceeded

2

n

Shutdown Mode with I < 50μA

for software polling. Data is reported via a standard I C

interface. Shutdown mode reduces current consumption

to 25μA typically.

Q

n

Split SDA Pin Eases Opto-Isolation

n

Available in 16-Lead 4mm × 3mm DFN and MSOP

Packages

2

The LTC2992 I C interface includes separate data input

2

and output pins for use with standard or opto-isolated I C

applicaTions

connections. The LTC2992-1 has an inverted data output

for use with inverting opto-isolator configurations.

n

Telecom Infrastructure

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog

Devices, Inc. All other trademarks are the property of their respective owners.

Industrial Equipment

n

Automotive

Computer Systems and Servers

n

Typical applicaTion

Dual Wide Range Power Monitor

ADC Error (GPIO)

0.01Ω

0.50

V

IN2

0V TO 100V

V

12-BIT MODE

OUT2

0.01Ω

V

IN1

3V TO 100V

0.25

V

OUT1

MAX ERROR

+

–

+

–

SENSE1 SENSE1

SENSE2 SENSE2

0

MEASURED

VOLTAGE 1

TYPICAL

V

DD

GPIO1

SDAI

MEASURED

VOLTAGE 2

LTC2992

GPIO2

2

I C

–0.25

SDAO

SCL

INTERFACE

DATAREADY

GPIO3

GPIO4

2992 TA01a

ALERT

INTV

CC

GND ADR0 ADR1

–0.50

0

1024

2048

3072

4096

CODE

2992 TA01b

0.1μF

2992f

1

For more information www.linear.com/LTC2992

LTC2992

absoluTe MaxiMuM raTings

(Notes 1, 2)

Average Pin Currents

Supply Voltages

INTV .............................................. –10mA to 35mA

V

...................................................... –0.3V to 100V

CC

DD

SCL, SDAI............................................................5mA

SDAO, SDAO, GPIO1-4.......................................20mA

Operating Junction Temperature Range

INTV (Note 3) .....–0.3V to Lesser of 5.8V, V + 0.3V

CC

DD

Analog Input Voltages

+

–

SENSEn , SENSEn .................................–1V to 100V

–

LTC2992C................................................ 0°C to 70°C

LTC2992I .............................................–40°C to 85°C

LTC2992H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10sec)

SENSEn to SENSEn ..................................–1V to 1V

ADR0, ADR1 ............................................ –0.3V to 7V

GPIO1-4................................................... –0.3V to 7V

Digital Input/Output Voltages

SCL, SDAI (Note 4)............................... –0.3V to 5.9V

SDAO, SDAO, GPIO1-4............................. –0.3V to 7V

MS Package Only..............................................300°C

pin conFiguraTion

LTC2992

TOP VIEW

–

+

–

+

SENSE1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SENSE2

GPIO2

GPIO4

GND

TOP VIEW

–

+

–

+

1

2

3

4

5

6

7

8

SENSE1

16 SENSE2

15 SENSE2

14 GPIO2

13 GPIO4

12 GND

GPIO1

GPIO3

ADR1

ADR0

GPIO1

GPIO3

ADR1

ADR0

17

11 SDAO

10 SDAI

SDAO

SDAI

INTV

V

CC

DD

INTV

CC

9

SCL

V

SCL

DD

MS PACKAGE

16-LEAD PLASTIC MSOP

DE PACKAGE

T

= 150°C, θ = 120°C/W, θ = 21°C/W

16-LEAD (4mm × 3mm) PLASTIC DFN

JMAX

JA

JC

T

= 150°C, θ = 43°C/W, θ = 5.5°C/W

JMAX

JA JC

EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL

LTC2992-1

TOP VIEW

–

+

–

+

SENSE1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SENSE2

GPIO2

GPIO4

GND

TOP VIEW

–

+

–

+

1

2

3

4

5

6

7

8

SENSE1

16 SENSE2

GPIO1

GPIO3

ADR1

ADR0

15 SENSE2

14 GPIO2

13 GPIO4

12 GND

GPIO1

GPIO3

ADR1

ADR0

17

11 SDAO

10 SDAI

SDAO

SDAI

INTV

V

CC

DD

INTV

CC

9

SCL

V

SCL

DD

MS PACKAGE

16-LEAD PLASTIC MSOP

= 150°C, θ = 120°C/W, θ = 21°C/W

JA JC

DE PACKAGE

T

16-LEAD (4mm × 3mm) PLASTIC DFN

JMAX

T

= 150°C, θ = 43°C/W, θ = 5.5°C/W

JMAX

JA JC

EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL

2992f

2

For more information www.linear.com/LTC2992

LTC2992

http://www.linear.com/product/LTC2992#orderinfo

orDer inForMaTion

TUBE

TAPE AND REEL

PART MARKING*

2992

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2992CDE#PBF

LTC2992IDE#PBF

LTC2992HDE#PBF

LTC2992CDE-1#PBF

LTC2992IDE-1#PBF

LTC2992HDE-1#PBF

LTC2992CMS#PBF

LTC2992IMS#PBF

LTC2992HMS#PBF

LTC2992CMS-1#PBF

LTC2992IMS-1#PBF

LTC2992HMS-1#PBF

LTC2992CDE#TRPBF

LTC2992IDE#TRPBF

LTC2992HDE#TRPBF

LTC2992CDE-1#TRPBF

LTC2992IDE-1#TRPBF

LTC2992HDE-1#TRPBF

LTC2992CMS#TRPBF

LTC2992IMS#TRPBF

LTC2992HMS#TRPBF

LTC2992CMS-1#TRPBF

LTC2992IMS-1#TRPBF

LTC2992HMS-1#TRPBF

16-Lead (4mm × 3mm) Plastic DFN

16-Lead Plastic MSOP

2992

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

2992

29921

2992

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

2992

16-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

2992

16-Lead Plastic MSOP

29921

16-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

16-Lead Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_DDis from ꢀV to 100V unless otherwise noted. (Note 2)

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

DD

V

CC

V

Input Supply Voltage

DD

3

100

5.8

V

INTV Input Supply Voltage

2.7

CC

l

I

DD

V

Supply Current

V

= 48V, INTV Open

1.2

25

1.6

50

mA

µA

DD

CC

Shutdown

l

I

CC

INTV Supply Current

INTV = V = 5V

1.0

25

1.4

50

mA

µA

CC

DD

Shutdown

l

V

INTV Linear Regulator Voltage

8V < V < 100V

LOAD

4.6

5.8

5

5.4

V

CC(LDO)

CC

DD

= 0mA

I

l

ΔV

INTV Linear Regulator Load Regulation

8V < V < 100V

100

6.2

250

mV

CC(LDO)

CC

DD

I

= 0mA to 10mA

LOAD

l

V

CCZ

Shunt Regulator Voltage at INTV

V

DD

V

DD

= 48V, I = 1.5mA

6.7

250

2.69

3

V

mV

V

CC

ΔV

Shunt Regulator Load Regulation

INTV Supply Undervoltage Lockout

= 48V, I = 1.5mA to 35mA

CC

CCZ

V

INTV Rising, V = INTV

CC

2.2

2.4

1.7

2.5

2.7

2.1

CC(UVL)

CC

DD

V

Supply Undervoltage Lockout

V

Rising, INTV Open

V

DD(UVL)

CCI2C(RST)

DDI2C(RST)

DD

CC

2

INTV I C Logic Reset

INTV Falling, V = INTV

CC

V

CC

DD

2

V

I C Logic Reset

V

Falling, INTV Open

V

DD

CC

SENSE Inputs

+

−

l

+

I

48V SENSE Input Current

SENSE , SENSE , V = 48V

120

170

2

µA

SENSE (HI)

DD

Shutdown

−

+

−

l

I

48V SENSE Input Current

SENSE , SENSE , V = 48V

20

1

µA

SENSE (HI)

DD

Shutdown

2992f

3

For more information www.linear.com/LTC2992

LTC2992

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_DDis from ꢀV to 100V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

−

+

l

I

0V SENSE Source Current

SENSE , SENSE = 0V, V = 48V

–10

–1

µA

SENSE (LO)

DD

Shutdown

−

+

−

l

I

0V SENSE Source Current

SENSE , SENSE = 0V, V = 48V

–5

–1

µA

SENSE (LO)

DD

Shutdown

ADC

l

RES

Resolution (No Missing Codes)

(Note 5)

NADC[7] = 1

NADC[7] = 0

8

12

Bits

l

V

FS

Full-Scale Voltage

ΔSENSE (Note 6)

50.9

102

2.042

51.2

102.4

2.048

51.5

102.8

2.054

mV

V

+

SENSE

GPIO

LSB

TUE

LSB Step Size

8-Bit Mode

ΔSENSE

200

400

8

µV

mV

+

SENSE

GPIO

LSB Step Size

12-Bit Mode

ΔSENSE

12.5

25

0.5

µV

mV

+

SENSE

GPIO

l

Total Unadjusted Error (Note 7)

8-Bit Mode

ΔSENSE

±0.8

%

+

SENSE

GPIO

l

Total Unadjusted Error

12-Bit Mode

ΔSENSE

±0.6

±0.4

±0.3

%

+

SENSE

GPIO

+

l

V

OS

Offset Error

8-Bit Mode

ΔSENSE, SENSE , GPIO

±1

LSB

l

Offset Error

12-Bit Mode

ΔSENSE (C-, I-Grade)

ΔSENSE (H-Grade)

±2.1

±3.1

±1.5

±1.1

LSB

+

SENSE

GPIO

+

l

INL

Integral Nonlinearity

8-Bit Mode

ΔSENSE, SENSE , GPIO

±1

LSB

l

Integral Nonlinearity

12-Bit Mode

ΔSENSE

±3.5

±2

LSB

+

SENSE , GPIO

Transition Noise

ΔSENSE

0.5

0.3

5

µV

RMS

σ

T

RMS

+

SENSE

mV

µV

GPIO

l

t

Conversion Time (Snapshot Mode)

8-Bit Mode

ΔSENSE

3.9

0.97

4.1

1.02

4.3

1.08

ms

CONV

+

SENSE , GPIO

l

Conversion Time (Snapshot Mode)

12-Bit Mode

ΔSENSE

62.4

15.6

65.6

16.4

68.8

17.2

ms

+

SENSE , GPIO

GPIO

l

V

GPIO Pin Input Threshold

GPIO Pin Output Low Voltage

GPIO Pin Input Current

V

Rising

= 8mA

1.13

1.23

0.15

0

1.33

0.4

±1

V

GPIO(TH)

GPIO(OL)

GPIO

I

GPIO

I

V

DD

= 48V, GPIO = 3V

μA

GPIO

2

I C Interface (V = 48V)

DD

l

V

ADR0, ADR1 Input High Threshold

ADR0, ADR1 Input Low Threshold

ADR0, ADR1 Input Current

1.8

0.3

2.4

0.6

2.7

0.9

±13

±7

V

ADR(H)

ADR(L)

I

ADR0, ADR1 = 0V, 3V

μA

ADR(IN)

ADR(IN,Z)

Allowable Leakage When Open

2992f

4

For more information www.linear.com/LTC2992

LTC2992

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_DDis from ꢀV to 100V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

, I = 8mA

MIN

TYP

0.15

0

MAX

0.4

±1

UNITS

l

V

SDAO, SDAO, Output Low Voltage

SDAI, SDAO, SDAO, SCL Leakage Current

SDAI, SCL Input Threshold

SDAI, SCL Clamp Voltage

I

V

μA

V

OD(OL)

SDAO SDAO

I

SDAI, SDAO, SDAO, SCL = 5V

SDA,SCL(IN)

V

1.5

5.9

1.8

2.1

6.9

SDA,SCL(TH)

I

, I

= 0.5mA, 5mA

V

SDA,SCL(CL)

SDAI SCL

2

I C Interface Timing

l

f

t

Maximum SCL Clock Frequency

SCL Low Period

400

kHz

μs

SCL(MAX)

LOW

0.65

50

1.3

600

1.3

SCL High Period

ns

HIGH

Bus Free Time Between STOP/START

Condition

0.12

μs

BUF(MIN)

l

t

Hold Time after (Repeated) START Condition

Repeated START Condition Setup Time

STOP Condition Setup Time

Data Hold Time Input

140

30

600

0

ns

ms

pF

HD, STA(MIN)

SU, STA(MIN)

SU, STO(MIN)

HD, DATI(MIN)

HD, DATO(MIN)

SU, DAT(MIN)

SP(MAX)

30

−100

600

30

Data Hold Time Output

300

900

100

250

Data Setup Time

Maximum Suppressed Spike Pulse Width

Stuck Bus Reset Time

50

25

110

33

SCL or SDAI Held Low

RST

C

SCL, SDAI Input Capacitance (Note 5)

5

10

X

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of

5.9V. Driving these pins to voltages beyond the clamp may damage the

part. The pins can be safely tied to higher voltages through resistors that

limit the current below 5mA.

Note 2: All currents into pins are positive. All voltages are referenced to

ground, unless otherwise noted.

Note 5: Guaranteed by design and not subjected to test.

+

–

Note 6: ΔSENSE is defined as V

– V

SENSE

Note ꢀ: An internal shunt regulator limits the INTV pin to a minimum of

CC

Note 7: TUE is the maximum ADC error for any code expressed as a

percentage of full-scale.

5.8V. Driving this pin to voltages beyond 5.8V may damage the part. This

pin can be safely tied to higher voltages through a resistor that limits the

current below 35mA.

2992f

5

For more information www.linear.com/LTC2992

LTC2992

Typical perForMance characTerisTics

V_DDSupply Current

INTV_CCSupply Current

INTV_CCLoad Regulation

1.4

1.2

1.0

0.8

1.4

1.2

1.0

5.2

5.1

5.0

4.9

4.8

NORMAL

0.8

30

26

22

18

45

35

25

15

SHUTDOWN

0

20

40

60

80

100

2

3

4

5

6

0

2

4

6

8

10

V

DD

SUPPLY VOLTAGE (V)

INTV SUPPLY VOLTAGE (V)

LOAD CURRENT (mA)

CC

2992 G01

2992 G02

2992 G03

INTV_CCShunt Regulator

Load Regulation

INTV_CCLine Regulation

SENSE Input Current

6.30

6.25

6.20

6.15

6.10

5.5

5.0

4.5

4.0

3.5

3.0

2.5

250

200

150

100

50

+

SENSE

–

SENSE

0

–50

0

10

20

30

40

0

20

40

60

80

100

0

20

40

60

80

100

INTV SHUNT CURRENT (mA)

V

DD

SUPPLY VOLTAGE (V)

SENSE VOLTAGE (V)

CC

2992 G05

2992 G04

2992 G06

ADR Voltage with Current

Source or Sink

SCL/SDAI Loaded Clamp Voltage

vs Load Current

GPIO, SDAO, SDAO Loaded Output

Low Voltage vs Load Current

3.0

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

0.2

0.1

0

6.40

6.30

6.20

6.10

6.00

5.90

5.80

–10

–5

0

5

10

0

2

4

6

8

10

0.01

0.1

1

10

I

(µA)

I

(mA)

OD

I

(mA)

ADR

LOAD

2992 G07

2992 G09

2992 G08

2992f

6

For more information www.linear.com/LTC2992

LTC2992

Typical perForMance characTerisTics

ADC Differential Nonlinearity

ADC Error (GPIO)

ADC Integral Nonlinearity (GPIO)

(GPIO)

0.50

0.25

0

0.3

0.2

0.3

0.2

12–BIT MODE

0.1

MAX ERROR

0.0

TYPICAL

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–0.25

–0.50

0

1024

2048

3072

4096

0

1024

2048

3072

4096

0

1024

2048

3072

4096

CODE

2992 G10

2992 G11

2992 G12

ADC Integral Nonlinearity

(ΔSENSE)

ADC Differential Nonlinearity

(ΔSENSE)

ADC Error (ΔSENSE)

0.75

0.50

0.25

0

2.0

1.0

0.5

12–BIT MODE

MAX ERROR

TYPICAL

0

–0.25

–0.50

–0.75

–1.0

–2.0

–0.5

–1.0

0

1024

2048

3072

4096

0

1024

2048

3072

4096

0

1024

2048

3072

4096

CODE

2992 G13

2992 G14

2992 G15

ADC Input Signal Attenuation

(GPIO)

ADC Input Signal Attenuation

(GPIO, Low Frequencies)

ADC Input Signal Attenuation

(ΔSENSE)

0

–20

0

–20

–40

–60

–80

0

–20

–40

–60

–80

–100

0

62.5

125

187.5

250

0

62.5

125

187.5

250

0

60

120

180

240

FREQUENCY (kHz)

FREQUENCY (Hz)

FREQUENCY (kHz)

2992 G16

2992 G17

2992 G18

2992f

7

For more information www.linear.com/LTC2992

LTC2992

Typical perForMance characTerisTics

ADC Input Signal Attenuation

(ΔSENSE, Low Frequencies)

Current Sense Amplifier Offset

Drift Over Temperature

Current Sense Amplifier Offset

Drift Over Input Common Mode

0

–20

–40

–60

–80

25

15

10

8

INITIAL CALIBRATION DONE AT V = 48V

INITIAL CALIBRATION DONE AT 25°C

NO CALIBRATION THEREAFTER

12–BIT MODE

CM

NO CALIBRATION THEREAFTER

12–BIT MODE

CALIBRATION

OFF

6

CALIBRATION

OFF

CALIBRATION

ON

5

4

–5

2

CALIBRATION

ON

–15

0

–25

–2

0

60

120

180

240

–50 –25

0

25

50

75 100 125

0

25

50

75

100

FREQUENCY (Hz)

TEMPERATURE (°C)

COMMON MODE VOLTAGE (V)

2992 G19

2992 G20

2992 G21

pin FuncTions

2

ADR1,ADR0:I CDeviceAddressInputs.Connectingthese

GPIO4: General Purpose Input/Output (Open Drain).

Configurable to general purpose output, logic input, data

converter input or SMBus alert (ALERT). As ALERT, it is

pulled to ground when a fault occurs to alert the host con-

troller. A fault alert is enabled by setting the corresponding

bit in the ALERT registers as shown in Tables 7, 11, 13

and 15. Tie to ground if unused. See Tables 18 and 19 in

Applications Information section for details.

pins to INTV , GND or leaving the pins open configures

CC

oneofninepossibleaddresses.SeeTable3inApplications

Information section for details.

EXPOSEDPAD:ExposedPadmaybeleftopenorconnected

to device ground. For best thermal performance, connect

to a copper plane with an array of vias.

GND: Device Ground.

INTV : Internal Low Voltage Supply Input/Output. This

CC

GPIO1, GPIO2: General Purpose Input/Output (Open

Drain). Configurable to general purpose output, logic in-

put, or data converter input. Tie to ground if unused. See

Table 18 in Applications Information section for details.

pin is used to power internal circuitry. It can be configured

as a direct input for a low voltage supply, as linear regula-

tor from a higher voltage supply connected to V , or as

DD

a shunt regulator. Connect this pin directly to a 2.7V to

5.8V supply if available. When INTV is powered from an

CC

GPIO3: General Purpose Input/Output (Open Drain).

Configurable to general purpose output, logic input, data

converter input or data ready signal (DATAREADY). As

DATAREADY, it is latched low or pulses low for 16µs or

128µs when any of the ADC’s data becomes available. Tie

to ground if unused. See Table 18 in Applications Informa-

tion section for details.

external supply, connect the V pin to INTV . If V is

DD

CC

DD

connected to a 8V to 100V supply, INTV becomes the

CC

5V output of an internal series regulator that can supply

up to 10mA to external circuitry. For even higher supply

voltages or if a floating topology is desired, INTV can

CC

be used as a 6.2V shunt regulator. Connect the supply to

2992f

8

For more information www.linear.com/LTC2992

LTC2992

pin FuncTions

2

INTV through a resistor or current source that limits the

SDAO (LTC2992-1 only): Inverted I C Bus Data Output.

Open-drain output used for sending data back to the

master controller or acknowledging a write operation.

Data is inverted for convenience of opto-isolation. An

external pull-up resistor or current source is required. The

CC

currenttolessthan35mA. Anundervoltagelockoutcircuit

disables the ADC when the voltage at this pin drops below

2.5V. Connect a bypass capacitor of 0.1µF or greater from

this pin to ground. If an external load is present, for loop

stability, use a bypass capacitor of 1µF or greater. See

Flexible Power Supply section.

2

LTC2992-1cannotbeusedinnonisolatedI Capplications

without additional components.

2

+

SCL: I C Bus Clock Input. Data at the SDAI pin is shifted

SENSE1 , SENSE2 : Supply Voltage and Current Sense

Input. Used as a voltage supply and current sense input

for internal current sense amplifier. The voltage at this pin

is monitored by the onboard ADC with a full-scale input

range of 102.4V. See Figure 19 for recommended Kelvin

connection.

in or out on rising edges of SCL. This pin is driven by an

open-collectoroutputfromamastercontroller.Anexternal

pull-up resistor or current source is required and can be

placed between SCL and V or INTV . The voltage at

SCL is internally clamped to 6.3V typically.

DD

CC

2

–

SDAI: I C Bus Data Input. Used for shifting in address,

SENSE1 , SENSE2 : Current Sense Input. Connect an

+

–

command or data bits. This pin is driven by an open-

collector output from a master controller. An external

pull-up resistor or current source is required and can be

external sense resistor between SENSE and SENSE .

The differential voltage between SENSE and SENSE is

monitored by the onboard ADC with a full-scale sense

voltage of 51.2mV. Tie both SENSE and SENSE together

to a voltage between 0V and 100V if current measurement

is unused.

+

–

+

placed between SDAI and V or INTV . The voltage at

DD

CC

SDAI is internally clamped to 6.3V typically. Tie to SDAO

2

for normal I C operation.

2

SDAO (LTC2992 only): I C Bus Data Output. Open-drain

V :HighVoltageSupplyInput.Thispinpowersaninternal

DD

output used for sending data back to the master controller

or acknowledging a write operation. An external pull-up

resistor or current source is required. Tie to SDAI for

series regulator with input voltages ranging from 3V to

100V and produces 5V at INTV when V is above 8V.

CC

DD

Connect a bypass capacitor of 0.1µF or greater from this

2

normal I C operation.

pin to ground if external load is present on the INTV pin.

CC

See Flexible Power Supply section.

2992f

9

For more information www.linear.com/LTC2992

LTC2992

FuncTional DiagraM

10

9

6

5

11

SDAI

SCL

ADR0

ADR1

SDAO (LTC2992)

SDAO (LTC2992-1)

6.3V

DECODER

–

SENSE1

1

–

40X

V

REF

2.048V

+

2

I C

+

SENSE1

2

12

I1

IADC1

P1

–

SENSE2

16

–

1.23V

–

40X

GPIO1

GPIO2

GPIO3

GPIO4

+

3

14

4

+

I2

IADC2

VADC

+

P2

SENSE2

15

V

735k

15k

735k

15k

DD

S1

S2

G1

G2

G3

G4

8

7

INTV

13

CC

5V

LDO

6.2V

4

I1 + I2

P1 + P2

GND

12

2992 FD

TiMing DiagraM

SDA

t

SP

t

SU, STA

t

SU, DAT

t

BUF

HD, DATO,

HD, DATI

t

HD, STA

t

SU, STO

t

SP

2992 TD

SCL

t

HD, STA

REPEATED START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

2992f

10

For more information www.linear.com/LTC2992

LTC2992

operaTion

The LTC2992 accurately monitors current, voltage and

power of two 0V to 100V supplies. An internal linear

regulatorallowstheLTC2992tooperatedirectlyfroma3V

to 100V rail, or from an external supply voltage between

2.7V and 5.8V. Quiescent current is less than 1.6mA in

normal operation. Enabling shutdown mode via the I C

interface reduces the quiescent current to below 50µA.

The GPIO1 to GPIO4 pins are also general purpose inputs

orgeneralpurposeopen-drainoutputs.Inaddition,GPIO3

may be configured as DATAREADY output while GPIO4

is also an SMBus alert (ALERT) output. DATAREADY in-

dicates availability of the most recent conversion results

from any of the ADCs while ALERT indicates one or more

faults have occurred.

2

There are three onboard 8-/12-bit ADCs as shown in the

Functional Diagram. Each supply’s load current is mea-

sured with an external current sense resistor connected

Onboard memory stores the minimum and maximum

values for each ADC measurement and calculates power

data by digitally multiplying the stored current and voltage

data. When the ADC measured value falls outside its pro-

grammed window thresholds, a fault event is logged and

the ALERT (GPIO4) may optionally pull low. The LTC2992

also calculates the total current and power consumption

of the two monitored supplies.

+

–

between SENSE and SENSE . Internal amplifiers gain up

the voltage drop across the sense resistor for monitoring

bytheIADCs(full-scale51.2mV).VADCisusedforvoltage

measurements and its input is selectively connected to

+

SENSE1 , SENSE2 (full-scale 102.4V) or any of the four

GPIOpins(full-scale2.048V).Eachconversiontakes33ms

for the IADCs and 16ms for the VADC in 12-bit mode. The

conversion time can be shortened by a factor of 16 when

8-bit mode is selected.

2

The LTC2992 includes an I C interface to access the

onboard data registers and to program the alert thresh-

old, configuration and control registers. Two three-state

pins, ADR1 and ADR0, are decoded to allow nine device

addresses (see Table 3). The SDA pin is split into SDAI

(input) and SDAO (output, LTC2992) or SDAO (output,

LTC2992-1)tofacilitateopto-isolation.TieSDAIandSDAO

TheADCscanbeconfiguredtoruncontinuously(continu-

ous scan) or on demand (snapshot mode). In continuous

scan mode, the VADC measures selected voltages of the

six inputs in round robin fashion. See the Applications

Information section for more details. Status bits in the

ADC STATUS register signal new conversion results from

the ADCs have been written into onboard registers.

2

together for normal, nonisolated I C operation.

2992f

11

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

The LTC2992 offers a compact and complete solution to

monitor power from two supply rails in high side and/or

low side current sensing applications. With an input com-

mon mode range of 0V to 100V and a wide input supply

operating voltage range from 2.7V to 100V, this device is

ideal for a wide variety of power management applications

includingautomotive,industrialandtelecominfrastructure.

The basic application circuit shown in Figure 1 provides

monitoringofhighsidecurrents(5.12A/10.24Afull-scale),

input voltages (102.4V full-scale) and two external volt-

ages (2.048V full-scale), all using internal 12-bit ADCs.

ers connected to the GPIO1 and GPIO2 pins. See Flexible

Power Supply section for details.

TheoperationandconversionsequenceoftheADCs, mul-

tiplier operand and VADC input selections are controlled

by the settings in the CTRLA register as shown in Table 1.

The timing sequence for some of these configurations are

shown in Figure 2 (2a to 2f). The timing diagram shown

in Figure 2a illustrates the conversion sequence in the

defaultconfiguration(CTRLA[7:0]=0x00).Uponpower-up

(t ), the IADCs will always measure their corresponding

1

current sense amplifier’s offset (calibration) and then the

loadcurrent(ΔSENSE1/2).Meanwhile,VADCbeginsmea-

Data Converters

+

surement of SENSE1 , SENSE2 , GPIO1, GPIO2, GPIO3

and GPIO4 successively.

The LTC2992 features three Δ∑ A/D converters (ADC)

that can be configured to 8- or 12-bit. The Δ∑ architec-

ture inherently averages input signals and noise during

the measurement period. Two ADCs (IADC1 and IADC2)

At t a new IADC conversion begins. To generate power,

3

the most recent voltage data (S1 at t , S2 at t ) from VADC

2

3

+

is stored in a latch as an operand to the adder as shown

in Figure 3. IMOD1 represents IADC1’s modulator which

converts the load current into a 1-bit data stream. Each

1 in the bitstream adds to the accumulators the voltage

data such that they contain the power values I1 × S1 and

monitor the differential voltages between SENSE and

–

SENSE (ΔSENSE)with51.2mVfull-scaletoallowaccurate

measurement of load currents across low value shunt

+

resistors. The third ADC (VADC) monitors two SENSE

and four GPIO pins with full-scale of 102.4V for SENSE

I2 × S2 at the end of the IADC conversions at t . Voltage

5

and 2.048V for GPIO.

latch content is then updated to the corresponding data

registers. I1 is added to I2 to generate total current and

P1 is added to P2 to generate total power. In the summing

process,theleastsignificantbitoftheresultsaretruncated.

Consequently, the summing results need to be shifted one

bit to the left to restore the correct quantity. Note that the

+

The supply voltage data are derived from SENSE1 and

+

SENSE2 or GPIO1 and GPIO2 depending on the external

+

application circuit. SENSE1 and SENSE2 are selected

by default as these are normally connected to the supply

voltages. In negative supply voltage systems, the supply

voltagescanbemeasuredthroughexternalresistivedivid-

3.3V

R

SENSE1

0.01Ω

V

IN1

OUT1

5A

3V TO 100V

R1

2k

R2

2k

R3

2k

R4

2k

+

–

V

DD

SENSE1 SENSE1

V

DD

SDAI

SDA

MEASURED

VOLTAGE 1

GPIO1

SDAO

SCL

MEASURED

VOLTAGE 2

LTC2992

µP

GPIO2

SCL

ALERT

DATAREADY

GPIO4

GPIO3

INT0

INT1

+

–

INTV

GND ADR0 ADR1 SENSE2 SENSE2

GND

CC

2992 F01

0.1μF

V

IN2

OUT2

10A

0V TO 100V

R

SENSE2

0.005Ω

Figure 1. Dual High Side Power Monitor

2992f

12

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

calculated LSB (see Design Example section) for current

and power of both supplies have to match. Otherwise,

external µP can be used to first compute physical amount

of current and power for each supply and then perform

the summing.

input. Therefore, inputsignalssuchassupplyrailvoltages

with average value that varies at less than 5Hz can be ac-

curately monitored. Otherwise, the input update rate can

be increased by reducing the number of inputs monitored

+

via CTRLA[4:3]. Figure 2c shows only the SENSE pins

being monitored in continuous scan mode with an effec-

tive update rate of 30Hz. The remaining inputs may be

monitored by switching to snapshot mode when needed.

The LTC2992 measures the current sense amplifier’s

input offset to calibrate subsequent IADC measurements.

During offset measurement, IADC cannot capture load

current information. By default, such calibration is done

for every IADC conversion as shown in Figure 2a. In most

applications, the calibration frequency can be reduced by

writing to CTRLA register with its CTRLA[7] bit set to 1.

A one-off calibration is then performed immediately after

A snapshot mode is available to make on-demand mea-

surement of a single selected voltage without power data

+

update (SENSE1 , SENSE2 , GPIO1, GPIO2, GPIO3 or

+

GPIO4) or two selected voltages (either SENSE1 and

SENSE2 ,orGPIO1andGPIO2).Tomakeasnapshotmea-

+

2

the I C write operation as shown in Figure 2b.

surement, write the 3-bit code of the desired voltage input

to CTRLA[2:0] and 01 to CTRLA[6:5]. After completion of

the conversion, the ADCs will halt and the corresponding

VADC by default monitors six input voltages sequentially

as shown in Figure 2a with an update rate of 10Hz for each

Table 1. ADC Configuration Via CTRLA Register

BIT

NAME

OPERATION

CTRLA[7]

Offset Calibration Offset Calibration for Current Measurements

[1] = Calibrate on Demand

[0] = Every Conversion (Default)

CTRLA[6:5]

Measurement

Mode

[11] = Shutdown

[10] = Single Cycle mode

+

The VADC converts SENSE1 , SENSE2 , GPIO1, GPIO2, GPIO3, GPIO4 once and stops. The IADCs stop after

one conversion.

+

P1 = SENSE1 × ΔSENSE1; P2 = SENSE2 × ΔSENSE2

[01] = Snapshot Mode

Snapshot Initializes Conversion on All 3 ADCs Simultaneously.

VADC Converts the Channel(s) per CTRLA[2:0]

[00] = Continuous Scan Mode (Default)

The Selected Channels for VADC are Defined by CTRLA[4:3]

CTRLA[4:3]

CTRLA[2:0]

Voltage Selection CTRLA[4:3]

VADC

P1

P2

for Continuous

11

GPIO1, GPIO2,

GPIO3, GPIO4

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

Scan Mode

10

GPIO1, GPIO2

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

+

01

SENSE1 , SENSE2

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

+

00 (Default)

SENSE1 , SENSE2 ,

GPIO1, GPIO2,

GPIO3, GPIO4

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

Voltage Selection CTRLA[2:0]

VADC

P1

P2

for Snapshot

Mode

111

GPIO1, GPIO2

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

+

110

SENSE1 , SENSE2

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

101

GPIO4

GPIO3

GPIO2

GPIO1

ΔSENSE1/2 without P1/P2 updates

100

011

010

+

001

SENSE2

+

000 (Default)

SENSE1

2992f

13

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

t

4

t

5

t

1

2

3

6

7

8

9

10

16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms

POWER UP

S1 S2 G1 G2 G3 G4 S1 S2 G1

G2

VADC

IADC1

IADC2

CAL

I1 AND P1

CAL

I1 AND P1

CAL

I2 AND P2

(2a) Continuous Scan Mode with Calibration Every Cycle (Default)

+

S1, S2, G1, G2, G3, G4: SENSE1 , SENSE2 , GPIO1, GPIO2, GPIO3, and GPIO4

CAL: Calibration of Current Sense Ampliﬁer

I1, I2: ∆SENSE1, ∆SENSE2

P1, P2: POWER1, POWER2

WRITE 0x80 TO

CTRLA REGISTER

WRITE 0x80 TO

CTRLA REGISTER

S1

S2

G1

G2

G3

G4

S1

S2

S1

S2

G1

G2

VADC

IADC1

IADC2

CAL

I1 AND P1

CAL

I1 AND P1

I2 AND P2

(2b) Continuous Scan Mode with On-Demand Calibration. CTRLA[7:0] = 0x80

WRITE 0x88 TO

CTRLA REGISTER

WRITE 0x20 TO

CTRLA REGISTER

S1

S2

S1

S2

S1

S2

S1

IDLE

VADC

IADC1

IADC2

VADC

IADC1

IADC2

CAL

I1 AND P1

CAL

I1

I2

IDLE

CAL

I2 AND P2

CAL

(2c) Continuous Scan Mode with On-Demand

Calibration. CTRLA[7:0] = 0x88

(2d) Snapshot Mode for Single Voltage. CTRLA[7:0] = 0x20

WRITE 0x40 TO

WRITE 0x27 TO

CTRLA REGISTER

t

1

t

2

t

3

t

4

t

5

t

6

t

7

G1

G2

IDLE

S1

S2

G1

G2

G3

G4

IDLE

VADC

IADC1

IADC2

VADC

IADC1

IADC2

CAL

I1 AND P1

I2 AND P2

IDLE

CAL

I1 AND P1

I2 AND P2

IDLE

2992 F02

(2e) Snapshot Mode for Two Voltages. CTRLA[7:0] = 0x27

(2f) Single Cycle Mode. CTRLA[7:0] = 0x40

Figure 2

2992f

14

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

junction temperature rises above 150°C, and the output

is protected against accidental shorts. Bypass capacitors

DATA

VOLTAGE

LATCH

VADC

of 0.1μF, or greater, at both the V and INTV pins are

DD

CC

+

POWER1

recommendedforoptimaltransientperformance.Notethat

ACCUMULATOR

LATCH

operation with high V voltages can result in significant

DD

IMOD1

power dissipation, and care is required to ensure that the

maximum operating junction temperature stays below

125°C. For improved thermal resistance, use the DFN

package and solder the exposed pad to a large copper

region on the PCB.

2992 F03

Figure 3. POWER1 Generator Blocks

bits in ADC STATUS register (Table 10) are set to indicate

the availability of new data. An alert may be generated at

the end of a snapshot conversion by setting bit AL4[7:6]

in the ALERT4 register (Table 15). To make another snap-

shot measurement, rewrite the CTRLA register. Figure 2d

Figure 4a shows the LTC2992 being used to monitor input

suppliesthatrangefrom4Vto100V.Noseparatesupplyis

needed since V can be connected to either of the input

DD

supplies. To prevent loss of operation from either supply’s

+

failure, V is connected to V and V via diodes. If

DD

IN1

IN2

shows a snapshot operation of SENSE1 with no updates

the LTC2992 is used to monitor input supplies of 0V to

100V, it can derive power from a wide range separate sup-

to power data since only single voltage is selected while

Figure 2e shows combo snapshot operation of GPIO1 and

GPIO2 with new power data.

ply connected to the V pin as shown in Figure 4b. The

DD

R

A single cycle mode allows all six voltages to be measured

SENSE1

BAV23CLT1G

0.01Ω

2

V

IN1

4V TO 100V

once with a single I C command. To initiate such mode,

V

OUT1

+

write 10 to CTRLA[6:5] as shown in Figure 2f. SENSE1 ,

+

SENSE2 are updated together with current and power

values at t . At t the conversions are done and the ADCs

5

7

+

–

V

DD

SENSE1 SENSE1

are halted.

INTV

CC

2

C2

LTC2992

IfthereisanextendedperiodofI Ccommunicationbetween

the LTC2992 and the controller, some of the ADC result

GND

+

–

SENSE2 SENSE2

2

may be lost. This is because during the I C communica-

tion, the ADCs are prevented from updating the internal

registers to avoid corrupting the data. This problem can

be overcome by breaking the I C communication into

blocks of less than one conversion period (16.4ms for

12-bit mode and 1ms for 8-bit mode).

V

IN2

4V TO 100V

V

OUT2

R

SENSE2

0.005Ω

2992 F04a

2

(4a) Derives Power from the Supplies Being Monitored

R

SENSE1

0.01Ω

V

IN1

Flexible Power Supply

V

OUT1

0V TO 100V

TheLTC2992canbeexternallyconfiguredtoderivepower

from a wide range of supplies. The LTC2992 includes an

onboard linear regulator to power the low voltage inter-

+

–

SENSE1 SENSE1

V

3V TO 100V

DD

INTV

CC

LTC2992

C2

nal circuitry connected to the INTV pin from high V

CC

DD

GND

+

–

SENSE2 SENSE2

voltages. The linear regulator operates with V voltages

DD

from 3V to 100V, and a shunt regulator is available for

voltages above 100V. The linear regulator produces a 5V

V

IN2

V

OUT2

0V TO 100V

R

SENSE2

0.005Ω

2992 F04b

output capable of supplying 10mA at the INTV pin when

CC

(4b) Derives Power from a Separate Wide Range Supply

V

is greater than 8V. The regulator is disabled when the

DD

2992f

15

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

R

SENSE1

MBR10100

0.01Ω

V

IN1

RTN1

RTN

V

OUT1

0V TO 100V

MBR10100

+

–

SENSE1 SENSE1

RTN2

V

DD

2.7V TO 5.8V

R8

R9

1M

LTC2992

INTV

V

CC

DD

INTV

CC

GPIO1

GND

C2

+

–

SENSE2 SENSE2

GPIO2

GND

LTC2992

V

IN2

0V TO 100V

R10

20k

R11

20k

V

OUT2

–

+

–

+

R

SENSE1 SENSE1

SENSE2 SENSE2

SENSE2

2992 F04c

0.005Ω

(4c) Derives Power from a Separate Low Voltage Supply

MBR10100

V

IN2

–5V TO –100V

+/–

SENSE pins can be biased independently of the part’s

R

SENSE2

0.01Ω

MBR10100

supply voltage. Alternatively, if a low voltage supply is

V

5A

IN1

–5V TO –100V

OUT

present it can be connected to the INTV pin, as shown

CC

R

SENSE1

0.01Ω

2992 F05b

inFigure4c, tominimizeon-chippowerdissipation. When

(5b) Derives Power from the Supply Monitored in a Low

Side Current Sense Topology

INTV is powered from a separate supply, connect V

CC

DD

to INTV .

CC

R

SENSE1

TOP LAYER

MBR10100

R

SENSE2

0.01Ω

V

IN1

0V TO 100V

V

OUT1

V

IN2

+

–

R

SHUNT

SENSE1 SENSE1

> 100V

INTV

CC

BOTTOM LAYER

V

DD

LTC2992

C2

GND

+

–

SENSE2 SENSE2

V

OUT

V

IN2

0V TO 100V

V

OUT2

R

SENSE2

0.005Ω

2992 F05a

(5a) Derives Power Through a Low Side Shunt

Regulator in a High Side Current Sense Topology

V

IN1

2992 F05c

MBR10100

R

SENSE1

Figure5ashowsahighsiderail-to-railpowermonitorwhich

derives power from a separate supply greater than 100V.

(5c) Recommended Layout for Figure 5b’s SENSE Pins

Connection

The voltage at INTV is clamped at 6.3V above ground in

CC

a low side shunt regulator configuration to power the part.

+

(V ) close to the SENSE terminal of the sense resistors

OUT

Indualfeed,lowsidepowermonitorapplications,thedevice

ground and the current sense inputs are connected to the

diode-ORedoutputoftheinputsupplies’negativeterminal

with a wide track to prevent excessive potential difference

+

between the SENSE pins when load current is supplied

entirely by V or V

.

IN1

IN2

–

as shown in Figure 5b. Note that the SENSE pins operate

at a voltage more negative than the device ground. It is

Supply Undervoltage Lockout

+

highly recommended that the SENSE pins be operating

2

During power-up, the internal I C logic and the ADCs

are enabled when either V or INTV rises above its

at as close to device ground potential as possible so that

–

DD

CC

at full-scale the SENSE pins are limited to 80mV below

under-voltage lockout threshold (2.7V for V and 2.5V

DD

device ground for accurate measurements. A recom-

mended layout for Figure 5b’s SENSE pins connection

is shown in Figure 5c. Layout the common connection

for INTV typically). During power-down, the ADCs are

CC

disabled when V and INTV fall below their respective

DD

CC

2992f

16

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

undervoltagelockoutthresholds.IfV orINTV remains

Configuring the GPIO Pins

DD

CC

2

abovetheirtypical2.1VI Cresetthreshold,theinternalI C

The LTC2992 has four GPIO pins configurable through

the GPIO IO CONTROL register (Table 18) to be used as

general purpose input/output pins. By configuring the

CTRLA register, the voltage at the four GPIO pins can

be measured by the VADC. GPIO1 through GPIO4 have

comparators monitoring the voltage on these pins with a

threshold of 1.23V typically, the results of which may be

read from bits GS[3:0] in the GPIO STATUS register, as

showninTable17.Analertmaybegenerated,whenGPIO1,

GPIO2 or GPIO3 cross the comparator threshold voltage

(1.23V typical), by setting bits AL4[3:1], respectively, in

the ALERT4 register.

logicretainsthestatebeforepower-down.IfV orINTV

DD

CC

is then increased as in a normal power-up, the ADCs will

run according to CTRLA register’s setting at that point in

2

time. The internal I C logic is reset when V and INTV

DD

CC

2

fall below their respective I C reset thresholds.

Shutdown Mode

The LTC2992 includes a low quiescent current shutdown

mode,controlledbybitsCTRLA[6:5]intheCTRLAregister

(Table1).SettingCTRLA[6:5]=11putsthepartinshutdown

mode, powering down the ADC, internal reference and on-

2

board linear regulator. The internal I C bus remains active,

GPIO1, GPIO2, GPIO3 and GPIO4 can be pulled low as

general purpose outputs, which are otherwise high im-

pedance. GPIO3 can also be used as a data ready output

(DATAREADY) to indicate new data from any of the three

ADCs by configuring GIO[5:4] in the GPIO IO CONTROL

register. The output can be in the form of a low pulse with

duration of 16µs or 128µs or a latched low state. The ADC

STATUS register (Table 10) indicates which of the moni-

tored voltages has been recently updated. This register is

cleared-on-read, which will also release the GPIO3 from

its latched low state.

and although the ADR1 and ADR0 pins are disabled, the

2

device will retain the most recently programmed I C bus

address.Allonboardregistersretaintheircontentsandcan

2

be accessed through the I C interface. To re-enable ADC

conversions, reset bit CTRLA[6:5] in the CTRLA register.

The analog circuitry will power up and all registers will

retain their contents.

Theonboardlinearregulatorisdisabledinshutdownmode

to conserve power. If the onboard linear regulator is used

2

to power external I C bus related circuitry such as opto-

2

couplers or pull-ups, I C communication will be lost when

GPIO4 is by default an SMBus alert (ALERT) output that

pulls low when an alert event is present. To pull GPIO4

(ALERT) low in the absence of an alert event, set GC[7]

of the GPIO4 CONTROL register (Table 19). Clearing this

bit will release the GPIO4 (ALERT). GC[7] is set whenever

an alert event occurs. Setting GC[6] will similarly pull

GPIO4 low.

the part is shut down. The LTC2992 would then have to

be reset by cycling its power to come out of shutdown. If

low I mode is not required, ensure 11 cannot be written

Q

to CTRLA[6:5] in the CTRLA register during software de-

velopment. It is recommended that external regulators be

used in such applications if powering down the LTC2992

is desirable. As an added layer of protection against this

scenario, bit CTRLB[4] in the CTRLB register can be set

during system configuration to enable the LTC2992 to

2

I C Reset

2

To avoid the need of power-cycling the part for a reset,

LTC2992 features a software reset which is enabled by

setting CTRLB[0] of CTRLB register (Table 6). This bit

is self-cleared. All internal registers except the present

value data registers are reset to their default states. The

ADCs will sample continuously after reset without any

reconfiguration since this is the default behavior.

automatically exit shutdown mode when the I C lines

are low for more than 33ms (which can be a result of

accidental shutdown of the LTC2992’s linear regulator

2

powering the I C). The user can elect to be alerted of this

event by setting bit AL4[4] in the ALERT4 register (Table

15). Quiescent current drops below 50μA in shutdown

mode with the internal regulator disabled.

2992f

17

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LTC2992

applicaTions inForMaTion

2

Storing Minimum and Maximum Values

if the V and INTV fall below their respective I C logic

DD

CC

reset threshold.

The LTC2992 compares each measurement including the

calculated power with the stored values in the respective

MIN and MAX registers for each parameter (Table 4). If

the new conversion is beyond the stored minimum or

maximum values, the MIN or MAX registers are updated

with the new values. The MIN and MAX registers are

refreshed only when ADCs update the internal registers.

ADC Resolution and Conversion Rate

The resolution of the ADCs can be configured to 8-bit by

setting bit NADC[7] of NADC register (Table 9) through an

I C write command to speed up ADC conversions.

2

Table 2. ADC Resolution and Conversion Rate

2

Writing via I C to the ADC registers does not affect the

RESOLUTION

12-BIT

0

8-BIT

1

MIN and MAX registers. To initiate a new peak hold cycle

for all measurements, set CTRLB[3] of CTRLB register

(Table 6). This bit is self-cleared. For new peak hold cycle

of selective measurement, write all 1’s to its MIN regis-

NADC[7]

+

Conversion Time SENSE , GPIO

16.4ms

65.6ms

25mV

0.5mV

12.5μV

1.02ms

4.1ms

400mV

8mV

ΔSENSE*

+

LSB Step Size

SENSE

GPIO

2

ter and all 0’s to its MAX register via the I C bus. These

registers will be updated when the next respective ADC

conversion is done.

ΔSENSE

200μV

*Snapshot mode

The LTC2992 also includes MIN and MAX threshold reg-

isters (Table 4) for the measured parameters including the

If the resolution is changed while an ADC conversion is

in progress, that conversion will be aborted. In continu-

ous scan mode, a new conversion of the same quantity

will be started with the new resolution and continues in

the original sequence. Otherwise, a new snapshot of one,

two or multiple quantities (single cycle) will take place.

Resetting the peak hold registers by setting CTRLB[3] in

2

calculated power. At power-up or reset by I C command,

the MAX threshold registers are set to all 1’s, and MIN

threshold registers are set to all 0’s, effectively disabling

them. The MIN and MAX threshold registers can be repro-

2

grammed to any desired value via the I C bus.

2

the CTRLB register via I C bus prior to changing the ADC

Fault Alert and Resetting Faults

resolution is recommended to ensure integrity of the peak

hold values.

As soon as a measured quantity falls below the minimum

thresholdorexceedsthemaximumthreshold,theLTC2992

setsthecorrespondingflagintheFAULT1(Table8),FAULT2

(Table 12) and FAULT3 registers (Table 14). Other events

such as GPIO state change have their present status in

the GPIO STATUS (Table 17) register and any fault is

latched in the FAULT4 (Table 16) register. The GPIO4 pin

is pulled low if the appropriate bit in the ALERT1 (Table 7),

ALERT2 (Table 11), ALERT3 (Table 13) and ALERT4 (Table

15) registers is set when the fault occurs. More details

on the alert behavior can be found in the Alert Response

Protocol section.

Theformatfordatain8-bitmodeisleftjustifiedbyfourbits

with respect to the 12-bit’s format as shown in Figure 6.

POWER REGISTER VALUE

MODE

BIT

23:20

Data

19:16

Data

15:12

Data

11:8

Data

7:4

Data

0x0

3:0

Data

0x0

12-bit

8-bit

VOLTAGE/CURRENT REGISTER VALUE

BIT

MODE

15:12

Data

11:8

Data

7:4

Data

0x0

3:0

0x0

An active fault indication can be reset by writing zeros

to the corresponding FAULT register bits or setting bit

CTRLB[5] in the CTRLB register. If bit CTRLB[5] is set,

reading the fault register will cause the corresponding

register to reset. All FAULT register bits are also cleared

12-bit

8-bit

Figure 6. Data Format in 12-Bit and 8-Bit Mode

2992f

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LTC2992

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ADC Status and Data Ready Signal

2. If adjacent GPIO pins have to be used, then decouple

the analog signal to device ground near the GPIO pin

with an external capacitor. Typically, a capacitance of

0.1µF should suffice.

ADC STATUS register (Table 10) indicates availability of

new measurement results in the internal registers and is

2

reset after it is read via I C bus. Details on configuring

GPIO3 as DATAREADY can be found in Configuring the

GPIOPinssection.ToillustratethebehaviorofDATAREADY

as new data becomes available, an example in which the

ADCs are continuously converting is shown in Figure 7.

GPIO3 is initially configured to output a 16µs low pulse

3. Shield the sensitive signal with ground.

4. In a multi-layer PCB, the sensitive signal should be

routed mostly sandwiched between two ground layers

and exit next to the part for connection to the pin.

AlayoutexampleisgiveninLayoutConsiderationssection

for two-layered board design.

with new data as is seen at t and t . As S1 and S2 data

4

5

are updated together with I1 and I2 at t , no GPIO3 pulse

5

is seen at t and t . GPIO3 is then reconfigured to latch

2

3

I C Interface

low with new data—this happens at t . GPIO3 is released

6

2

TheLTC2992includesanI C/SMBus-compatibleinterface

from its latched state when an I C read command to ADC

toprovideaccesstotheonboardregisters. Figure8shows

STATUS register is done.

2

a general data transfer format using the I C bus.

Crosstalk Mitigation

The LTC2992 is a read/write slave device and supports the

SMBus read byte, write byte, read word and write word

protocols. The LTC2992 also supports extended read

and write commands that allow reading or writing more

than two bytes of data. When using the read/write word

or extended read and write commands, the bus master

issues an initial register address and the internal register

address pointer automatically increments by 1 after each

byte of data is read or written. After the register address

reaches 0x97, it will roll over to 0x00 and continue incre-

menting. A STOP condition resets the register address

pointerto0x00.Thedataformatsfortheabovecommands

are shown in Figure 8 through Figure 14. Note that only

The GPIO pins are general purpose pins that can be used

tomonitordigitaloranalogsignals.Evenwithanaveraging

architecture of the Δ∑ ADCs, crosstalk may still be prob-

lematic if an application requires monitoring of precision

analogsignalsandnoisydigitalsignalswiththeGPIOpins.

To preserve measurement accuracy of the analog signals,

a few measures can be taken:

1. Physically separate the clean and noisy signals. For ex-

ample, thecleansignalmaybemonitoredwithGPIO1/3

while the noisy signal is monitored with GPIO2/4 on

the other side of the part.

POWER UP

t

5

t

8

1

2

3

4

6

7

VADC

IADC1

IADC2

S1

S2

G1

G2

G3

G4

S1

S2

CAL

I1 AND P1

I2 AND P2

CAL

I1 AND P1

I2 AND P2

WRITE

READ

REG: 0x32

DATA: 0x00

READ

REG: 0x32

DATA: 0x00

WRITE

REG: 0x96

DATA: 0x33

READ

REG: 0x32

DATA: 0xFF

2

I C BUSES

REG: 0x96

IDLE

DATA: 0x13

GPIO3

2992 F07

16µs PULSE

Figure 7. Configuring GPIO3 as DATAREADY

2992f

19

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LTC2992

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the read byte command is available to the 0xE7 and 0xE8

(MFR_SPECIAL_ID) registers (Table 4).

to several LTC2992s simultaneously, regardless of their

individualaddresssettings.TheLTC2992willalsorespond

to the standard SMBus ARA address (0001100)b if the

GPIO4 (ALERT) pin is asserted. See the Alert Response

Protocol section for more details. The LTC2992 will not

respond to the ARA address if no alerts are pending.

2

I C Device Addressing

2

Nine distinct I C bus addresses are configurable using

the three-state pins ADR0 and ADR1, as shown in Table

3. ADR0 and ADR1 should be tied to INTV , to GND, or

CC

Start and Stop Conditions

left floating (NC) to configure the lower four address bits.

During low power shutdown, the address select state

is latched into memory powered from standby supply.

Address bits a6, a5 and a4 are permanently set to 110

and the least significant bit is the R/W bit. In addition, all

LTC2992 devices will respond to a common mass write

address (1100110)b; this allows the bus master to write

2

When the I C bus is idle, both SCL and SDA are in the high

state. A bus master signals the beginning of a transmis-

sion with a START condition by transitioning SDA from

high to low while SCL stays high. When the master has

finished communicating with the slave, it issues a STOP

SDA

SCL

a6 - a0

1 - 7

b7 - b0

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

2992 F08

Figure 8. General Data Transfer Over I²C

S

ADDRESS W A

COMMAND

A

DATA

A

P

S

ADDRESS W A

COMMAND

A

DATA

b7:b0

A

DATA

b7:b0

A

P

1 1 0 a3:a0

0

b7:b0

0

1 1 0 a3:a0

0

b7:b0

0

b7:b0

0

2992 F09

2992 F10

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH) S: START CONDITION

R: READ BIT (HIGH) P: STOP CONDITION

W: WRITE BIT (LOW)

Figure 10. Serial Bus SDA Write Word Protocol

Figure 9. Serial Bus SDA Write Byte Protocol

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

DATA

A

DATA

A

...

DATA

A

P

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

P

0

b7:b0

0

b7:b0

0

b7:b0

0

...

b7:b0

0

b7:b0

0

1 1 0 a3:a0

1

0

b7:b0

1

2992 F11

2992 F12

Figure 11. Serial Bus SDA Write Page Protocol

Figure 12. Serial Bus SDA Read Byte Protocol

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

A

P

0

b7:b0

0

1 1 0 a3:a0

1

0

b7:b0

0

b7:b0

1

2992 F13

Figure 13. Serial Bus SDA Read Word Protocol

S

ADDRESS W A

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

...

DATA

A

P

1 1 0 a3:a0

0

b7:b0

0

1 1 0 a3:a0

1

0

b7:b0

0

b7:b0

...

b7:b0

1

2992 F14

Figure 14. Serial Bus SDA Read Page Protocol

2992f

20

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LTC2992

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condition by transitioning SDA from low to high while SCL

stays high. The bus is then free for another transmission.

bytes will be acknowledged by the LTC2992, the register

address pointer will automatically increment by one, and

data will be written as previously stated. The write opera-

tion terminates and the register address pointer resets to

0x00 when the master sends a STOP condition.

Stuck-Bus Reset

2

TheLTC2992I Cinterfacefeaturesastuck-busresettimer

to prevent it from holding the bus lines low indefinitely if

the SCL signal is interrupted during a transfer. The timer

starts when either SCL or SDAI is low, and resets when

both SCL and SDAI are pulled high. If either SCL or SDAI

are low for over 33ms, the stuck-bus timer will expire, and

Read Protocol

The master begins a read operation with a START condi-

tion followed by the 7-bit slave address and the R/W bit

set to zero. After the addressed LTC2992 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

read.TheLTC2992acknowledgesthisandthenlatchesthe

command byte into its internal register address pointer.

The master then sends a repeated START condition fol-

lowed by the same 7-bit address with the R/W bit now set

to 1. The LTC2992 acknowledges and sends the contents

of the requested register. The transmission terminates

when the master sends a STOP condition. If the master

acknowledges the transmitted data byte, as in a read word

command, the LTC2992 will send the contents of the next

register. If the master keeps acknowledging, the LTC2992

will keep incrementing the register address pointer and

sending out data bytes. The read operation terminates

and the register address pointer resets to 0x00 when the

master sends a STOP condition.

2

theinternalI CinterfaceandtheSDAOpinpull-downlogic

will be reset to release the bus. Normal communication

will resume at the next START command.

Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave to indicate that the last byte of

data was received. The master always releases the SDA

lineduringtheacknowledgeclockpulse.TheLTC2992will

pulltheSDAlinelowonthe9thclockcycletoacknowledge

receipt of the data. If the slave fails to acknowledge by

leaving SDA high, then the master can abort the transmis-

sion by generating a STOP condition. When the master is

receivingdatafromtheslave,themastermustacknowledge

the slave by pulling down the SDA line during the 9th clock

pulse to indicate receipt of a data byte. After the last byte

has been received by the master, it will leave the SDA line

high (not acknowledge) and issue a STOP condition to

terminate the transmission.

Alert Response Protocol

When any of the fault bits in the fault registers (FAULT1,

FAULT2, FAULT3 and FAULT4) are set, a bus alert is gener-

ated if the appropriate bit in the ALERT1, ALERT2, ALERT3

or ALERT4 registers has been set. This allows the bus

mastertoselectwhichfaultswillgeneratealerts.Atpower-

up, all ALERT registers are cleared (no alerts enabled) and

the GPIO4 (ALERT) pin is high. If an alert is enabled, the

corresponding fault causes the GPIO4 (ALERT) pin to pull

low. The bus master responds to the alert in accordance

with the SMBus alert response protocol by broadcasting

the alert response address (0001100)b, and the LTC2992

replieswithitsownaddressandreleasesitsGPIO4(ALERT)

pin, as shown in Figure 15. The GPIO4 (ALERT) line is also

released if CTRLB[7] is set and the LTC2992 is addressed

(see Table 6) by any message. The GPIO4 (ALERT) signal

Write Protocol

The master begins a write operation with a START condi-

tion followed by the 7-bit slave address and the R/W bit

set to zero. After the addressed LTC2992 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

write. The LTC2992 acknowledges this and then latches

thecommandbyteintoitsinternalregisteraddresspointer.

The master then delivers the data byte and the LTC2992

acknowledges once more and writes the data into the in-

ternal register pointed to by the register address pointer. If

the master continues sending additional data bytes with a

writewordorextendedwritecommand,theadditionaldata

2992f

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LTC2992

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is not pulled low again until the fault registers indicate a

different fault has occurred or the original fault is cleared

and it occurs again. Note that this means repeated or

continuing faults will not generate additional alerts until

the associated fault register bits have been cleared.

open-drain opto-isolators can use the LTC2992 with the

SDAI and SDAO pins separated, as shown in Figure 16.

Connect SDAI to the output of the incoming opto-isolator

with a pull-up resistor to INTV or a local 5V supply; con-

CC

nect SDAO to the cathode of the outgoing opto-isolator

with a current-limiting resistor in series with the anode.

The input and output must be connected together on the

isolatedsideofthebustoallowtheLTC2992toparticipate

ALERT

RESPONSE

ADDRESS

DEVICE

ADDRESS

S

R

A

P

2

0 0 0 1 1 0 0

1

0

a7:a0

1

in I C arbitration. Note that maximum I C bus speed will

generally be limited by the speed of the opto-couplers

used in this application.

2992 F15

Figure 15. Serial Bus SDA Alert Response Protocol

If two or more LTC2992s on the same bus are generat-

ing alerts when the ARA is broadcast, the bus master

will repeat the alert response protocol until the GPIO4

Figure 17 shows an alternate connection for use with low

speedopto-couplersandtheLTC2992-1. Thiscircuituses

a limited-current pull-up on the internally clamped SDAI

pin and clamps the SDAO pin with the input diode of the

2

(ALERT) line is released. Standard I C arbitration causes

the device with the highest priority (lowest address) to

reply first and the device with the lowest priority (highest

address) to reply last.

outgoing opto-isolator, removing the need to use INTV

CC

for biasing in the absence of a separate low voltage sup-

ply. For proper clamping:

2

V

_IN(MAX)– V_SDA,SCL(MIN)

V_IN(MIN)– V_SDA,SCL(MAX)

Opto-Isolating the I C Bus

(1)

≤R4≤

I_SDA,SCL(MAX)

I_SDA,SCL(MIN)

2

Opto-isolating a standard I C device is complicated by the

V_IN(MAX)–5.9V

V_IN(MIN)–6.9V

bidirectional SDA pin. The LTC2992/LTC2992-1 minimize

≤R4≤

2

thisproblembysplittingthestandardI CSDAlineintoSDAI

5mA

0.5mA

(input) and SDAO (output, LTC2992) or SDAO (inverted

output,LTC2992-1).TheSCLisaninput-onlypinanddoes

not require special circuitry to isolate. For conventional

As an example, a supply that operates from 36V to 72V

would require the value of R4 to be between 13k and

58k. The LTC2992-1 must be used in this application

to ensure that SDAO signal polarity is correct. R4 may

2

nonisolated I C applications, use the LTC2992 and tie

2

the SDAI and SDAO pins together to form a standard I C

SDA pin. Low speed isolated interfaces that use standard

3.3V

V

48V

IN

3.3V

5V

R4

R5

R6

R7

R8

R10

R4

20k

R5

5.1k

4.7k 4.7k 0.82k

0.47k 0.47k 2k

R6

0.51k

R7

2k

SCL

LTC2992

V

DD

SDAI

SCL

V

DD

SDAI

LTC2992-1

µP

1/2 MOCD207M

MOCD207M

SDAO

GND

SDA

GND

2992 F17

2992 F16

SDAO

GND

1/2 MOCD207M

Figure 16. Opto-Isolation of a 10kHz I²C Interface Between

LTC2992 and Microcontroller

Figure 17. Opto-Isolation of a 1.5kHz I²C Interface Between

LTC2992-1 and Microcontroller (SCL Omitted for Clarity)

2992f

22

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LTC2992

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be split into two or more series connected units to meet

thermal requirements.

Layout Considerations

A Kelvin connection between the sense resistor R

and

SNS

The LTC2992 can also be used with high speed optocou-

plers with push-pull outputs and inverted logic as shown

inFigure18.Theincomingopto-isolatordrawspowerfrom

the LTC2992 is recommended to achieve accurate current

sensing (Figure 19). The recommended minimum trace

width for 1oz copper foil is 0.02˝ per amp to ensure the

trace stays at a reasonable temperature. Using 0.03˝ per

amp or wider is preferred. Note that 1oz copper exhibits

a sheet resistance of about 530μΩ per square. In very

high current applications where the sense resistor can

dissipate significant power, the PCB layout should include

good thermal management techniques such as extra vias

and wide metal area. 2oz or thicker copper should be

considered for such applications. The trace from sense

INTV , and the data output is connected directly to the

CC

SDAI pin with no pull-up required. Ensure current drawn

does not exceed the 10mA maximum capability of the

INTV pin. The SDAO pin is connected to the cathode of

CC

the outgoing opto-coupler with a current limiting resistor

connected back to INTV . An additional discrete diode

CC

is required at the output of the outgoing opto-coupler to

2

provide the open-drain pull-down that the I C requires.

+

Finally,theinputoftheincomingopto-isolatorisconnected

back to the output as in the low speed case.

resistors to SENSE pins should be as short as possible

to minimize IR drop due to pin current.

V

IN

48V

V

DD

INTV

CC

3.3V

C1

C2

1µF

R5

2k

1/2 ACPL-064L*

1µF

V

CC

LTC2992

R6

2k

R7

2k

GND

BAT54

SDAO

1/2 ACPL-064L*

V

DD

V

CC

µP

SDAI

ISO_SDA

GND

SDA

GND

*:CMOS OUTPUT

2992 F18

Figure 18. Opto-Isolation of a I²C Interface with Low Power, High Speed Opto-Couplers (SCL Omitted for Clarity)

BOTTOM LAYER

V

IN1

V

IN2

TOP LAYER

R

SNS1

R

SNS2

1

2

3

16

15

TO LOAD1

TO LOAD2

14

13

4

17

5

12

GND

6

7

8

11

10

VIA

9

2992 F19

Figure 19. Recommended PCB Layout

2992f

23

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LTC2992

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Design Example

Choose R10,11 = 1MΩ, and R12,13 = 20kΩ to allow a

input voltage measurement range from 0V to 104.4V.

As a design example, consider a –36V to –72V Advanced

2

R11+R13

R13

R10+R12

25.5mV

LSB

TCA system with I C current, voltage and power monitors

Voltage of V

=

• V

=

IN1

GPIO1

(See Figure 20).

25.5mV

The load current is either supplied by V

or V

or

IN2

IN1

• V

=

IN2

GPIO2

R12

LSB

both depending on their voltages. Choose similar values

for R

and R

in accordance to the following

SENSE1

SENSE2

An error term can be added to the voltage results above

to account for the voltage drop across the N-channel

MOSFET and sense resistor:

equation:

V

FS(ΔSENSE1,2)

R_SENSE1,2

<

I_LOAD(MAX)

V

= ΔV of FDS3672 + ΔSENSE

DS

ERROR

51.2mV

The maximum error occurs when the load current is at

its maximum of 5A. Using the above equation, this works

out to be 160mV with 110mV contribution (see below for

calculation)fromtheFDS3672.Withoutcompensation,this

=10.24mΩ

5A

R

and R

are chosen to be 10mΩ.

12.5µV

SENSE1

SENSE2

would cause measurement error of 0.45% for V = 36V.

IN

Current of V or V

=

= 1.25mA /LSB

IN1

IN2

R_SENSE

LTC4354 and LTC4355 low side and high side ideal diode-

OR controllers drive N-channel MOSFETs to minimize the

diode power consumption. The 100V, N-channel MOSFET

Total Current = 2.5mA/LSB

FDS3672 in the SO-8 package with R

= 22mΩ

DS(ON)

We also have to consider the power dissipated in the

sense resistors which can be calculated with the follow-

ing equation:

(max) is chosen as switches. The maximum voltage drop

across it is:

2

ΔV = 5A × 22mΩ = 110mV

DS

P = (I

) • R

LOAD

2

SENSE

Since external resistive dividers are used for supply volt-

age measurement, CTRLA register 0x00 is set to 0x10 to

continuously monitor GPIO1 and GPIO2.

P = (5A) • 10mΩ = 0.25W

Use at least 0.5W rated sense resistors to ensure thermal

compliance.

POWER1 = V • Current of V

IN1

Next, select the resistive dividers that measure the supply

POWER1 = 25.5mV • 1.25mA/LSB = 31.875µW/LSB

POWER2 = 31.875µW/LSB

voltages V and V

Note that the voltage drop across

IN1

IN2.

the N-channel MOSFET and sense resistor is not included

in the derivation for the following equations.

Total Power = 63.75µW/LSB

V

FS(GPIO1)

R12

R13

R11+R13

FS(GPIO2)

<

,

<

R10+R12

V

IN1

IN2

R12

R10+R12

R13

2.048V

72V

2.048V

= 0.028

<

R11

+

R13

72V

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Table 3. Device Addressing

ADDRESS

DESCRIPTION

HEX DEVICE

ADDRESS*

BINARY DEVICE ADDRESSING

ADDRESS PINS

7-BIT

66

8-BIT

CC

19

a6

1

0

1

a5

1

0

1

a4

0

a3

0

a2

1

0

1

a1

1

0

1

0

1

0

1

a0

0

1

0

1

0

1

0

1

0

1

R/W

0

ADR1

X

ADR0

X

Mass Write

Alert Response

0C

67

1

X

0

1

2

3

4

5

6

7

8

CE

0

H

L

68

D0

D2

D4

D6

D8

DA

DC

DE

1

0

NC

H

69

1

0

H

6A

6B

6C

6D

6E

1

0

NC

L

NC

L

1

0

1

0

H

1

0

H

NC

L

1

0

L

6F

1

0

L

H = Tie to INTV , NC = No Connect = Open, L = Tie to GND, X = Don’t Care

CC

*8-Bit hexadecimal address with LSB R/W bit = 0

7-Bit hexadecimal address with MSB a7 = 0

Table 4. Register Addresses and Contents

REGISTER

READ/

WRITE

NUMBER

OF BYTES* DEFAULT

REGISTER NAME

ADDRESS

DESCRIPTION

CTRLA

0x00

Operation Control Register A

Operation Control Register B

R/W

1

3

0x00

NA

CTRLB

0x01

ALERT1

FAULT1

NADC

0x02

Selects Which CHANNEL 1 Faults Generate Alerts

CHANNEL 1 Fault Log

0x03

0x04

ADC Resolution

P1

0x05-0x07

0x08-0x0A

0x0B-0x0D

0x0E-0x10

POWER1 Data

MAX P1

MIN P1

Maximum POWER1 Data

NA

Minimum POWER1 Data

NA

MAX P1

THRESHOLD

Maximum POWER1 Threshold to Generate Alert

0xFFFFFF

MIN P1

THRESHOLD

0x11-0x13

Minimum POWER1 Threshold to Generate Alert

R/W

3

0x000000

I1

0x14-0x15

0x16-0x17

0x18-0x19

0x1A-0x1B

ΔSENSE1 Data

R/W

2

NA

MAX I1

MIN I1

Maximum ΔSENSE1 Data

NA

Minimum ΔSENSE1 Data

NA

MAX I1

THRESHOLD

Maximum ΔSENSE1 Threshold to Generate Alert

0xFFF0

MIN I1

THRESHOLD

0x1C-0x1D

Minimum ΔSENSE1 Threshold to Generate Alert

R/W

2

0x0000

+

S1

0x1E-0x1F

0x20-0x21

0x22-0x23

SENSE1 Data

R/W

2

NA

+

MAX S1

MIN S1

Maximum SENSE1 Data

+

Minimum SENSE1 Data

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Table 4. Register Addresses and Contents (continued)

REGISTER

READ/

WRITE

NUMBER

OF BYTES DEFAULT

REGISTER NAME

ADDRESS

DESCRIPTION

+

MAX S1

THRESHOLD

0x24-0x25

Maximum SENSE1 Threshold to Generate Alert

R/W

2

0xFFF0

+

MIN S1

THRESHOLD

0x26-0x27

Minimum SENSE1 Threshold to Generate Alert

R/W

2

0x0000

G1

0x28-0x29

0x2A-0x2B

0x2C-0x2D

0x2E-0x2F

GPIO1 Data

R/W

2

NA

MAX G1

MIN G1

Maximum GPIO1 Data

NA

Minimum GPIO1 Data

NA

MAX G1

THRESHOLD

Maximum GPIO1 Threshold to Generate Alert

0xFFF0

MIN G1

THRESHOLD

0x30-0x31

Minimum GPIO1 Threshold to Generate Alert

R/W

2

0x0000

ADC STATUS

RESERVED

ALERT2

FAULT2

0x32

0x33

ADC Status Information

R

1

3

NA

Manufacturer Reserved

R

0x00

NA

0x34

Selects Which CHANNEL 2 Faults Generate Alerts

CHANNEL 2 Fault Log

R/W

R

0x35

RESERVED

P2

0x36

Manufacturer Reserved

0x37-0x39

0x3A-0x3C

0x3D-0x3F

0x40-0x42

POWER2 Data

R/W

MAX P2

MIN P2

Maximum POWER2 Data

NA

Minimum POWER2 Data

NA

MAX P2

THRESHOLD

Maximum POWER2 Threshold to Generate Alert

0xFFFFFF

MIN P2

THRESHOLD

0x43-0x45

Minimum POWER2 Threshold to Generate Alert

R/W

3

0x000000

I2

0x46-0x47

0x48-0x49

0x4A-0x4B

0x4C-0x4D

ΔSENSE2 Data

R/W

2

NA

MAX I2

MIN I2

Maximum ΔSENSE2 Data

NA

Minimum ΔSENSE2 Data

NA

MAX I2

THRESHOLD

Maximum ΔSENSE2 Threshold to Generate Alert

0xFFF0

MIN I2

THRESHOLD

0x4E-0x4F

Minimum ΔSENSE2 Threshold to Generate Alert

R/W

2

0x0000

+

S2

0x50-0x51

0x52-0x53

0x54-0x55

0x56-0x57

SENSE2 Data

R/W

2

NA

+

MAX S2

MIN S2

Maximum SENSE2 Data

NA

+

Minimum SENSE2 Data

NA

+

MAX S2

THRESHOLD

Maximum SENSE2 Threshold to Generate Alert

0xFFF0

+

MIN S2

THRESHOLD

0x58-0x59

Minimum SENSE2 Threshold to Generate Alert

R/W

2

0x0000

G2

0x5A-0x5B

0x5C-0x5D

0x5E-0x5F

0x60-0x61

GPIO2 Data

R/W

2

NA

MAX G2

MIN G2

Maximum GPIO2 Data

NA

Minimum GPIO2 Data

NA

MAX G2

THRESHOLD

Maximum GPIO2 Threshold to Generate Alert

0xFFF0

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Table 4. Register Addresses and Contents

REGISTER

(continued)

READ/

WRITE

NUMBER

OF BYTES DEFAULT

REGISTER NAME

ADDRESS

DESCRIPTION

MIN G2

THRESHOLD

0x62-0x63

Minimum GPIO2 Threshold to Generate Alert

R/W

2

0x0000

G3

0x64-0x65

0x66-0x67

0x68-0x69

0x6A-0x6B

GPIO3 Data

R/W

2

NA

MAX G3

MIN G3

Maximum GPIO3 Data

NA

Minimum GPIO3 Data

NA

MAX G3

THRESHOLD

Maximum GPIO3 Threshold to Generate Alert

0xFFF0

MIN G3

THRESHOLD

0x6C-0x6D

Minimum GPIO3 Threshold to Generate Alert

R/W

2

0x0000

G4

0x6E-0x6F

0x70-0x71

0x72-0x73

0x74-0x75

GPIO4 Data

R/W

2

NA

MAX G4

MIN G4

Maximum GPIO4 Data

NA

Minimum GPIO4 Data

NA

MAX G4

THRESHOLD

Maximum GPIO4 Threshold to Generate Alert

0xFFF0

MIN G4

THRESHOLD

0x76-0x77

Minimum GPIO4 Threshold to Generate Alert

R/W

2

0x0000

ISUM

0x78-0x79

0x7A-0x7B

0x7C-0x7D

0x7E-0x7F

(ΔSENSE1 + ΔSENSE2) Data

R/W

2

NA

MAX ISUM

MIN ISUM

Maximum (ΔSENSE1 + ΔSENSE2) Data

Minimum (ΔSENSE1 + ΔSENSE2) Data

Maximum (ΔSENSE1 + ΔSENSE2) Threshold to Generate Alert

NA

MAX ISUM

THRESHOLD

0xFFF0

MIN ISUM

THRESHOLD

0x80-0x81

Minimum (ΔSENSE1 + ΔSENSE2) Threshold to Generate Alert

R/W

2

0x0000

PSUM

0x82-0x84

0x85-0x87

0x88-0x8A

0x8B-0x8D

(POWER1 + POWER2) Data

R/W

3

NA

MAX PSUM

MIN PSUM

Maximum (POWER1 + POWER2) Data

Minimum (POWER1 + POWER2) Data

Maximum (POWER1 + POWER2) Threshold to Generate Alert

NA

MAX PSUM

THRESHOLD

0xFFFFFF

MIN PSUM

0x8E-0x90

0x91

Minimum (POWER1 + POWER2) Threshold to Generate Alert

R/W

3

1

0x000000

0x00

THRESHOLD

ALERT3

Selects Which GPIO or Total Current/Power Faults Generate

Alerts

FAULT3

0x92

0x93

0x94

0x95

0x96

GPIO and Total Current/Power Fault Log

Selects Which Additional Faults Generate Alerts

Additional Fault Log

R/W

R

1

0x00

NA

ALERT4

FAULT4

GPIO STATUS

GPIO Status Information

GPIO IO

CONTROL

GPIO1,2,3 Input/Output Control Command

R/W

0x03

GPIO4 CONTROL

0x97

0xE7

GPIO4 Control Command

R/W

R

1

0x00

MFR_SPECIAL_ID

MSB

Manufacturer Special ID MSB Data

MFR_SPECIAL_ID

LSB

0xE8

Manufacturer Special ID LSB Data

R

1

0x62

* For the 2-/3-byte data registers, the MSB value is at the lowest address

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Table 5. CTRLA Register (0x00) – Read/Write

BIT

NAME

OPERATION

CTRLA[7]

Offset Calibration Offset Calibration for Current Measurements

[1] = Calibrate on Demand

[0] = Every Conversion (Default)

CTRLA[6:5]

Measurement

Mode

[11] = Shutdown

[10] = Single Cycle mode

+

The VADC converts SENSE1 , SENSE2 , GPIO1, GPIO2, GPIO3, GPIO4 once and stops. The IADCs stop after

one conversion.

+

P1 = SENSE1 × ΔSENSE1; P2 = SENSE2 × ΔSENSE2

[01] = Snapshot Mode

Snapshot Initializes Conversion on All 3 ADCs Simultaneously.

VADC Converts the Channel(s) per CTRLA[2:0]

[00] = Continuous Scan Mode (Default)

The Selected Channels for VADC are Defined by CTRLA[4:3]

CTRLA[4:3]

Voltage Selection CTRLA[4:3]

VADC

P1

P2

for Continuous

11

GPIO1, GPIO2,

GPIO3, GPIO4

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

Scan Mode

10

GPIO1, GPIO2

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

+

01

SENSE1 , SENSE2

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

+

00 (Default)

SENSE1 , SENSE2 ,

GPIO1, GPIO2,

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

GPIO3, GPIO4

CTRLA[2:0]

Voltage Selection CTRLA[2:0]

VADC

P1

P2

for Snapshot

111

GPIO1, GPIO2

GPIO1 × ΔSENSE1

GPIO2 × ΔSENSE2

Mode

+

110

SENSE1 , SENSE2

SENSE1 × ΔSENSE1

SENSE2 × ΔSENSE2

101

GPIO4

GPIO3

GPIO2

GPIO1

ΔSENSE1/2 without P1/P2 updates

100

011

010

+

001

SENSE2

+

000 (Default)

SENSE1

Table 6. CTRLB Register (0x01) – Read/Write

BIT

NAME

OPERATION

CTRLB[7]

ALERT Clear Enable

Clear ALERT if Device is Addressed by the Master

[1] = Enable

[0] = Disable (Default)

CTRLB[6]

CTRLB[5]

Reserved

Always Returns 0, Not Writable

Cleared on Read Control

FAULT Registers Cleared on Read

[1] = Cleared on Read

[0] = Registers Not Affected by Reading (Default)

CTRLB[4]

CTRLB[3]

Stuck Bus Timeout Auto Wake Up

Peak Hold Values Reset

Allows Part to Exit Shutdown Mode when Stuck Bus Timer is Reached

[1] = Enable

[0] = Disable (Default)

Reset of Min and Max Registers

[1] = Reset All Min and Max Registers

[0] = Disable Reset of Min and Max Registers (Default)

CTRLB[2:1]

CTRLB[0]

Reserved

Reset

Always Returns 00, Not Writable

[1] = Reset All Registers

[0] = Disable Reset (Default)

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Table 7. ALERT1 Register (0x02) – Read/Write

BIT

NAME

OPERATION

AL1[7]

Maximum POWER1 Alert

Enables Alert When POWER1 > Maximum POWER1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

AL1[6]

AL1[5]

AL1[4]

AL1[3]

AL1[2]

AL1[1]

AL1[0]

Minimum POWER1 Alert

Maximum ΔSENSE1 Alert

Minimum ΔSENSE1 Alert

Enables Alert When POWER1 < Minimum POWER1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When ΔSENSE1 > Maximum ΔSENSE1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When ΔSENSE1 < Minimum ΔSENSE1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

+

Maximum SENSE1 Alert

Enables Alert When SENSE1 > Maximum SENSE1 Threshold

[1] = Enable Alert

[0] = Disable Alert(Default)

+

Minimum SENSE1 Alert

Enables Alert When SENSE1 < Minimum SENSE1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Maximum GPIO1 Alert

Minimum GPIO1 Alert

Enables Alert When GPIO1 > Maximum GPIO1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When GPIO1 < Minimum GPIO1 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Table 8. FAULT1 Register (0x03) – Read/Write

BIT

NAME

OPERATION

F1[7]

POWER1 Overvalue Fault

POWER1 > Maximum POWER1 Threshold

[1] = POWER1 Overvalue Fault Occurred

[0] = No POWER1 Overvalue Fault Occurred (Default)

F1[6]

F1[5]

F1[4]

F1[3]

F1[2]

F1[1]

F1[0]

POWER1 Undervalue Fault

ΔSENSE1 Overvalue Fault

ΔSENSE1 Undervalue Fault

POWER1 < Minimum POWER1 Threshold

[1] = POWER1 Undervalue Fault Occurred

[0] = No POWER1 Undervalue Fault Occurred (Default)

ΔSENSE1 > Maximum ΔSENSE1 Threshold

[1] = ΔSENSE1 Overvalue Fault Occurred

[0] = No ΔSENSE1 Overvalue Fault Occurred (Default)

ΔSENSE1 < Minimum ΔSENSE1 Threshold

[1] = ΔSENSE1 Undervalue Fault Occurred

[0] = No ΔSENSE1 Undervalue Fault Occurred (Default)

+

SENSE1 Overvalue Fault

SENSE1 > Maximum SENSE1 Threshold

+

[1] = SENSE1 Overvalue Fault Occurred

[0] = No SENSE1 Overvalue Fault Occurred (Default)

+

SENSE1 Undervalue Fault

SENSE1 < Minimum SENSE1 Threshold

+

[1] = SENSE1 Undervalue Fault Occurred

[0] = No SENSE1 Undervalue Fault Occurred (Default)

+

GPIO1 Overvalue Fault

GPIO1 Undervalue Fault

GPIO1 > Maximum GPIO1 Threshold

[1] = GPIO1 Overvalue Fault Occurred

[0] = No GPIO1 Overvalue Fault Occurred (Default)

GPIO1 < Minimum GPIO1 Threshold

[1] = GPIO1 Undervalue Fault Occurred

[0] = No GPIO1 Undervalue Fault Occurred (Default)

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Table 9. NADC Register (0x04) – Read/Write

BIT

NAME

OPERATION

NADC[7]

ADC Resolution

Selects ADC Resolution for All ADCs

[1] = 8-Bit

[0] = 12-Bit (Default)

NADC[6:0]

Reserved

Always Returns 0000000, Not Writable

Table 10. ADC STATUS Register (0x32) – Read Only (Clear-On-Read)

BIT

NAME

OPERATION

AS[7]

IADCs Data Ready

[1] = Ready

[0] = Not ready

AS[6]

VADC Data Ready

[1] = Ready

[0] = Not ready

Check AS[5:0] for the channel information

AS[5]

AS[4]

AS[3]

AS[2]

AS[1]

AS[0]

GPIO4 Data Ready

GPIO3 Data Ready

GPIO2 Data Ready

GPIO1 Data Ready

[1] = New Data Available

[0] = New Data Not Available

[1] = New Data Available

[0] = New Data Not Available

[1] = New Data Available

[0] = New Data Not Available

[1] = New Data Available

[0] = New Data Not Available

+

SENSE2 Data Ready

[1] = New Data Available

[0] = New Data Not Available

+

SENSE1 Data Ready

[1] = New Data Available

[0] = New Data Not Available

Table 11. ALERT2 Register (0x34) – Read/Write

BIT

NAME

OPERATION

AL2[7]

Maximum POWER2 Alert

Enables Alert When POWER2 > Maximum POWER2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

AL2[6]

AL2[5]

AL2[4]

AL2[3]

AL2[2]

AL2[1]

AL2[0]

Minimum POWER2 Alert

Maximum ΔSENSE2 Alert

Minimum ΔSENSE2 Alert

Enables Alert When POWER2 < Minimum POWER2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When ΔSENSE2 > Maximum ΔSENSE2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When ΔSENSE2 < Minimum ΔSENSE2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

+

Maximum SENSE2 Alert

Enables Alert When SENSE2 > Maximum SENSE2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

+

Minimum SENSE2 Alert

Enables Alert When SENSE2 < Minimum SENSE2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Maximum GPIO2 Alert

Minimum GPIO2 Alert

Enables Alert When GPIO2 > Maximum GPIO2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When GPIO2 < Minimum GPIO2 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

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Table 12. FAULT2 Register (0x35) – Read/Write

BIT

NAME

OPERATION

F2[7]

POWER2 Overvalue Fault

POWER2 > Maximum POWER2 Threshold

[1] = POWER2 Overvalue Fault Occurred

[0] = No POWER2 Overvalue Fault Occurred (Default)

F2[6]

F2[5]

F2[4]

F2[3]

F2[2]

F2[1]

F2[0]

POWER2 Undervalue Fault

ΔSENSE2 Overvalue Fault

ΔSENSE2 Undervalue Fault

POWER2 < Minimum POWER2 Threshold

[1] = POWER2 Undervalue Fault Occurred

[0] = No POWER2 Undervalue Fault Occurred (Default)

ΔSENSE2 > Maximum ΔSENSE2 Threshold

[1] = ΔSENSE2 Overvalue Fault Occurred

[0] = No ΔSENSE2 Overvalue Fault Occurred (Default)

ΔSENSE2 < Minimum ΔSENSE2 Threshold

[1] = ΔSENSE2 Undervalue Fault Occurred

[0] = No ΔSENSE2 Undervalue Fault Occurred (Default)

+

SENSE2 Overvalue Fault

SENSE2 > Maximum SENSE2 Threshold

+

[1] = SENSE2 Overvalue Fault Occurred

+

[0] = No SENSE2 Overvalue Fault Occurred (Default)

+

SENSE2 Undervalue Fault

SENSE2 < Minimum SENSE2 Threshold

+

[1] = SENSE2 Undervalue Fault Occurred

+

[0] = No SENSE2 Undervalue Fault Occurred (Default)

GPIO2 Overvalue Fault

GPIO2 Undervalue Fault

GPIO2 > Maximum GPIO2 Threshold

[1] = GPIO2 Overvalue Fault Occurred

[0] = No GPIO2 Overvalue Fault Occurred (Default)

GPIO2 < Minimum GPIO2 Threshold

[1] = GPIO2 Undervalue Fault Occurred

[0] = No GPIO2 Undervalue Fault Occurred (Default)

Table 13. ALERT3 Register (0x91) – Read/Write

BIT

NAME

OPERATION

AL3[7]

Maximum GPIO3 Alert

Enables Alert When GPIO3 > Maximum GPIO3 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

AL3[6]

AL3[5]

AL3[4]

AL3[3]

Minimum GPIO3 Alert

Enables Alert When GPIO3 < Minimum GPIO3 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Maximum GPIO4 Alert

Enables Alert When GPIO4 > Maximum GPIO4 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Minimum GPIO4 Alert

Enables Alert When GPIO4 < Minimum GPIO4 Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Maximum (ΔSENSE1 + ΔSENSE2) Alert

Enables Alert When (ΔSENSE1 + ΔSENSE2) > Maximum (ΔSENSE1 +

ΔSENSE2) Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

AL3[2]

AL3[1]

AL3[0]

Minimum (ΔSENSE1 + ΔSENSE2) Alert

Maximum (POWER1 + POWER2) Alert

Minimum (POWER1 + POWER2) Alert

Enables Alert When (ΔSENSE1 + ΔSENSE2) < Minimum (ΔSENSE1 +

ΔSENSE2) Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When (POWER1 + POWER2) > Maximum (POWER1 +

POWER2) Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

Enables Alert When (POWER1 + POWER2) < Minimum (POWER1 +

POWER2) Threshold

[1] = Enable Alert

[0] = Disable Alert (Default)

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Table 14. FAULT3 Register (0x92) – Read/Write

BIT

NAME

OPERATION

F3[7]

GPIO3 Overvalue Fault

GPIO3 > Maximum GPIO3 Threshold

[1] = GPIO3 Overvalue Fault Occurred

[0] = No GPIO3 Overvalue Fault Occurred (Default)

F3[6]

F3[5]

F3[4]

F3[3]

F3[2]

F3[1]

F3[0]

GPIO3 Undervalue Fault

GPIO3 < Minimum GPIO3 Threshold

[1] = GPIO3 Undervalue Fault Occurred

[0] = No GPIO3 Undervalue Fault Occurred (Default)

GPIO4 Overvalue Fault

GPIO4 > Maximum GPIO4 Threshold

[1] = GPIO4 Overvalue Fault Occurred

[0] = No GPIO4 Overvalue Fault Occurred (Default)

GPIO4 Undervalue Fault

GPIO4 < Minimum GPIO4 Threshold

[1] = GPIO4 Undervalue Fault Occurred

[0] = No GPIO4 Undervalue Fault Occurred (Default)

(ΔSENSE1 + ΔSENSE2) Overvalue Fault

(ΔSENSE1 + ΔSENSE2) Undervalue Fault

(POWER1 + POWER2) Overvalue Fault

(POWER1 + POWER2) Undervalue Fault

(ΔSENSE1 + ΔSENSE2) > Maximum (ΔSENSE1 + ΔSENSE2) Threshold

[1] = Summed Current Overvalue Fault Occurred

[0] = No Summed Current Overvalue Fault Occurred (Default)

(ΔSENSE1 + ΔSENSE2) < Minimum (ΔSENSE1 + ΔSENSE2) Threshold

[1] = Summed Current Undervalue Fault Occurred

[0] = No Summed Current Undervalue Fault Occurred (Default)

(POWER1 + POWER2) > Maximum (POWER1 + POWER2) Threshold

[1] = Summed Power Overvalue Fault Occurred

[0] = No Summed Power Overvalue Fault Occurred (Default)

(POWER1 + POWER2) < Minimum (POWER1 + POWER2) Threshold

[1] = Summed Power Undervalue Fault Occurred

[0] = No Summed Power Undervalue Fault Occurred (Default)

Table 15. ALERT4 Register (0x93) – Read/Write

BIT

NAME

OPERATION

AL4[7]

VADC Data Ready Alert

Alert when VADC Data Ready

[1] = Enable

[0] = Disable (Default)

AL4[6]

IADC Data Ready Alert

Alert when IADCs Data Ready

[1] = Enable

[0] = Disable (Default)

AL4[5]

AL4[4]

Reserved

Always Returns 0, Not Writable

Stuck Bus Time-Out Wakeup Alert

Alert if Part Exits Shutdown Mode After Stuck Bus Timer Expires with CTRLB[4] = 1

[1] = Enable Alert

[0] = Disable Alert (Default)

AL4[3]

AL4[2]

AL4[1]

AL4[0]

GPIO1 Input Alert

GPIO2 Input Alert

GPIO3 Input Alert

Reserved

[1] = Enable Alert

[0] = Disable Alert (Default)

[1] = Enable Alert

[0] = Disable Alert (Default)

[1] = Enable Alert

[0] = Disable Alert(Default)

Always Returns 0, Not Writable

2992f

33

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

Table 16. FAULT4 Register (0x94) – Read/Write

BIT

NAME

OPERATION

F2[7:5]

F4[4]

Reserved

Always Returns 000, Not Writable

Stuck Bus Time-Out Wakeup Fault

With CTRLB[4] = 1

[1] = Part Exited Shutdown Mode After Stuck Bus Timer Expired

[0] = No Stuck Bus Time-Out Wakeup Fault Occurred (Default)

F4[3]

F4[2]

F4[1]

F4[0]

GPIO1 Input Fault

GPIO2 Input Fault

GPIO3 Input Fault

Reserved

[1] = GPIO1 Input was at Alert Level

[0] = GPIO1 Input was not at Alert Level (Default)

Alert Polarity is set in GIO[3] (Table 18)

[1] = GPIO2 Input was at Alert Level

[0] = GPIO2 Input was not at Alert Level (Default)

Alert Polarity is set in GIO[2] (Table 18)

[1] = GPIO3 Input was at Alert Level

[0] = GPIO3 Input was not at Alert Level (Default)

Alert Polarity is set in GIO[1] (Table 18)

Always Returns 0, Not Writable

Table 17. GPIO STATUS Register (0x95) – Read Only

BIT

NAME

OPERATION

GS[7:4]

GS[3]

Reserved

GPIO1 State

Always Returns 0000, Not Writable

[1] = GPIO1 High

[0] = GPIO1 Low

GS[2]

GS[1]

GS[0]

GPIO2 State

GPIO3 State

GPIO4 State

[1] = GPIO2 High

[0] = GPIO2 Low

[1] = GPIO3 High

[0] = GPIO3 Low

[1] = GPIO4 High

[0] = GPIO4 Low

Table 18. GPIO IO CONTROL Register (0x96) – Read/Write

BIT

NAME

OPERATION

GIO[7]

GPIO1 Output

[1] = Pulls Low

[0] = Hi-Z (Default)

GIO[6]

GPIO2 Output

[1] = Pulls Low

[0] = Hi-Z (Default)

GIO[5:4]

GPIO3 Configuration

[11] = Pulls Low when Any of the ADCs Data Becomes Ready, Resets to High

by Reading ADC STATUS Register 0x32

[10] = 128µs Low Pulse when Any of the ADCs Data Becomes Available

[01] = 16µs Low Pulse when Any of the ADCs Data Becomes Available

[00] = General Purpose Input/Output (Default)

GIO[3]

GIO[2]

GIO[1]

GIO[0]

GPIO1 Alert Polarity Configuration

GPIO2 Alert Polarity Configuration

GPIO3 Alert Polarity Configuration

GPIO3 Output

[1] = Alert on GPIO1 Input High

[0] = Alert on GPIO1 Input Low (Default)

[1] = Alert on GPIO2 Input High

[0] = Alert on GPIO2 Input Low (Default)

[1] = Alert on GPIO3 Input High (Default)

[0] = Alert on GPIO3 Input Low

[1] = Pulls Low (Default)

[0] = Hi-Z

2992f

34

For more information www.linear.com/LTC2992

LTC2992

applicaTions inForMaTion

Table 19. GPIO4 CONTROL Register (0x97) – Read/Write

BIT

NAME

OPERATION

GC[7]

Alert Generated

[1] = Alert Generated

[0] = No Alert Generated

2

Latched to 1 when an Alert is generated and can be cleared via I C by writing a 0 to it

or setting CTRLB[7] (Table 6) to 1

GC[6]

GPIO4 Output

Reserved

[1] = Pulls Low

[0] = Hi-Z (Default)

GC[5:0]

Always Returns 000000, Not Writable

Table 20. Register Data Format – Read/Write: ADC, Min/Max ADC, Min/Max ADC Threshold, ISUM, Min/Max ISUM, Min/Max ISUM

Threshold

12-Bit Mode:

BIT(7)

Data(11)

Data(3)

BIT(6)

Data(10)

Data(2)

BIT(5)

Data(9)

Data(1)

BIT(4)

Data(8)

Data(0)

BIT(3)

Data(7)

0

BIT(2)

Data(6)

0

BIT(1)

Data(5)

0

BIT(0)

Data(4)

0

MSB Register

LSB Register

8-Bit Mode:

BIT(7)

Data(7)

0

BIT(6)

Data(6)

0

BIT(5)

Data(5)

0

BIT(4)

Data(4)

0

BIT(3)

Data(3)

0

BIT(2)

Data(2)

0

BIT(1)

Data(1)

0

BIT(0)

Data(0)

0

MSB Register

LSB Register

Table 21. Register Data Format – Read/Write: Power, Min/Max Power, Min/Max Power Threshold, PSUM, Min/Max PSUM, Min/Max

PSUM Threshold

12-Bit Mode:

BIT(7)

Data(23)

Data(15)

Data(7)

BIT(6)

Data(22)

Data(14)

Data(6)

BIT(5)

Data(21)

Data(13)

Data(5)

BIT(4)

Data(20)

Data(12)

Data(4)

BIT(3)

Data(19)

Data(11)

Data(3)

BIT(2)

Data(18)

Data(10)

Data(2)

BIT(1)

Data(17)

Data(9)

Data(1)

BIT(0)

Data(16)

Data(8)

Data(0)

MSB2 Register

MSB1 Register

LSB Register

8-Bit Mode:

BIT(7)

Data(15)

Data(7)

0

BIT(6)

Data(14)

Data(6)

0

BIT(5)

Data(13)

Data(5)

0

BIT(4)

Data(12)

Data(4)

0

BIT(3)

Data(11)

Data(3)

0

BIT(2)

Data(10)

Data(2)

0

BIT(1)

Data(9)

Data(1)

0

BIT(0)

Data(8)

Data(0)

0

MSB2 Register

MSB1 Register

LSB Register

2992f

35

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

–48V Redundant Feed with Transient Protection to 200V (1.5kHz I²C Interface)

MBR20200*

Q1, PZTA42

RTN1

R

9.1k

1W

SHUNT1

MBR20200*

RTN2

R14

100Ω

R

9.1k

1W

SHUNT2

R3

1k

R4

0.51k

R1

2k

R2

2k

3.3V

C1

1µF

R9

R10

R11 R12 R13

2k 10k

R5

1M

R6

1M

V

INTV

CC

DD

0.51k 0.51k 2k

MOCD207M

V

DD

SCL

GPIO1

GPIO2

SCL

SDAI

ADR1

ADR0

LTC2992-1

µP

MOCD207M

R7

R8

20k

SDAO

SDA

TEMPERATURE

GPIO3

SENSOR

ALERT

INT

GPIO4

GND

–

+

–

+

SENSE2 SENSE2

SENSE1 SENSE1

2992 TA02

MBR20200*

V

–48V

IN1

R

SENSE1

0.01Ω

MBR20200*

V

–48V

V

5A

IN2

OUT

R

SENSE2

0.01Ω

*APPROPRIATELY SIZED HEAT SINK IS REQUIRED

2992f

36

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

High Side and Low Side Current Sensing on a Wide Range Supply

R

SENSE1

0.01Ω

+

–

SENSE1 SENSE1

V

DD

INTV

CC

VISHAY

NTCS0402E3104*HT

100k AT 25°C

1%

C1

1µF

LTC2992

ADR0

ADR1

GND

SDAI

SDAO

SCL

2

I C

INTERFACE

+

–

V

IN

R3

19.1k

1%

R1

40.2k

1%

7V TO

100V

LOAD

5A

GPIO1

GPIO4

ALERT

GPIO2

GPIO3

GP OUTPUT

R4

20k

1%

R2

10k

1%

–

+

SENSE2 SENSE2

2992 TA03

R

SENSE2

0.01Ω

CODE

GPIO1

TEMPERATURE T(°C) = 41.51 • (

– 0.1233), 20°C < T < 60°C

CODE

GPIO2

2992f

37

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Dual 12V High Power Monitor with One Negative Voltage Monitor

R

= RESISTOR ARRAY

SENSE1

10 × 5mΩ PARALLEL SENSE RESISTORS

10 × PAIRS OF 1Ω RESISTORS

R

SENSE1_1

5mΩ

R

SP1_1

1Ω

R

SM1_1

1Ω

R

SENSE1_10

5mΩ

R

SP1_10

1Ω

SM1_10

1Ω

R

SENSE1

0.5mΩ

V

12V

V

OUT1

100A

IN1

V

NEG

+

–

SENSE1 SENSE1

V

DD

0V TO –60V

SDAI

R1

640k

1%

2

I C

SDAO

INTERFACE

LTC2992

GPIO1

SCL

R2

17.8k

1%

GPIO2

GPIO4

ALERT

GPIO3

DATAREADY

+

–

INTV

GND ADR0 ADR1 SENSE2 SENSE2

CC

C1

1µF

V

12V

V

100A

IN2

OUT2

R

SENSE2

0.5mΩ

4mV/K

V

CC

+

V

PTAT

D

C2

470pF

MEASURES BOARD

TEMPERATURE

LTC2997

1.8V

–

V

REF

D

GND

MMBT3904

TEMPERATURE T(°C) = CODE

/8 – 273.15

GPIO2

V

(V) = 36.955 × CODE

× GPIO LSB STEP SIZE – 64.7191, –60V < V

< 0V

NEG

GPIO1

NEG

2992 TA04

2992f

38

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Power Monitor for 48V, 500W Electric Bike/Scooter

R

SENSE2

0.005Ω

10A

DC BRUSHLESS MOTOR

R

SENSE1

0.2Ω

200mA

+

–

3.3V

48V

V

DD

+

–

+

–

R3

R4

R5

R6

SENSE1 SENSE1

SENSE2 SENSE2

330k 10k 10k 10k

SDA

V

DD

SDAI

SDAO

SCL

MCU

SCL

LTC2992

ALERT

GPIO4

INT

2992 TA05

HEADLIGHT

GPIO3

RELAY CONTROL

GPIO2 INTV

GND ADR0 ADR1

GPIO1

CC

C1, 1µF

4mV/K

GND

+

V

PTAT

V

D

CC

C2

470pF

MEASURE BOARD

TEMPERATURE

R2

10k

LTC2997

–

D

GND

MMBT3904

GP OUTPUT

PIN NOT USED IN LTC2997 CIRCUIT: V

REF

TEMPERATURE T(°C) = CODE

/8 – 273.15

GPI01

2992f

39

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Four Quadrant Power Monitor (10kHz I²C Interface)

+

–

3.3V

Q1

PZTA42

SEPARATE

5V SUPPLY

R10

R11

R12 R13 R14

R8

R9

V

DD

0.47k 0.47k 2k

2k

10k

MOCD207M

V

DD

4.7k 4.7k

R1

SCL

1M

R16

100k

GPIO1

SCL

SDAI

R3

20k

µP

Q4*

MMBT2222L

LTC2992-1

R6

R7

NC

ORGND

(GND PIN

OF LTC2992-1)

33k 0.82k

MOCD207M

NC

Q5*

SDAO

SDA

R2

20k

MMBT2222L

ALERT

R17

100k

INT

GPIO4

ADR1

ADR0

GND

GPIO2

INTV

CC

R4

1M

C1

1µF

ORGND

GND

TEMPERATURE

SENSOR

GPIO3

V

Z

V

DD

SS

SB

SA

C2

1nF

C3

1nF

LTC4371

Q2

BSP297

Q3

BSP297

GB

GA

R15, 10k

–

+

–

+

SENSE1 SENSE2

SENSE2 SENSE1

DB

DA

V

IN

V

OUT

5A

PIN NOT USED IN LTC4371 CIRCUIT: FAULTB

–95V TO

100V

R

SENSE

NC: NO CONNECT

0.01Ω

*MAX EMITTER-BASE BREAKDOWN VOLTAGE OF Q4, Q5 SHOULD BE LESS THAN 7V

|V | – |V

IN

|–|V

|

1

RSENSE

DS,Q2

CODE

=

×

GPIO1

GPIO2

51

GPIO LSB STEP SIZE

2992 TA06

|V | – |V

IN

|

1

DS,Q3

CODE

×

51

GPIO LSB STEP SIZE

IF CODE

> CODE

< CODE

, MEASURED V = –[CODE

× GPIO LSB STEP SIZE × 51]

GPIO1

GPIO2

IN

GPIO1

× GPIO LSB STEP SIZE × 51

, MEASURED V = CODE

IN

GPIO2

V

, V

ARE DRAIN TO SOURCE VOLTAGE OF Q2 AND Q3

IS VOLTAGE ACROSS R

DS,Q2 DS,Q3

RSENSE

SENSE

2992f

40

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Power Efficiency Meter

–

SDAI

SENSE2

2

I C

+

SDAO

SENSE2

INTERFACE

SCL

INTV

CC

C

0.1µF

A

LTC2992

ADR1

ADR0

R

PU1

100k

R

PU4

100k

GND

V

DD

+

SENSE1

GPIO1

–

SENSE1

GPIO4

ALERT

GPIO2 GPIO3

V

IN

14V TO 100V

R

SENSE1

C

+

INB

C

10mΩ

INA

100µF

0.47µF

×4

RUN

MTOP

×2

V

TG

IN

MODE

BOOST

R

C

0.1µF

SENSE2

6mΩ

B

L1, 33µH

V

ILIM

OUT

12V

5A

SW

R

PU2

100k

PU3

100k

LTC3895

MBOT

BG

+

C

OUTA

150µF

×2

INTV

OUTB

22µF

CC

C

INTVCC

0.1µF

CRUMP_EN

+

SENSE

C

1nF

C

SNS

SS

0.1µF

–

SS

SENSE

EXTV

CC

R , 140k

B

NDRV

V

FB

DRV

CC

ITH

C

DRVCC

4.7µF

DRVSET

DRVUV

OVLO

FREQ

GND

R

ITH

10k

R

A

10k

R

80.6k

DRV

C

EXT

1µF

ITHB

100pF

R

C

ITHA

4.7nF

FREQ

30.1k

2992 TA07

PINS NOT USED IN LTC3895 CIRCUIT:

CLKOUT, PLLIN, PHASMD, PGOOD, VPRG

MTOP, MBOT: BSC520N15NS3G

D : DIODES INC. SMAZ12-13-F

EXT

L1: WURTH 7443633300

: SUNCON 35CE68LX

C

OUTA

2992f

41

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Bidirectional 30V to 300V High Side Power Monitor

R

SENSE

0.01Ω

V

5A

OUT

V

IN

3.3V

R11

2k

R1

2k

–

+

–

+

SENSE2 SENSE1

SENSE1 SENSE2

R8

1k

R9

1k

R10

10k

C2

R3 R4 R7

Z1*

5.1V

V

DD

0.1µF 5k

2k 2k

V

DD

INTV

CC

V

DD1

SDAI

SDAO

SCL

DD2

µP

SDA

ADUM1251

C1

NST30010MXV6

SDA

SCL

GND

2

1

0.1µF

LTC2992

GPIO1

GPIO2

ADR1

ADR0

SCL

2

GND

2

R12

374k

R2

5.1k

FODM217C

R13

374k

INT

GND

ALERT

GPIO4

FAN ON

OUTPUT

GPIO3

GND

R11

100Ω

M1

BSP135

Q1

2N3904

Q2

USE GPIO TO MEASURE INPUT VOLTAGE

SEE TABLE 5

*DDZ9689, DIODES INC.

MMBT6520L

M3

BSP135

Q3

2N3904

R5

10k

R6

10k

2992 TA08

2992f

42

For more information www.linear.com/LTC2992

LTC2992

Typical applicaTions

Bipolar Supply Power Monitor (1.5kHz I²C Interface)

R

SENSE1

0.01Ω

V

POS

10V TO 20V

5A

3.3V

R4

15k

R5

R6

R7

+

–

R9

0.2k

R10 R11 R12

R8

0.2k

SENSE1 SENSE1

V

DD

3.3k 15k 15k

2k

10k

MOCD207M

V

DD

TEMPERATURE

SENSOR

GPIO1

SCL

BAT54*

SCL

SDAI

LTC2992-1

µP

R1

118k

GPIO2

MOCD207M

R2

10k

BAT54*

SDAO

SDA

GND

C1

1µF

ALERT

INT

INTV

CC

GPIO4

ADR1

ADR0

R3

10k

GND

GPIO3

–

+

SENSE2 SENSE2

V

NEG

–10V TO –20V

5A

R

SENSE2

0.01Ω

2992 TA09

*DIODES ENSURE LTC2992-1’S OPERATION WHEN EITHER SUPPLY FAILS OPEN

2992f

43

For more information www.linear.com/LTC2992

LTC2992

package DescripTion

Please refer to http://www.linear.com/product/LTC2992#packaging for the most recent package drawings.

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)

0.70 0.05

3.30 0.05

ꢀ.70 0.05

3.60 0.05

2.20 0.05

PACKAGE

OUTLINE

0.25 0.05

0.45 BSC

3.ꢀ5 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.ꢀꢀ5

TYP

0.40 0.ꢀ0

4.00 0.ꢀ0

(2 SIDES)

9

ꢀ6

R = 0.05

TYP

3.30 0.ꢀ0

3.00 0.ꢀ0

(2 SIDES)

ꢀ.70 0.ꢀ0

PIN ꢀ NOTCH

R = 0.20 OR

PIN ꢀ

TOP MARK

(SEE NOTE 6)

0.35 × 45°

CHAMFER

(DEꢀ6) DFN 0806 REV Ø

8

ꢀ

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

3.ꢀ5 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

2992f

44

For more information www.linear.com/LTC2992

LTC2992

package DescripTion

Please refer to http://www.linear.com/product/LTC2992#packaging for the most recent package drawings.

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

2992f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

For more rmation www.linree .cilom/LTC2992

tion that the interconnection of its cinircfouits as described he inarw l not infringe on existing patent rights.

45

LTC2992

Typical applicaTion

Bidirectional Wide Range Power Monitor

R

SENSE

0.01Ω

V

IN

V

OUT

3V TO 100V

–

+

–

+

SENSE2 SENSE1 SENSE1 SENSE2

SDAI

SDAO

SCL

V

DD

2

I C

BOARD

TEMPERATURE

GPIO1

INTERFACE

LTC2992

µP

GPIO2

TEMPERATURE

ALERT

GPIO4

DATAREADY

GPIO3

INTV

CC

GND ADR0 ADR1

2992 TA10

0.1μF

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LT^®2940

LTC2941

LTC2942

LTC2943

LTC294±

LTC2947

LTC2990

LTC41±0

LTC41±1

LTC421±

Power and Current Monitor

4-Quadrant Multiplication, ±±5 Power ꢀccuracy, 4V to 80V Operation

2.7V to ±.±V Operation, 15 Charge ꢀccuracy

2

I C Battery Gas Gauge

2

I C Battery Gas Gauge

2.7V to ±.±V Operation, 15 Charge, Voltage and Temperature

3.6V to 20V Operation, 15 Charge, Voltage, Current and Temperature

0V to 80V Operation, 12-Bit ꢀDC with ±0.7±5 TꢁU

High Voltage Battery Gas Gauge

2

Wide Range I C Power Monitor

Power/Unergy Monitor with Integrated Sense Resistor ±30ꢀ Current Range with 9mꢀ Offset

2

Quad I C Temperature, Voltage and Current Monitor

Coulomb Counter/Battery Gas Gauge

3V to ±.±V Operation, 14-Bit ꢀDC

2.7V to 8.±V Operation, Voltage-to-Frequency Converter

7V to 80V Operation, 12-Bit Resolution with ±1.2±5 TꢁU

8-Bit ꢀDC, ꢀdjustable Current Limit and Inrush, 2.9V to 1±V Operation

2

High Voltage I C Current and Voltage Monitor

2

Single Channel, Hot Swap Controller with I C

Monitoring

2

LTC4222

LTC4260

LTC4261

Dual Channel, Hot Swap Controller with I C

10-Bit ꢀDC, ꢀdjustable Current Limit and Inrush, 2.9V to 29V Operation

8-Bit ꢀDC, ꢀdjustable Current Limit and Inrush, 8.±V to 80V Operation

10-Bit ꢀDC, Floating Topology, ꢀdjustable Inrush

Monitoring

2

Positive High Voltage Hot Swap Controller with I C

Monitoring

2

Negative High Voltage Hot Swap Controller with I C

Monitoring

2992f

LT 1017 • PRINTED IN USA

www.linear.com/LTC2992

46

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTC2992


型号：	LTC2992HMS-1#PBF
厂家：	Linear
描述：	LTC2992 - Dual Wide Range Power Monitor; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
文件：	总46页 (文件大小：1935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2992HMS-1#PBF [Linear]

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