LTC3111 [Linear]
15V, 1.5A Synchronous Buck-Boost DC/DC Converter;
| 型号： | LTC3111 |
| 厂家： | 
Linear |
| 描述： | 15V, 1.5A Synchronous Buck-Boost DC/DC Converter |
| 文件： | 总32页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3111
15V, 1.5A Synchronous
Buck-Boost DC/DC
Converter
FEATURES
DESCRIPTION
The LTC®3111 is a fixed frequency, synchronous buck-
boost DC/DC converter with an extended input and output
range. The unique 4-switch, single inductor architecture
provides low noise and seamless operation from input
voltages above, below or equal to the output voltage.
n
Regulated Output with V Above, Below
IN
or Equal to V
OUT
n
n
2.5V to 15V Input and Output Voltage Range
1.5A Continuous Output Current: V ≥ 5V,
IN
V
= 5V, PWM Mode
OUT
n
n
n
n
Single Inductor
Withaninputandoutputrangeof2.5Vto15V,theLTC3111
is well suited for a wide variety of single or multiple-cell
batteries,back-upcapacitororwalladaptersourceapplica-
Accurate RUN Threshold
Up to 95% Efficiency
800kHz Switching Frequency, Synchronizable
Between 600kHz and 1.5MHz
49µA No-Load Quiescent Current in Burst Mode®
Operation
Output Disconnect in Shutdown
Shutdown Current < 1µA
Internal Soft-Start
tions. Low R
internal N-channel MOSFET switches
DS(ON)
and selectable PWM or Burst Mode operation produce
high efficiency over a wide range of operating conditions.
n
n
n
n
n
An accurate RUN pin allows the user to program the
turn-on threshold voltage of the converter. Other features
include: short-circuit protection, internal soft-start and
thermal shutdown.
Small, Thermally Enhanced 14-Lead (3mm × 4mm ×
0.75mm) DFN and 16-Lead MSOP Packages
The LTC3111 is offered in both thermally enhanced
14-lead (3mm × 4mm × 0.75mm) DFN and 16-lead MSOP
packages.
APPLICATIONS
n
3.3V or 5V from 1, 2 or 3 Li-Ion, Multiple-Cell
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, LTspice are registered
trademarks and No R
and PowerPath are trademarks of Linear Technology Corporation.
SENSE
Alkaline/NiMH Batteries
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 6404251, 6166527, 5481178, 6304066, 6580258.
n
RF Transmitters
Military, Industrial Power Systems
n
TYPICAL APPLICATION
5V, 800kHz Wide Input Voltage Buck-Boost Regulator
Efficiency at 5VOUT
100
4.7µH
PWM
90
0.1µF
0.1µF
SW1
SW2
BURST
80
V
BST1
BST2
OUT
5V
V
IN
V
IN
V
OUT
1.5A
70
60
50
40
2.5V TO 15V
680pF
27pF
1µF
10µF
22µF
(V > 5V)
IN
LTC3111
26.1k
20k
33pF
COMP
FB
1M
BURST PWM
OFF ON
PWM/SYNC
RUN
V
V
V
= 2.7V
= 5V
IN
IN
IN
191k
SNSGND
SGND
V
CC
PGND
= 12V
3111 TA01a
30
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3111 TA01b
3111fa
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LTC3111
ABSOLUTE MAXIMUM RATINGS (Notes 1, 3)
V Voltage................................................. –0.3V to 16V
OUT
Operating Junction Temperature Range (Notes 2, 5)
LTC3111E, LTC3111I........................... –40°C to 125°C
LTC3111H........................................... –40°C to 150°C
LTC3111MP........................................ –55°C to 150°C
Maximum Junction Temperature (Note 3)............. 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)
IN
V
Voltage.............................................. –0.3V to 16V
SW1 Voltage (Note 4) ................... –0.3V to (V + 0.3V)
IN
OUT
SW1
SW2
SW2 Voltage (Note 4) .................–0.3V to (V
+ 0.3V)
+ 6V)
+ 6V)
BST1 Voltage ...................(V
BST2 Voltage ...................(V
– 0.3V) to (V
SW1
SW2
– 0.3V) to (V
RUN Voltage............................................... –0.3V to 16V
PWM/SYNC, V Voltage............................. –0.3V to 6V
MSOP ...............................................................300°C
CC
FB, COMP, Voltage ....................................... –0.3V to 6V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
COMP
FB
1
2
3
4
5
6
7
14 SGND
1
2
3
4
5
6
7
8
COMP
FB
16 SGND
13 PWM/SYNC
15 PWM/SYNC
SNSGND
RUN
12
V
CC
SNSGND
RUN
14 V
CC
15
17
PGND
13 NC
11 NC
PGND
V
12 V
OUT
IN
V
10
9
V
OUT
SW1
BST1
PGND
11 SW2
10 BST2
IN
SW1
SW2
9
PGND
BST1
8
BST2
MSE PACKAGE
16-LEAD PLASTIC MSOP
DE PACKAGE
T
JMAX
= 150°C, θ = 40°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
14-LEAD (4mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 43°C/W, θ = 5°C/W
JA JC
JMAX
EXPOSED PAD (PIN 15) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3111EDE#PBF
LTC3111IDE#PBF
TAPE AND REEL
PART MARKING*
3111
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3111EDE#TRPBF
LTC3111IDE#TRPBF
LTC3111HDE#TRPBF
LTC3111MPDE#TRPBF
LTC3111EMSE#TRPBF
LTC3111IMSE#TRPBF
LTC3111HMSE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic MSOP
3111
LTC3111HDE#PBF
LTC3111MPDE#PBF
LTC3111EMSE#PBF
LTC3111IMSE#PBF
LTC3111HMSE#PBF
LTC3111MPMSE#PBF
3111
3111
3111
3111
16-Lead Plastic MSOP
3111
16-Lead Plastic MSOP
LTC3111MPMSE#TRPBF 3111
16-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3111fa
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LTC3111
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = PWM/SYNC = RUN = 5V unless otherwise
noted.
PARAMETER
CONDITION
Rising
MIN
2.5
TYP
MAX
15
UNITS
V
l
l
Input Operating Range
V
V
V
V
UVLO Threshold
UVLO Hysteresis
UVLO Threshold
UVLO Hysteresis
1.9
2.1
200
2.35
190
2.3
V
IN
mV
V
IN
l
Rising
2.2
2.5
CC
CC
mV
V
l
l
Output Voltage Adjust Range
INTV Clamp Voltage
2.5
3.9
15
4.5
80
1
V
= 5V or 15V
IN
4.2
55
0
V
CC
Quiescent Current—Burst Mode Operation FB = 1V, PWM/SYNC = 0V
µA
µA
V
Quiescent Current—Shutdown
Feedback Voltage
RUN = V
= V = 0V, Not Including Switch Leakage
OUT CC
l
PWM Operation
FB = 0.8V
0.78
2.3
85
0.8
0
0.82
50
5
Feedback Leakage
nA
µA
mΩ
mΩ
A
NMOS Switch Leakage
NMOS Switch On-Resistance
Switches A, B, C, D, V = V
= 15V
OUT
0.5
90
105
3
IN
Switch A
Switch B, C, D
l
Input Current Limit
3.7
Peak Current Limit
5.8
0.8
0.1
–1
90
A
Burst Current Limit
PWM/SYNC = 0V
PWM/SYNC = 0V
A
Burst Zero Current Threshold
Reverse Current Limit
Maximum Duty Cycle
A
A
l
l
Percentage of the Period SW2 is Low in Boost Mode
(Note 7)
%
Minimum Duty Cycle
Percentage of the Period SW1 is Low in Buck Mode
(Note 7)
0
%
SW1, SW2 Minimum Low Time
Frequency
(Note 7)
160
800
ns
kHz
kHz
V
l
l
l
l
l
l
PWM/SYNC = 5V
(Note 6)
700
600
0.5
900
1500
1.5
SYNC Frequency Range
PWM/SYNC Threshold
0.9
0.8
RUN Threshold to Enable V
Rising
Falling
Rising
0.35
0.3
1.15
V
CC
RUN Threshold to Disable V
V
CC
RUN Threshold to Enable Switching
RUN Hysteresis
1.15
1.18
120
1.23
V
mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetimes.
to 125°C junction temperature, the LTC3111H is guaranteed to meet
performance specifications from –40°C to 150°C junction temperature
and the LTC3111MP is guaranteed and tested to meet performance
specifications from –55°C to 150°C junction temperature. High junction
temperatures degrade operating lifetimes: operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 2: The LTC3111 is tested under pulsed load conditions such that
T ≈ T . The LTC3111E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3111I is guaranteed to meet performance specifications from –40°C
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LTC3111
ELECTRICAL CHARACTERISTICS
Note 5: The junction temperature (T in °C) is calculated from the ambient
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperatures will exceed 150°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
J
temperature (T in °C) and power dissipation (P in Watts) according to
A
D
the formula:
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
Note 4: Voltage transients on the switch pins beyond the DC limit specified
in the Absolute Maximum Ratings, are non-disruptive to normal operation
when using good layout practices, as shown on the demo board or
described in the data sheet and application notes.
Note 6: SYNC frequency range is tested with a square wave. Operation
with 100ns minimum high or low time is assured by design.
Note 7: Switch timing measurements are made in an open-loop test
configuration. Timing in the application may vary somewhat from these
values due to differences in the switch pin voltage during the non-overlap
durations when the switch pin voltage is influenced by the magnitude and
direction of the inductor current.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified
Maximum Output Current
in PWM Mode vs VIN
Maximum Load Current in Burst
Mode Operation vs VIN
Wide VIN to 5VOUT Efficiency
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
800
700
600
500
400
300
200
100
0
PWM
V
V
V
= 3.3V
= 5V
= 12V
OUT
OUT
OUT
BURST
INPUT CURRENT LIMIT = 2.3A
V
V
V
= 3.3V, L = 4.7µH
= 5V, L = 6.8µH
= 12V, L = 10µH
V
IN
V
IN
V
IN
= 2.7V
= 5V
= 12V
OUT
OUT
OUT
2
3
4
5
6
7
8
9
10 11 12 13 14 15
2
3
4
5
6
7
15
8
9
10 11 12 13 14
0.0001 0.001
0.01
0.1
1
10
V
(V)
V
IN
(V)
LOAD CURRENT (A)
IN
3111 G03
3111 G02
3111 G01
Wide VIN to 5VOUT Power Loss
Wide VIN to 3.3VOUT Efficiency
Wide VIN to 3.3VOUT Power Loss
10
10
1
100
90
80
70
60
50
40
30
V
IN
V
IN
V
IN
= 2.7V
= 5V
= 12V
PWM
1
0.1
PWM
PWM
BURST
0.1
0.01
0.001
0.0001
BURST
0.01
BURST
0.001
0.0001
V
V
V
= 2.7V
V
IN
V
IN
V
IN
= 2.7V
IN
IN
IN
= 5V
= 5V
= 12V
= 12V
0.0001
0.001
0.01
0.1
1
0.0001 0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3111 G04
3111 G05
3111 G06
3111fa
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LTC3111
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified
12VIN to 12VOUT Efficiency at
f = 600kHz, 800kHz, 1MHz and
1.5MHz with L = 10µH
Wide VIN to 12VOUT Efficiency
Wide VIN to 12VOUT Power Loss
10
1
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
PWM
PWM
BURST
0.1
BURST
0.01
0.001
0.0001
f = 600kHz
V
IN
V
IN
V
IN
= 2.7V
V
V
V
= 2.7V
IN
IN
IN
f = 800kHz
f = 1MHz
= 5V
= 5V
= 12V
= 12V
f = 1.5MHz
0.0001 0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3111 G08
3111 G07
3111 G09
Burst Mode No-Load Current with
VCC from VIN or Back-Fed from
VOUT with an Optional Diode
800kHz PWM Mode No-Load Input
Current
V
CC Voltage vs VIN PWM Mode
No Load
20
18
16
14
12
10
8
450
400
350
300
250
200
150
100
50
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
V
= 5V
OUT
6
V
FROM V
4
CC
IN
2
V
FROM V
OUT
CC
0
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15
2
3
4
5
6
7
8
9
10 11 12 13 14 15
2
3
4
5
6
7
8
15
9
10 11 12 13 14
V
(V)
V
(V)
V (V)
IN
IN
IN
31111 G10
3111 G12
3111 G11
Normalized N-Channel MOSFET
Resistance vs VCC
Normalized N-Channel MOSFET
Resistance vs Temperature
VCC Voltage vs VCC Current
4.2
4.1
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.30
1.25
1.20
1.15
4.0
3.9
3.8
3.7
3.6
1.10
1.05
1.00
0.95
0.90
3.5
10 20
CURRENT FROM V (mA)
80
0
30 40 50 60 70
–50
0
50
TEMPERATURE (°C)
100
150
3.0
3.5
4.5
2.5
5.0
4.0
(V)
V
CC
CC
3111 G13
3111 G15
3111 G14
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LTC3111
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified
Feedback Pin Program Voltage
vs Temperature
VCC and VIN UVLO Voltage
Thresholds vs Temperature
RUN Threshold to Enable/Disable
VCC vs VIN
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
800.5
800.0
799.5
799.0
798.5
798.0
797.5
797.0
796.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
V
UVLO RISING
CC
RISING
V
UVLO FALLING
UVLO RISING
UVLO FALLING
CC
V
IN
FALLING
V
IN
50
–50
0
100
150
50
–50
0
100
150
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
IN
3111 G16
3111 G17
3111 G18
RUN Threshold to Enable/Disable
VCC vs Temperature
RUN Threshold to Enable/Disable
Switching vs VIN
RUN Threshold to Enable/Disable
Switching vs Temperature
1.30
1.25
1.20
1.15
1.10
1.05
1.00
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1.30
1.25
RISING
RISING
1.20
1.15
RISING
FALLING
FALLING
1.10
1.05
FALLING
1.00
–50
0
50
100
150
–50
0
50
100
150
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
IN
3111 G21
3111 G19
3111 G20
PWM Mode Input, Peak and
Reverse Current Limits vs
Temperature
Burst Mode Peak Current, IZERO
Limits vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
6
5
PEAK CURRENT LIMIT
PEAK CURRENT LIMIT
4
INPUT CURRENT LIMIT
3
2
1
0
REVERSE CURRENT LIMIT
I
ZERO
50
–1
–2
–50
0
100
150
50
–50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
3111 G23
3111 G22
3111fa
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LTC3111
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified
3VIN to 5VOUT 0.05A to 0.25A
Load Response
5VIN to 5VOUT 0.05A to 0.5A
Load Response
12VIN to 5VOUT 0.05A to 0.5A
Load Response
V
OUT
V
OUT
200mV/DIV
V
OUT
200mV/DIV
500mV/DIV
INDUCTOR
CURRENT
500mA/DIV
LOAD
CURRENT
200mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
1A/DIV
LOAD
CURRENT
500mA/DIV
LOAD
CURRENT
500mA/DIV
3111 G24
3111 G25
3111 G26
500µs/DIV
FRONT PAGE APPLICATION
500µs/DIV
FRONT PAGE APPLICATION
500µs/DIV
FRONT PAGE APPLICATION
5VIN to 5VOUT Burst to PWM
Response
12VIN to 5VOUT Burst Mode VOUT
Ripple
12VIN to 5VOUT PWM VOUT Ripple
V
OUT
V
OUT
V
OUT
200mV/DIV
200mV/DIV
50mV/DIV
PWM/SYNC
5V/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3111 G27
3111 G29
3111 G28
I
= 10mA
500µs/DIV
I
= 500mA
1µs/DIV
I
= 50mA
20µs/DIV
LOAD
LOAD
LOAD
L = 4.7µH
= 22µF
L = 4.7µH
C = 22µF
OUT
L = 4.7µH
= 22µF
C
C
OUT
OUT
7.5VIN to 5VOUT Start-Up
Response
1.5MHz SYNC Signal Capture and
Release
12VIN to 5VOUT SW1 and SW2
Waveforms
SW2
5V/DIV
V
OUT
RUN
200mV/DIV
5V/DIV
SW1
10V/DIV
PWM/SYNC
5V/DIV
V
OUT
2V/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
1A/DIV
3111 G31
3111 G32
3111 G30
100µs/DIV
1µs/DIV
I
= 500mA 500µs/DIV
LOAD
L = 4.7µH
= 22µF
C
OUT
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LTC3111
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified
3.3VOUT Die Temperature Rise vs
Continuous Load Current 4-Layer
Demo Board at 25°C
VOUT Short-Circuit Response and
Recovery
VCC Short-Circuit Response and
Recovery
50
45
40
35
30
25
20
15
10
5
V
CC
5V/DIV
V
OUT
V
= 2.7V
IN
2V/DIV
SOFT-START
V
V
IN
= 12V
OUT
2V/DIV
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
V
= 5V
IN
3111 G33
3111 G34
1ms/DIV
1ms/DIV
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
3111 G35
5VOUT Die Temperature Rise vs
Continuous Load Current 4-Layer
Demo Board at 25°C
12VOUT Die Temperature Rise vs
Continuous Load Current 4-Layer
Demo Board at 25°C
60
50
80
70
60
50
40
30
20
10
0
V
= 12V
IN
40
30
V
= 12V
V
= 2.7V
V
= 5V
IN
IN
IN
V
= 2.7V
V
= 5V
IN
IN
20
10
0
0.8 1.0
1.2 1.4 1.6 1.8 2.0
0
0.2 0.4 0.6
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
LOAD CURRENT (A)
3111 G37
3111 G36
SW1, SW2 Minimum Low Time
vs VCC
SW1, SW2 Minimum Low Time
vs Temperature
250
230
210
190
170
150
130
110
90
300
250
200
150
100
50
I
= 300mA
I
= 300mA
LOAD
LOAD
SW1, V = 4V
IN
SW1, V = 4V
IN
SW2, V = 6V
IN
SW2, V = 6V
IN
70
50
0
2
3
3.5
(V)
4
4.5
5
–50
0
50
100
150
2.5
V
TEMPERATURE (°C)
CC
3111 G38
3111 G39
3111fa
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LTC3111
PIN FUNCTIONS (DFN/MSOP)
COMP (Pin 1/Pin 1): Error Amp Output. An R-C network
connected from this pin to FB sets the loop compensa-
tion for the voltage converter. Refer to the Applications
Information section for component selection details.
BST1 (Pin 7/Pin 7): Boosted Floating Driver Supply for
A-Switch Driver. Connect a 0.1µF capacitor from this pin
to SW1.
BST2 (Pin 8/Pin 10): Boosted Floating Driver Supply for
D-Switch Driver. Connect a 0.1µF capacitor from this pin
to SW2.
FB (Pin 2/Pin 2): Feedback Voltage Input. Connect the
V
resistordividertaptothispin.Theoutputvoltagecan
OUT
be adjusted from 2.5V to 15V by the following equation:
SW2 (Pin 9/Pin 11): The external inductor and internal
switches C and D are connected here.
R1
R2
VOUT = 0.8V • 1+
V
OUT
(Pin 10/Pin 12): Regulated Output Voltage. This pin
should be connected to a low ESR ceramic capacitor. The
capacitor should be placed as close to the pin as possible
and have a short return to the ground plane.
where R1 is the resistor between V
the resistor between FB and GND
and FB and R2 is
OUT
SNSGND (Pin 3/Pin 3): This pin must be connected to
ground.
NC (Pin 11/Pin 13): Not Connected. This pin should be
connected to ground.
RUN(Pin4/Pin4):InputtoEnableorDisabletheICandSet
Custom Input Undervoltage Lockout (UVLO) Thresholds.
The RUN pin can be driven by an external logic signal to
enable and disable the IC. In addition, the voltage on this
pin can be set by a resistive voltage divider connected to
the input supply in order to provide accurate turn-on and
turn-off (UVLO) thresholds determined by:
V
(Pin 12/Pin 14): External Capacitor Connection for
CC
the Regulated V Supply. This supply is used to operate
CC
internal circuitry and switch drivers. V will track V up
to 4.2V typical, but will maintain this voltage when V >
CC
IN
IN
4.2V. Connect a 1µF ceramic capacitor from this pin to
GND. This pin can be tied to an external supply up to 5.5V.
Refer to the Operation section of this data sheet under
Power V from an External Source for more details.
R5
R6
CC
V
= 1.2V • 1+
IN(RUN)
PWM/SYNC (Pin 13/Pin 15): Burst Mode Control and
Synchronization Input. A DC voltage < 0.5V commands
Burst Mode operation independent of load current, >1.5V
commands 800kHz fixed frequency mode. A digital pulse
train between 600kHz and 1.5MHz applied to this pin will
override the internal oscillator and set the operating fre-
quency. The pulse train should have a minimum high time
orlowtimegreaterthan100ns(Note6).NotetheLTC3111
has reduced power capability when operating in Burst
Mode operation. This pin should not be left unconnected.
The IC is enabled if RUN exceeds 1.2V nominally. Once
enabled, the UVLO threshold has a built-in hysteresis of
approximately120mV,turn-offwilloccurwhenthevoltage
on RUN drops to below 1.08V nominally. To continuously
enable the IC, RUN can be tied directly to the input voltage
up to the absolute maximum rating. This pin should not
be left unconnected.
V (Pin 5/Pin 5): Input Supply Voltage. This pin should
IN
be bypassed to the ground plane with at least 10µF of low
ESR, low ESL ceramic capacitance. Place this capacitor as
close to the pin as possible and provide as short a return
path to the ground plane as possible.
SGND (Pin 14/Pin 16): Signal Ground. Terminate the RUN
input voltage divider and output voltage divider to SGND.
PGND(ExposedPadPin15/Pin8,9,ExposedPadPin17)
Power Ground. The exposed pad must be soldered to
the PCB and electrically connected to ground through
the shortest and lowest impedance connection possible.
SW1 (Pin 6/Pin 6): The external inductor and internal
switches A and B are connected here.
3111fa
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For more information www.linear.com/LTC3111
LTC3111
SIMPLIFIED BLOCK DIAGRAM
4.7µH
BST1
V
SW1
SW2
V
BST2
IN
OUT
V
CC
V
CC
C
IN
C
OUT
DDRV
ADRV
V
CC
V
CC
BDRV
CDRV
GND
GND
ADRV BDRV CDRV DDRV
DRIVERS
V
CC
REVERSE
I
LIM
–
+
–
+
I
ZERO
0.1A
5.8A
3A
–1A
LOGIC
I
+
–
PEAK
V
CC
I
LIMIT
+
–
V
V
IN OUT
+
RUN
RUN
–
+
+
FB
+
–
–
STOP
÷
0.8V
1.2V
0.8V
+
–
SOFT-START
RAMP
ERROR AMP
+
–
COMP
START
UVLO
800k
OSCILLATOR
V
+
–
V
IN
IN
2.1V
+
–
V
UVLO
CC
PLL
2.35V
PWM/SYNC
Burst Mode
OPERATION
4.2V
V
CC
START
REGULATOR/
CLAMP
REFERENCE
1.2V
3111 BD
3111fa
10
For more information www.linear.com/LTC3111
LTC3111
OPERATION
INTRODUCTION
V
OUT
LTC3111
V
V
The LTC3111 is an extended input and output range, syn-
chronous1.5Abuck-boostDC/DCconverteroptimizedfor
avarietyofapplications.TheLTC3111utilizesaproprietary
switching algorithm, which allows its output voltage to be
regulated above, below or equal to the input voltage. The
erroramplifieroutputonCOMPdeterminestheoutputduty
IN OUT
R
FF
R1
0.8V
FB
+
–
SW1
PWM
COMPARATORS
C
FF
÷
SW2
C
FB
R
FB
COMP
R2
SGND
C
POLE
3111 F01
cycle of the switches. The low R
, low gate charge
DS(ON)
synchronousswitchesprovidehighefficiencypulsewidth
modulation control. High efficiency is achieved at light
loads when Burst Mode operation is commanded.
Figure 1. Error Amplifier and Compensation Network
on designing the compensation network for the LTC3111
applications can be found in the Applications Information
section of this data sheet.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator, Phase Lock Loop
Current Limit Operation
An internal oscillator circuit sets the normal frequency of
operation to 800kHz. A pulse train applied to the PWM/
SYNCpinallowstheoperatingfrequencytobeprogrammed
between600kHzto1.5MHzviaaninternalphase-lock-loop
circuit. The pulse train must have a minimum high or low
state of at least 100ns to guarantee operation (see Note 6
of the Electrical Characteristics).
The buck-boost converter has two current limit circuits.
The input current limit sources current into the feedback
divider network whenever the current in switch A exceeds
3A typical. Due to the high gain of the feedback loop, the
injectedcurrentforcestheerroramplifieroutputtodecrease
until the average current through switch A decreases ap-
proximately to the current limit value. The input current
limit utilizes the error amplifier in an active state and
thereby provides a smooth recovery with little overshoot
once the current limit fault condition is removed. Since
the current limit is based on the average current through
switch A, the peak inductor current in current limit will
have a dependency on the duty cycle (i.e., on the input
and output voltages) in the overcurrent condition. For this
current limit feature to be most effective, the Thevenin
resistance from the FB to ground should exceed 100kΩ.
Error Amplifier
The LTC3111 contains a high gain operational amplifier
which provides frequency compensation of the control
loop to maintain output voltage regulation. To ensure
loop stability, an external compensation network must be
installedintheapplicationcircuit. ATypeIIIcompensation
network, as shown in Figure 1, is recommended for most
applications since it provides the flexibility to optimize
the converter’s transient response while simultaneously
minimizing any DC error in the output voltage.
The speed of the input current limit circuit is limited by the
dynamics of the converter loop. On a hard output short, it
ispossiblefortheinductorcurrenttoincreasesubstantially
beyondtheinputcurrentlimitbeforetheinputcurrentlimit
circuit can react. For this reason, there is a peak current
limitcircuitwhichturnsoffswitchAifthecurrentinswitch
A exceeds approximately 190% of the input current limit
value. This provides additional protection in the case of
an instantaneous hard output short.
As shown in Figure 1, the error amplifier is followed by
an internal analog divider which adjusts the loop gain by
the reciprocal of the input voltage when the converter is in
buck mode and by the output voltage when the converter
is in boost mode which minimizes loop-gain variation
over changes in the input voltage. This simplifies design
of the compensation network and optimizes the transient
response over the entire range of input voltages. Details
3111fa
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LTC3111
OPERATION
Should the output voltage become shorted, the input
current limit is reduced to approximately one half of the
normal operating current limit.
The temperature rise curves given in the Typical Perfor-
mance Characteristics section can be used as a guide to
predict junction temperature rise from ambient. These
curves were generated by mounting the LTC3111 to the
4-layer FR-4 demo printed circuit board layout shown in
Figure 4. The curves were taken at room temperature,
elevated ambient temperature will result in greater ther-
Reverse Current Limit
During fixed frequency operation, a reverse current com-
paratoronswitchDmonitorsthecurrententeringtheV
pin. When this current exceeds 1A (typical) switch D will
be turned off for the remainder of the switching cycle. This
feature protects the buck-boost converter from excessive
reverse current if the buck-boost output is held above the
regulation voltage.
OUT
mal rise rates due to increased R
of the N-channel
DS(ON)
MOSFETs with temperature. The die temperature of the
LTC3111 should be kept below the maximum junction
rating of 125°C for E- and I-grades and 150°C for H- and
MP-grades.
In the event that the junction temperature gets too high
(approximately 170°C), the input current limit will be
linearly decreased from its typical value. If the junction
temperature continues to rise and exceeds approximately
175°C the LTC3111 will be disabled. All power devices
are turned off and all switch nodes put to a high imped-
ance state. The soft-start circuit for the converter is reset
during thermal shutdown to provide a smooth recovery
once the overtemperature condition is eliminated. When
the die temperature drops to approximately 170°C the
LTC3111 will restart.
Internal Soft-Start
The LTC3111 buck-boost converter has an independent
internal soft-start circuit with a nominal duration of 2ms.
The converter remains in regulation during soft-start and
will therefore respond to output load transients which
occur during this time. In addition, the output voltage rise
time has minimal dependency on the size of the output
capacitororloadcurrentduringstart-up.Soft-startisreset
during a thermal shutdown.
THERMAL CONSIDERATIONS
UNDERVOLTAGE LOCKOUTS
For the LTC3111 to provide maximum output power, it is
imperative that a good thermal path be provided to dis-
sipate the heat generated within the package. This can be
accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that
multipleviasintheprintedcircuitboardbeusedtoconduct
the heat away from the IC and into a copper plane with as
much area as possible.
The LTC3111 buck-boost converter is disabled and all
power devices are turned off until the V supply reaches
CC
2.35V(typical). Thesoft-startcircuitisresetduringunder-
voltage lockout to provide a smooth restart once the input
voltage rises above the undervoltage lockout threshold. A
second UVLO circuit disables all power devices if V is
IN
below 2.1V rising, 1.9V falling (typical). This can provide
a lower V operating range in applications where V is
IN
CC
The efficiency and maximum output current capability of
the LTC3111 will be reduced if the converter is required
to continuously deliver large amounts of power or oper-
ate at high temperatures. The amount of output current
derated is dependent upon factors such as board ground
plane or heat sink area, ambient operating temperature
and the input/output voltages of the application. A poor
thermal design can cause excessive heating, resulting in
impaired performance or reliability.
powered from an alternate source or V
after start-up.
OUT
INDUCTOR DAMPING
When the LTC3111 is disabled (RUN = 0V) or sleeping
during Burst Mode operation (PWM/SYNC = 0V), active
circuits“damp”theinductorvoltagethrough1kΩ(typical)
impedance between SW1 and SW2 and GND to reduce
ringing and EMI.
3111fa
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LTC3111
OPERATION
PWM MODE OPERATION
This switching algorithm provides a seamless transition
between operating modes and eliminates discontinuities
in average inductor current, inductor current ripple, and
loop transfer function throughout the operational modes.
Theseadvantagesresultinincreasedefficiencyandstabil-
ity in comparison to the traditional 4-switch buck-boost
converter.
When the PWM/SYNC pin is held high, the LTC3111 buck-
boostconverteroperatesinafixed-frequencypulse-width
modulation(PWM)modeusingvoltagemodecontrol. Full
outputcurrentisonlyavailableinPWM mode.Aproprietary
switching algorithm allows the converter to transition
between buck, buck-boost, and boost modes without
discontinuity in inductor current. The switch topology for
the buck-boost converter is shown in Figure 2.
OUTPUT VOLTAGE PROGRAMMING
The output voltage is set via the external resistor divider
comprised of resistors R1 and R2 as show in Figures 1.
Theresistordividervaluesdeterminetheoutputregulation
voltage according to:
V
V
IN
OUT
A
D
L
R1
R2
B
C
VOUT = 0.8V • 1+
3111 F02
Figure 2. Buck-Boost Switch Topology
In addition to setting the output voltage, the value of R1 is
instrumentalincontrollingthedynamicsofthecompensa-
tion network. When changing the value of this resistor,
care must be taken to understand the impact this will have
on the compensation network.
When the input voltage is significantly greater than the
output voltage, the buck-boost converter operates in buck
mode. Switch D turns on at maximum duty cycle and
switch C turns on just long enough to refresh the voltage
on the BST2 capacitor used to drive switch D. Switches A
and B are pulse-width modulated to produce the required
duty cycle to support the output regulation voltage.
Inaddition,theTheveninequivalentresistanceoftheresis-
tor divider controls the gain of the input current limit. To
maintain sufficient gain in this loop, it is recommended
that the Thevenin resistance be greater than 100kΩ.
As the input voltage nears the output voltage, switches A
and D are on for a greater portion of the switching pe-
riod, providing a direct current path from V to V
Switches B and C are turned on only enough to ensure
proper regulation and/or provide charging of the BST1
and BST2 capacitors. The internal control circuitry will
determine the proper duty cycle in all modes of operation,
which will vary with load current.
RUN Comparator
.
IN
OUT
Inadditiontoservingasalogic-levelinputtoenabletheIC,
the RUN pin includes an accurate internal comparator that
allows it to be used to set custom rising and falling on/off
thresholdswiththeadditionofanexternalresistordivider.
When RUN is driven above its logic threshold (0.8V typi-
cal), the LDO regulator is enabled, which provides power
to the internal control circuitry of the IC. If the voltage
on RUN is increased further so that it exceeds the RUN
comparator accurate analog threshold (1.2V typical), all
functions of the buck-boost converter will be enabled and
a start-up sequence will ensue.
As the input voltage drops well below the output voltage,
the converter operates solely in boost mode. Switch A
turns on at maximum duty cycle and switch B turns on
just long enough to refresh the voltage on the BST1 ca-
pacitor used to drive A. Switches C and D are pulse-width
modulated to produce the required duty cycle to regulate
the output voltage.
IfRUNisbroughtbelowtheaccuratecomparatorthreshold,
the buck-boost converter will inhibit switching, but the
3111fa
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LTC3111
OPERATION
LDO regulator and control circuitry will remain powered
unlessRUNisbroughtbelowitslogicthreshold.Therefore,
in order to completely shut down the IC, it is necessary
to ensure that RUN is brought below its worst-case low
logic threshold of 0.3V. RUN is a high voltage input and
Powering V from an External Source
CC
The LTC3111’s V regulator can be powered or back-fed
CC
from an external source up to 5.5V. The advantage of back
feedingV fromavoltageabove4.2Vishigherefficiency.
CC
For 5V
OUT
applications, V can be easily powered from
OUT
CC
can be tied directly to V to continuously enable the IC
IN
V
using an external low current Schottky as shown in
when the input supply is present. The RUN pin can be
several applications circuits in the Typical Applications
driven above V or V
as long as it stays within the
IN
OUT
section.
operating range of 15V.
Back feeding V also improves a light load PWM mode
CC
With the addition of an optional resistor divider as shown
in Figure 3, the RUN pin can be used to establish a user-
programmable turn on and turn off threshold.
outputvoltageripplethatoccurswhentheinductorpasses
throughzerocurrentbyreducingtheswitchpinanti-cross
conduction times. A disadvantage of powering V from
CC
V
IN
V
is that no-load quiescent current increases at lower
OUT
LTC3111
–
+
input voltage in Burst Mode operation as shown in the
1.2V
R5
R6
ENABLE SWITCHING
RUN
Typical Performance Characteristics (compared to V
powered from V ).
CC
ACCURATE
THRESHOLD
IN
–
+
0.8V
ENABLE SWITCHING LDO
AND CONTROL CIRCUITS
Burst Mode OPERATION
When the PWM/SYNC pin is held low, the buck-boost
converter operates utilizing a variable frequency switch-
ing algorithm designed to improve efficiency at light load
and reduce the standby current at zero load. In Burst
Mode operation, the inductor is charged with fixed peak
amplitude current pulses and as a result only a fraction
of the maximum output current can be delivered when in
Burst Mode operation.
LOGIC
THRESHOLD
3111 F03
Figure 3. Accurate RUN Comparator
The buck-boost converter is enabled when the voltage
on RUN reaches 1.2V (nominal). Therefore, the turn-on
voltage threshold on V is given by:
IN
R5
R6
These current pulses are repeated as often as necessary
to maintain the output regulation voltage. The maximum
V
= 1.2V • 1+
IN(RUN)
output current, I
, which can be supplied in Burst Mode
MAX
Once the converter is enabled, the RUN comparator in-
cludes a built-in hysteresis of approximately 120mV, so
thattheturn-offthresholdwillbeapproximately10%lower
than the turn-on threshold. Put another way, the internal
threshold level for the RUN comparator looks like 1.08V
after the IC is enabled.
operation is dependent upon the input and output voltage
as approximated by the following formula:
IPK
2
V
IN
V + V
IMAX
=
•η •
A
IN
OUT
where I is the Burst Mode peak current limit (0.8A typi-
PK
The RUN comparator is relatively noise insensitive, but
there may be cases due to PCB layout, very large value
resistors for R5 and R6 or proximity to noisy components
where noise pickup is unavoidable and may cause the
turn-on or turn-off of the IC to be intermittent. In these
cases, a filter capacitor can be added across R6 to ensure
proper operation.
cal) in amps and η is the efficiency.
If the buck-boost load exceeds the maximum Burst Mode
current capability, the output rail will lose regulation. In
BurstModeoperation, theerroramplifierisconfiguredfor
low power operation and used to hold the compensation
pin, COMP, to reduce transients that may occur during
transitions from and to burst and PWM mode operation.
3111fa
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LTC3111
APPLICATIONS INFORMATION
ThebasicLTC3111applicationcircuitisshownonthefront
page of this data sheet. The external component selection
is dependent upon the required performance of the IC in
each particular application given trade-offs such as PCB
area, output voltages, output currents, ripple voltages,
and efficiency. This section of the data sheet provides
some basic guidelines and considerations to aid in the
selection of external components and the design of the
application circuit.
reaching the current limit value. However, in boost mode,
especially at large step-up ratios, the output current capa-
bility can also be limited by the total resistive losses in the
power stage. These include switch resistances, inductor
resistance, and PCB trace resistance. Use of an inductor
with high DC resistance can degrade the output current
capability from that shown in the graph in the Typical
Performance Characteristics section of this data sheet.
Differentinductorcorematerialsandstyleshaveanimpact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizesthechancesofinterferencewithothercircuitry.
The choice of inductor style depends upon the price,
sizing, and EMI requirements of a particular application.
Table 1 provides a small sampling of inductors that are
well suited to many LTC3111 buck-boost converter ap-
plications. Within each family (i.e., at a fixed size), the DC
resistance generally increases and the maximum current
generally decreases with increased inductance.
Inductor Selection
To achieve high efficiency, a low ESR inductor should be
utilizedforthebuck-boostconverter.Inaddition,thebuck-
boost inductor must have a saturation current rating that
is greater than the worst-case average inductor current
plus half the ripple current. The peak-to-peak inductor
current ripple for buck or boost mode operation can be
calculated from the following formulas:
VOUT V – V
1
f
IN
OUT
∆IL(P-P_BUCK)
=
•
•
– t
LOW
Table 1. Representative Buck-Boost Surface Mount Inductors
MAX DC
L
V
IN
VALUE
(μH)
DCR
(mΩ)
CURRENT
(A)
SIZE (mm)
W × L × H
IN
V
L
VOUT – V
VOUT
1
f
IN
PART NUMBER
∆IL(P-P_BOOST)
=
•
•
– t
LOW
Coilcraft
LPS6225
LPS6235
4.7
6.8
65
75
3.2
2.8
6.2 × 6.2 × 2.5
6.2 × 6.2 × 3.5
where f is the frequency in Hz and L is the inductance in
Cooper-Bussmann
FP3-8R2-R
CD1-150-R
Henries and t
is the switch pin minimum low time in
LOW
8.2
15
74
50
3.4
3.6
7.3 × 6.7 × 3.0
10.5 × 10.4 × 4.0
seconds, which is typically 160ns.
Sumida
In addition to affecting output current ripple, the inductor
value can also impact the stability of the feedback loop. In
boost mode, the converter transfer function has a right-
half-planezeroatafrequencythatisinverselyproportional
to the value of the inductor. As a result, a large inductance
can move this zero to a frequency that is low enough to
degrade the phase margin of the feedback loop. It is rec-
ommended that the inductor value be chosen less than
15μH if the converter is to be used in the boost region.
For 800kHz operation, a 4.7μH inductor is recommended
CDRH8D28/HP
CDRH8D28NP
10
78
3.0
3.4
8.3 × 8.3 × 3.0
8.3 × 8.3 × 3.0
4.7
24.7
TOKO
B1047AS-6R8N
B1179BS-150M
6.8
15
36
56
2.9
2.7
7.6 × 7.6 × 5.0
12.0 × 12.0 × 6.0
Würth
7447789004
744311470
4.7
4.7
33
19.5
2.9
6
7.3 × 7.3 × 3.2
6.9 × 6.9 × 3.8
Output Capacitor Selection
A low ESR output capacitor should be utilized at the
buck-boost converter output in order to minimize output
voltage ripple. Multilayer X5R and X7R dielectric ceramic
capacitorsareanexcellentchoiceastheyhavelowESRand
are available in small footprints. The capacitor should be
for 5V
and 10μH for 12V
.
OUT
OUT
The inductor DC resistance can impact the efficiency of
the buck-boost converter as well as the maximum output
current capability at low input voltage. In buck mode,
the output current is limited only by the inductor current
3111fa
15
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LTC3111
APPLICATIONS INFORMATION
Capacitor Vendor Information
chosenlargeenoughtoreducetheoutputvoltagerippleto
acceptable levels. The minimum output capacitor needed
for a given output voltage ripple (neglecting the capacitor
ESRandESL)canbecalculatedbythefollowingformulas:
Both the input bypass capacitors and output capacitors
used with the LTC3111 must be low ESR and designed
to handle the large AC currents generated by switching
converters.Thisisimportanttomaintainproperfunctioning
of the IC and to reduce input/output ripple. Many modern
low voltage ceramic capacitors experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for a
small surface mount ceramic capacitor to lose more than
50% of its rated capacitance when operated near its rated
voltage. As a result, it is sometimes necessary to use a
larger value capacitance or a capacitor with a larger case
size than required in order to actually realize the intended
capacitance at the full operating voltage. For details, con-
sult the capacitor vendor’s curve of capacitance versus
DC bias voltage.
ILOAD •tLOW
∆VP-P BUCK
=
(
)
COUT
IN
VOUT – V + tLOW •f•V
ILOAD
f•COUT
IN
∆VP-P BOOST
=
•
(
)
VOUT
where f is the frequency in Hz, C
is the output capaci-
OUT
tance in μF, I
is the output current in amps and t
LOAD
LOW
is the switch pin minimum low time in seconds, which is
typically 160ns.
In addition to output ripple generated across the output
capacitor, there is also output ripple produced across
the internal resistance of the output capacitor. The ESR-
generated output voltage ripple is proportional to the
series resistance of the output capacitor and is given by
the following expression:
ThecapacitorslistedinTable2provideasamplingofsmall
surface mount ceramic capacitors that are well suited to
LTC3111applicationcircuits.Alllistedcapacitorsareeither
X5R or X7R dielectric in order to ensure that capacitance
loss over temperature is minimized.
ILOAD •RESR
1– tLOW •f
∆VP-P BUCK
=
≅ ILOAD •RESR
(
)
Table 2. Representative Bypass and Output Capacitors
VALUE
(μF)
VOLTAGE SIZE (mm) L × W × H
ILOAD •RESR •VOUT ILOAD •RESR •VOUT
∆VP-P BOOST
=
≅
PART NUMBER
(V)
(FOOTPRINT)
(
)
V
1– t
•f
V
IN
IN
LOW
AVX
12103D226MAT2A
22
25
3.2 × 2.5 × 2.79
X5R Ceramic
where R
is the series resistor of the output capacitor
and all other terms are as previously defined.
ESR
Kemet
C220X226K3RACTU
22
22
25
16
5.7 × 5.0 × 2.4
X7R Ceramic
7.3 × 4.3 × 2.8
Al Poly, 25mΩ
Input Capacitor Selection
A700D226M016ATE030
It is recommended that a low ESR ceramic capacitor with
Murata
GRM32ER71E226KE15L
a value of at least 10μF be located as close to the V pin
IN
22
22
47
47
25
25
25
35
3.2 × 2.5 × 2.5
as possible. In addition, the return trace from the pin to
the ground plane should be made as short as possible.
It is important to minimize any stray resistance from the
converter to the battery or power source. If cabling is
required to connect the LTC3111 to the battery or power
supply, a higher ESR capacitor or a series resistor with a
low ESR capacitor in parallel with the low ESR capacitor
may be required to damp out ringing caused by the cable
inductance.
X7R Ceramic
Panasonic
ECJ-4YB1E226M
3.2 × 2.5 × 2.5
X5R Ceramic
Sanyo
25SVPF47M
6.6 × 6.6 × 5.9
OS-CON, 30mΩ
Vishay
94SVPD476X0035F12
10.3 × 10.3 × 12.6
OS-CON, 30mΩ
3111fa
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PCB Layout Considerations
2. The exposed pad is the power ground connection for
the LTC3111. Multiple vias should connect the back
pad directly to the ground plane. In addition maximi-
zation of the metallization connected to the back pad
will improve the thermal environment and improve the
power handling capabilities of the IC.
The LTC3111 switches large currents at high frequencies.
Special attention should be paid to the PCB layout to en-
sure a stable, noise-free and efficient application circuit.
Figure 4 presents a representative PCB layout to outline
some of the primary considerations. A few key guidelines
are outlined below:
3. The circled components and their connections should
all be placed over a complete ground plane to minimize
loop cross-sectional areas. This minimizes EMI and
reduces inductive drops.
1. Allcirculatinghighcurrentpathsshouldbekeptasshort
as possible. This can be accomplished by keeping the
routes to all circled components in the figure below
as short and as wide as possible. Capacitor ground
connections should via down to the ground plane in
the shortest route possible. The bypass capacitors on
4. Connections to all of the circled components should be
madeaswideaspossibletoreducetheseriesresistance.
This will improve efficiency and maximize the output
current capability of the buck-boost converter.
V should be placed as close to the IC as possible and
IN
should have the shortest possible paths to ground.
THERMAL AND
PGND VIAS
C
IN
C
OUT
C
C
BST2
BST1
Figure 4a. Top and Fabrication Layer of Example PCB
Figure 4b. Bottom and Fabrication Layer of Example PCB
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mum low time, which is typically 160ns. The parameter
S
stageandcanbeapproximatedastwicetheaveragepower
switch resistance plus the DC resistance of the inductor.
5. To prevent large circulating currents from disrupting
theoutputvoltagesensing, thegroundforeachresistor
divider should be returned to the ground plane using
a via placed close to the IC and away from the power
connections.
R represents the average series resistance of the power
GBUCK = GDIVIDER •GPWM •GPOWER
6. Keep the connection from the resistor dividers to the
feedback pins (FB pin) as short as possible and away
from the switch pin connections.
18
GDIVIDER
=
V
IN
7. Crossoverconnectionsshouldbemadeoninnercopper
layers if available. If it is necessary to place these on
the ground plane, make the trace on the ground plane
as short as possible to minimize the disruption to the
ground plane.
GPWM = 2.5• 1– t
•f
(
)
LOW
V •R
•f • R+ R
) (
IN
GPOWER
=
1– t
(
)
LOW
S
Notice that the gain of the analog divider cancels the input
voltage dependence of the power stage. As a result, the
buck mode gain is approximated by a constant as given
by the following equation:
Buck Mode Small-Signal Model
TheLTC3111usesavoltagemodecontrollooptomaintain
regulation of the output voltage. An externally compen-
sated error amplifier drives the COMP pin to generate the
appropriate duty cycle of the power switches. Use of an
external compensation network provides the flexibility for
optimization of closed-loop performance over the wide
variety of output voltages, switching frequencies, and
external component values supported by the LTC3111.
R
R+ RS
GBUCK = 45•
≅ 45= 33dB
The buck mode transfer function has a single zero which
is generated by the ESR of the output capacitor. The zero
frequency, f , is given by the following expression where
Z
The small-signal transfer function of the buck-boost con-
verterisdifferentinthebuckandboostmodesofoperation
andcaremustbetakentoensurestabilityinbothoperating
regions. When stepping down from a higher input voltage
to a lower output voltage, the converter will operate in
buck mode and the small-signal transfer function from
the error amplifier output COMP, to the converter output
voltage is given by the following equation:
R and C are the ESR and value of the output filter ca-
C
O
pacitor respectively.
1
fZ =
2•π •RC •CO
In most applications, an output capacitor with a very low
ESR is utilized in order to reduce the output voltage ripple
to acceptable levels. Such low values of capacitor ESR
result in a very high frequency zero and as a result the zero
is commonly too high in frequency to significantly impact
compensation of the feedback loop. The denominator of
thebuckmodetransferfunctionexhibitsapairofresonant
poles generated by the LC filtering of the power stage. The
s
1+
VO
VCOMP
2•π •fZ
= GBUCK
2
BUCK
s
s
1+
+
2•π •fO •Q 2•π •f
O
resonant frequency of the power stage, f , is given by the
The gain term, G
, is comprised of three different
O
BUCK
following expression where L is the value of the inductor:
components: the gain of the analog divider, the gain of the
pulse-width modulator, and the gain of the power stage as
1
R+ RS
1
given by the following expressions where V is the input
fO =
•
≅
IN
2•π L•C R+ R
2•π • L•CO
(
)
O
C
voltage to the converter, f is the switching frequency, R
is the load resistance, and t
is the switch pin mini-
LOW
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The quality factor, Q, has a significant impact on compen-
sation of the voltage loop since a higher Q factor produces
a sharper loss of phase near the resonant frequency. The
qualityfactorisinverselyrelatedtotheamountofdamping
in the power stage and is substantially influenced by the
the same as in buck mode operation, but the gain of the
analog divider and power stage in boost mode are given
by the following equation:
18
VOUT
GDIVIDER
=
average series resistance of the power stage, R . Lower
S
2
values of R will increase the Q and result in a sharper
S
VOUT
GPOWER
=
loss of phase near the resonant frequency and will require
more phase boost or lower bandwidth to maintain an
adequate phase margin.
1– t
•f •V
(
)
IN
LOW
By combining the individual terms, the total gain in boost
mode can be reduced to the following expression. Notice
that unlike in buck mode, the gain in boost mode is a
function of both the input and output voltage:
L•C R+ R • R+ R
(
C ) (
)
O
S
Q =
R•R •C + L+ C •R • R+ R
(
)
C
O
O
S
C
VOUT
L•CO
GBOOST = 45•
≅
V
L
R
IN
+ CO •RS
In boost mode operation, the frequency of the right-half-
plane zero, f
, is given by the following expression.
RHPZ
Boost Mode Small-Signal Model
The frequency of the right-half-plane zero decreases at
higher loads and with larger inductors:
When stepping up from a lower input voltage to a higher
output voltage, the buck-boost converter will operate in
boost mode where the small-signal transfer function from
control voltage, V
the following expression:
•f 2 •V
2
R• 1– t
(
)
IN
LOW
fRHPZ
−
2
, to the output voltage is given by
2•π •L•VOUT
COMP
In boost mode, the resonant frequency of the power stage
hasadependenceontheinputandoutputvoltageasshown
by the following equation:
• 1–
s
s
1+
2•π •f
2•π •f
VO
Z
RHPZ
= GBOOST
2
O
VCOMP BOOST
s
s
2
R•V
IN
1+
+
RS +
2•π •fO •Q 2•π •f
2
1
VOUT
1
V
1
IN
fO =
•
≅
•
•
2•π L•C • R+ R
2•π VOUT
L•CO
(
)
O
C
Inboostmodeoperation,thetransferfunctionischaracter-
izedbyapairofresonantpolesandazerogeneratedbythe
ESR of the output capacitor as in buck mode. However, in
addition there is a right-half-plane zero which generates
increasing gain and decreasing phase at higher frequen-
cies. As a result, the crossover frequency in boost mode
operation generally must be set lower than in buck mode
in order to maintain sufficient phase margin.
Finally, the magnitude of the quality factor of the power
stage in boost mode operation is given by the following
expression:
2
R•V
IN
L•CO •R• RS +
2
VOUT
Q =
L+ CO •RS •R
The boost mode gain, G
, is comprised of three
BOOST
components: the analog divider, the pulse width modula-
tor and the power stage. The gain of the PWM remains
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Compensation Of The Voltage Loop
GAIN
The small-signal models of the LTC3111 reveal that the
transfer function from the error amplifier output, COMP,
to the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 5.
In boost mode operation, there is an additional right-half-
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency is
low enough that the phase loss from the right-half-plane
zero is minimized. The low frequency gain in buck mode
–40dB/DEC
–20dB/DEC
PHASE
BUCK MODE
BOOST MODE
f
f
3111 F05
O
RHPZ
is a constant, but varies with both V and V
in boost
IN
OUT
mode.
Figure 5: Buck-Boost Converter Bode Plot
For charging or other applications that do not require an
optimized output voltage transient response, a simple
Type I compensation network as shown in Figure 6 can
be used to stabilize the voltage loop. To ensure sufficient
phase margin, the gain of the error amplifier must be low
enoughthattheresultantcrossoverfrequencyofthecontrol
loop is well below the resonant frequency.
V
OUT
LTC3111
R1
0.8V
FB
+
–
C1
COMP
R2
SGND
3111 F06
Inmostapplications, thelowbandwidthoftheTypeIcom-
pensatedloopwillnotprovidesufficienttransientresponse
performance. To obtain a wider bandwidth feedback loop,
optimize the transient response, and minimize the size of
the output capacitor, a Type III compensation network as
shown in Figure 7 is required.
Figure 6: Error Amplifier with Type I Compensation
V
OUT
A Bode plot of the typical Type III compensation network
is shown in Figure 8. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
LTC3111
R
FF
C
R1
0.8V
FB
+
–
FF
regulation voltage. Two zeros located at f
and f
C
FB
ZERO1
ZERO2
R
FB
COMP
R2
provide sufficient phase boost to allow the loop crossover
C
POLE
frequency to be set above the resonant frequency, f , of
SGND
O
3111 F07
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency f
, reduces the error amplifier gain to a
POLE2
Figure 7: Error Amplifier with Type III Compensation
zero slope to prevent the loop crossover from extending
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where all frequencies are in Hz, resistances are in ohms,
and capacitances are in farads.
GAIN
1
fZERO1
fZERO2
fPOLE2
=
=
=
–20dB/DEC
2•π •RFB •CFB
–20dB/DEC
1
1
≅
2•π R1+ R •C
2•π •R1•CFF
(
)
FF
FF
1
1
PHASE
≅
CFB •CPOLE
CFB + CPOLE
2•π •RFB •CPOLE
2•π •
•RFB
f
3111 F08
f
f
f
ZERO1
POLE2 POLE3
f
ZERO2
1
fPOLE3
=
Figure 8: Type III Compensation Bode Plot
2•π •RFF •CFF
too high in frequency. The third pole at frequency f
Inmostapplicationsthecompensationnetworkisdesigned
sothattheloopcrossoverfrequencyisabovetheresonant
frequency of the power stage, but sufficiently below the
boostmoderight-half-planezerotominimizetheadditional
phaseloss.Oncethecrossoverfrequencyisdecidedupon,
the phase boost provided by the compensation network
is centered at that point in order to maximize the phase
margin. A larger separation in frequency between the
zeros and higher order poles will provide a higher peak
phase boost but may also increase the gain of the error
amplifier which can push out the loop crossover to a
higher frequency.
POLE3
provides attenuation of high frequency switching noise.
The transfer function of the compensated Type III error
amplifierfromtheinputoftheresistordividertotheoutput
of the error amplifier, COMP, is:
s
s
1+
• 1+
ZERO1
2•π •f
2•π •f
VCOMP
VO
ZERO2
s
= GCOMP
•
s
s• 1+
• 1+
POLE2
2•π •f
2•π •f
POLE3
The compensation gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determineshowrapidlythe180°ofphaselossinthepower
most cases since C is typically much larger in value
FB
than C
.
POLE
1
1
stage occurs. For very low values of series resistance, R ,
S
GCOMP
≅
≅
R1• C + C
R1•CFB
(
)
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to–180°abovetheresonantfrequencyandthetotalphase
margin must be provided by the compensation network.
FB
POLE
ThepoleandzerofrequenciesoftheTypeIIIcompensation
network can be calculated from the following equations
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theworst-caseinductorcurrentrippletolessthan1Apeak
to peak. A low ESR output capacitor with a value of 22µF
is specified to yield a worst-case output voltage ripple
(occurring at the worst-case step-up ratio and maximum
load current) of approximately 20mV. In summary, the
key power stage specifications for this LTC3111 example
application are given below.
However, with higher losses in the power stage (larger
R ) the Q factor will be lower and the phase loss will occur
S
more gradually. As a result, the power stage phase will
not be as close to –180° at the crossover frequency and
lessphaseboostisrequiredofthecompensationnetwork.
The LTC3111 error amplifier is designed to have a fixed
maximum bandwidth in order to provide rejection of
switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated
in Figure 9. The nominal frequency of this pole is 400kHz.
For typical loop crossover frequencies below about 60kHz
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
f = 0.8MHz, t
= 160ns
LOW
V = 3.5V to 15V
IN
V
OUT
C
OUT
= 5V at R = 10Ω
= 22µF, R = 10mΩ
C
L = 4.7µH, R = 25mΩ
L
R = 200mΩ
S
With the power stage parameters specified, the compen-
sation network can be designed. In most applications,
the most challenging compensation corner is boost
mode operation at the greatest step-up ratio and highest
load current since this generates the lowest frequency
right-half-plane zero and results in the greatest phase
loss. Therefore, a reasonable approach is to design the
compensation network at this worst-case corner and then
verify that sufficient phase margin exists across all other
LTC3111
R
FILT
0.8V
FB
+
–
C
FILT
COMP
3111 F09
Figure 9. Internal Loop Filter
operating conditions. In this example application, at V =
IN
3.5V and the full 500mA load current, the right-half-plane
zero will be located at 136kHz and this will be a dominant
factor in determining the bandwidth of the control loop.
Loop Compensation Example
This section provides an example illustrating the design of
acompensationnetworkforatypicalLTC3111application
circuit. In this example a 5V regulated output voltage is
generated with the ability to supply a 500mA load from an
input power source ranging from 3.5V to 15V. To reduce
switching losses a 800kHz switching frequency has been
chosen for this example. In this application the maximum
inductor current ripple will occur at the highest input volt-
age. An inductor value of 4.7µH has been chosen to limit
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
a phase margin of 60°, the loop crossover frequency, f ,
C
should be selected as the frequency at which the phase
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of the buck-boost converter reaches –180°. As a result, at
theloopcrossoverfrequencythetotalphasewillbesimply
the 60° of phase provided by the error amplifier as shown:
model equations using LTspice® software. In this case,
the phase reaches –180° at 40kHz making f = 40kHz the
C
target crossover frequency for the compensated loop.
Phase Margin = ϕ
+ ϕ
+ 180°
ERRORAMPLIFIER
FromtheBodeplotofFigure10thegainofthepowerstage
at the target crossover frequency is 13.5dB. Therefore, in
order to make this frequency the crossover frequency in
BUCK-BOOST
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches –195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
the compensated loop, the total loop gain at f must be
C
adjusted to 0dB. To achieve this, the gain of the compen-
sation network must be designed to be –13.5dB at the
crossover frequency.
At this point in the design process, there are three con-
straints that have been established for the compensation
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
network.Itmusthave–13.5dBofgainatf =40kHz,apeak
C
phase boost of 60° that is centered at f = 40kHz. One way
C
crossover frequency, f , will be the point at which the
to design a compensation network to meet these targets
is to simulate the compensation error amplifier Bode plot
in LTspice for the typical compensation network shown
on the front page of this data sheet. Then, the gain, pole
and zero frequencies can be iteratively adjusted until the
required constraints are met. Alternatively, an analytical
approach can be used to design a compensation network
with the desired phase boost, center frequency and gain.
In general, this procedure can be cumbersome due to the
large number of degrees of freedom in the Type III com-
pensation network. However the design process can be
simplified by assuming that both the compensation zeros
C
phase of the buck-boost converter reaches –180°. It is
generally difficult to determine this frequency analytically
given that it is significantly impacted by the Q factor of
the resonance in the power stage. As a result, it is best
determined from a Bode plot of the buck-boost converter
as shown in Figure 10. This Bode plot is for the LTC3111
buck-boostconverterusingthepreviouslyspecifiedpower
stageparametersandwasgeneratedfromthesmall-signal
40
30
90
45
GAIN
20
0
occur at the same frequency, f , and both higher order
Z
poles (f
P
and f
) occur at the common frequency,
f . In most cases this is a reasonable assumption since
10
–45
–90
–135
–180
–255
–270
POLE2
POLE3
PHASE
0
the zeros are typically located between 1kHz and 10kHz
and the poles are typically located neareachother at much
higher frequencies. Given this assumption, the maximum
phaseboost,providedbythecompensationerroramplifier
isdeterminedsimplybytheamountofseparationbetween
the poles and zeros as shown by the following equation:
–10
–20
–30
–40
f
= 40kHz
10k
C
10
100
1k
100k
1M
(Hz)
3111 F10
fP
fZ
Figure 10. Converter Bode Plot VIN = 3.5V, VOUT = 5V, R = 10Ω
φMAX = 4•arctan
–270°
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This equation completes the set of constraints needed to
determine the compensation component values. Specifi-
A reasonable choice is to pick the frequency of the poles,
f , to be 50 times higher than the frequency of the zeros,
P
cally, the two zeros, f
and f
, should be located
f , which provides a peak phase boost of approximately
ZERO1
ZERO2
Z
near 5.71kHz. The two poles, f
and f
, should be
POLE3
60° as was assumed previously. Next, the phase boost
must be centered so that the peak phase occurs at the
targetcrossoverfrequency.Thefrequencyofthemaximum
POLE2
located near 280kHz and the gain should be set to provide
a gain at the crossover frequency of G = –13.5dB.
CENTER
phase boost, f
, is the geometric mean of the pole
CENTER
and zero frequency as:
The first step in defining the compensation component
values is to pick a value for R1 that provides an acceptably
low quiescent current through the resistor divider. A value
fCENTER = fP •fZ = 50 •fZ ≅ 7•fZ
of R1 = 1MΩ is a reasonable choice. Next, the value of C
FB
can be found in order to set the error amplifier gain at the
Therefore, inordertocenterthephaseboostgivenafactor
of 50 separation between the pole and zero frequencies,
thezeroshouldbelocatedatone-seventhofthecrossover
frequencyandthepolesshouldbelocatedatseventhtimes
thecrossoverfrequencyasgivenbythefollowingequation:
crossover frequency to –13.5dB as follows:
50
GCENTER = –13.5dB= 20•log
2•π •40kHz •1MΩ•CFB
50
fC 40kHz
CFB =
≅ 1000pF
fZ =
=
= 5.71kHz
2•π •40kHz •1MΩ •10–13.5
7
7
20
fP = 7•fC = 7•40kHz = 280kHz
The compensation poles can be set at 280kHz and the
zeros at 5.71kHz by using the expressions for the pole and
zero frequencies given in the previous sections. Setting
the frequency of the first zero, f
in the following value for R :
Thisplacementofthepolesandzeroswillyieldapeakphase
boost of 60° that is centered at the crossover frequency,
f . Next, in order to produce the desired target crossover
, to 5.71kHz results
ZERO1
C
frequency, the gain of the compensation network at the
FB
point of maximum phase boost, G
, must be set to
CENTER
1
–13.5dB. The gain of the compensated error amplifier at
the point of the phase gain is given by:
RFB =
≅ 28.0kΩ
2•π •5.71kHz•1000pF
This leaves the free parameter, C
POLE1
, to set frequency
POLE
2•π •fP
GCENTER = 10•log
dB
f
to the common pole frequency of 280kHz as given:
2
2•π •f 3 • R1•C
(
Z ) (
)
FB
1
CPOLE
=
≅ 22pF
2•π •280kHz •28kΩ
Assuming a multiple of 50 separation between the pole
and zero frequencies this can be simplified to the follow-
ing expression:
50
GCENTER = 20•log
dB
2•π •f •R1•C
FB
C
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40
30
90
45
0
Next, C can be chosen to set the second zero, f
, to
FF
ZERO2
the common zero frequency of 5.71kHz.
40kHz, 57°
PHASE
20
1
40kHz, –14dB
GAIN
CFF =
≅ 27pF
10
2•π •5.71kHz•1MΩ
0
Finally, the resistor value R can be chosen to place the
FF
–10
–20
–30
–40
second pole at 280kHz.
–45
1
RFF =
≅ 20kΩ
2•π •280kHz •27pF
–90
1M
10
100
1k
10k
100k
(Hz)
Now that the pole frequencies, zero frequencies and gain
of the compensation network have been established, the
next step is to generate a Bode plot for the compensated
error amplifier to confirm its gain and phase properties.
A Bode plot of the error amplifier with the designed com-
pensation component values is shown in Figure 11. The
Bode plot confirms that the peak phase occurs at 40kHz
and the phase boost at that point is 57°. In addition, the
gain at the peak phase frequency is –14dB which is close
to the design target.
3111 F11
Figure 11: Compensation Error Amplifier Bode Plot
60
50
40
30
180
135
90
40kHz, 59°
PHASE
GAIN
45
20
10
0
–45
0
–10
–20
–30
–40
–90
The final step in the design process is to compute the
Bode plot for the entire designed compensation network
and confirm its phase margin and crossover frequency.
The complete loop Bode plot for this example is shown
in Figure 12. The loop crossover frequency is 40kHz and
the phase margin is approximately 59°.
–135
–180
–225
–270
10
100
1k
10k
100k
1M
(Hz)
3111 F12
TheBodeplotforthecompleteloopshouldbecheckedover
all operating conditions and for variations in component
values to ensure that sufficient phase margin exist in all
cases. The stability of the loop should also be confirmed
via time domain simulation and by the transient response
of the converter in the actual circuit.
Figure 12: Complete Loop Bode Plot
3111fa
25
For more information www.linear.com/LTC3111
LTC3111
TYPICAL APPLICATIONS
1, 2, 3 Li-Ion to 5V
4.7µH
0.1µF
0.1µF
26.1k
SW1
SW2
V
BST1
BST2
OUT
5V
V
IN
V
IN
V
OUT
750mA
3V TO 12.6V
680pF
27pF
10µF
22µF
V
LTC3111
> 4V
+
IN
20k
33pF
1 TO 3-CELL
Li-Ion
COMP
FB
1M
BURST PWM
PWM/SYNC
RUN
R
191k
SNSGND
SGND
NUMBER
OF CELLS
V
CC
PGND
R
1µF
3111 TA02a
1
2
3
274k
698k
1.13M
154k
Wide VIN to 5VOUT Efficiency
100
90
80
70
60
50
40
30
V
V
V
= 3.6V
= 7.2V
= 10.8V
IN
IN
IN
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3111 TA02b
3111fa
26
For more information www.linear.com/LTC3111
LTC3111
TYPICAL APPLICATIONS
LTC3111 Synchronized to a 1.5MHz Clock, 5V/1A Output
2.2µH
0.1µF
0.1µF
SW1
SW2
V
BST1
BST2
OUT
5V
1A
V
V
IN
V
IN
V
OUT
2.5V TO 15V
270pF
10µF
22µF
LTC3111
> 5V
57.6k
1µF
IN
COMP
FB
1M
1.5MHz CLOCK
15pF
PWM/SYNC
RUN
MBR0520L
OPTIONAL
OFF ON
191k
SNSGND
SGND
V
CC
PGND
3111 TA03a
PWM/SYNC
5V/DIV
SW1
10V/DIV
SW2
5V/DIV
INDUCTOR
CURRENT
1A/DIV
3111 TA03b
500ns/DIV
3.3V Backup from a High Voltage Capacitor Bank Runs Down to VIN = 2V with 500mA Load
4.7µH
0.1µF
0.1µF
SW1
SW2
BST1
BST2
V
OUT
V
IN
3.3V
V
IN
V
OUT
2V TO 15V
1600pF
33pF
C
500mA
IN
100µF
33µF
LTC3111
24.3k
V
214mF
CC
20k
36pF
COMP
1M
PWM/SYNC
RUN
MBR0520L
OPTIONAL
FB
V
CC
316k
SNSGND
SGND
V
CC
1µF
PGND
3111 TA04a
POWER SUPPLY REMOVED
V
IN
5V/DIV
V
OUT
2V/DIV
I
OUT
500mA/DIV
3111 TA04b
2 SEC/DIV
3111fa
27
For more information www.linear.com/LTC3111
LTC3111
TYPICAL APPLICATIONS
Stepped Response from 1 or 2 Li-Ion to 12V Adapter Source VOUT = 5V
1- OR 2-SERIES
Li-Ion CELLS
4.7µH
LT®4352
IDEAL
DIODE
0.1µF
0.1µF
26.1k
SW1
SW2
B520C
V
BST1
BST2
OUT
5V
12V
ADAPTER
V
IN
V
OUT
1.5A
680pF
27pF
47µF
22µF
LTC3111
V
IN
> 5V
20k
33pF
COMP
1M
BURST PWM
OFF ON
PWM/SYNC
RUN
FB
191k
V
SNSGND
SGND
CC
1µF
PGND
3111 TA05a
V
OUT
500mV/DIV
V
IN
2V/DIV
TWO Li-Ion CELLS
INDUCTOR
CURRENT
1A/DIV
3111 TA05b
I
= 500mA
1ms/DIV
OUT
Custom Input Undervoltage Lockout Thresholds
4.7µH
0.1µF
0.1µF
SW1
SW2
BST1
BST2
V
OUT
V
IN
5V
V
V
OUT
IN
5V TO 15V
680pF
27pF
1.5A
10µF
22µF
LTC3111
26.1k
20k
33pF
V
CC
COMP
1M
ENABLED WHEN
REACHED 5V
PWM/SYNC
RUN
1M
V
IN
FB
DISABLED WHEN V
FALLS BELOW 4.5V
V
CC
IN
316k
191k
V
CC
SNSGND
SGND
1µF
PGND
3111 TA08a
V
IN
V
IN
10V/DIV
10V/DIV
V
V
OUT
OUT
5V/DIV
5V/DIV
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
3111 TA08b
3111 TA08c
R
LOAD
= 3.3Ω
2ms/DIV
R
LOAD
= 3.3Ω
2ms/DIV
3111fa
28
For more information www.linear.com/LTC3111
LTC3111
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ±0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ±0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3111fa
29
For more information www.linear.com/LTC3111
LTC3111
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3111fa
30
For more information www.linear.com/LTC3111
LTC3111
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
1/14
Clarified graphs
1, 4, 5, 6
3111fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3111
TYPICAL APPLICATION
Regulated 12V Output from Wide Range Input Supply
Wide VIN to 12VOUT Efficiency
100
90
80
70
60
50
40
30
PWM
10µH
BURST
0.1µF
0.1µF
SW1
SW2
V
BST1
BST2
OUT
12V
V
IN
V
IN
V
OUT
0.5A, V > 5V
2.5V TO 15V
IN
1000pF
39pF
10µF
22µF
1.0A, V > 9V
IN
LTC3111
44.2k
20k
18pF
V
CC
COMP
2.21M
BURST PWM
OFF ON
PWM/SYNC
RUN
FB
V
V
= 5V
IN
IN
158k
SNSGND
SGND
V
CC
= 12V
1µF
PGND
3111 TA06a
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3111 TA06b
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
V : 1.8V to 5.5V, V : 1.8V to 5.25V, I = 40μA, I < 1μA, DFN Package
LTC3533
LTC3113
LTC3534
2A (I ), 2MHz Synchronous Buck-Boost DC/DC
OUT
Converter
IN
OUT
Q
SD
3A (I ), 2MHz Low Noise Buck-Boost DC/DC
V : 1.8V to 5.5V, V : 1.8V to 5.5V, I = 40μA, I < 1μA, DFN and TSSOP
OUT
IN
OUT
Q
SD
Converter
Packages
7V, 500mA (I ), Synchronous Buck-Boost DC/DC V : 2.4V to 7V, V : 1.8V to 7V, I = 25μA, I < 1μA, DFN and GN Packages
OUT
IN
OUT
Q
SD
Converter
LTC3129/
LTC3129-1
15V, 200mA (I ), Synchronous Buck-Boost DC/DC V : 2.42V to 15V, V : 1.4V to 15.75V, I = 1.3μA, I < 100nA, QFN and
OUT
IN
OUT
Q
SD
Converter with 1.3µA Quiescent Current
MSOP Packages
LTC3112
15V, 2.5A (I ), Synchronous Buck-Boost DC/DC
V : 2.7V to 15V, V
= 5V, I = 50μA, I < 1μA, DFN and TSSOP Packages
OUT Q SD
OUT
IN
Converter
LTC3785
10V, High Efficiency, Synchronous, No R
Buck-Boost Controller
™
SENSE
V : 2.7V to 10V, V : 2.7V to 10V, I = 86μA, I < 15μA, QFN Package
IN
OUT
Q
SD
LTC3115-1/
LTC3115-2
40V, 2A (I ), Synchronous Buck-Boost DC/DC
V : 2.7V to 40V, V
= 2.7V to 40V, I = 30μA, I < 1μA, DFN and TSSOP
Q SD
OUT
IN
OUT
Converter
Packages
LTC3789
High Efficiency, Synchronous, 4-Switch Buck-Boost V : 4V to 38V, V : 0.8V to 38V, I = 3mA, I < 60μA, QFN and SSOP
IN
OUT
Q
SD
Converter
Packages
LTC3122
15V, 2.5A (I ), Synchronous Step-Up DC/DC
V :1.8V to 5.5V, V : 2.2V to 15V. I = 25µA, I < 1µA, DFN and MSOP
OUT
IN
OUT
Q
SD
Converter with Output Disconnect
Packages
3111fa
LT 0114 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3111
LINEAR TECHNOLOGY CORPORATION 2013
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