LTC3255HMSE#PBF [Linear]
LTC3255 - Wide VIN Range Fault Protected 50mA Step-Down Charge Pump; Package: MSOP; Pins: 10; Temperature Range: -40°C to 125°C;
| 型号： | LTC3255HMSE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3255 - Wide VIN Range Fault Protected 50mA Step-Down Charge Pump; Package: MSOP; Pins: 10; Temperature Range: -40°C to 125°C 光电二极管 |
| 文件： | 总16页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3255
Wide V Range
IN
Fault Protected 50mA
Step-Down Charge Pump
FEATURES
DESCRIPTION
The LTC®3255 is a switched-capacitor step-down DC/DC
converter that produces a regulated output (2.4V to 12.5V
adjustable) from a 4V to 48V input. In applications where
the input voltage exceeds twice the output voltage, 2:1
capacitivechargepumpingextendsoutputcurrentcapabil-
ity beyond input supply current limits. At no load, Burst
n
Input Voltage Range: 4V to 48V
n
Adjustable Regulated Output: 2.4V to 12.5V
n
Output Current: 50mA Maximum
n
16μA Quiescent Current in Regulation at No Load
n
Input Fault Protection from –52V to 60V
n
Multimode Charge Pump (2:1, 1:1) with Automatic
Mode Switching Maintains Regulation Over Wide
Mode® operation cuts V quiescent current to 16µA.
IN
V Range
IN
With its integrated V shunt regulator, the LTC3255
IN
n
n
n
n
n
Input Voltage Shunt Mode for Current-Fed Applications
excels in 4mA to 20mA current loop applications. The
device enables current multiplication; a 4mA input current
can power a 7.4mA load continuously. Alternatively, the
LTC3255 serves as a higher efficiency replacement for
linear regulators and provides a space-saving inductor-
free alternative to buck DC/DC converters.
Power Good Output
Overtemperature and Short-Circuit Protection
Operating Junction Temperature: 150°C Maximum
Thermally Enhanced 10-Lead MSOP and 10-Lead
(3mm × 3mm) DFN packages
APPLICATIONS
The LTC3255 withstands reverse-polarity input supplies
and output short-circuits without damage. Safety features
including current limit and overtemperature protection
further enhance robustness. The LTC3255 is available in
thermally enhanced 10-lead MSOP and low profile 3mm
× 3mm 10-lead DFN packages.
n
Industrial Control, Factory Automation, Sensors, and
SCADA Systems
n
Housekeeping Power Supplies
n
Current-Boosting Voltage Regulators for 4mA to
20mA Current Loops
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Available Output Current
vs Input Current
7.4mA DC Supply from 4mA to 20mA Current Loop
40
37
34
1µF
OUTPUT
+
–
31
C
C
+
3.3V
V
V
OUT
IN
28
7.4mA
AVAILABLE
EN
LTC3255
220k
PGOOD
25
22
19
16
13
10
7
INCREASED
CAPABILITY
I
OUT
I
OUT
PGOOD
FB
4mA TO 20mA INPUT
>10V COMPLIANCE
1µF
10µF
SHUNT
BIAS
2.15M
1.21M
GND
INPUT
CURRENT
0.1µF
3255 TA01a
–
4
4
6
8
10 12 14 16 18 20
INPUT CURRENT (mA)
3255 TA01b
3255f
1
For more information www.linear.com/LTC3255
LTC3255
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
V , EN........................................................ –52V to 60V
I
When V
< 0V (Note 5) .....................100µA
PGOOD
IN
PGOOD
V
OUT
V
OUT
..........................................................................15V
Short-Circuit Duration (Note 6) ............... Indefinite
Operating Junction Temperature
Range (Notes 3, 6)................................. –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
I
When V
< 0V (Note 4).............................50mA
VOUT
OUT
FB ............................................................................. 6V
PGOOD......................................................................15V
MSE Only..........................................................300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
+
+
C
1
2
3
4
5
10
9
V
C
IN
–
C
1
2
3
4
5
10
9
V
C
GND
BIAS
EN
IN
–
V
OUT
FB
V
OUT
FB
SHUNT
PGOOD
11
11
GND
8
8
GND
BIAS
EN
GND
7
6
SHUNT
PGOOD
7
6
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
T
= 150°C, θ = 40°C/W
JA
JMAX
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
T
= 150°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3255EDD#PBF
LTC3255IDD#PBF
LTC3255HDD#PBF
LTC3255MPDD#PBF
LTC3255EMSE#PBF
LTC3255IMSE#PBF
LTC3255HMSE#PBF
LTC3255MPMSE#PBF
TAPE AND REEL
PART MARKING*
LGHD
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3255EDD#TRPBF
LTC3255IDD#TRPBF
LTC3255HDD#TRPBF
LTC3255MPDD#TRPBF
LTC3255EMSE#TRPBF
LTC3255IMSE#TRPBF
LTC3255HMSE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LGHD
LGHD
LGHD
LTGHF
LTGHF
10-Lead Plastic MSOP
LTGHF
10-Lead Plastic MSOP
LTC3255MPMSE#TRPBF LTGHF
10-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3255f
2
For more information www.linear.com/LTC3255
LTC3255
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
4
TYP
MAX
48
UNITS
l
l
V
V
V
Input Voltage Range (Note 7)
Output Voltage Range
V
V
IN
2.4
12.5
2.7
OUT
V
Undervoltage Lockout Threshold
V Rising, SHUNT = GND
IN
Hysteresis, SHUNT = GND
2.4
50
V
mV
UVLO_BK
IN
with Shunt Disabled
V
V
Undervoltage Lockout Threshold
V Rising, SHUNT= BIAS
IN
5
5.7
V
UVLO_SH
VIN
IN
with Shunt Enabled
V Quiescent Current
IN
Hysteresis, SHUNT= BIAS
200
mV
I
EN Low
EN High, SHUNT = GND
EN High, SHUNT = BIAS
Shutdown
Enabled, Output in Regulation
Enabled, Output in Regulation
3
16
30
6
35
45
µA
µA
µA
I
Available Output Current
Shunt Disabled
Shunt Enabled
VOUT
l
l
SHUNT = GND
50
7.4
mA
mA
SHUNT = BIAS, I = 4mA, V
= 3.3V
OUT
7.8
VIN
l
V
Regulated Feedback Voltage
FB Pin Leakage
1.176
1.200
1.224
10
V
nA
V
FB
I
FB
V
= 1.3V
FB
l
l
V
V
EN High Level Input Voltage
EN Low Level Input Voltage
EN Pin Input Current
1.4
EN_VIH
0.4
V
EN_VIL
I
EN
V
V
= 12V
= 0V
0
0
1
1
µA
µA
EN
EN
I
f
V
Current Limit
OUT
120
500
94
mA
kHz
%
LIM
Oscillator Frequency
OSC
l
l
V
V
PGOOD Rising Threshold
PGOOD Output Low Voltage
PGOOD High Impedance Leakage
% of Final Regulation Voltage
90
98
0.4
1
PGTHRESH
I
= 200µA
= 12V
0.1
V
PG(LOW)
PGOOD
V
µA
PGOOD
Note 4: The LTC3255 has an internal diode that conducts whenever V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
OUT
is pulled below GND. When so pulled, absolute maximum current out of
is 50mA.
V
OUT
Note 5: The LTC3255 has an internal diode that conducts whenever
PGOOD is pulled below GND. When so pulled, absolute maximum current
out of PGOOD is 100µA.
Note 2: All voltages are referenced to GND unless otherwise specified.
Note 3: The LTC3255E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3255I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3255H is guaranteed over the –40°C to 150°C
operating junction temperature range. The LTC3255MP is guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 6: This IC has overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 7: This IC has input overvoltage protection that shuts down the
device whenever V exceeds the specified input voltage range. Shutdown
IN
typically occurs when V exceeds 52V. V subsequently must fall below
IN
IN
50V (typical) for the IC to re-enable.
The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in Watts) according to
A
D
the formula:
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
3255f
3
For more information www.linear.com/LTC3255
LTC3255
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Input Operating Current
vs Input Voltage
Input Operating Current
vs Temperature
Input Shutdown Current
vs Input Voltage
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
EN = GND
SHUNT = GND
V
V
= 12V
= 5V
IN
OUT
SHUNT = GND
V
T
= 5V
OUT
A
= 25°C
150°C
125°C
25°C
–55°C
40
0
0
0
0
20
30
(V)
50
60
60
90 120 150
10
–60
0
30
–30
5
10 15 20 25 30 35 40 45 50
V
TEMPERATURE (°C)
V
(V)
IN
IN
3255 G03
3255 G02
3255 G01
FB Pin Regulation Voltage
vs Input Voltage (IOUT = 1mA)
FB Pin Regulation Voltage
vs Input Voltage (IOUT = 50mA)
FB Pin Regulation Voltage
vs Temperature
1.224
1.220
1.216
1.212
1.208
1.204
1.200
1.196
1.192
1.188
1.184
1.180
1.176
1.224
1.220
1.216
1.212
1.208
1.204
1.200
1.196
1.192
1.188
1.184
1.180
1.176
1.224
1.220
1.216
1.212
1.208
1.204
1.200
1.196
1.192
1.188
1.184
1.180
1.176
I
= 1mA
= 5V
I
= 50mA
= 5V
V
I
OUT
= 12V
OUT
OUT
OUT
IN
V
V
OUT
= 1mA
OUT
SHUNT = GND
SHUNT = GND
V
= 5V
–60°C
–60°C
25°C
105°C
25°C
105°C
150°C
5
10 15 20 25 30 35 40 45 50
(V)
5
10 15 20 25 30 35 40 45 50
(V)
–60
0
30
60
90 120 150
–30
V
V
IN
TEMPERATURE (°C)
IN
3255 G04
3255 G05
3255 G06
Operating Mode Transition
Voltage vs Input Voltage
(IOUT = 5mA)
Operating Mode Transition
Voltage vs Input Voltage
(IOUT = 50mA)
Typical Minimum VIN – 2 • VOUT
Compliance Required for Shunt
Mode Operation
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
25
23
21
19
17
15
13
11
9
25
23
21
19
17
15
13
11
9
I
= 20mA
SHUNT = GND
SHUNT = GND
VIN
2:1 MODE
2:1 MODE
1:1 MODE
1:1 MODE
•
•
TRANSITION
REGION
TRANSITION
REGION
V
OUT
V
OUT
V
OUT
V
OUT
= 2.5V
= 3.3V
= 5V
7
7
= 12V
5
5
2
3
4
5
6
7
8
9
10 11 12
2
3
4
5
6
7
8
9
10 11 12
–60
0
30
60
90 120 150
–30
TEMPERATURE (°C)
V
(V)
V
(V)
OUT
OUT
3255 G07
3255 G08
3255 G09
3255f
4
For more information www.linear.com/LTC3255
LTC3255
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
3.3VOUT Efficiency
vs Input Voltage at 50mA Load
5VOUT Efficiency
vs Input Voltage at 50mA Load
5VOUT Efficiency
vs Output Current
90
80
70
60
50
40
30
120
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
V
= 12V
SHUNT = GND
SHUNT = GND
IN
EFFICIENCY
100
80
60
40
20
0
LTC3255
LTC3255
IDEAL LDO
IDEAL LDO
POWER LOSS
0.1
1
10
100
12 14
INPUT VOLTAGE (V)
4
6
8
10
16 18 20
5
7
9
11 13 15
25
17 19 21 23
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
3255 G18
3255 G16
3255 G17
2.5V Output Voltage
vs Falling Input Voltage
Output Ripple
Load Transient
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
SHUNT = GND
I
= 50mA
OUT
V
OUT
V
OUT
50mV/DIV
20mV/DIV
AC-COUPLED
AC-COUPLED
50mA
I
OUT
5mA
–60°C
25°C
125°C
3255 G10
V
V
I
= 12V
40µs/DIV
IN
3255 G11
V
V
= 12V
40µs/DIV
= 3.3V
OUT
= 5mA
IN
OUT
= 3.3V
OUT
2
6
8
9
3
4
5
7
10
V
(V)
IN
3255 G12
3.3V Output Voltage
vs Falling Input Voltage
5V Output Voltage
vs Falling Input Voltage
12V Output Voltage
vs Falling Input Voltage
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
12.25
SHUNT = GND
OUT
SHUNT = GND
OUT
SHUNT = GND
OUT
12.20
12.15
12.10
12.05
12.00
11.95
11.90
11.85
11.80
11.75
I
= 50mA
I
= 50mA
I
= 50mA
–60°C
25°C
–60°C
25°C
–60°C
25°C
125°C
125°C
125°C
2
6
8
9
3
4
5
7
10 11 12
4
8
10 11
(V)
5
6
7
9
12 13 14 15
10
18
V
22 24
26 28 30
12 14 16
20
(V)
V
(V)
V
IN
IN
IN
3255 G13
3255 G14
3255 G15
3255f
5
For more information www.linear.com/LTC3255
LTC3255
PIN FUNCTIONS
C (Pin 1): Flying Capacitor Positive Connection. This pin
must not be driven externally.
+
EN (Pin 6): Logic Input. A logic high on the EN pin will
enable the charge pump. A logic low shuts down the
LTC3255. Do not float this pin.
V
(Pin 2): Charge Pump Output Voltage.
OUT
BIAS (Pin 7): Connect this pin to a 0.1µF bypass capaci-
tor to GND. A ceramic capacitor of at least 10V rating is
recommended.
FB (Pin 3): Feedback pin for setting the regulated output
voltage, usually connected to V through an external
OUT
resistor divider. In operation, the LTC3255 servos the FB
pin to 1.2V by transferring charge from V to V
.
OUT
GND(Pin8andExposedPadPin11):GroundConnection.
Exposedpad(Pin11)mustbesolderedtothecircuitboard
groundplaneforproperthermalandelectricalconduction.
IN
SHUNT (Pin 4): Configuration pin that must connect to
either the BIAS or GND pins to enable or defeat, respec-
tively,theLTC3255’sshuntregulatorfeature.Connectthis
pin to either BIAS or GND on the circuit board layout. Do
not float this pin.
–
C (Pin 9): Flying Capacitor Negative Connection. This pin
must not be driven externally.
V (Pin 10):Input SupplyVoltage. Bypass thispin to GND
IN
PGOOD (Pin 5): Power Good Open-Drain Logic Output.
This pin becomes high impedance when the feedback
voltage on the FB pin rises above 94% (typical) of the
regulation voltage.
with at least 1µF capacitance.
3255f
6
For more information www.linear.com/LTC3255
LTC3255
SIMPLIFIED BLOCK DIAGRAM
V
IN
10
BIAS
INTERNAL
BIASING
7
2
+
–
V
C
C
OUT
1
9
SHUNT
CONTROL
SHUNT
EN
4
6
FB
+
–
3
CHARGE
PUMP
CONTROL
1.2V
PGOOD
–
+
5
1.13V
GND
GND
11
8
3255 BD
3255f
7
For more information www.linear.com/LTC3255
LTC3255
APPLICATIONS INFORMATION
General Operation
Regulation Loop
The LTC3255 uses switched-capacitor-based DC/DC
conversion to provide efficiency advantages associated
with inductor-based circuits together with the cost and
simplicity advantages of linear regulators. No inductors
arerequired.TheLTC3255usesaninternalswitchnetwork
and fractional conversion ratios to achieve high efficiency
Regulation is achieved via a Burst Mode control loop that
allows the LTC3255 to achieve high efficiency even at
light loads. As shown in the Block Diagram, a comparator
monitors the output voltage via a feedback pin, FB, which
receives a fraction of V
via an external resistor divider.
OUT
WhileV isbelowregulation, theLTC3255transfersfixed
FB
and regulation over widely varying V and output load
packets of charge from V to V , paced by an internal
IN
IN
OUT
OUT
conditions. A defeatable V shunt regulator allows the
oscillator. This causes V
FB
and hence FB to rise. When
IN
LTC3255 to operate with current-fed V supplies, such
V
enters regulation, the LTC3255 stops charge transfer
IN
as 4mA to 20mA current loops.
and enters a low quiescent current sleep state. During this
sleepstate,theoutputloadissuppliedentirelybytheoutput
capacitor. The LTC3255 remains in sleep until the output
drops enough to require another burst of charge. As load
current decreases, the output capacitor takes longer to
discharge, so sleep time increases.
Automatic 2:1/1:1 Mode Switching with V Shunt
IN
Disabled (SHUNT Pin Connected to GND)
Connecting the SHUNT pin to GND defeats the V shunt
IN
regulator. With the shunt regulator defeated, the LTC3255
functions as a general purpose step-down charge pump
offering two conversion modes: 2:1 and 1:1. Internal cir-
cuitry automatically chooses the optimal conversion ratio
Shutdown and Undervoltage Lockout (UVLO)
Driving the EN pin low puts the LTC3255 in shutdown,
based on V , V , and output load conditions, generally
which disables all circuitry except the internal bias. V
IN OUT
IN
preferring 2:1 mode when V exceeds twice V , but
supply current is minimized. When the EN pin is high, the
IN
OUT
falling back to 1:1 mode as needed to maintain regulation.
charge pump will enable if V satisfies the V undervolt-
IN IN
age lockout (UVLO) threshold. If the shutdown feature is
Forced 2:1 Mode Operation When V Shunt Regulator
not needed, the EN pin can be connected to V , as both
IN
IN
is Enabled (SHUNT Pin Connected to BIAS)
pins share the same Absolute Maximum rating.
With the SHUNT pin connected to BIAS, the V shunt
IN
Reverse Polarity Input Protection
regulator is enabled, and the LTC3255 expects a high
impedance power source at V , such as a 4mA to 20mA
The V and EN pins are designed to withstand connection
IN
IN
current loop, or a resistor to a DC supply. With the shunt
regulatorenabled,thechargepumprunsin2:1conversion
mode only, extending its output current capability beyond
to voltages below ground without damage. When V is
IN
belowground,theLTC3255preventsV fromgoingmore
OUT
than a diode drop below GND to protect the load circuit.
that of the V source. For example, the LTC3255 can
IN
Short-Circuit/Thermal Protection
typically boost the current capability of a 4mA source to
power a 7.4mA load continuously. See V Shunt Regula-
IN
The LTC3255 has built-in short-circuit current limiting as
well as overtemperature protection. During short-circuit
conditions output current is automatically limited by the
output current limit circuitry.
tor in the Operation section for V compliance and other
IN
operating information.
3255f
8
For more information www.linear.com/LTC3255
LTC3255
APPLICATIONS INFORMATION
The LTC3255 has thermal protection that will shut
down the device if the junction temperature exceeds the
overtemperature threshold (typically 175°C). Thermal
shutdown is included to protect the IC in cases of exces-
sivelyhighambienttemperatures, or incases ofexcessive
power dissipation inside the IC. The charge transfer will
reactivate once the junction temperature drops back to
approximately 165°C.
2:1 Step-Down Charge Pump Operation
In 2:1 step-down mode, charge transfer from V to V
IN
OUT
happens in two phases. On the first phase, the flying ca-
pacitor (C ) is connected between V and V . On this
FLY
IN
OUT
phase C is charged up and current is delivered to V
.
FLY
OUT
and
Onthesecondphase, C isconnectedbetweenV
FLY
OUT
GND. The charge stored on C during the first phase is
FLY
transferred to V
on the second phase. When in 2:1
OUT
When the thermal protection is active, the junction tem-
perature is beyond the specified operating range. Thermal
protection is intended for momentary overload conditions
outsidenormaloperation.Continuousoperationabovethe
specified maximum operating junction temperature may
impair device reliability.
step-down mode, the input current will be approximately
half of the total output current. The efficiency (η) and chip
power dissipation (P ) in 2:1 mode are approximately:
D
POUT VOUT •IOUT 2VOUT
η =
=
=
1
P
V
IN
IN
V • I
IN
OUT
2
V
2
Programming the Output Voltage (FB Pin)
IN
P =
– V
I
D
OUT
OUT
The LTC3255 output voltage is set by connecting its FB
pin to a resistor divider between V
in Figure 1.
and GND as shown
OUT
1:1 Step-Down Charge Pump Operation
1:1 step-down mode is similar to how a linear regulator
works.ChargeisdelivereddirectlyfromV toV through
The desired adjustable output voltage is programmed by
solving the following equation for R and R :
IN
OUT
A
B
most of the internal oscillator period. The charge transfer
is briefly interrupted at the end of the period. When in 1:1
step-down mode the input current will be approximately
equal to the total output current. Thus efficiency (η) and
RA VOUT
=
–1
RB 1.2V
Select a value for R in the range of 20k to 2M and solve
B
chippowerdissipation(P )in1:1modeareapproximately:
D
for R . Note that the resistor divider current adds to the
A
POUT VOUT •IOUT VOUT
total no-load operating current. Thus a larger value for R
B
η =
=
=
will result in lower operating current.
P
V •I
V
IN
IN
IN
OUT
P = V – V
I
(
)
D
IN
OUT OUT
R
R
A
B
V
V
=
1.2V 1 +
OUT
LTC3255
FB
OUT
(
)
R
R
A
B
C
OUT
GND
3255 F01
Figure 1. Setting the Output Voltage
3255f
9
For more information www.linear.com/LTC3255
LTC3255
APPLICATIONS INFORMATION
Power Good Output Operation (PGOOD)
where I is the time-averaged current being fed into V
IN
IN
by the current loop, V
is the output voltage, and I
OUT
OUT
TheLTC3255includesanopen-drainpowergood(PGOOD)
output pin. If the chip is in shutdown or undervoltage
lockout, or if the FB pin voltage is less than 90% (typi-
cal) of its regulation voltage, PGOOD is low impedance
is the output load current. Notice that the largest power
dissipation occurs when output load current is zero. This
is because any power fed into V must be dissipated in
IN
either the load or the LTC3255. If the load is not drawing
any current, then the LTC3255 must dissipate all of the
input power.
to ground. PGOOD becomes high impedance when V
OUT
rises to 94% (typical) of its regulation voltage. PGOOD
stays high impedance until V is shut down or drops
OUT
below the PGOOD falling threshold (90% typical). A pull-
When the shunt regulator is enabled, the LTC3255 charge
pump is locked in 2:1 mode. To achieve output regulation,
the input current to the part must have sufficient voltage
up resistor can be inserted between PGOOD and V to
OUT
signal a valid power good condition. The use of a large
value pull-up resistor on PGOOD and a capacitor placed
betweenPGOODandGNDcanbeusedtodelaythePGOOD
signal if desired.
complianceabovetwiceV .ThegraphinFigure2shows
OUT
the typical minimum compliance required at the V pin
IN
for correct operation. For V
≤ 5.5V, a V compliance
OUT
IN
of 2V
+ 3.5V is recommended. For V
> 5.5V, a V
OUT IN
OUT
V Shunt Regulator Operation
IN
compliance of 2V
+ 4V is recommended.
OUT
TheV shuntregulatorfeatureoftheLTC3255isintended
IN
3.5
I
= 20mA
VIN
for applications where V is current-fed, such as in 4mA
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
IN
to 20mA current loops. A circuit powered by a current
loop must limit the voltage drop it presents to the loop to
avoid exceeding the loop compliance, which would break
thecurrentloop.TheLTC3255’sV shuntregulatormoni-
IN
tors V and V , drawing V current as necessary to
IN
OUT
IN
keep V from rising much beyond 3V above twice V
.
IN
OUT
V
V
V
V
= 2.5V
OUT
OUT
OUT
OUT
= 3.3V
= 5V
The shunt regulator is enabled by connecting the SHUNT
pin to the BIAS pin in the circuit board layout. The shunt
is disabled by connecting the SHUNT pin to GND.
= 12V
–60
0
30
60
90 120 150
–30
TEMPERATURE (°C)
3255 F02
The shunt regulator dissipates power which must be ac-
counted for in thermal budgeting. Total power dissipation
Figure 2. Typical Minimum VIN – 2 • VOUT Compliance Required
for Shunt Mode Operation
(P
) in the LTC3255 with shunt regulator enabled is
DSHUNT
equal to the input power minus the output power of the
LTC3255, or approximately:
PD(SHUNT) = P –P
IN
OUT
= V •I – VOUT •IOUT
IN IN
≈ 2•V + 2V •I – VOUT •IOUT
(
)
IN
OUT
3255f
10
For more information www.linear.com/LTC3255
LTC3255
APPLICATIONS INFORMATION
Flying Capacitor Selection
V
OUT
Ripple and Capacitor Selection
The flying capacitor should always be a ceramic type.
Polarizedcapacitorssuchastantalumoraluminumelectro-
lytics are not recommended. The flying capacitor controls
the strength of the charge pump. In order to achieve the
rated output current, it is necessary for the flying capaci-
tor to have at least 0.4μF of capacitance over operating
temperature with a bias voltage equal to the programmed
The type and value of capacitors used with the LTC3255
determine several important parameters such as output
ripple and charge pump strength. The value of C
OUT
directly controls the amount of output ripple for a given
load current. Increasing the size of C
output ripple.
will reduce the
OUT
To reduce output noise and ripple, it is suggested that a
low ESR (equivalent series resistance < 0.1Ω) ceramic
V
(see Ceramic Capacitor Selection Guidelines). The
OUT
voltage rating of the ceramic capacitor should be V
1V or greater.
+
OUT
capacitor (10μF or greater) be used for C . Ceramic
OUT
capacitors typically have exceptionally low ESR which,
combined with a tight board layout, should yield excellent
performance. Tantalum and aluminum capacitors can be
used in parallel with a ceramic capacitor to increase the
total capacitance but are not recommended to be used
alone because of their high ESR.
Ceramic Capacitor Selection Guidelines
Capacitors of different materials lose their capacitance
with higher temperature and voltage at different rates.
For example, a ceramic capacitor made of X5R or X7R
material will retain most of its capacitance from –40°C
to 85°C, whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range (60% to 80%
loss typical). Z5U and Y5V capacitors may also have a
very strong voltage coefficient, causing them to lose an
additional60%ormoreoftheircapacitancewhentherated
voltage is applied. Therefore, when comparing different
capacitors, it is often more appropriate to compare the
amount of achievable capacitance for a given case size
ratherthandiscussingthespecifiedcapacitancevalue.For
example, over rated voltage and temperature conditions,
a 4.7μF, 10V, Y5V ceramic capacitor in an 0805 case may
not provide any more capacitance than a 1μF, 10V, X5R
or X7R available in the same 0805 case. In fact, over bias
and temperature range, the 1μF, 10V, X5R or X7R will
provide more capacitance than the 4.7μF, 10V, Y5V. The
capacitor manufacturer’s data sheet should be consulted
to determine what value of capacitor is needed to ensure
minimum capacitance values are met over operating
temperature and bias voltage. Table 1 is a list of ceramic
capacitor manufacturers in alphabetical order:
V Capacitor Selection
IN
The total amount and type of capacitance necessary for
input bypassing is very dependent on the impedance of
the input power source as well as existing bypassing al-
ready on the V node. For optimal input noise and ripple
IN
reduction, it is recommended that a low ESR ceramic
capacitor be used for C bypassing. Low ESR will reduce
IN
the voltage steps caused by changing input current, while
the absolute capacitor value will determine the level of
ripple. An electrolytic or tantalum capacitor may be used
in parallel with the ceramic capacitor on C to increase
IN
the total capacitance, but due to the higher ESR, it is not
recommendedthatanelectrolyticortantalumcapacitorbe
used alone for input bypassing. The LTC3255 will operate
withcapacitorslessthan1μF,butdependingonthesource
impedance, input noise can feed through to the output
causing degraded performance. For best performance,
1μF or greater total capacitance is suggested for C .
IN
3255f
11
For more information www.linear.com/LTC3255
LTC3255
APPLICATIONS INFORMATION
Table 1
largegroundplaneunderthedevicecanreducethethermal
resistanceofthepackageandPCboardconsiderably.Poor
board layout and failure to connect the die paddle (Pin
11) to a large ground plane can result in thermal junction
to ambient impedance well in excess of 40°C/W (MSE
package) or in excess of 43°C/W (DD package). Thermal
junction to ambient impedance is specified per JEDEC
standard JESD 51-5.
CERAMIC CAPACITOR MANUFACTURER WEBSITE
AVX
www.avxcorp.com
www.kemet.com
www.murata.com
www.t-yuden.com
www.tdk.com
Kemet
Murata
Taiyo Yuden
TDK
Layout Considerations
Because of the wide input operating range it is possible to
exceed the specified operating junction temperature and
even reach thermal shutdown. It is the responsibility of
the user of the LTC3255 to calculate worst-case operat-
ing conditions (temperature and power) to make sure
the LTC3255’s specified operating junction temperature
is not exceeded for extended periods of time. The 2:1
Due to the high switching frequency and transient cur-
rents produced by the LTC3255, careful board layout is
necessary for optimal performance. A true ground plane
and short connections to all capacitors will optimize
performance, reduce noise and ensure proper regulation
over all conditions.
Step-Down, 1:1 Step-Down, and V Shunt Regulator
IN
When using the LTC3255 with an external resistor divider
it is important to minimize any stray capacitance to the FB
node. Stray capacitance from FB to C or C can degrade
performance significantly and should be minimized and/
or shielded if necessary.
Operation sections provide equations for calculating the
power dissipation (P ) in each mode.
+
–
D
For example, if it is determined that the maximum power
dissipation (P ) is 1.2W under normal operation, then
D
the maximum junction to ambient temperature rise in the
Thermal Management
MSE package will be:
The on chip power dissipation in the LTC3255 will cause
the junction to ambient temperature to rise at a rate of
40°C/W or more in the MSE package, or 43°C/W or more
in the DD package. To reduce the maximum junction
temperature, a good thermal connection to the PC board
is recommended. Connecting the die paddle (Pin 11) to a
Junction to Ambient = 1.2W • 40°C/W = 48°C
Thus, the ambient temperature under this condition can
not exceed 102°C if the junction temperature is to remain
below150°C.Forambienttemperaturesexceedingroughly
127°C, the device will cycle in and out of the thermal
shutdown.
3255f
12
For more information www.linear.com/LTC3255
LTC3255
TYPICAL APPLICATIONS
Wide Input Range 5V Microcontroller Supply (with Power-On Reset Delay)
1µF
V
= 5V
OUT
+
–
C
C
INPUT
6V TO 48V
V
DD
V
V
IN
OUT
EN
LTC3255
383k
121k
10µF
1µF
510k
µCONTROLLER
BIAS
FB
0.1µF
RESET
PGOOD
SHUNT
1µF
GND
GND
3255 TA02
7mA 5V Supply from 4mA to 20mA Current Loop
1µF
OUTPUT
5V
7mA
+
–
C
C
+
V
V
IN
OUT
FB
220k
EN
LTC3255
383k
121k
10µF
4mA TO 20mA INPUT
13.5V COMPLIANCE
1µF
BIAS
PGOOD
PGOOD
SHUNT
GND
0.1µF
3255 TA03
–
3255f
13
For more information www.linear.com/LTC3255
LTC3255
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3255f
14
For more information www.linear.com/LTC3255
LTC3255
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.88 ±0.102
(.074 ±.004)
0.889 ±0.127
(.035 ±.005)
1
0.29
REF
1.68
(.066)
0.05 REF
5.10
(.201)
MIN
1.68 ±0.102
3.20 – 3.45
DETAIL “B”
(.066 ±.004) (.126 – .136)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ±.0015)
TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.497 ±0.076
(.0196 ±.003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.50
(.0197)
BSC
MSOP (MSE) 0213 REV I
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
3255f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
15
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3255
TYPICAL APPLICATION
Wide Input Range 12V Supply
1µF
OUTPUT
12V
50mA
+
–
C
C
INPUT
13V TO 48V
V
V
IN
OUT
FB
220k
EN
LTC3255
1.1M
121k
10µF
1µF
BIAS
0.1µF
PGOOD
PGOOD
SHUNT
GND
3255 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1751-3.3/LTC1751-5
100mA, 800kHz Regulated Doubler
V : 2V to 5V, V
= 3.3V/5V, I = 20μA, I < 2μA,
OUT(MAX) Q SD
IN
MS8 Package
LTC1983-3/LTC1983-5
LTC3200-5
100mA, 900kHz Regulated Inverter
V : 3.3V to 5.5V, V
= –3V/–5V, I = 25μA, I < 2μA,
Q SD
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
ThinSOT™ Package
100mA, 2MHz Low Noise, Doubler/White LED Driver
V : 2.7V to 4.5V, V
= 5V, I = 3.5mA, I < 1μA,
Q SD
IN
ThinSOT Package
LTC3202
125mA, 1.5MHz Low Noise, Fractional White LED Driver V : 2.7V to 4.5V, V
= 5.5V, I = 2.5mA, I < 1μA,
Q SD
IN
DFN, MS Packages
LTC3204-3.3/LTC3204B-3.3
LTC3204-5/LTC3204B-5
V : 1.8V to 4.5V (LTC3204B-3.3), 2.7V to 5.5V (LTC3204B-5),
Low Noise, Regulated Charge Pumps in (2mm × 2mm)
DFN Package
IN
I = 48μA, LTC3204B Version without Burst Mode Operation,
Q
6-Lead (2mm × 2mm) DFN Package
LTC3440
LTC3441
LTC3443
600mA (I ) 2MHz Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.5V to 5.5V, V
= 2.5V, I = 25μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
Converter
I
≤ 1μA, 10-Lead MS Package
SD
High Current Micropower 1MHz Synchronous
Buck-Boost DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 2.5V, I = 25μA,
Q
IN
I
≤ 1μA, DFN Package
SD
High Current Micropower 600kHz Synchronous
Buck-Boost DC/DC Converter
96% Efficiency, V : 2.4V to 5.5V, V
= 2.4V, I = 28μA,
Q
IN
I
< 1μA, DFN Package
SD
LTC3240-3.3/
LTC3240-2.5
3.3V/2.5V Step-Up/Step-Down Charge Pump DC/DC
Converter
V : 1.8V to 5.5V, V
= 3.3V/2.5V, I = 65μA, I < 1μA,
OUT(MAX) Q SD
IN
(2mm × 2mm) DFN Package
LTC3245
Wide V Range Low Noise 250mA Buck-Boost
V : 2.7V to 38V, V
= 5V, I = 20µA, I = 4µA,
IN
IN
OUT(MAX) Q SD
Charge Pump
12-Lead MS and (3mm × 4mm) DFN Packages
LTC3260
Low Noise Dual Supply Inverting Charge Pump
Inverting Charge Pump With Integrated Dual Polarity 50mA LDO
Post-Regulated Outputs. V : 4.5V to 32V, Charge Pump V
:
IN
OUT
–0.94 • V , 100mA
IN
LTC3261
High Voltage, Low Quiescent Current Inverting
Charge Pump
V : 4.5V to 32V, V
= –V , I = 100mA, MSOP-12 Package
IN OUT
IN
OUT
3255f
LT 0813 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3255
●
●
LINEAR TECHNOLOGY CORPORATION 2013
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