LTC3388IDD-3#PBF [Linear]
LTC3388 - 20V High Efficiency Nanopower Step-Down Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3388IDD-3#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3388 - 20V High Efficiency Nanopower Step-Down Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 开关 光电二极管 输出元件 |
| 文件： | 总22页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3388-1/LTC3388-3
20V High Efficiency
Nanopower
Step-Down Regulator
FEATURES
DESCRIPTION
TheLTC®3388-1/LTC3388-3arehighefficiencystep-down
DC/DCconverterswithinternalhighsideandsynchronous
powerswitchesthatdrawonly720nAtypicalDCsupplycur-
rentatnoloadwhilemaintainingoutputvoltageregulation.
n
720nA Input I in Regulation (No Load), V = 4V
Q
IN
n
n
n
n
n
820nA Input I in Regulation (No Load), V = 20V
Q
IN
400nA Input I in UVLO
Q
2.7V to 20V Input Operating Range
Up to 50mA of Output Current
Pin Selectable Output Voltages:
Capableofsupplying50mAofloadcurrent,theLTC3388-1/
LTC3388-3 also incorporate an accurate undervoltage
lockout (UVLO) feature to disable the converter and main-
tain a low quiescent current state when the input voltage
fallsbelow2.3V. Inregulation, theLTC3388-1/LTC3388-3
enter a sleep state in which both input and output quies-
cent currents are minimal. The buck converter turns on
and off as needed to maintain regulation. An additional
standby mode disables buck switching while the output is
in regulation for short duration loads requiring low ripple.
n
1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1)
2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3)
High Efficiency Hysteretic Synchronous
DC/DC Conversion
Standby Mode Disables Buck Switching
n
n
n
n
Available in 10-Lead MSE and 3mm × 3mm
DFN Packages
APPLICATIONS
Output voltages of 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1)
and2.8V,3.0V,3.3V,5.0V(LTC3388-3)arepinselectable.
n
n
n
n
Keep Alive Power for Portable Products
Industrial Control Supplies
TheLTC3388-1/LTC3388-3canoperatewithV upto20V
IN
while the no load quiescent current remains below 1µA.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
Distributed Power Systems
Battery-Operated Devices
TYPICAL APPLICATION
Efficiency vs Load Current
50mA Step-Down Converter
100
V
= 1.8V, L = 100µH
OUT
2.7V TO 20V
V
90
80
70
60
50
40
30
20
10
0
IN
1µF
6V
LTC3388-1/
LTC3388-3
100µH
SW
OUT
V
OUT
CAP
2.2µF
25V
47µF
6V
V
V
IN2
PGOOD
D0, D1
EN
4.7µF
6V
2
OUTPUT
VOLTAGE
SELECT
STBY
GND
338813 TA01a
V
IN
V
IN
V
IN
= 3.0V
= 10V
= 20V
1µ
10µ
100µ
1m
10m
LOAD CURRENT (A)
338813 TA01b
338813fa
1
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
ABSOLUTE MAXIMUM RATINGS (Note 1)
V ............................................................. –0.3V to 22V
I
.......................................................................210mA
IN
SW
D0, D1..............–0.3V to [Lesser of (V + 0.3V) or 6V]
Operating Junction Temperature Range
IN2
CAP......................[Higher of –0.3V or (V – 6V)] to V
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
IN
IN
V
, V
..........–0.3V to [Lesser of (V + 0.3V) or 6V]
IN2 OUT IN
EN, STBY ..................................................... –0.3V to 6V
PGOOD......................................................... –0.3V to 6V
MSE Only..............................................................300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
EN
STBY
CAP
1
2
3
4
5
10 PGOOD
EN
STBY
CAP
IN
SW
1
2
3
4
5
10 PGOOD
9
8
7
6
D0
D1
9
8
7
6
D0
D1
11
11
GND
GND
V
V
V
IN2
OUT
V
IN
V
V
IN2
SW
OUT
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
T
JMAX
= 125°C, θ = 45°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
10-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W, θ = 7.5°C/W
JA JC
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC3388EDD-1#PBF
LTC3388IDD-1#PBF
LTC3388EMSE-1#PBF
LTC3388IMSE-1#PBF
LTC3388EDD-3#PBF
LTC3388IDD-3#PBF
LTC3388EMSE-3#PBF
LTC3388IMSE-3#PBF
TAPE AND REEL
PART MARKING*
LFWN
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 125°C
LTC3388EDD-1#TRPBF
LTC3388IDD-1#TRPBF
LFWN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTC3388EMSE-1#TRPBF LTFWM
LTC3388IMSE-1#TRPBF LTFWM
10-Lead Plastic MSOP
LTC3388EDD-3#TRPBF
LTC3388IDD-3#TRPBF
LFWQ
LFWQ
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTC3388EMSE-3#TRPBF LTFWP
LTC3388IMSE-3#TRPBF LTFWP
10-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
338813fa
2
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). Unless otherwise noted, VIN = 5.5V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
IN
Input Voltage Range
2.7
20
V
I
Q
V
IN
Quiescent Current When Enabled
UVLO
Sleep
Sleep
Active
V
V
V
= 2V
400
720
820
150
600
1100
1200
250
nA
nA
nA
µA
IN
IN
IN
= 4V
= 20V
= 0A (Note 4)
I
SW
I
I
V
Quiescent Current Enabled, in Standby
Q,STBY
IN
Sleeping
V
V
= 4V
= 4V
720
1100
3000
nA
nA
IN
IN
Not Sleeping
2000
V
V
Quiescent Current When Disabled
Undervoltage Lockout Threshold
V
IN
V
IN
= 4V
= 20V
520
620
800
900
nA
nA
Q,SD
IN
IN
l
l
V
V
V
IN
V
IN
Rising
Falling
2.5
2.3
2.65
V
V
UVLO
2.15
Regulated Output Voltage (LTC3388-1)
1.2V Output Selected; D1 = 0, D0 = 0
Sleep Threshold
OUT
l
l
1.208
1.192
1.260
1.560
1.863
2.600
V
V
Wake-Up Threshold
1.140
1.440
1.737
2.400
1.5V Output Selected; D1 = 0, D0 = 1
Sleep Threshold
l
l
1.508
1.492
V
V
Wake-Up Threshold
1.8V Output Selected; D1 = 1, D0 = 0
Sleep Threshold
l
l
1.808
1.792
V
V
Wake-Up Threshold
2.5V Output Selected; D1 = 1, D0 = 1
Sleep Threshold
l
l
2.508
2.492
V
V
Wake-Up Threshold
V
Regulated Output Voltage (LTC3388-3)
2.8V Output Selected; D1 = 0, D0 = 0
Sleep Threshold
OUT
l
l
2.816
2.784
2.912
3.105
3.399
5.180
V
V
Wake-Up Threshold
2.688
2.895
3.201
3.0V Output Selected; D1 = 0, D0 = 1
Sleep Threshold
l
l
3.016
2.984
V
V
Wake-Up Threshold
3.3V Output Selected; D1 = 1, D0 = 0
Sleep Threshold
l
l
3.316
3.284
V
V
Wake-Up Threshold
5.0V Output Selected; D1 = 1, D0 = 1
Sleep Threshold
l
l
5.016
4.984
V
V
Wake-Up Threshold
4.820
83
PGOOD Threshold
As a Percentage of the Selected V
100µA Into Pin
92
%
V
OUT
l
V
PGOOD Output Low Voltage
Output Quiescent Current
0.2
OL, PGOOD
I
LTC3388-1: V
LTC3388-3: V
= 2.5V
= 5.0V
60
120
nA
nA
VOUT
OUT
OUT
l
l
I
I
PMOS Switch Peak Current
Available Output Current
PMOS Switch On-Resistance
NMOS Switch On-Resistance
Maximum Duty Cycle
100
50
150
210
mA
mA
Ω
PEAK
OUT
R
R
1.1
1.3
P, BUCK
Ω
N, BUCK
l
100
%
338813fa
3
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). Unless otherwise noted, VIN = 5.5V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
V
V
V
D0/D1/EN/STBY Input High Voltage
D0/D1 Input Low Voltage
1.2
IH
0.4
150
10
V
IL(D0, D1)
IL(EN,STBY)
EN/STBY Input Low Voltage
D0/D1/EN/STBY Input High Current
D0/D1/EN/STBY Input Low Current
mV
nA
nA
nA
nA
I
IH
I
IL
10
Additional I at V with EN at V
V
V
= 1.2V, V = 4V
40
40
Q
IN
IH(MIN)
EN
IN
Additional I at V with STBY at V
= 1.2V, V = 4V
IN
Q
IN
IH(MIN)
STBY
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 2: The LTC3388-1/LTC3388-3 are tested under pulsed load
conditions such that T ≈ T . The LTC3388E-1/LTC3388E-3 are
Note 3: The junction temperature (T , in °C) is calculated from the ambient
temperature (T , in °C) and power dissipation (PD, in Watts) according
A
J
A
J
guaranteed to meet specifications from 0°C to 85°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3388I-1/LTC3388I-3 are guaranteed
to the formula: T = T + (P • θ ), where θ (in °C/W) is the package
J
A
D
JA
JA
thermal impedance.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
TYPICAL PERFORMANCE CHARACTERISTICS
Input IQ vs VIN, UVLO
Input IQ vs VIN, No Load
Input IQ vs VIN, EN Low
1600
1400
1200
1000
800
800
700
600
500
400
300
200
100
0
1200
1000
800
600
400
200
0
D1 = D0 = 0
125°C
125°C
85°C
125°C
85°C
25°C
–40°C
85°C
25°C
25°C
–40°C
–40°C
600
400
200
2
4
6
8
10 12 14 16 18 20
(V)
0
0.5
1
1.5
(V)
2
2.5
0
2
4
6
8
10 12 14 16 18 20
V (V)
IN
V
V
IN
IN
338813 G02
338813 G01
338813 G03
338813fa
4
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
TYPICAL PERFORMANCE CHARACTERISTICS
R
P,BUCK/RN,BUCK
UVLO vs Temperature
IPEAK vs Temperature
vs Temperature
180
170
160
150
140
130
120
2.0
1.8
1.6
1.4
1.2
1.0
0.8
2.8
2.6
2.4
2.2
2.0
NMOS
PMOS
UVLO RISING
UVLO FALLING
–50 –25
0
25 50 75 100 125
–55 –35 –15
5
25 45 65 85 105 125
–50 –25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
338813 G05
338813 G06
338813 G04
1.2V Output vs Temperature
(LTC3388-1)
1.5V Output vs Temperature
(LTC3388-1)
Operating Waveforms
1.24
1.54
1.52
1.50
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
V
OUT
SLEEP THRESHOLD
SLEEP THRESHOLD
50mV/DIV
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
AC-COUPLED
WAKE-UP THRESHOLD
V
SW
WAKE-UP THRESHOLD
2V/DIV
0V
INDUCTOR
CURRENT
100mA/DIV
PGOOD FALLING
PGOOD FALLING
0mA
338813 G07
5µs/DIV
V
LOAD
= 5.5V, V = 1.8V
IN
OUT
I
= 20mA
–50 –25
0
25 50 75 100 125
–50 –25
0
25 50 75 100 125
L = 22µH, C = 47µF
OUT
TEMPERATURE (°C)
TEMPERATURE (°C)
338813 G08
338813 G09
1.8V Output vs Temperature
(LTC3388-1)
2.5V Output vs Temperature
(LTC3388-1)
2.8V Output vs Temperature
(LTC3388-3)
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.50
1.85
1.80
1.75
1.70
1.65
1.60
SLEEP THRESHOLD
SLEEP THRESHOLD
SLEEP THRESHOLD
WAKE-UP THRESHOLD
WAKE-UP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
PGOOD FALLING
PGOOD FALLING
–50 –25
0
25 50 75 100 125
–50 –25
0
25 50 75 100 125
–50 –25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
338813 G11
338813 G12
338813 G10
338813fa
5
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
TYPICAL PERFORMANCE CHARACTERISTICS
3.0V Output vs Temperature
(LTC3388-3)
3.3V Output vs Temperature
(LTC3388-3)
5.0V Output vs Temperature
(LTC3388-3)
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
5.1
5.0
4.9
4.8
4.7
4.6
4.5
SLEEP THRESHOLD
SLEEP THRESHOLD
SLEEP THRESHOLD
WAKE-UP THRESHOLD
WAKE-UP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
PGOOD FALLING
PGOOD FALLING
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
338813 G13
338813 G14
338813 G15
VOUT Load Regulation
(LTC3388-1)
VOUT Load Regulation
(LTC3388-3)
VOUT Line Regulation
(LTC3388-1)
1.56
1.54
1.52
1.50
1.48
1.46
1.44
1.56
1.54
1.52
1.50
1.48
1.46
1.44
3.36
3.34
3.32
3.30
3.28
3.26
3.24
L = 22µH, I
= 30mA, D1 = 0, D0 = 1
V
= 5.5V, L = 22µH, C
= 100µF,
V
= 5.5V, L = 22µH, C
= 100µF,
OUT
LOAD
IN
OUT
IN
D1 = 0, D0 = 1
D1 = 1, D0 = 0
4
6
8
10 12 14 16 18 20
(V)
1µ
10µ
100µ
1m
10m
1µ
10µ
100µ
1m
10m
V
IN
LOAD CURRENT (A)
LOAD CURRENT (A)
338813 G18
338813 G16
338813 G17
VOUT Line Regulation
(LTC3388-3)
IVOUT vs Temperature (LTC3388-
1)
IVOUT vs Temperature (LTC3388-
3)
80
70
60
50
40
30
20
3.36
3.34
3.32
3.30
3.28
3.26
3.24
160
140
120
100
80
L = 22µH, I
= 30mA, D1 = 0, D0 = 1
V
V
V
V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
V
V
V
V
= 5.0V
= 3.3V
= 3.0V
= 2.8V
LOAD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
60
40
–50 –25
0
25
50
75 100 125
4
6
8
10 12 14 16 18 20
(V)
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
V
IN
TEMPERATURE (°C)
338813 G20
338813 G19
338813 G21
338813fa
6
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs ILOAD, L = 22µH
(LTC3388-1)
Efficiency vs ILOAD, L = 100µH
(LTC3388-1)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
IN
= 3.0V
V
IN
= 3.0V
V
V
V
V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
V
V
V
V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1µ
10µ
100µ
1m
10m
1µ
10µ
100µ
1m
10m
LOAD CURRENT (A)
LOAD CURRENT (A)
338813 G22
338813 G23
Efficiency vs VIN for ILOAD = 50mA,
L = 22µH (LTC3388-1)
Efficiency vs VIN for ILOAD = 50mA,
L = 100µH (LTC3388-1)
100
95
90
85
80
75
70
100
95
90
85
80
75
70
V
V
V
V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
V
V
V
V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
4
6
8
10 12 14 16 18 20
(V)
2
4
6
8
10 12 14 16 18 20
(V)
V
V
IN
IN
338813 G24
338813 G25
Efficiency vs VIN for VOUT = 1.8V,
L = 22µH (LTC3388-1)
Efficiency vs VIN for VOUT = 1.8V,
L = 100µH (LTC3388-1)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
I
I
I
I
I
= 50mA
= 100µA
= 50µA
= 30µA
= 10µA
I
I
I
I
I
= 50mA
= 100µA
= 50µA
= 30µA
= 10µA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
2
4
6
8
10 12 14 16 18 20
(V)
2
4
6
8
10 12 14 16 18 20
(V)
V
V
IN
IN
338813 G26
338813 G27
338813fa
7
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs ILOAD, L = 22µH
(LTC3388-3)
Efficiency vs ILOAD, L = 100µH
(LTC3388-3)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
IN
= 6.0V
V
IN
= 6.0V
V
V
V
V
= 5.0V
= 3.3V
= 3.0V
= 2.8V
V
V
V
V
= 5.0V
= 3.3V
= 3.0V
= 2.8V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1µ
10µ
100µ
1m
10m
1µ
10µ
100µ
1m
10m
LOAD CURRENT (A)
LOAD CURRENT (A)
338813 G29
338813 G28
Efficiency vs VIN for ILOAD = 50mA,
L = 100µH (LTC3388-3)
Efficiency vs VIN for ILOAD = 50mA,
L = 22µH (LTC3388-3)
100
95
90
85
80
75
70
100
95
90
85
80
75
70
V
V
V
V
= 5.0V
= 3.3V
= 3.0V
= 2.8V
V
V
V
V
= 5.0V
= 3.3V
= 3.0V
= 2.8V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
4
6
8
10 12 14 16 18 20
(V)
4
6
8
10 12 14 16 18 20
(V)
V
IN
V
IN
338813 G31
338813 G30
Efficiency vs VIN for VOUT = 3.3V,
L = 22µH (LTC3388-3)
Efficiency vs VIN for VOUT = 3.3V,
L = 100µH (LTC3388-3)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
I
I
I
I
I
= 50mA
= 100µA
= 50µA
= 30µA
= 10µA
I
I
I
I
I
= 50mA
= 100µA
= 50µA
= 30µA
= 10µA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
4
6
8
10 12 14 16 18 20
4
6
8
10 12 14 16 18 20
V
IN
(V)
V
IN
(V)
338813 G32
338813 G33
338813fa
8
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
PIN FUNCTIONS
EN (Pin 1): Enable Input. Logic level input referenced to
V
(Pin 6): Sense pin used to monitor the output volt-
OUT
V
. A logic high on EN will enable the buck converter.
age and adjust it through internal feedback.
IN2
Driving EN to V will result in no additional quiescent
IN2
V
(Pin 7): Internal low voltage rail to serve as gate drive
IN2
current on V . However, if EN is driven near V or V
40nA of additional quiescent current can appear on V .
IN
IH
IL
IN
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7µF capacitor
STBY (Pin 2): Standby Input. Logic level input referenced
should be connected from V to GND. This pin is not
IN2
to V . A logic high on STBY will place the part in standby
intended for use as an external system rail.
IN2
mode. Driving STBY to V will result in no additional
IN2
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
quiescent current on V . However, if STBY is driven
IN
high to V or low to GND to select desired V
(see
IN2
OUT
near V or V 40nA of additional quiescent current can
IH
IL
Table 1).
appear on V .
IN
D0 (Pin 9): Output Voltage Select Bit. D0 should be tied
CAP (Pin 3): Internal rail referenced to V to serve as gate
IN
high to V or low to GND to select desired V
(see
IN2
OUT
drive for buck PMOS switch. A 1µF capacitor should be
Table 1).
connected between CAP and V . This pin is not intended
IN
PGOOD (Pin 10): Power Good Open-Drain NMOS Output.
The PGOOD pin is Hi-Z when V
target value.
for use as an external system rail.
is above 92% of the
OUT
V
(Pin 4): Input Voltage. A 2.2µF or larger capacitor
IN
should be connected from V to GND.
IN
GND (Exposed Pad Pin 11): Ground. The exposed pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3388-1/LTC3388-3.
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 22µH or larger inductor should be connected from SW
to V
.
OUT
338813fa
9
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
BLOCK DIAGRAM
4
V
IN
INTERNAL RAIL
GENERATION
V
IN2
3
5
7
CAP
SW
40nA
UVLO
1
EN
V
IN2
V
IN2
BUCK
CONTROL
40nA
GND
11
STBY
2
SLEEP
V
OUT
6
BANDGAP
REFERENCE
8, 9
D1, D0
10
PGOOD
2
PGOOD
–
+
REF
338813 BD
338813fa
10
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
OPERATION
The LTC3388-1/LTC3388-3 is an ultralow quiescent
current power supply designed to maintain a regulated
output voltage by means of a nanopower high efficiency
synchronous buck regulator.
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V
sense pin. The buck converter charges an output
OUT
capacitorthroughaninductortoavalueslightlyhigherthan
the regulation point. It does this by ramping the inductor
currentupto150mAthroughaninternalPMOSswitchand
then ramping it down to 0mA through an internal NMOS
switch. This efficiently delivers energy to the output ca-
Undervoltage Lockout (UVLO)
When the voltage on V rises above the UVLO rising
IN
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output ca-
pacitor. If V falls below the UVLO falling threshold the
pacitor. The ramp rate is determined by V , V , and the
IN
IN OUT
part will re-enter UVLO. In UVLO the quiescent current is
inductor value. When the buck brings the output voltage
intoregulationtheconverterentersalowquiescentcurrent
sleep state that monitors the output voltage with a sleep
comparator. During this operating mode load current is
provided by the buck output capacitor. When the output
voltage falls below the regulation point the buck regulator
wakes up and the cycle repeats. This hysteretic method
of providing a regulated output reduces losses associated
with FET switching and maintains an output at light loads.
The buck delivers a minimum of 50mA of average load
current when it is switching.
approximately 400nA and the buck converter is disabled.
Internal Rail Generation
Two internal rails, CAP and V , are generated from V
IN2
IN
and are used to drive the high side PMOS and low side
NMOSofthebuckconverter,respectively.Additionallythe
V
rail serves as logic high for EN, STBY, and output
IN2
voltage select bits D0 and D1. The V rail is regulated
IN2
at 4.6V above GND while the CAP rail is regulated at 4.8V
below V . The V and CAP rails are not intended to be
IN
IN2
used as external rails. Bypass capacitors are connected
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be
in the middle of a cycle with current still flowing through
the inductor. Normally both synchronous switches would
turn off and the current in the inductor would freewheel
to zero through the NMOS body diode. The LTC3388-1/
LTC3388-3 keeps the NMOS switch on during this time to
prevent the conduction loss that would occur in the diode
if the NMOS were off. If the PMOS is on when the sleep
comparator trips, the NMOS will turn on immediately in
order to ramp down the current. If the NMOS is on it will
be kept on until the current reaches zero.
to the CAP and V pins to serve as energy reservoirs for
IN2
driving the buck switches. When V is below 4.6V, V
IN
IN2
is equal to V . CAP is at GND until V rises above 4.8V.
IN
IN
Figure 1 shows the ideal V , V and CAP relationship.
IN IN2
18
16
14
V
IN
12
10
8
6
V
IN2
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when the output voltage discharges
to the sleep falling threshold. Thus, the buck operating
quiescentcurrentisaveragedwiththelowsleepquiescent
current. This allows the converter to remain very efficient
at loads as low as 10µA.
4
2
CAP
0
0
5
10
15
V
IN
(V)
338813 F01
Figure 1. Ideal VIN, VIN2 and CAP Relationship
338813fa
11
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
OPERATION
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or V . Table 1 shows the
fourD0/D1codesandtheircorrespondingoutputvoltages
as well as the difference in output voltages between the
LTC3388-1 and LTC3388-3.
output is in regulation. The PGOOD pin will remain Hi-Z
until V
falls to 92% of the desired regulation voltage.
IN2
OUT
Additionally, if PGOOD is high and V falls below the
IN
UVLO falling threshold, PGOOD will remain high until
V
falls to 92% of the desired regulation point. This
OUT
allows output energy to be used even if the input is lost.
Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection
Figure 2 shows the behavior for V
= 1.8V and a 10µA
OUT
D1
0
D0
0
V
V
OUT
Quiescent Current (I
28nA/66nA
)
VOUT
OUT
load. At t = 2s V becomes high impedance and is dis-
IN
1.2V/2.8V
1.5V/3.0V
1.8V/3.3V
2.5V/5.0V
charged by the quiescent current of the LTC3388-1 and
0
1
36nA/72nA
through servicing V . V crosses UVLO falling but
OUT
IN
OUT
1
0
43nA/78nA
PGOOD remains high until V
desired regulation point.
decreases to 92% of the
1
1
60nA/120nA
The internal feedback network draws a small amount of
current from V as listed in Table 1.
This scenario is likely for cases in which the selected
output voltage is below the UVLO falling threshold. If the
input becomes high impedance and begins to fall it will
be supported by the output through the body diode of
the PMOS switch. For a high enough output voltage the
OUT
Dropout Operation
When the input supply voltage decreases towards the
output voltage, the rate of change of inductor current
decreases, reducing the switching frequency of the cur-
rent bursts. Further reduction in input supply voltage will
eventually cause the PMOS to be turned on 100%, i.e.,
DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the PMOS
and the inductor.
part will not necessarily enter UVLO while V
remains
OUT
PGOOD.Thisisalwaystruefortheoutputvoltagesavailable
on the LTC3388-3.
The D0/D1 inputs can be switched while in regulation as
showninFigure3. IfV
isprogrammedtoavoltagewith
OUT
aPGOODfallingthresholdabovetheoldV , PGOODwill
OUT
transition low until the new regulation point is reached.
When V
is programmed to a lower voltage, PGOOD
OUT
Power Good Comparator
will remain high through the transition.
A power good comparator causes the PGOOD pin to
go Hi-Z the first time the converter reaches the sleep
The PGOOD pin is designed to drive a microprocessor or
other chip I/O and is not intended to drive higher current
loads such as an LED.
threshold of the programmed V , signaling that the
OUT
6
3.5
C
= 100µF, I
= 50mA
LOAD
D1=D0=1
C
IN
= 22µF, C
= 100µF, I
= 10µA
LOAD
OUT
OUT
D1=D0=0
D1=D0=0
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
V
IN
= UVLO FALLING
V
IN
V
OUT
V
OUT
PGOOD = LOGIC 1
PGOOD
6
0
2
4
6
8
10 12 14 16 18 20
0
2
4
8
10
TIME (ms)
TIME (sec)
338813 F03
338813 F02
Figure 2. PGOOD Operation During Transition to UVLO
Figure 3. PGOOD Operation During D0/D1 Transition
338813fa
12
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
OPERATION
Enable and Standby Modes
Thesleepcomparatorhaslowerquiescentcurrentthanthe
PGOODcomparatorandwhentheLTC3388-1/LTC3388-3
is in sleep mode the PGOOD comparator is shut down and
PGOOD is held high. The same occurs in standby mode.
If the LTC3388-1/LTC3388-3 was in sleep before entering
standbyitwillstayinsleepinstandby,savingthequiescent
Two logic pins, EN and STBY, determine the operating
mode of the LTC3388-1/LTC3388-3. When EN is high
and STBY is low the synchronous buck converter is
enabled and will regulate the output if the input voltage
is above the programmed output voltage and above the
UVLO threshold. If EN is low the buck converter circuitry
is powered down to save quiescent current. The internal
rail generation circuits are kept alive and the voltages at
current of the PGOOD comparator. If V
falls below the
OUT
sleep falling threshold the PGOOD comparator will be
enabled. If V
falls below the PGOOD falling threshold
OUT
the PGOOD pin will be pulled low.
V
and CAP are maintained. When low, EN also shuts
IN2
down the PGOOD circuitry and pulls the PGOOD pin low.
If EN is high and the input falls below the UVLO threshold,
the buck converter is shut down.
If STBY is driven high with EN low it will be ignored and
the LTC3388-1/LTC3388-3 will remain shut down.
If EN and STBY are driven high but near V or low but
IH
While enabled, the LTC3388-1/LTC3388-3 can be placed
in standby mode by bringing STBY high. In standby mode
the buck converter is disabled, eliminating the quiescent
current used to run the buck circuitry. The PGOOD and
sleep comparators are kept alive to maintain the state of
the PGOOD pin.
near V , additional quiescent current may appear on V .
IL IN
This additional quiescent current is typically 40nA and
depends on V and temperature. Driving EN or STBY to
IN
0VorV willpreventadditionalquiescentcurrentonV .
IN2
IN
Figure 4 shows V
during a transition into and out of
OUT
standby.Whileinstandby,thebuckisoffandV
isquiet.
OUT
V
OUT
50mV/DIV
AC-COUPLED
STANDBY
5V/DIV
0V
338813 F04
500µs/DIV
= 100µF
V
= 5.5V,
IN
L = 22µH, C
OUT
STANDBY TRANSIENT
Figure 4. LTC3388-3 Standby Transient,
VOUT = 3.3V, ILOAD = 5mA
338813fa
13
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
Introduction
supply. Figure 5 shows this circuit and the typical values
required to dampen the ringing. The RC resistor may be
replaced by a single electrolytic capacitor that has an ESR
equivalent to the needed series resistance of the network.
See Application Note 88 for a complete discussion of this
phenomenon.
The basic LTC3388-1/LTC3388-3 application circuit is
shownonthefrontpage.Externalcomponentsareselected
basedontheperformancerequirementsoftheapplication.
Input Capacitor Selection
TheinputcapacitoratV shouldbeselectedtoadequately
Output Capacitor Selection
IN
bypasstheLTC3388-1/LTC3388-3andfiltertheswitching
The duration for which the regulator sleeps depends on
the load current and the size of the output capacitor.
The sleep time decreases as the load current increases
and/or as the output capacitor decreases. The DC sleep
currentpresentedbythebuckregulator. TheV capacitor
IN
should be rated to withstand the highest voltage ever
present at V . It should be placed as close as possible
IN
to the LTC3388-1/LTC3388-3 to force the high frequency
switchingcurrentintoatightlocallooptominimizeEMI. A
2.2μF ceramic X7R or X5R capacitor should be adequate
for bypassing.
hysteresis window, V
, is 8mV and 16mV around
HYST
the programmed output voltage on the LTC3388-1 and
LTC3388-3 respectively. Ideally this means that the sleep
time is determined by the following equation:
Highripplecurrent,highvoltagerating,andlowESRmake
ceramic capacitors ideal for switching regulator applica-
tions. However, caremustbetakenwhenthesecapacitors
areusedattheinputandoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
VHYST
ILOAD
t
SLEEP =COUT
This is true for output capacitors on the order of 100μF
or larger, but as the output capacitor decreases towards
10μF delays in the internal sleep comparator along with
the load current may result in the V
past the 8mV/ 16mV thresholds. This will lengthen the
sleep time and increase V
10μF is not recommended as V
to an undesirable level.
induceringingattheinput, V . Asuddeninrushofcurrent
voltage slewing
IN
OUT
through the long wires can potentially cause a voltage
spike at V large enough to damage the part.
ripple. A capacitor less than
IN
OUT
ripple could increase
OUT
For such applications with inductive source impedance,
such as a long wire, a series RC network may be required
in parallel with C to dampen the ringing of the input
IN
LTC3388-1/
LTC3388-3
L
IN
V
IN
LIN
CIN
338813 F05
R =
4 • C
C
IN
IN
Figure 5. Series RC to Reduce VIN Ringing
338813fa
14
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
If transient load currents above 50mA are required then a
larger capacitor can be used at the output. This capacitor
willbecontinuouslydischargedduringaloadconditionand
a DC current rating greater than 200mA. The DCR of the
inductor can have an impact on efficiency as it is a source
of loss. Trade-offs between price, size, and DCR should be
evaluated. Table 2 lists several inductors that work well
with the LTC3388-1/LTC3388-3.
the capacitor can be sized for an acceptable drop in V
:
OUT
tLOAD
C
OUT = (ILOAD – IBUCK )
–
VOUT+ – VOUT
is the value of V when PGOOD goes high
OUT
Table 2. Recommended Inductors for LTC3388-1/LTC3388-3
MAX
DC
MAX
DCR
(Ω)
+
–
L
I
SIZE in mm
(L × W × H)
MANU-
FACTURER
Here V
and V
OUT
INDUCTOR TYPE (µH) (mA)
is the desired lower limit of V . I
is the
OUT
OUT BUCK
CDRH2D18/LDNP 22
A997AS-220M 22
300
390
700
350
0.320 3.2 × 3.2 × 2.0
0.440 4.0 × 4.0 × 1.8
0.190 4.9 × 4.9 × 3.0
1.400 4.0 × 4.0 × 1.2
0.250 7.0 × 7.0 × 4.5
Sumida
Toko
average current being delivered from the buck converter,
typically I /2.
PEAK
LPS5030-223MLC 22
LPS4012-473MLC 47
Coilcraft
Coilcraft
TDK
A standard surface mount ceramic capacitor can be used
for C , though some applications may be better suited
OUT
SLF7045T
100 500
to a low leakage aluminum electrolytic capacitor or a
supercapacitor. These capacitors can be obtained from
manufacturers such as Vishay, Illinois Capacitor, AVX,
or CAP-XX.
V
and CAP Capacitors
IN2
A 1μF capacitor should be connected between V and
CAP and a 4.7μF capacitor should be connected between
IN
V
and GND. These capacitors hold up the internal rails
IN2
Inductor
during buck switching and compensate the internal rail
generation circuits. In applications where the input source
is limited to less than 6V, the CAP pin can be tied to GND
The buck is optimized to work with an inductor of at least
22μH. This value represents a suitable trade-off between
sizeandefficiencyfortypicalapplications.Alargerinductor
will benefit high voltage applications by increasing the
on-time of the PMOS switch and improving efficiency
by reducing gate charge loss. Choose an inductor with
and the V pin can be tied to V as shown in Figure 6.
IN2
IN
This circuit does not require the capacitors on V and
IN2
CAP, saving components and allowing a lower voltage
rating for the single V capacitor.
IN
EN
EN
LTC3388-1
STBY
STBY
PGOOD
PGOOD
V
IN
2.7V TO 5.5V
V
IN2
22µH
V
OUT
SW
OUT
CAP
D1
1.2V
2.2µF
6V
V
10µF
6V
D0
GND
338813 F06
Figure 6. Smallest Solution Size 1.2V
Low Input Voltage Power Supply
338813fa
15
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
Efficiency Considerations
MOSFET switches. Each time the gate is switched
from high to low to high again, a packet of charge, dQ,
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
moves from V to ground. The resulting dQ/dt is the
IN
current out of V that is typically larger than the DC
IN
bias current. Of course, this switching current only
appears when the buck is on and is important at high
load currents. Gate charge loss can be reduced by in-
creasing the inductor, thereby reducing the switching
frequency when the buck is active.
Efficiency = 100% – (η1 + η 2 + η 3 + ...)
whereη1,η2,etc.aretheindividuallossesasapercentage
of input power.
2
3. I R losses are calculated from the resistances of the
internal switches, R , and the external inductor DCR.
SW
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
When switching, the average output current flowing
through the inductor is “chopped” between the high
sidePMOSswitchandthelowsideNMOSswitch.Thus,
the series resistance looking back into the switch pin is
a function of the top and bottom switch on-resistance
the losses: 1) DC V operating current while active and
IN
2
in sleep, 2) MOSFET gate charge loss, and 3) I R losses.
The V operating current dominates the efficiency loss
IN
at very low load currents whereas the gate charge and
2
and the duty cycle (DC = V /V ) as follows:
OUT IN
I R loss dominates the efficiency loss at medium to high
load currents.
R
SW
= (R )DC + (R )(1 – DC)
P,BUCK N,BUCK
1. The DC V current is the average of the quiescent
Theon-resistanceforboththetopandbottomMOSFETs
can be obtained from the curves in the Typical Perfor-
IN
supply currents, given in the electrical characteristics,
in the active and sleep modes. This can be estimated
with the following equation:
2
mance Characteristics section. Thus, to obtain the I R
losses, simply add R to the DCR and multiply the
SW
LOAD
result by the square of the average output current:
ILOAD
I
I
IVIN(AVG)
=
IQ(ACTIVE) + 1−
I
Q(SLEEP)
2
2
I R Loss = I (R + DCR)
IBUCK
O
SW
BUCK
This loss term only occurs when the buck is operating
and must be multiplied by the percentage of time the
where I
is the average current being delivered
BUCK
from the buck converter, typically I
/2. For very
PEAK
buck is operating versus sleeping or I
/I
to see
LOAD BUCK
light loads I
will dominate this loss term which
Q(SLEEP)
its overall effect.
is why the extremely low quiescent current in sleep of
the LTC3388-1/LTC3388-3 is critical.
Otherlosses,includingC andC ESRdissipativelosses
IN
OUT
and inductor core losses, generally account for less than
2. Internal MOSFET gate charge currents result from
switching the gate capacitance of the internal power
2% of the total power loss.
338813fa
16
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
Interfacing with a Microprocessor
will cease and the output capacitor will support the load of
the microprocessor and other circuitry. While in standby
the output voltage will decrease as it’s loaded. The output
capacitor should be sized to minimize the decline.
The PGOOD, STBY, and EN pins can be useful when pow-
ering a microprocessor from the LTC3388-1/LTC3388-3.
ThePGOODsignalcanbeusedtoenableasleepingmicro-
TheENpincanbeusedtoactivatetheLTC3388-1/LTC3388-3.
For instance, in Figure 8 the LTC3388-1 is enabled by the
PGOOD output of the LTC3588-1, a piezoelectric energy
harvesting power supply, to create a 1.2V rail. The quies-
cent current that the LTC3388-1 draws will appear at the
input of the LTC3588-1, reduced by the conversion ratio
oftheLTC3588-1buckconverter. BecausetheLTC3388-1
is driven by a 3.3V supply no capacitors are needed for
processororothercircuitrywhenV reachesregulation,
OUT
as shown in Figure 7. While active, a microprocessor may
drawasmallloadwhenoperatingsensors,andthendrawa
largeloadtotransmitdata.Figure7showstheLTC3388-1/
LTC3388-3 responding smoothly to such a load step.
The microprocessor or other circuitry may require a quiet
supplyforperformingsomefunctions. TheSTBYpinallows
the microprocessor to place the LTC3388-1/LTC3388-3
intostandbymodewherethebuckconverterisinactive.Any
ripple in the output voltage of the LTC3388-1/LTC3388-3
the internal V and CAP rails.
IN2
2.7V TO 4.2V
V
STBY
STBY
EN
V
V
OUT
IN
20mV/DIV
PGOOD
T
X
IN2
AC-COUPLED
+
LTC3388-1
MICROPROCESSOR
1M
EN
22µH
Li-ION
SW
OUT
CORE
GND
D1
10µF
6V
LOAD
CURRENT
25mA/DIV
1.8V
V
CAP
D0
47µF
6V
0mA
GND
338813 F07b
250µs/DIV
= 100µF
338813 F07a
V
= 5.5V
IN
L = 22µH, C
OUT
LOAD STEP BETWEEN 5mA AND 50mA
Figure 7. 1.8V Step-Down Converter Powering a Microprocessor
with a Wireless Transmitter and 45mA Load Step Response
338813fa
17
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
MIDE V21BL
PZ2
PZ1
PGOOD
PGOOD
LTC3388-1
V
IN
EN
V
1µF
6V
LTC3588-1
1M
47µH
IN2
22µH
1.2V
SW
OUT
SW
OUT
CAP
V
IN
10µF
25V
3.3V
V
V
V
IN2
CAP
D1
D1
D0
10µF
6V
47µF
6V
4.7µF
6V
STBY
D0
GND
GND
338813 F07
Figure 8. Piezoelectric Energy Harvester and 1.2V Secondary Rail
338813fa
18
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
338813fa
19
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev D)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.88 ± 0.102
0.889 ± 0.127
1
0.29
REF
(.074 ± .004)
(.035 ± .005)
1.68
(.066)
0.05 REF
5.23
(.206)
MIN
1.68 ± 0.102 3.20 – 3.45
(.066 ± .004) (.126 – .136)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MSE) 0210 REV D
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
338813fa
20
For more information www.linear.com/LTC3388
LTC3388-1/LTC3388-3
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/15 Modified C
Equation
15
OUT
338813fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3388-1/LTC3388-3
TYPICAL APPLICATION
Piezoelectric Energy Harvester with Dual, 3.3V Outputs
PZ2
PZ1
PGOOD
V
IN
1µF
6V
LTC3588-1
22µH
3.3V
V
SW
OUT
CAP
IN
10µF
25V
1µF
6V
PGOOD
LTC3388-3
V
V
47µF
6V
IN2
CAP
D1
D0
22µH
2.2µF
10V
*
4.7µF
6V
SW
OUT
V
IN2
GND
V
EN
D1
D0
47µF
6V
4.7µF
6V
STBY
GND
–3.3V
338813 TA02
* EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM
SYSTEM GROUND AND CONNECTED TO THE –3.3V RAIL.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1389
Nanopower Precision Shunt Voltage Reference
Nanopower Comparator with Reference
800nA Operating Current, 1.25V/2.5V/4.096V
LTC1540
LT3009
0.3µA I , Drives 0.01µF, Adjustable Hysteresis, 2V to 11V Input Range
Q
3µA I , 20mA Low Dropout Linear Regulator
Low 3µA I , 1.6V to 20V Range, 20mA Output Current
Q
Q
LTC3588-1
Piezoelectric Energy Harvesting Power Supply
<1µA I in Regulation, 2.7V to 20V Input Range,
Integrated Bridge Rectifier
Q
LTC3588-2
Piezoelectric Energy Harvesting Power Supply
<1µA I in Regulation, UVLO Rising = 16V, UVLO Falling = 14V,
Q
V
= 3.45V, 4.1V, 4.5V, 5.0V
OUT
LT3652
LT3970
LT3971
LT3991
LTC3631
LTC3642
Power Tracking 2A Battery Charger for Solar Power
40V, 350mA Step-Down Regulator with 2.5µA I
MPPT for Solar, 4.95V to 32V, Up to 2A Charge Current
Integrated Boost and Catch Diodes, 4.2V to 40V Operating Range
4.3V to 38V Operating Range, Low Ripple Burst Mode® Operation
4.3V to 55V Operating Range, Low Ripple Burst Mode Operation
4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V
4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V
Q
38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA I
Q
55V, 1.2A 2MHz Step-Down Regulator with 2.8µA I
Q
45V, 100mA, Synchronous Step-Down Regulator with 12µA I
Q
45V, 50mA, Synchronous Step-Down Regulator with 12µA I
Q
338813fa
LT 0815 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3388
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